rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

prompt stringlengths 162 4.26M	response stringlengths 109 5.16M
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_95 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_95( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OutputUnit_121 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[10], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[10], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[10], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[10], out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} reg states : { `9` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `8` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `7` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `6` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `5` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `4` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `3` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `2` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `1` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `0` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, clock connect io.channel_status[0].occupied, states.`0`.occupied connect io.channel_status[0].flow, states.`0`.flow connect io.channel_status[1].occupied, states.`1`.occupied connect io.channel_status[1].flow, states.`1`.flow connect io.channel_status[2].occupied, states.`2`.occupied connect io.channel_status[2].flow, states.`2`.flow connect io.channel_status[3].occupied, states.`3`.occupied connect io.channel_status[3].flow, states.`3`.flow connect io.channel_status[4].occupied, states.`4`.occupied connect io.channel_status[4].flow, states.`4`.flow connect io.channel_status[5].occupied, states.`5`.occupied connect io.channel_status[5].flow, states.`5`.flow connect io.channel_status[6].occupied, states.`6`.occupied connect io.channel_status[6].flow, states.`6`.flow connect io.channel_status[7].occupied, states.`7`.occupied connect io.channel_status[7].flow, states.`7`.flow connect io.channel_status[8].occupied, states.`8`.occupied connect io.channel_status[8].flow, states.`8`.flow connect io.channel_status[9].occupied, states.`9`.occupied connect io.channel_status[9].flow, states.`9`.flow connect io.out.flit, io.in node _T = bits(io.out.vc_free, 9, 9) when _T : node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(states.`9`.occupied, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf assert(clock, states.`9`.occupied, UInt<1>(0h1), "") : assert connect states.`9`.occupied, UInt<1>(0h0) when io.allocs[9].alloc : connect states.`9`.occupied, UInt<1>(0h1) connect states.`9`.flow, io.allocs[9].flow node _io_credit_available_0_T = neq(states.`0`.c, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_credit_available_1_T = neq(states.`1`.c, UInt<1>(0h0)) connect io.credit_available[1], _io_credit_available_1_T node _io_credit_available_2_T = neq(states.`2`.c, UInt<1>(0h0)) connect io.credit_available[2], _io_credit_available_2_T node _io_credit_available_3_T = neq(states.`3`.c, UInt<1>(0h0)) connect io.credit_available[3], _io_credit_available_3_T node _io_credit_available_4_T = neq(states.`4`.c, UInt<1>(0h0)) connect io.credit_available[4], _io_credit_available_4_T node _io_credit_available_5_T = neq(states.`5`.c, UInt<1>(0h0)) connect io.credit_available[5], _io_credit_available_5_T node _io_credit_available_6_T = neq(states.`6`.c, UInt<1>(0h0)) connect io.credit_available[6], _io_credit_available_6_T node _io_credit_available_7_T = neq(states.`7`.c, UInt<1>(0h0)) connect io.credit_available[7], _io_credit_available_7_T node _io_credit_available_8_T = neq(states.`8`.c, UInt<1>(0h0)) connect io.credit_available[8], _io_credit_available_8_T node _io_credit_available_9_T = neq(states.`9`.c, UInt<1>(0h0)) connect io.credit_available[9], _io_credit_available_9_T node free = bits(io.out.credit_return, 0, 0) node free_1 = bits(io.out.credit_return, 1, 1) node free_2 = bits(io.out.credit_return, 2, 2) node free_3 = bits(io.out.credit_return, 3, 3) node free_4 = bits(io.out.credit_return, 4, 4) node free_5 = bits(io.out.credit_return, 5, 5) node free_6 = bits(io.out.credit_return, 6, 6) node free_7 = bits(io.out.credit_return, 7, 7) node free_8 = bits(io.out.credit_return, 8, 8) node free_9 = bits(io.out.credit_return, 9, 9) node _states_9_c_T = add(states.`9`.c, free_9) node _states_9_c_T_1 = sub(_states_9_c_T, io.credit_alloc[9].alloc) node _states_9_c_T_2 = tail(_states_9_c_T_1, 1) connect states.`9`.c, _states_9_c_T_2 node _T_4 = asUInt(reset) when _T_4 : connect states.`0`.occupied, UInt<1>(0h0) connect states.`1`.occupied, UInt<1>(0h0) connect states.`2`.occupied, UInt<1>(0h0) connect states.`3`.occupied, UInt<1>(0h0) connect states.`4`.occupied, UInt<1>(0h0) connect states.`5`.occupied, UInt<1>(0h0) connect states.`6`.occupied, UInt<1>(0h0) connect states.`7`.occupied, UInt<1>(0h0) connect states.`8`.occupied, UInt<1>(0h0) connect states.`9`.occupied, UInt<1>(0h0) connect states.`0`.c, UInt<3>(0h4) connect states.`1`.c, UInt<3>(0h4) connect states.`2`.c, UInt<3>(0h4) connect states.`3`.c, UInt<3>(0h4) connect states.`4`.c, UInt<3>(0h4) connect states.`5`.c, UInt<3>(0h4) connect states.`6`.c, UInt<3>(0h4) connect states.`7`.c, UInt<3>(0h4) connect states.`8`.c, UInt<3>(0h4) connect states.`9`.c, UInt<3>(0h4)	module OutputUnit_121( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_9, // @[OutputUnit.scala:58:14] output io_channel_status_9_occupied, // @[OutputUnit.scala:58:14] input io_allocs_9_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_9_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [9:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [9:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_9_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_9_c; // @[OutputUnit.scala:66:19]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_24 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<27>(0h4000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<27>(0h4000000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<27>(0h4000000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<27>(0h4000000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<27>(0h4000000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<27>(0h4000000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<27>(0h4000000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<27>(0h4000000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<27>(0h4000000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<28>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _T_1085 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1086 = orr(a_set_wo_ready) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) node _T_1088 = or(_T_1085, _T_1087) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_48 node _T_1092 = orr(inflight) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) node _T_1094 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1095 = or(_T_1093, _T_1094) node _T_1096 = lt(watchdog, plusarg_reader.out) node _T_1097 = or(_T_1095, _T_1096) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1101 = and(io.in.a.ready, io.in.a.valid) node _T_1102 = and(io.in.d.ready, io.in.d.valid) node _T_1103 = or(_T_1101, _T_1102) when _T_1103 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1104 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1105 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1106 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = and(_T_1104, _T_1107) when _T_1108 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1109 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1110 = and(_T_1109, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1111 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1112 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1113 = and(_T_1111, _T_1112) node _T_1114 = and(_T_1110, _T_1113) when _T_1114 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1115 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1116 = bits(_T_1115, 0, 0) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1124 = and(io.in.d.ready, io.in.d.valid) node _T_1125 = and(_T_1124, d_first_2) node _T_1126 = and(_T_1125, UInt<1>(0h1)) node _T_1127 = and(_T_1126, d_release_ack_1) when _T_1127 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1128 = and(io.in.d.valid, d_first_2) node _T_1129 = and(_T_1128, UInt<1>(0h1)) node _T_1130 = and(_T_1129, d_release_ack_1) when _T_1130 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1131 = dshr(inflight_1, io.in.d.bits.source) node _T_1132 = bits(_T_1131, 0, 0) node _T_1133 = or(_T_1132, same_cycle_resp_1) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1137 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_109 else : node _T_1141 = eq(io.in.d.bits.size, c_size_lookup) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_110 node _T_1145 = and(io.in.d.valid, d_first_2) node _T_1146 = and(_T_1145, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1147 = and(_T_1146, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1148 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1149 = and(_T_1147, _T_1148) node _T_1150 = and(_T_1149, d_release_ack_1) node _T_1151 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1152 = and(_T_1150, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<28>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1154 = or(_T_1153, _WIRE_27.ready) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_111 node _T_1158 = orr(c_set_wo_ready) when _T_1158 : node _T_1159 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_49 node _T_1163 = orr(inflight_1) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) node _T_1165 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = lt(watchdog_1, plusarg_reader_1.out) node _T_1168 = or(_T_1166, _T_1167) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<28>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1172 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1173 = and(io.in.d.ready, io.in.d.valid) node _T_1174 = or(_T_1172, _T_1173) when _T_1174 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_24( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1101 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1101; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1101; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1174 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1174; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1174; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1174; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1027 = _T_1101 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1042 = _T_1174 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1145 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1145 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1127 = _T_1174 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1127 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1127 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1127 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MSHR_7 : input clock : Clock input reset : Reset output io : { flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>}, idx_match : UInt<1>, tag : UInt<20>, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, refill : { way_en : UInt<8>, addr : UInt<12>}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, sdq_id : UInt<5>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<2>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, probe_rdy : UInt<1>} regreset state : UInt<4>, clock, reset, UInt<4>(0h0) reg req : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>}, clock node req_idx = bits(req.addr, 11, 6) node req_tag = shr(req.addr, 12) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) node _idx_match_T = bits(io.req_bits.addr, 11, 6) node idx_match = eq(req_idx, _idx_match_T) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req_bits.cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req_bits.cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req_bits.cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req_bits.cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req_bits.cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req_bits.cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req_bits.cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req_bits.cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req_bits.cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req_bits.cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req_bits.cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req_bits.cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req_bits.cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req_bits.cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req_bits.cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req_bits.cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req_bits.cmd, req.cmd) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, io.mem_grant.valid) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when io.mem_grant.valid : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 3) node _sec_rdy_T = eq(state, UInt<4>(0h1)) node _sec_rdy_T_1 = eq(state, UInt<4>(0h2)) node _sec_rdy_T_2 = eq(state, UInt<4>(0h3)) node _sec_rdy_T_3 = or(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_4 = or(_sec_rdy_T_3, _sec_rdy_T_2) node _sec_rdy_T_5 = eq(state, UInt<4>(0h4)) node _sec_rdy_T_6 = eq(state, UInt<4>(0h5)) node _sec_rdy_T_7 = or(_sec_rdy_T_5, _sec_rdy_T_6) node _sec_rdy_T_8 = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_9 = and(_sec_rdy_T_7, _sec_rdy_T_8) node _sec_rdy_T_10 = eq(refill_done, UInt<1>(0h0)) node _sec_rdy_T_11 = and(_sec_rdy_T_9, _sec_rdy_T_10) node _sec_rdy_T_12 = or(_sec_rdy_T_4, _sec_rdy_T_11) node sec_rdy = and(idx_match, _sec_rdy_T_12) inst rpq of Queue16_ReplayInternal connect rpq.clock, clock connect rpq.reset, reset node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req_bits.cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req_bits.cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req_bits.sdq_id connect rpq.io.enq.bits.no_xcpt, io.req_bits.no_xcpt connect rpq.io.enq.bits.no_alloc, io.req_bits.no_alloc connect rpq.io.enq.bits.no_resp, io.req_bits.no_resp connect rpq.io.enq.bits.phys, io.req_bits.phys connect rpq.io.enq.bits.dv, io.req_bits.dv connect rpq.io.enq.bits.dprv, io.req_bits.dprv connect rpq.io.enq.bits.signed, io.req_bits.signed connect rpq.io.enq.bits.size, io.req_bits.size connect rpq.io.enq.bits.cmd, io.req_bits.cmd connect rpq.io.enq.bits.tag, io.req_bits.tag connect rpq.io.enq.bits.addr, io.req_bits.addr node _rpq_io_deq_ready_T = eq(state, UInt<4>(0h8)) node _rpq_io_deq_ready_T_1 = and(io.replay.ready, _rpq_io_deq_ready_T) node _rpq_io_deq_ready_T_2 = eq(state, UInt<4>(0h0)) node _rpq_io_deq_ready_T_3 = or(_rpq_io_deq_ready_T_1, _rpq_io_deq_ready_T_2) connect rpq.io.deq.ready, _rpq_io_deq_ready_T_3 reg acked : UInt<1>, clock when io.mem_grant.valid : connect acked, UInt<1>(0h1) node _T = eq(state, UInt<4>(0h8)) node _T_1 = eq(rpq.io.deq.valid, UInt<1>(0h0)) node _T_2 = and(_T, _T_1) when _T_2 : connect state, UInt<4>(0h0) node _T_3 = eq(state, UInt<4>(0h7)) when _T_3 : connect state, UInt<4>(0h8) node _T_4 = eq(state, UInt<4>(0h6)) node _T_5 = and(_T_4, io.meta_write.ready) when _T_5 : connect state, UInt<4>(0h7) node _T_6 = eq(state, UInt<4>(0h5)) node _T_7 = and(_T_6, refill_done) when _T_7 : connect new_coh, coh_on_grant connect state, UInt<4>(0h6) node _T_8 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_8 : connect state, UInt<4>(0h5) node _T_9 = eq(state, UInt<4>(0h3)) node _T_10 = and(_T_9, io.meta_write.ready) when _T_10 : connect state, UInt<4>(0h4) node _T_11 = eq(state, UInt<4>(0h2)) node _T_12 = and(_T_11, io.wb_req.ready) node _T_13 = and(_T_12, acked) when _T_13 : connect state, UInt<4>(0h3) node _T_14 = and(io.wb_req.ready, io.wb_req.valid) when _T_14 : connect state, UInt<4>(0h2) node _T_15 = and(io.req_sec_val, io.req_sec_rdy) when _T_15 : connect req.cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_16 = and(io.req_pri_val, io.req_pri_rdy) when _T_16 : connect req, io.req_bits connect acked, UInt<1>(0h0) node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.req_bits.old_meta.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _r_c_cat_T = eq(io.req_bits.cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(io.req_bits.cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(io.req_bits.cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(io.req_bits.cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(io.req_bits.cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(io.req_bits.cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, io.req_bits.old_meta.coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 when io.req_bits.tag_match : when is_hit : connect new_coh, coh_on_hit connect state, UInt<4>(0h6) else : connect new_coh, io.req_bits.old_meta.coh connect state, UInt<4>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 node _state_T = mux(needs_wb, UInt<4>(0h1), UInt<4>(0h3)) connect state, _state_T inst grantackq of Queue1_TLBundleE_a32d64s2k3z4c connect grantackq.clock, clock connect grantackq.reset, reset node _can_finish_T = eq(state, UInt<4>(0h0)) node _can_finish_T_1 = eq(state, UInt<4>(0h4)) node can_finish = or(_can_finish_T, _can_finish_T_1) node _grantackq_io_enq_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantackq_io_enq_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantackq_io_enq_valid_T_2 = eq(_grantackq_io_enq_valid_T_1, UInt<1>(0h0)) node _grantackq_io_enq_valid_T_3 = and(_grantackq_io_enq_valid_T, _grantackq_io_enq_valid_T_2) node _grantackq_io_enq_valid_T_4 = and(refill_done, _grantackq_io_enq_valid_T_3) connect grantackq.io.enq.valid, _grantackq_io_enq_valid_T_4 wire grantackq_io_enq_bits_e : { sink : UInt<3>} connect grantackq_io_enq_bits_e.sink, io.mem_grant.bits.sink connect grantackq.io.enq.bits.sink, grantackq_io_enq_bits_e.sink node _io_mem_finish_valid_T = and(grantackq.io.deq.valid, can_finish) connect io.mem_finish.valid, _io_mem_finish_valid_T connect io.mem_finish.bits, grantackq.io.deq.bits node _grantackq_io_deq_ready_T = and(io.mem_finish.ready, can_finish) connect grantackq.io.deq.ready, _grantackq_io_deq_ready_T node _io_idx_match_T = neq(state, UInt<4>(0h0)) node _io_idx_match_T_1 = and(_io_idx_match_T, idx_match) connect io.idx_match, _io_idx_match_T_1 connect io.refill.way_en, req.way_en node _io_refill_addr_T = or(req_block_addr, refill_address_inc) connect io.refill.addr, _io_refill_addr_T connect io.tag, req_tag node _io_req_pri_rdy_T = eq(state, UInt<4>(0h0)) connect io.req_pri_rdy, _io_req_pri_rdy_T node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_17 = neq(meta_hazard, UInt<1>(0h0)) when _T_17 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_18 = and(io.meta_write.ready, io.meta_write.valid) when _T_18 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(idx_match, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<4>(0h1)) node _io_probe_rdy_T_2 = eq(state, UInt<4>(0h2)) node _io_probe_rdy_T_3 = eq(state, UInt<4>(0h3)) node _io_probe_rdy_T_4 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_4, _io_probe_rdy_T_3) node _io_probe_rdy_T_6 = eq(_io_probe_rdy_T_5, UInt<1>(0h0)) node _io_probe_rdy_T_7 = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_8 = and(_io_probe_rdy_T_6, _io_probe_rdy_T_7) node _io_probe_rdy_T_9 = or(_io_probe_rdy_T, _io_probe_rdy_T_8) connect io.probe_rdy, _io_probe_rdy_T_9 node _io_meta_write_valid_T = eq(state, UInt<4>(0h6)) node _io_meta_write_valid_T_1 = eq(state, UInt<4>(0h3)) node _io_meta_write_valid_T_2 = or(_io_meta_write_valid_T, _io_meta_write_valid_T_1) connect io.meta_write.valid, _io_meta_write_valid_T_2 connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.tag, io.tag node _io_meta_write_bits_data_coh_T = eq(state, UInt<4>(0h3)) node _io_meta_write_bits_data_coh_T_1 = mux(_io_meta_write_bits_data_coh_T, coh_on_clear, new_coh) connect io.meta_write.bits.data.coh, _io_meta_write_bits_data_coh_T_1 connect io.meta_write.bits.data.tag, io.tag connect io.meta_write.bits.way_en, req.way_en node _io_wb_req_valid_T = eq(state, UInt<4>(0h1)) connect io.wb_req.valid, _io_wb_req_valid_T connect io.wb_req.bits.source, UInt<1>(0h0) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.voluntary, UInt<1>(0h1) node _io_mem_acquire_valid_T = eq(state, UInt<4>(0h4)) node _io_mem_acquire_valid_T_1 = and(_io_mem_acquire_valid_T, grantackq.io.enq.ready) connect io.mem_acquire.valid, _io_mem_acquire_valid_T_1 node _io_mem_acquire_bits_T = cat(io.tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = xor(_io_mem_acquire_bits_T_1, UInt<17>(0h10000)) node _io_mem_acquire_bits_legal_T_7 = cvt(_io_mem_acquire_bits_legal_T_6) node _io_mem_acquire_bits_legal_T_8 = and(_io_mem_acquire_bits_legal_T_7, asSInt(UInt<33>(0h8c011000))) node _io_mem_acquire_bits_legal_T_9 = asSInt(_io_mem_acquire_bits_legal_T_8) node _io_mem_acquire_bits_legal_T_10 = eq(_io_mem_acquire_bits_legal_T_9, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_11 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0hc000000)) node _io_mem_acquire_bits_legal_T_12 = cvt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = and(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_14 = asSInt(_io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = eq(_io_mem_acquire_bits_legal_T_14, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_16 = or(_io_mem_acquire_bits_legal_T_5, _io_mem_acquire_bits_legal_T_10) node _io_mem_acquire_bits_legal_T_17 = or(_io_mem_acquire_bits_legal_T_16, _io_mem_acquire_bits_legal_T_15) node _io_mem_acquire_bits_legal_T_18 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_17) node _io_mem_acquire_bits_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_20 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_19) node _io_mem_acquire_bits_legal_T_21 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0h8000000)) node _io_mem_acquire_bits_legal_T_22 = cvt(_io_mem_acquire_bits_legal_T_21) node _io_mem_acquire_bits_legal_T_23 = and(_io_mem_acquire_bits_legal_T_22, asSInt(UInt<33>(0h8c010000))) node _io_mem_acquire_bits_legal_T_24 = asSInt(_io_mem_acquire_bits_legal_T_23) node _io_mem_acquire_bits_legal_T_25 = eq(_io_mem_acquire_bits_legal_T_24, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_26 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_27 = cvt(_io_mem_acquire_bits_legal_T_26) node _io_mem_acquire_bits_legal_T_28 = and(_io_mem_acquire_bits_legal_T_27, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_29 = asSInt(_io_mem_acquire_bits_legal_T_28) node _io_mem_acquire_bits_legal_T_30 = eq(_io_mem_acquire_bits_legal_T_29, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_31 = or(_io_mem_acquire_bits_legal_T_25, _io_mem_acquire_bits_legal_T_30) node _io_mem_acquire_bits_legal_T_32 = and(_io_mem_acquire_bits_legal_T_20, _io_mem_acquire_bits_legal_T_31) node _io_mem_acquire_bits_legal_T_33 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_18) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_33, _io_mem_acquire_bits_legal_T_32) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, UInt<1>(0h0) connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a node _io_meta_read_valid_T = eq(state, UInt<4>(0h8)) connect io.meta_read.valid, _io_meta_read_valid_T connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, io.tag node _io_meta_read_bits_way_en_T = not(UInt<8>(0h0)) connect io.meta_read.bits.way_en, _io_meta_read_bits_way_en_T node _io_replay_valid_T = eq(state, UInt<4>(0h8)) node _io_replay_valid_T_1 = and(_io_replay_valid_T, rpq.io.deq.valid) connect io.replay.valid, _io_replay_valid_T_1 connect io.replay.bits, rpq.io.deq.bits connect io.replay.bits.phys, UInt<1>(0h1) node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(io.tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_19 = eq(io.meta_read.ready, UInt<1>(0h0)) when _T_19 : connect rpq.io.deq.ready, UInt<1>(0h0) connect io.replay.bits.cmd, UInt<3>(0h5)	module MSHR_7( // @[NBDcache.scala:150:7] input clock, // @[NBDcache.scala:150:7] input reset, // @[NBDcache.scala:150:7] input io_req_pri_val, // @[NBDcache.scala:151:14] output io_req_pri_rdy, // @[NBDcache.scala:151:14] input io_req_sec_val, // @[NBDcache.scala:151:14] output io_req_sec_rdy, // @[NBDcache.scala:151:14] input [39:0] io_req_bits_addr, // @[NBDcache.scala:151:14] input [6:0] io_req_bits_tag, // @[NBDcache.scala:151:14] input [4:0] io_req_bits_cmd, // @[NBDcache.scala:151:14] input [1:0] io_req_bits_size, // @[NBDcache.scala:151:14] input io_req_bits_signed, // @[NBDcache.scala:151:14] input [1:0] io_req_bits_dprv, // @[NBDcache.scala:151:14] input io_req_bits_dv, // @[NBDcache.scala:151:14] input io_req_bits_phys, // @[NBDcache.scala:151:14] input io_req_bits_no_resp, // @[NBDcache.scala:151:14] input io_req_bits_no_alloc, // @[NBDcache.scala:151:14] input io_req_bits_no_xcpt, // @[NBDcache.scala:151:14] input [4:0] io_req_bits_sdq_id, // @[NBDcache.scala:151:14] input io_req_bits_tag_match, // @[NBDcache.scala:151:14] input [1:0] io_req_bits_old_meta_coh_state, // @[NBDcache.scala:151:14] input [19:0] io_req_bits_old_meta_tag, // @[NBDcache.scala:151:14] input [7:0] io_req_bits_way_en, // @[NBDcache.scala:151:14] output io_idx_match, // @[NBDcache.scala:151:14] output [19:0] io_tag, // @[NBDcache.scala:151:14] input io_mem_acquire_ready, // @[NBDcache.scala:151:14] output io_mem_acquire_valid, // @[NBDcache.scala:151:14] output [2:0] io_mem_acquire_bits_param, // @[NBDcache.scala:151:14] output [31:0] io_mem_acquire_bits_address, // @[NBDcache.scala:151:14] input io_mem_grant_valid, // @[NBDcache.scala:151:14] input [2:0] io_mem_grant_bits_opcode, // @[NBDcache.scala:151:14] input [1:0] io_mem_grant_bits_param, // @[NBDcache.scala:151:14] input [3:0] io_mem_grant_bits_size, // @[NBDcache.scala:151:14] input [1:0] io_mem_grant_bits_source, // @[NBDcache.scala:151:14] input [2:0] io_mem_grant_bits_sink, // @[NBDcache.scala:151:14] input io_mem_grant_bits_denied, // @[NBDcache.scala:151:14] input [63:0] io_mem_grant_bits_data, // @[NBDcache.scala:151:14] input io_mem_grant_bits_corrupt, // @[NBDcache.scala:151:14] input io_mem_finish_ready, // @[NBDcache.scala:151:14] output io_mem_finish_valid, // @[NBDcache.scala:151:14] output [2:0] io_mem_finish_bits_sink, // @[NBDcache.scala:151:14] output [7:0] io_refill_way_en, // @[NBDcache.scala:151:14] output [11:0] io_refill_addr, // @[NBDcache.scala:151:14] input io_meta_read_ready, // @[NBDcache.scala:151:14] output io_meta_read_valid, // @[NBDcache.scala:151:14] output [5:0] io_meta_read_bits_idx, // @[NBDcache.scala:151:14] output [19:0] io_meta_read_bits_tag, // @[NBDcache.scala:151:14] input io_meta_write_ready, // @[NBDcache.scala:151:14] output io_meta_write_valid, // @[NBDcache.scala:151:14] output [5:0] io_meta_write_bits_idx, // @[NBDcache.scala:151:14] output [7:0] io_meta_write_bits_way_en, // @[NBDcache.scala:151:14] output [19:0] io_meta_write_bits_tag, // @[NBDcache.scala:151:14] output [1:0] io_meta_write_bits_data_coh_state, // @[NBDcache.scala:151:14] output [19:0] io_meta_write_bits_data_tag, // @[NBDcache.scala:151:14] input io_replay_ready, // @[NBDcache.scala:151:14] output io_replay_valid, // @[NBDcache.scala:151:14] output [39:0] io_replay_bits_addr, // @[NBDcache.scala:151:14] output [6:0] io_replay_bits_tag, // @[NBDcache.scala:151:14] output [4:0] io_replay_bits_cmd, // @[NBDcache.scala:151:14] output [1:0] io_replay_bits_size, // @[NBDcache.scala:151:14] output io_replay_bits_signed, // @[NBDcache.scala:151:14] output [1:0] io_replay_bits_dprv, // @[NBDcache.scala:151:14] output io_replay_bits_dv, // @[NBDcache.scala:151:14] output io_replay_bits_no_resp, // @[NBDcache.scala:151:14] output io_replay_bits_no_alloc, // @[NBDcache.scala:151:14] output io_replay_bits_no_xcpt, // @[NBDcache.scala:151:14] output [4:0] io_replay_bits_sdq_id, // @[NBDcache.scala:151:14] input io_wb_req_ready, // @[NBDcache.scala:151:14] output io_wb_req_valid, // @[NBDcache.scala:151:14] output [19:0] io_wb_req_bits_tag, // @[NBDcache.scala:151:14] output [5:0] io_wb_req_bits_idx, // @[NBDcache.scala:151:14] output [2:0] io_wb_req_bits_param, // @[NBDcache.scala:151:14] output [7:0] io_wb_req_bits_way_en, // @[NBDcache.scala:151:14] output io_probe_rdy // @[NBDcache.scala:151:14] ); wire [19:0] io_tag_0; // @[NBDcache.scala:150:7] wire _grantackq_io_enq_ready; // @[NBDcache.scala:263:25] wire _grantackq_io_deq_valid; // @[NBDcache.scala:263:25] wire _rpq_io_enq_ready; // @[NBDcache.scala:200:19] wire _rpq_io_deq_valid; // @[NBDcache.scala:200:19] wire [39:0] _rpq_io_deq_bits_addr; // @[NBDcache.scala:200:19] wire [4:0] _rpq_io_deq_bits_cmd; // @[NBDcache.scala:200:19] wire io_req_pri_val_0 = io_req_pri_val; // @[NBDcache.scala:150:7] wire io_req_sec_val_0 = io_req_sec_val; // @[NBDcache.scala:150:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[NBDcache.scala:150:7] wire [6:0] io_req_bits_tag_0 = io_req_bits_tag; // @[NBDcache.scala:150:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[NBDcache.scala:150:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[NBDcache.scala:150:7] wire io_req_bits_signed_0 = io_req_bits_signed; // @[NBDcache.scala:150:7] wire [1:0] io_req_bits_dprv_0 = io_req_bits_dprv; // @[NBDcache.scala:150:7] wire io_req_bits_dv_0 = io_req_bits_dv; // @[NBDcache.scala:150:7] wire io_req_bits_phys_0 = io_req_bits_phys; // @[NBDcache.scala:150:7] wire io_req_bits_no_resp_0 = io_req_bits_no_resp; // @[NBDcache.scala:150:7] wire io_req_bits_no_alloc_0 = io_req_bits_no_alloc; // @[NBDcache.scala:150:7] wire io_req_bits_no_xcpt_0 = io_req_bits_no_xcpt; // @[NBDcache.scala:150:7] wire [4:0] io_req_bits_sdq_id_0 = io_req_bits_sdq_id; // @[NBDcache.scala:150:7] wire io_req_bits_tag_match_0 = io_req_bits_tag_match; // @[NBDcache.scala:150:7] wire [1:0] io_req_bits_old_meta_coh_state_0 = io_req_bits_old_meta_coh_state; // @[NBDcache.scala:150:7] wire [19:0] io_req_bits_old_meta_tag_0 = io_req_bits_old_meta_tag; // @[NBDcache.scala:150:7] wire [7:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[NBDcache.scala:150:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[NBDcache.scala:150:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[NBDcache.scala:150:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[NBDcache.scala:150:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[NBDcache.scala:150:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[NBDcache.scala:150:7] wire [1:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[NBDcache.scala:150:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[NBDcache.scala:150:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[NBDcache.scala:150:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[NBDcache.scala:150:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[NBDcache.scala:150:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[NBDcache.scala:150:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[NBDcache.scala:150:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[NBDcache.scala:150:7] wire io_replay_ready_0 = io_replay_ready; // @[NBDcache.scala:150:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[NBDcache.scala:150:7] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire io_replay_bits_phys = 1'h1; // @[NBDcache.scala:150:7] wire io_wb_req_bits_voluntary = 1'h1; // @[NBDcache.scala:150:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_corrupt = 1'h0; // @[NBDcache.scala:150:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[NBDcache.scala:150:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[NBDcache.scala:150:7] wire [7:0] io_meta_read_bits_way_en = 8'hFF; // @[NBDcache.scala:150:7] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire [7:0] _io_meta_read_bits_way_en_T = 8'hFF; // @[NBDcache.scala:308:31] wire [1:0] io_mem_acquire_bits_source = 2'h0; // @[NBDcache.scala:150:7] wire [1:0] io_wb_req_bits_source = 2'h0; // @[NBDcache.scala:150:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] io_mem_acquire_bits_a_source = 2'h0; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[NBDcache.scala:150:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[NBDcache.scala:150:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire _io_req_pri_rdy_T; // @[NBDcache.scala:275:27] wire _io_req_sec_rdy_T; // @[NBDcache.scala:276:29] wire _io_idx_match_T_1; // @[NBDcache.scala:271:41] wire [19:0] io_meta_read_bits_tag_0 = io_tag_0; // @[NBDcache.scala:150:7] wire [19:0] io_meta_write_bits_tag_0 = io_tag_0; // @[NBDcache.scala:150:7] wire [19:0] io_meta_write_bits_data_tag_0 = io_tag_0; // @[NBDcache.scala:150:7] wire _io_mem_acquire_valid_T_1; // @[NBDcache.scala:298:50] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantackq_io_enq_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire _io_mem_finish_valid_T; // @[NBDcache.scala:267:49] wire _io_meta_read_valid_T; // @[NBDcache.scala:305:31] wire [5:0] req_idx; // @[NBDcache.scala:177:25] wire _io_meta_write_valid_T_2; // @[package.scala:81:59] wire [1:0] _io_meta_write_bits_data_coh_T_1_state; // @[NBDcache.scala:286:37] wire _io_replay_valid_T_1; // @[NBDcache.scala:310:44] wire _io_wb_req_valid_T; // @[NBDcache.scala:290:28] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire _io_probe_rdy_T_9; // @[NBDcache.scala:281:30] wire [2:0] io_mem_acquire_bits_param_0; // @[NBDcache.scala:150:7] wire [31:0] io_mem_acquire_bits_address_0; // @[NBDcache.scala:150:7] wire io_mem_acquire_valid_0; // @[NBDcache.scala:150:7] wire [2:0] io_mem_finish_bits_sink_0; // @[NBDcache.scala:150:7] wire io_mem_finish_valid_0; // @[NBDcache.scala:150:7] wire [7:0] io_refill_way_en_0; // @[NBDcache.scala:150:7] wire [11:0] io_refill_addr_0; // @[NBDcache.scala:150:7] wire [5:0] io_meta_read_bits_idx_0; // @[NBDcache.scala:150:7] wire io_meta_read_valid_0; // @[NBDcache.scala:150:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[NBDcache.scala:150:7] wire [5:0] io_meta_write_bits_idx_0; // @[NBDcache.scala:150:7] wire [7:0] io_meta_write_bits_way_en_0; // @[NBDcache.scala:150:7] wire io_meta_write_valid_0; // @[NBDcache.scala:150:7] wire [39:0] io_replay_bits_addr_0; // @[NBDcache.scala:150:7] wire [6:0] io_replay_bits_tag_0; // @[NBDcache.scala:150:7] wire [4:0] io_replay_bits_cmd_0; // @[NBDcache.scala:150:7] wire [1:0] io_replay_bits_size_0; // @[NBDcache.scala:150:7] wire io_replay_bits_signed_0; // @[NBDcache.scala:150:7] wire [1:0] io_replay_bits_dprv_0; // @[NBDcache.scala:150:7] wire io_replay_bits_dv_0; // @[NBDcache.scala:150:7] wire io_replay_bits_no_resp_0; // @[NBDcache.scala:150:7] wire io_replay_bits_no_alloc_0; // @[NBDcache.scala:150:7] wire io_replay_bits_no_xcpt_0; // @[NBDcache.scala:150:7] wire [4:0] io_replay_bits_sdq_id_0; // @[NBDcache.scala:150:7] wire io_replay_valid_0; // @[NBDcache.scala:150:7] wire [19:0] io_wb_req_bits_tag_0; // @[NBDcache.scala:150:7] wire [5:0] io_wb_req_bits_idx_0; // @[NBDcache.scala:150:7] wire [2:0] io_wb_req_bits_param_0; // @[NBDcache.scala:150:7] wire [7:0] io_wb_req_bits_way_en_0; // @[NBDcache.scala:150:7] wire io_wb_req_valid_0; // @[NBDcache.scala:150:7] wire io_req_pri_rdy_0; // @[NBDcache.scala:150:7] wire io_req_sec_rdy_0; // @[NBDcache.scala:150:7] wire io_idx_match_0; // @[NBDcache.scala:150:7] wire io_probe_rdy_0; // @[NBDcache.scala:150:7] reg [3:0] state; // @[NBDcache.scala:174:22] reg [39:0] req_addr; // @[NBDcache.scala:176:16] reg [6:0] req_tag; // @[NBDcache.scala:176:16] reg [4:0] req_cmd; // @[NBDcache.scala:176:16] reg [1:0] req_size; // @[NBDcache.scala:176:16] reg req_signed; // @[NBDcache.scala:176:16] reg [1:0] req_dprv; // @[NBDcache.scala:176:16] reg req_dv; // @[NBDcache.scala:176:16] reg req_phys; // @[NBDcache.scala:176:16] reg req_no_resp; // @[NBDcache.scala:176:16] reg req_no_alloc; // @[NBDcache.scala:176:16] reg req_no_xcpt; // @[NBDcache.scala:176:16] reg [4:0] req_sdq_id; // @[NBDcache.scala:176:16] reg req_tag_match; // @[NBDcache.scala:176:16] reg [1:0] req_old_meta_coh_state; // @[NBDcache.scala:176:16] reg [19:0] req_old_meta_tag; // @[NBDcache.scala:176:16] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[NBDcache.scala:150:7, :176:16] reg [7:0] req_way_en; // @[NBDcache.scala:176:16] assign io_refill_way_en_0 = req_way_en; // @[NBDcache.scala:150:7, :176:16] assign io_meta_write_bits_way_en_0 = req_way_en; // @[NBDcache.scala:150:7, :176:16] assign io_wb_req_bits_way_en_0 = req_way_en; // @[NBDcache.scala:150:7, :176:16] assign req_idx = req_addr[11:6]; // @[NBDcache.scala:176:16, :177:25] assign io_meta_read_bits_idx_0 = req_idx; // @[NBDcache.scala:150:7, :177:25] assign io_meta_write_bits_idx_0 = req_idx; // @[NBDcache.scala:150:7, :177:25] assign io_wb_req_bits_idx_0 = req_idx; // @[NBDcache.scala:150:7, :177:25] wire [27:0] req_tag_0 = req_addr[39:12]; // @[NBDcache.scala:176:16, :178:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[NBDcache.scala:176:16, :179:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[NBDcache.scala:179:{34,51}] wire [5:0] _idx_match_T = io_req_bits_addr_0[11:6]; // @[NBDcache.scala:150:7, :180:47] wire idx_match = req_idx == _idx_match_T; // @[NBDcache.scala:177:25, :180:{27,47}] reg [1:0] new_coh_state; // @[NBDcache.scala:182:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_cmd == 5'h1; // @[NBDcache.scala:176:16] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_cmd == 5'h11; // @[NBDcache.scala:176:16] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_cmd == 5'h7; // @[NBDcache.scala:176:16] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_cmd == 5'h3; // @[NBDcache.scala:176:16] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_cmd == 5'h6; // @[NBDcache.scala:176:16] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] wire [1:0] coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_bits_cmd_0 == 5'h1; // @[NBDcache.scala:150:7] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_bits_cmd_0 == 5'h11; // @[NBDcache.scala:150:7] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_bits_cmd_0 == 5'h7; // @[NBDcache.scala:150:7] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_bits_cmd_0 == 5'h3; // @[NBDcache.scala:150:7] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_bits_cmd_0 == 5'h6; // @[NBDcache.scala:150:7] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_bits_cmd_0 : req_cmd; // @[Metadata.scala:106:42, :109:27] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & io_mem_grant_valid_0; // @[Edges.scala:232:33, :233:22] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _GEN_27 = state == 4'h1; // @[package.scala:16:47] wire _sec_rdy_T; // @[package.scala:16:47] assign _sec_rdy_T = _GEN_27; // @[package.scala:16:47] wire _io_probe_rdy_T_1; // @[package.scala:16:47] assign _io_probe_rdy_T_1 = _GEN_27; // @[package.scala:16:47] assign _io_wb_req_valid_T = _GEN_27; // @[package.scala:16:47] wire _T_11 = state == 4'h2; // @[package.scala:16:47] wire _sec_rdy_T_1; // @[package.scala:16:47] assign _sec_rdy_T_1 = _T_11; // @[package.scala:16:47] wire _io_probe_rdy_T_2; // @[package.scala:16:47] assign _io_probe_rdy_T_2 = _T_11; // @[package.scala:16:47] wire _T_9 = state == 4'h3; // @[package.scala:16:47] wire _sec_rdy_T_2; // @[package.scala:16:47] assign _sec_rdy_T_2 = _T_9; // @[package.scala:16:47] wire _io_probe_rdy_T_3; // @[package.scala:16:47] assign _io_probe_rdy_T_3 = _T_9; // @[package.scala:16:47] wire _io_meta_write_valid_T_1; // @[package.scala:16:47] assign _io_meta_write_valid_T_1 = _T_9; // @[package.scala:16:47] wire _io_meta_write_bits_data_coh_T; // @[NBDcache.scala:286:44] assign _io_meta_write_bits_data_coh_T = _T_9; // @[package.scala:16:47] wire _sec_rdy_T_3 = _sec_rdy_T \| _sec_rdy_T_1; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_4 = _sec_rdy_T_3 \| _sec_rdy_T_2; // @[package.scala:16:47, :81:59] wire _GEN_28 = state == 4'h4; // @[package.scala:16:47] wire _sec_rdy_T_5; // @[package.scala:16:47] assign _sec_rdy_T_5 = _GEN_28; // @[package.scala:16:47] wire _can_finish_T_1; // @[package.scala:16:47] assign _can_finish_T_1 = _GEN_28; // @[package.scala:16:47] wire _io_mem_acquire_valid_T; // @[NBDcache.scala:298:33] assign _io_mem_acquire_valid_T = _GEN_28; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 4'h5; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_9 = _sec_rdy_T_7 & _sec_rdy_T_8; // @[package.scala:81:59] wire _sec_rdy_T_10 = ~refill_done; // @[Edges.scala:233:22] wire _sec_rdy_T_11 = _sec_rdy_T_9 & _sec_rdy_T_10; // @[NBDcache.scala:197:65, :198:{52,55}] wire _sec_rdy_T_12 = _sec_rdy_T_4 \| _sec_rdy_T_11; // @[package.scala:81:59] wire sec_rdy = idx_match & _sec_rdy_T_12; // @[NBDcache.scala:180:27, :195:27, :196:56] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[NBDcache.scala:150:7, :201:39] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & sec_rdy; // @[NBDcache.scala:150:7, :195:27, :201:75] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[NBDcache.scala:201:{39,57,75}] wire _rpq_io_enq_valid_T_3 = io_req_bits_cmd_0 == 5'h2; // @[NBDcache.scala:150:7] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[NBDcache.scala:201:90] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[NBDcache.scala:201:{57,87,90}] wire _T = state == 4'h8; // @[NBDcache.scala:174:22, :203:49] wire _rpq_io_deq_ready_T; // @[NBDcache.scala:203:49] assign _rpq_io_deq_ready_T = _T; // @[NBDcache.scala:203:49] assign _io_meta_read_valid_T = _T; // @[NBDcache.scala:203:49, :305:31] wire _io_replay_valid_T; // @[NBDcache.scala:310:28] assign _io_replay_valid_T = _T; // @[NBDcache.scala:203:49, :310:28] wire _rpq_io_deq_ready_T_1 = io_replay_ready_0 & _rpq_io_deq_ready_T; // @[NBDcache.scala:150:7, :203:{40,49}] wire _rpq_io_deq_ready_T_2 = ~(\|state); // @[NBDcache.scala:174:22, :203:75] wire _rpq_io_deq_ready_T_3 = _rpq_io_deq_ready_T_1 \| _rpq_io_deq_ready_T_2; // @[NBDcache.scala:203:{40,66,75}] reg acked; // @[NBDcache.scala:205:18] wire _io_meta_write_valid_T = state == 4'h6; // @[package.scala:16:47] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_req_bits_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, io_req_bits_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire [3:0] _state_T = {2'h0, ~needs_wb, 1'h1}; // @[Misc.scala:38:9] wire _can_finish_T = ~(\|state); // @[package.scala:16:47] wire can_finish = _can_finish_T \| _can_finish_T_1; // @[package.scala:16:47, :81:59] wire _grantackq_io_enq_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantackq_io_enq_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantackq_io_enq_valid_T_2 = ~_grantackq_io_enq_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantackq_io_enq_valid_T_3 = _grantackq_io_enq_valid_T & _grantackq_io_enq_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire _grantackq_io_enq_valid_T_4 = refill_done & _grantackq_io_enq_valid_T_3; // @[Edges.scala:71:40, :233:22] assign _io_mem_finish_valid_T = _grantackq_io_deq_valid & can_finish; // @[package.scala:81:59] assign io_mem_finish_valid_0 = _io_mem_finish_valid_T; // @[NBDcache.scala:150:7, :267:49] wire _grantackq_io_deq_ready_T = io_mem_finish_ready_0 & can_finish; // @[package.scala:81:59] wire _io_idx_match_T = \|state; // @[NBDcache.scala:174:22, :203:75, :271:26] assign _io_idx_match_T_1 = _io_idx_match_T & idx_match; // @[NBDcache.scala:180:27, :271:{26,41}] assign io_idx_match_0 = _io_idx_match_T_1; // @[NBDcache.scala:150:7, :271:41] wire [39:0] _io_refill_addr_T = {req_block_addr[39:12], req_block_addr[11:0] \| refill_address_inc}; // @[Edges.scala:269:29] assign io_refill_addr_0 = _io_refill_addr_T[11:0]; // @[NBDcache.scala:150:7, :273:{18,36}] assign io_tag_0 = req_tag_0[19:0]; // @[NBDcache.scala:150:7, :178:26, :274:10] assign _io_req_pri_rdy_T = ~(\|state); // @[NBDcache.scala:174:22, :203:75, :275:27] assign io_req_pri_rdy_0 = _io_req_pri_rdy_T; // @[NBDcache.scala:150:7, :275:27] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[NBDcache.scala:195:27, :200:19, :276:29] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[NBDcache.scala:150:7, :276:29] reg [1:0] meta_hazard; // @[NBDcache.scala:278:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[NBDcache.scala:278:28, :279:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[NBDcache.scala:279:59] wire _io_probe_rdy_T = ~idx_match; // @[NBDcache.scala:180:27, :281:19] wire _io_probe_rdy_T_4 = _io_probe_rdy_T_1 \| _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = ~_io_probe_rdy_T_5; // @[package.scala:81:59] wire _io_probe_rdy_T_7 = meta_hazard == 2'h0; // @[NBDcache.scala:278:28, :281:86] wire _io_probe_rdy_T_8 = _io_probe_rdy_T_6 & _io_probe_rdy_T_7; // @[NBDcache.scala:281:{34,71,86}] assign _io_probe_rdy_T_9 = _io_probe_rdy_T \| _io_probe_rdy_T_8; // @[NBDcache.scala:281:{19,30,71}] assign io_probe_rdy_0 = _io_probe_rdy_T_9; // @[NBDcache.scala:150:7, :281:30] assign _io_meta_write_valid_T_2 = _io_meta_write_valid_T \| _io_meta_write_valid_T_1; // @[package.scala:16:47, :81:59] assign io_meta_write_valid_0 = _io_meta_write_valid_T_2; // @[package.scala:81:59] assign _io_meta_write_bits_data_coh_T_1_state = _io_meta_write_bits_data_coh_T ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] assign io_meta_write_bits_data_coh_state_0 = _io_meta_write_bits_data_coh_T_1_state; // @[NBDcache.scala:150:7, :286:37] assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[NBDcache.scala:150:7, :290:28] assign _io_mem_acquire_valid_T_1 = _io_mem_acquire_valid_T & _grantackq_io_enq_ready; // @[NBDcache.scala:263:25, :298:{33,50}] assign io_mem_acquire_valid_0 = _io_mem_acquire_valid_T_1; // @[NBDcache.scala:150:7, :298:50] wire [25:0] _GEN_29 = {io_tag_0, req_idx}; // @[NBDcache.scala:150:7, :177:25, :301:48] wire [25:0] _io_mem_acquire_bits_T; // @[NBDcache.scala:301:48] assign _io_mem_acquire_bits_T = _GEN_29; // @[NBDcache.scala:301:48] wire [25:0] io_replay_bits_addr_hi; // @[NBDcache.scala:313:29] assign io_replay_bits_addr_hi = _GEN_29; // @[NBDcache.scala:301:48, :313:29] wire [31:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[NBDcache.scala:179:51, :301:{48,66}] wire [31:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[NBDcache.scala:301:66] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1; // @[Edges.scala:346:17] wire [32:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[31:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[NBDcache.scala:301:66] wire [32:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[NBDcache.scala:301:66] wire [32:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 \| _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 \| _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [31:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[NBDcache.scala:301:66] wire [32:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_26 = _io_mem_acquire_bits_T_1 ^ 32'h80000000; // @[NBDcache.scala:301:66] wire [32:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 \| _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] assign io_meta_read_valid_0 = _io_meta_read_valid_T; // @[NBDcache.scala:150:7, :305:31] assign _io_replay_valid_T_1 = _io_replay_valid_T & _rpq_io_deq_valid; // @[NBDcache.scala:200:19, :310:{28,44}] assign io_replay_valid_0 = _io_replay_valid_T_1; // @[NBDcache.scala:150:7, :310:44] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[NBDcache.scala:200:19, :313:67] wire [31:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[NBDcache.scala:313:{29,67}] assign io_replay_bits_addr_0 = {8'h0, _io_replay_bits_addr_T_1}; // @[Edges.scala:232:25] assign io_replay_bits_cmd_0 = io_meta_read_ready_0 ? _rpq_io_deq_bits_cmd : 5'h5; // @[NBDcache.scala:150:7, :200:19, :311:18, :315:30, :317:24] wire _T_7 = _sec_rdy_T_6 & refill_done; // @[package.scala:16:47] wire _T_15 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[NBDcache.scala:150:7, :234:24] always @(posedge clock) begin // @[NBDcache.scala:150:7] if (reset) begin // @[NBDcache.scala:150:7] state <= 4'h0; // @[NBDcache.scala:174:22] new_coh_state <= 2'h0; // @[NBDcache.scala:182:24] r_counter <= 9'h0; // @[Edges.scala:229:27] meta_hazard <= 2'h0; // @[NBDcache.scala:278:28] end else begin // @[NBDcache.scala:150:7] if (_rpq_io_enq_valid_T) begin // @[NBDcache.scala:201:39] state <= io_req_bits_tag_match_0 ? {2'h1, is_hit, 1'h0} : _state_T; // @[Misc.scala:35:9] new_coh_state <= io_req_bits_tag_match_0 ? (is_hit ? coh_on_hit_state : io_req_bits_old_meta_coh_state_0) : 2'h0; // @[Misc.scala:35:9] end else begin // @[NBDcache.scala:201:39] if (io_wb_req_ready_0 & io_wb_req_valid_0) // @[Decoupled.scala:51:35] state <= 4'h2; // @[NBDcache.scala:174:22] else if (_T_11 & io_wb_req_ready_0 & acked) // @[package.scala:16:47] state <= 4'h3; // @[NBDcache.scala:174:22] else if (_T_9 & io_meta_write_ready_0) // @[package.scala:16:47] state <= 4'h4; // @[NBDcache.scala:174:22] else if (io_mem_acquire_ready_0 & io_mem_acquire_valid_0) // @[Decoupled.scala:51:35] state <= 4'h5; // @[NBDcache.scala:174:22] else if (_T_7) // @[NBDcache.scala:218:33] state <= 4'h6; // @[NBDcache.scala:174:22] else if (_io_meta_write_valid_T & io_meta_write_ready_0) // @[package.scala:16:47] state <= 4'h7; // @[NBDcache.scala:174:22] else if (state == 4'h7) // @[NBDcache.scala:174:22, :211:15] state <= 4'h8; // @[NBDcache.scala:174:22] else if (_T & ~_rpq_io_deq_valid) // @[NBDcache.scala:200:19, :203:49, :208:{31,34}] state <= 4'h0; // @[NBDcache.scala:174:22] if (_T_15 & is_hit_again) // @[Metadata.scala:105:27] new_coh_state <= dirtier_coh_state; // @[Metadata.scala:160:20] else if (_T_7) // @[NBDcache.scala:218:33] new_coh_state <= coh_on_grant_state; // @[Metadata.scala:160:20] end if (io_mem_grant_valid_0) // @[NBDcache.scala:150:7] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (io_meta_write_ready_0 & io_meta_write_valid_0) // @[Decoupled.scala:51:35] meta_hazard <= 2'h1; // @[NBDcache.scala:278:28] else if (\|meta_hazard) // @[NBDcache.scala:278:28, :279:21] meta_hazard <= _meta_hazard_T_1; // @[NBDcache.scala:278:28, :279:59] end if (_rpq_io_enq_valid_T) begin // @[NBDcache.scala:201:39] req_addr <= io_req_bits_addr_0; // @[NBDcache.scala:150:7, :176:16] req_tag <= io_req_bits_tag_0; // @[NBDcache.scala:150:7, :176:16] req_cmd <= io_req_bits_cmd_0; // @[NBDcache.scala:150:7, :176:16] req_size <= io_req_bits_size_0; // @[NBDcache.scala:150:7, :176:16] req_signed <= io_req_bits_signed_0; // @[NBDcache.scala:150:7, :176:16] req_dprv <= io_req_bits_dprv_0; // @[NBDcache.scala:150:7, :176:16] req_dv <= io_req_bits_dv_0; // @[NBDcache.scala:150:7, :176:16] req_phys <= io_req_bits_phys_0; // @[NBDcache.scala:150:7, :176:16] req_no_resp <= io_req_bits_no_resp_0; // @[NBDcache.scala:150:7, :176:16] req_no_alloc <= io_req_bits_no_alloc_0; // @[NBDcache.scala:150:7, :176:16] req_no_xcpt <= io_req_bits_no_xcpt_0; // @[NBDcache.scala:150:7, :176:16] req_sdq_id <= io_req_bits_sdq_id_0; // @[NBDcache.scala:150:7, :176:16] req_tag_match <= io_req_bits_tag_match_0; // @[NBDcache.scala:150:7, :176:16] req_old_meta_coh_state <= io_req_bits_old_meta_coh_state_0; // @[NBDcache.scala:150:7, :176:16] req_old_meta_tag <= io_req_bits_old_meta_tag_0; // @[NBDcache.scala:150:7, :176:16] req_way_en <= io_req_bits_way_en_0; // @[NBDcache.scala:150:7, :176:16] end else if (_T_15) // @[NBDcache.scala:234:24] req_cmd <= dirtier_cmd; // @[Metadata.scala:109:27] acked <= ~_rpq_io_enq_valid_T & (io_mem_grant_valid_0 \| acked); // @[NBDcache.scala:150:7, :201:39, :205:18, :206:{29,37}, :243:43, :245:11] always @(posedge) Queue16_ReplayInternal rpq ( // @[NBDcache.scala:200:19] .clock (clock), .reset (reset), .io_enq_ready (_rpq_io_enq_ready), .io_enq_valid (_rpq_io_enq_valid_T_7), // @[NBDcache.scala:201:87] .io_enq_bits_addr (io_req_bits_addr_0), // @[NBDcache.scala:150:7] .io_enq_bits_tag (io_req_bits_tag_0), // @[NBDcache.scala:150:7] .io_enq_bits_cmd (io_req_bits_cmd_0), // @[NBDcache.scala:150:7] .io_enq_bits_size (io_req_bits_size_0), // @[NBDcache.scala:150:7] .io_enq_bits_signed (io_req_bits_signed_0), // @[NBDcache.scala:150:7] .io_enq_bits_dprv (io_req_bits_dprv_0), // @[NBDcache.scala:150:7] .io_enq_bits_dv (io_req_bits_dv_0), // @[NBDcache.scala:150:7] .io_enq_bits_phys (io_req_bits_phys_0), // @[NBDcache.scala:150:7] .io_enq_bits_no_resp (io_req_bits_no_resp_0), // @[NBDcache.scala:150:7] .io_enq_bits_no_alloc (io_req_bits_no_alloc_0), // @[NBDcache.scala:150:7] .io_enq_bits_no_xcpt (io_req_bits_no_xcpt_0), // @[NBDcache.scala:150:7] .io_enq_bits_sdq_id (io_req_bits_sdq_id_0), // @[NBDcache.scala:150:7] .io_deq_ready (io_meta_read_ready_0 & _rpq_io_deq_ready_T_3), // @[NBDcache.scala:150:7, :203:{20,66}, :315:30, :316:22] .io_deq_valid (_rpq_io_deq_valid), .io_deq_bits_addr (_rpq_io_deq_bits_addr), .io_deq_bits_tag (io_replay_bits_tag_0), .io_deq_bits_cmd (_rpq_io_deq_bits_cmd), .io_deq_bits_size (io_replay_bits_size_0), .io_deq_bits_signed (io_replay_bits_signed_0), .io_deq_bits_dprv (io_replay_bits_dprv_0), .io_deq_bits_dv (io_replay_bits_dv_0), .io_deq_bits_no_resp (io_replay_bits_no_resp_0), .io_deq_bits_no_alloc (io_replay_bits_no_alloc_0), .io_deq_bits_no_xcpt (io_replay_bits_no_xcpt_0), .io_deq_bits_sdq_id (io_replay_bits_sdq_id_0) ); // @[NBDcache.scala:200:19] Queue1_TLBundleE_a32d64s2k3z4c grantackq ( // @[NBDcache.scala:263:25] .clock (clock), .reset (reset), .io_enq_ready (_grantackq_io_enq_ready), .io_enq_valid (_grantackq_io_enq_valid_T_4), // @[NBDcache.scala:265:41] .io_enq_bits_sink (grantackq_io_enq_bits_e_sink), // @[Edges.scala:451:17] .io_deq_ready (_grantackq_io_deq_ready_T), // @[NBDcache.scala:269:49] .io_deq_valid (_grantackq_io_deq_valid), .io_deq_bits_sink (io_mem_finish_bits_sink_0) ); // @[NBDcache.scala:263:25] assign io_req_pri_rdy = io_req_pri_rdy_0; // @[NBDcache.scala:150:7] assign io_req_sec_rdy = io_req_sec_rdy_0; // @[NBDcache.scala:150:7] assign io_idx_match = io_idx_match_0; // @[NBDcache.scala:150:7] assign io_tag = io_tag_0; // @[NBDcache.scala:150:7] assign io_mem_acquire_valid = io_mem_acquire_valid_0; // @[NBDcache.scala:150:7] assign io_mem_acquire_bits_param = io_mem_acquire_bits_param_0; // @[NBDcache.scala:150:7] assign io_mem_acquire_bits_address = io_mem_acquire_bits_address_0; // @[NBDcache.scala:150:7] assign io_mem_finish_valid = io_mem_finish_valid_0; // @[NBDcache.scala:150:7] assign io_mem_finish_bits_sink = io_mem_finish_bits_sink_0; // @[NBDcache.scala:150:7] assign io_refill_way_en = io_refill_way_en_0; // @[NBDcache.scala:150:7] assign io_refill_addr = io_refill_addr_0; // @[NBDcache.scala:150:7] assign io_meta_read_valid = io_meta_read_valid_0; // @[NBDcache.scala:150:7] assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[NBDcache.scala:150:7] assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[NBDcache.scala:150:7] assign io_meta_write_valid = io_meta_write_valid_0; // @[NBDcache.scala:150:7] assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[NBDcache.scala:150:7] assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[NBDcache.scala:150:7] assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[NBDcache.scala:150:7] assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[NBDcache.scala:150:7] assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[NBDcache.scala:150:7] assign io_replay_valid = io_replay_valid_0; // @[NBDcache.scala:150:7] assign io_replay_bits_addr = io_replay_bits_addr_0; // @[NBDcache.scala:150:7] assign io_replay_bits_tag = io_replay_bits_tag_0; // @[NBDcache.scala:150:7] assign io_replay_bits_cmd = io_replay_bits_cmd_0; // @[NBDcache.scala:150:7] assign io_replay_bits_size = io_replay_bits_size_0; // @[NBDcache.scala:150:7] assign io_replay_bits_signed = io_replay_bits_signed_0; // @[NBDcache.scala:150:7] assign io_replay_bits_dprv = io_replay_bits_dprv_0; // @[NBDcache.scala:150:7] assign io_replay_bits_dv = io_replay_bits_dv_0; // @[NBDcache.scala:150:7] assign io_replay_bits_no_resp = io_replay_bits_no_resp_0; // @[NBDcache.scala:150:7] assign io_replay_bits_no_alloc = io_replay_bits_no_alloc_0; // @[NBDcache.scala:150:7] assign io_replay_bits_no_xcpt = io_replay_bits_no_xcpt_0; // @[NBDcache.scala:150:7] assign io_replay_bits_sdq_id = io_replay_bits_sdq_id_0; // @[NBDcache.scala:150:7] assign io_wb_req_valid = io_wb_req_valid_0; // @[NBDcache.scala:150:7] assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[NBDcache.scala:150:7] assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[NBDcache.scala:150:7] assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[NBDcache.scala:150:7] assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[NBDcache.scala:150:7] assign io_probe_rdy = io_probe_rdy_0; // @[NBDcache.scala:150:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_23 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], _T_191, UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], _T_331, UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<17>(0h10000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<17>(0h10000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<17>(0h10000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<26>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_46 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<26>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_47 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<26>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1094 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1094; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1094; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_1162 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1162; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1027 = _T_1094 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1042 = _T_1162 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1138 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1138 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1120 = _T_1162 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1120 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1120 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1120 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a21d64s8k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleA_a21d64s8k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [20:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [20:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [7:0] saved_source; // @[Repeater.scala:21:18] reg [20:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid \| full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN \| full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18] saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_4 : input clock : Clock input reset : Reset output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<4>(0hf)) when _T : connect doing_reset, UInt<1>(0h0) reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0)) node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0) wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect f2_entry, entries[_f2_entry_T_1] node _T_1 = eq(io.update_idx, io.f2_req_idx) node _T_2 = and(io.update_repair, _T_1) when _T_2 : connect f2_entry.s_cnt, io.update_meta.s_cnt else : node _T_3 = eq(io.update_idx, io.f2_req_idx) node _T_4 = and(io.update_mispredict, _T_3) when _T_4 : connect f2_entry.s_cnt, UInt<1>(0h0) reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f3_entry, f2_entry reg f3_scnt_REG : UInt, clock connect f3_scnt_REG, io.f2_req_idx node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG) node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T) node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt) node _f3_tag_T = bits(io.f2_req_idx, 13, 4) reg f3_tag : UInt, clock connect f3_tag, _f3_tag_T connect io.f3_pred, io.f3_pred_in connect io.f3_meta.s_cnt, f3_scnt node _T_5 = eq(f3_entry.tag, f3_tag) when _T_5 : node _T_6 = eq(f3_scnt, f3_entry.p_cnt) node _T_7 = eq(f3_entry.conf, UInt<3>(0h7)) node _T_8 = and(_T_6, _T_7) when _T_8 : node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0)) connect io.f3_pred, _io_f3_pred_T reg f4_fire : UInt<1>, clock connect f4_fire, io.f3_req_fire reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f4_entry, f3_entry reg f4_tag : UInt, clock connect f4_tag, f3_tag reg f4_scnt : UInt, clock connect f4_scnt, f3_scnt reg f4_idx_REG : UInt, clock connect f4_idx_REG, io.f2_req_idx reg f4_idx : UInt, clock connect f4_idx, f4_idx_REG when f4_fire : node _T_9 = eq(f4_entry.tag, f4_tag) when _T_9 : node _T_10 = eq(f4_scnt, f4_entry.p_cnt) node _T_11 = eq(f4_entry.conf, UInt<3>(0h7)) node _T_12 = and(_T_10, _T_11) when _T_12 : node _T_13 = or(f4_idx, UInt<4>(0h0)) node _T_14 = bits(_T_13, 3, 0) connect entries[_T_14].age, UInt<3>(0h7) node _T_15 = or(f4_idx, UInt<4>(0h0)) node _T_16 = bits(_T_15, 3, 0) connect entries[_T_16].s_cnt, UInt<1>(0h0) else : node _T_17 = or(f4_idx, UInt<4>(0h0)) node _T_18 = bits(_T_17, 3, 0) node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1)) node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1) connect entries[_T_18].s_cnt, _entries_s_cnt_T_1 node _T_19 = or(f4_idx, UInt<4>(0h0)) node _T_20 = bits(_T_19, 3, 0) node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7)) node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1)) node _entries_age_T_2 = tail(_entries_age_T_1, 1) node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2) connect entries[_T_20].age, _entries_age_T_3 node _entry_T = or(io.update_idx, UInt<4>(0h0)) node _entry_T_1 = bits(_entry_T, 3, 0) node tag = bits(io.update_idx, 13, 4) node tag_match = eq(entries[_entry_T_1].tag, tag) node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt) wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect wentry, entries[_entry_T_1] node _T_21 = eq(doing_reset, UInt<1>(0h0)) node _T_22 = and(io.update_mispredict, _T_21) when _T_22 : node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_24 = and(_T_23, tag_match) when _T_24 : connect wentry.s_cnt, UInt<1>(0h0) node _wentry_conf_T = sub(entries[_entry_T_1].conf, UInt<1>(0h1)) node _wentry_conf_T_1 = tail(_wentry_conf_T, 1) connect wentry.conf, _wentry_conf_T_1 else : node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_26 = eq(tag_match, UInt<1>(0h0)) node _T_27 = and(_T_25, _T_26) when _T_27 : skip else : node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_29 = and(_T_28, tag_match) node _T_30 = and(_T_29, ctr_match) when _T_30 : node _wentry_conf_T_2 = add(entries[_entry_T_1].conf, UInt<1>(0h1)) node _wentry_conf_T_3 = tail(_wentry_conf_T_2, 1) connect wentry.conf, _wentry_conf_T_3 connect wentry.s_cnt, UInt<1>(0h0) else : node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_32 = and(_T_31, tag_match) node _T_33 = eq(ctr_match, UInt<1>(0h0)) node _T_34 = and(_T_32, _T_33) when _T_34 : connect wentry.conf, UInt<1>(0h0) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_36 = eq(tag_match, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) when _T_39 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_41 = eq(tag_match, UInt<1>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) when _T_44 : node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1)) node _wentry_age_T_1 = tail(_wentry_age_T, 1) connect wentry.age, _wentry_age_T_1 else : node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_46 = and(_T_45, tag_match) node _T_47 = and(_T_46, ctr_match) when _T_47 : connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_49 = and(_T_48, tag_match) node _T_50 = eq(ctr_match, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) when _T_51 : connect wentry.p_cnt, io.update_meta.s_cnt connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_53 = eq(tag_match, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) when _T_54 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt node _T_55 = or(io.update_idx, UInt<4>(0h0)) node _T_56 = bits(_T_55, 3, 0) connect entries[_T_56], wentry else : node _T_57 = eq(doing_reset, UInt<1>(0h0)) node _T_58 = and(io.update_repair, _T_57) when _T_58 : node _T_59 = eq(io.update_idx, f4_idx) node _T_60 = and(f4_fire, _T_59) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = and(tag_match, _T_61) when _T_62 : connect wentry.s_cnt, io.update_meta.s_cnt node _T_63 = or(io.update_idx, UInt<4>(0h0)) node _T_64 = bits(_T_63, 3, 0) connect entries[_T_64], wentry when doing_reset : wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect _entries_WIRE.s_cnt, UInt<10>(0h0) connect _entries_WIRE.p_cnt, UInt<10>(0h0) connect _entries_WIRE.age, UInt<3>(0h0) connect _entries_WIRE.conf, UInt<3>(0h0) connect _entries_WIRE.tag, UInt<10>(0h0) connect entries[reset_idx], _entries_WIRE	module LoopBranchPredictorColumn_4( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [35:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [35:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [35:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [35:0] f4_idx_REG; // @[loop.scala:92:35] reg [35:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire [3:0] _GEN_4 = {1'h0, _GEN_0[_entry_T_1]}; // @[loop.scala:66:28, :110:31, :119:36] wire [3:0] _wentry_conf_T = _GEN_4 - 4'h1; // @[loop.scala:119:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:119:36] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (\|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T_2 = _GEN_4 + 4'h1; // @[loop.scala:102:80, :119:36, :126:36] wire [2:0] _wentry_conf_T_3 = _wentry_conf_T_2[2:0]; // @[loop.scala:126:36] wire _T_34 = (\|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (\|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (\|_GEN_0[_entry_T_1]) & ~tag_match & (\|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_5 = _T_47 \| _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_6 = _T_30 \| _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 \| _T_24 \| _T_27 \| _GEN_6 \| ~(_T_39 \| ~(_T_44 \| _GEN_5 \| ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? _wentry_conf_T_1 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_3 : _T_34 ? 3'h0 : _T_39 \| ~(_T_44 \| ~(_T_47 \| ~(_T_51 \| ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:{22,36}, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_7 = _T_51 \| _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_8 = _T_34 \| _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| _GEN_8 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 \| _GEN_7 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| ~(_GEN_8 \| ~(_T_44 \| _T_47 \| ~_GEN_7)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 \| ~(_T_27 \| ~(_GEN_6 \| _T_39 \| ~(_T_44 \| ~(_GEN_5 \| _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_9 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_15 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, tail : UInt<1>}}[1]}, credit_alloc : { `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[3]}, switch_sel : { `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}} inst arbs_0 of SwitchArbiter_113 connect arbs_0.clock, clock connect arbs_0.reset, reset inst arbs_1 of SwitchArbiter_114 connect arbs_1.clock, clock connect arbs_1.reset, reset connect arbs_0.io.out[0].ready, UInt<1>(0h1) connect arbs_1.io.out[0].ready, UInt<1>(0h1) wire fires : UInt<1>[2] node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_0_valid_T_2 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_1) connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_2 connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid) connect fires[0], _fires_0_T node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid) connect fires[1], _fires_1_T node _io_req_0_0_ready_T = or(fires[0], fires[1]) connect io.req.`0`[0].ready, _io_req_0_0_ready_T wire fires_1 : UInt<1>[2] node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_1_valid_T_2 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_1) connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_2 connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid) connect fires_1[0], _fires_0_T_1 node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid) connect fires_1[1], _fires_1_T_1 node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1]) connect io.req.`1`[0].ready, _io_req_1_0_ready_T wire fires_2 : UInt<1>[2] node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_2_valid_T_2 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_1) connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_2 connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid) connect fires_2[0], _fires_0_T_2 node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid) connect fires_2[1], _fires_1_T_2 node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1]) connect io.req.`2`[0].ready, _io_req_2_0_ready_T node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0) node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T) node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2 node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1) node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T) node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2 node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2) node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T) node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2 node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0) node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T) node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2 node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1) node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T) node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2 node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2) node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T) node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2 connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0) connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0) connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0) node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0]) when _T : connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1]) when _T_1 : connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2]) when _T_2 : connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail node _T_3 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0]) when _T_3 : connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail	module SwitchAllocator_15( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_2_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_2_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_1_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_2_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_0_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [2:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:83:45] wire [2:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_0_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_0_0 \| io_req_0_0_bits_vc_sel_0_1 \| io_req_0_0_bits_vc_sel_0_2); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_0 \| io_req_1_0_bits_vc_sel_0_1 \| io_req_1_0_bits_vc_sel_0_2); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_0_0 \| io_req_2_0_bits_vc_sel_0_1 \| io_req_2_0_bits_vc_sel_0_2); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33] SwitchArbiter_112 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_0_io_in_0_ready), .io_in_0_valid (arbs_0_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_0_io_in_1_ready), .io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_in_2_ready (_arbs_0_io_in_2_ready), .io_in_2_valid (arbs_0_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_ready (1'h1), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_1_0 (/* unused /), .io_out_0_bits_vc_sel_0_0 (/ unused /), .io_out_0_bits_vc_sel_0_1 (_arbs_0_io_out_0_bits_vc_sel_0_1), .io_out_0_bits_vc_sel_0_2 (_arbs_0_io_out_0_bits_vc_sel_0_2), .io_out_0_bits_tail (/ unused /), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_112 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_1_io_in_1_ready), .io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_in_2_ready (_arbs_1_io_in_2_ready), .io_in_2_valid (arbs_1_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_ready (1'h1), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0), .io_out_0_bits_vc_sel_0_0 (/ unused /), .io_out_0_bits_vc_sel_0_1 (/ unused /), .io_out_0_bits_vc_sel_0_2 (/ unused */), .io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_2_0_ready = _arbs_0_io_in_2_ready & arbs_0_io_in_2_valid \| _arbs_1_io_in_2_ready & arbs_1_io_in_2_valid; // @[Decoupled.scala:51:35] assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid \| _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_0_io_in_0_ready & arbs_0_io_in_0_valid \| _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_0_1_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_2_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_1_0_2_0 = arbs_1_io_in_2_valid & _arbs_1_io_chosen_oh_0[2] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_2_0 = arbs_0_io_in_2_valid & _arbs_0_io_chosen_oh_0[2] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_0_0 = arbs_0_io_in_0_valid & _arbs_0_io_chosen_oh_0[0] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_72 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}} wire _in_flight_WIRE : UInt<1>[2] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_40 = and(_T_38, _T_39) node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_47 = and(_T_45, _T_46) node _T_48 = or(_T_12, _T_19) node _T_49 = or(_T_48, _T_26) node _T_50 = or(_T_49, _T_33) node _T_51 = or(_T_50, _T_40) node _T_52 = or(_T_51, _T_47) node _T_53 = or(_T_5, _T_52) node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : node _T_56 = eq(_T_53, UInt<1>(0h0)) when _T_56 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_53, UInt<1>(0h1), "") : assert_1 node _T_57 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_71 = and(_T_69, _T_70) node _T_72 = or(_T_64, _T_71) node _T_73 = or(_T_57, _T_72) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_73, UInt<1>(0h1), "") : assert_2	module NoCMonitor_72( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_91 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_179 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_91( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_179 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_34 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} inst input_buffer of InputBuffer_34 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) inst route_arbiter of Arbiter8_RouteComputerReq_34 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h15)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_9 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_9 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_10 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_11 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_12 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_13 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_14 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_15 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_16 : connect states[7].g, UInt<3>(0h2) node _T_17 = and(io.router_req.ready, io.router_req.valid) when _T_17 : node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_18, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_22 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_23 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_24 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_25 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_26 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_27 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_28 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_29 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.router_resp.vc_sel.`4` regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] wire vcalloc_vals : UInt<1>[8] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_30 = and(io.router_req.ready, io.router_req.valid) when _T_30 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_31 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_32 = or(_T_31, vcalloc_vals[2]) node _T_33 = or(_T_32, vcalloc_vals[3]) node _T_34 = or(_T_33, vcalloc_vals[4]) node _T_35 = or(_T_34, vcalloc_vals[5]) node _T_36 = or(_T_35, vcalloc_vals[6]) node _T_37 = or(_T_36, vcalloc_vals[7]) when _T_37 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = bits(vcalloc_sel, 0, 0) node _mask_T_12 = bits(vcalloc_sel, 1, 1) node _mask_T_13 = bits(vcalloc_sel, 2, 2) node _mask_T_14 = bits(vcalloc_sel, 3, 3) node _mask_T_15 = bits(vcalloc_sel, 4, 4) node _mask_T_16 = bits(vcalloc_sel, 5, 5) node _mask_T_17 = bits(vcalloc_sel, 6, 6) node _mask_T_18 = bits(vcalloc_sel, 7, 7) node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) node _mask_T_27 = or(_mask_T_19, _mask_T_20) node _mask_T_28 = or(_mask_T_27, _mask_T_21) node _mask_T_29 = or(_mask_T_28, _mask_T_22) node _mask_T_30 = or(_mask_T_29, _mask_T_23) node _mask_T_31 = or(_mask_T_30, _mask_T_24) node _mask_T_32 = or(_mask_T_31, _mask_T_25) node _mask_T_33 = or(_mask_T_32, _mask_T_26) wire _mask_WIRE : UInt<8> connect _mask_WIRE, _mask_T_33 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} wire _io_vcalloc_req_bits_WIRE_1 : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8] node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382 connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34 node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) wire _io_vcalloc_req_bits_WIRE_35 : UInt<1> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35 node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459) node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460) node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461) node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462) node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463) node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464) node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465) wire _io_vcalloc_req_bits_WIRE_36 : UInt<1> connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472 connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36 node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477) node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478) node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479) node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480) wire _io_vcalloc_req_bits_WIRE_37 : UInt<1> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487 connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29 wire _io_vcalloc_req_bits_WIRE_38 : UInt<1>[8] node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495) wire _io_vcalloc_req_bits_WIRE_39 : UInt<1> connect _io_vcalloc_req_bits_WIRE_39, _io_vcalloc_req_bits_T_502 connect _io_vcalloc_req_bits_WIRE_38[0], _io_vcalloc_req_bits_WIRE_39 node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504) node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510) wire _io_vcalloc_req_bits_WIRE_40 : UInt<1> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517 connect _io_vcalloc_req_bits_WIRE_38[1], _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519) node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520) node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521) node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522) node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523) node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525) wire _io_vcalloc_req_bits_WIRE_41 : UInt<1> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532 connect _io_vcalloc_req_bits_WIRE_38[2], _io_vcalloc_req_bits_WIRE_41 node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534) node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535) node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536) node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537) node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538) node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539) node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540) wire _io_vcalloc_req_bits_WIRE_42 : UInt<1> connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547 connect _io_vcalloc_req_bits_WIRE_38[3], _io_vcalloc_req_bits_WIRE_42 node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553) node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554) node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555) wire _io_vcalloc_req_bits_WIRE_43 : UInt<1> connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562 connect _io_vcalloc_req_bits_WIRE_38[4], _io_vcalloc_req_bits_WIRE_43 node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_44 : UInt<1> connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577 connect _io_vcalloc_req_bits_WIRE_38[5], _io_vcalloc_req_bits_WIRE_44 node _io_vcalloc_req_bits_T_578 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_579 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_580 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_581 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_582 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_583 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_584 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_585 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_586 = or(_io_vcalloc_req_bits_T_578, _io_vcalloc_req_bits_T_579) node _io_vcalloc_req_bits_T_587 = or(_io_vcalloc_req_bits_T_586, _io_vcalloc_req_bits_T_580) node _io_vcalloc_req_bits_T_588 = or(_io_vcalloc_req_bits_T_587, _io_vcalloc_req_bits_T_581) node _io_vcalloc_req_bits_T_589 = or(_io_vcalloc_req_bits_T_588, _io_vcalloc_req_bits_T_582) node _io_vcalloc_req_bits_T_590 = or(_io_vcalloc_req_bits_T_589, _io_vcalloc_req_bits_T_583) node _io_vcalloc_req_bits_T_591 = or(_io_vcalloc_req_bits_T_590, _io_vcalloc_req_bits_T_584) node _io_vcalloc_req_bits_T_592 = or(_io_vcalloc_req_bits_T_591, _io_vcalloc_req_bits_T_585) wire _io_vcalloc_req_bits_WIRE_45 : UInt<1> connect _io_vcalloc_req_bits_WIRE_45, _io_vcalloc_req_bits_T_592 connect _io_vcalloc_req_bits_WIRE_38[6], _io_vcalloc_req_bits_WIRE_45 node _io_vcalloc_req_bits_T_593 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_594 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_595 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_596 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_597 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_598 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_599 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_600 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_601 = or(_io_vcalloc_req_bits_T_593, _io_vcalloc_req_bits_T_594) node _io_vcalloc_req_bits_T_602 = or(_io_vcalloc_req_bits_T_601, _io_vcalloc_req_bits_T_595) node _io_vcalloc_req_bits_T_603 = or(_io_vcalloc_req_bits_T_602, _io_vcalloc_req_bits_T_596) node _io_vcalloc_req_bits_T_604 = or(_io_vcalloc_req_bits_T_603, _io_vcalloc_req_bits_T_597) node _io_vcalloc_req_bits_T_605 = or(_io_vcalloc_req_bits_T_604, _io_vcalloc_req_bits_T_598) node _io_vcalloc_req_bits_T_606 = or(_io_vcalloc_req_bits_T_605, _io_vcalloc_req_bits_T_599) node _io_vcalloc_req_bits_T_607 = or(_io_vcalloc_req_bits_T_606, _io_vcalloc_req_bits_T_600) wire _io_vcalloc_req_bits_WIRE_46 : UInt<1> connect _io_vcalloc_req_bits_WIRE_46, _io_vcalloc_req_bits_T_607 connect _io_vcalloc_req_bits_WIRE_38[7], _io_vcalloc_req_bits_WIRE_46 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_38 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_608 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_609 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_610 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_611 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_612 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_613 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_614 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_615 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_616 = or(_io_vcalloc_req_bits_T_608, _io_vcalloc_req_bits_T_609) node _io_vcalloc_req_bits_T_617 = or(_io_vcalloc_req_bits_T_616, _io_vcalloc_req_bits_T_610) node _io_vcalloc_req_bits_T_618 = or(_io_vcalloc_req_bits_T_617, _io_vcalloc_req_bits_T_611) node _io_vcalloc_req_bits_T_619 = or(_io_vcalloc_req_bits_T_618, _io_vcalloc_req_bits_T_612) node _io_vcalloc_req_bits_T_620 = or(_io_vcalloc_req_bits_T_619, _io_vcalloc_req_bits_T_613) node _io_vcalloc_req_bits_T_621 = or(_io_vcalloc_req_bits_T_620, _io_vcalloc_req_bits_T_614) node _io_vcalloc_req_bits_T_622 = or(_io_vcalloc_req_bits_T_621, _io_vcalloc_req_bits_T_615) wire _io_vcalloc_req_bits_WIRE_47 : UInt<3> connect _io_vcalloc_req_bits_WIRE_47, _io_vcalloc_req_bits_T_622 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_47 wire _io_vcalloc_req_bits_WIRE_48 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_623 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_624 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_625 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_626 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_627 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_628 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_629 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_630 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_631 = or(_io_vcalloc_req_bits_T_623, _io_vcalloc_req_bits_T_624) node _io_vcalloc_req_bits_T_632 = or(_io_vcalloc_req_bits_T_631, _io_vcalloc_req_bits_T_625) node _io_vcalloc_req_bits_T_633 = or(_io_vcalloc_req_bits_T_632, _io_vcalloc_req_bits_T_626) node _io_vcalloc_req_bits_T_634 = or(_io_vcalloc_req_bits_T_633, _io_vcalloc_req_bits_T_627) node _io_vcalloc_req_bits_T_635 = or(_io_vcalloc_req_bits_T_634, _io_vcalloc_req_bits_T_628) node _io_vcalloc_req_bits_T_636 = or(_io_vcalloc_req_bits_T_635, _io_vcalloc_req_bits_T_629) node _io_vcalloc_req_bits_T_637 = or(_io_vcalloc_req_bits_T_636, _io_vcalloc_req_bits_T_630) wire _io_vcalloc_req_bits_WIRE_49 : UInt<2> connect _io_vcalloc_req_bits_WIRE_49, _io_vcalloc_req_bits_T_637 connect _io_vcalloc_req_bits_WIRE_48.egress_node_id, _io_vcalloc_req_bits_WIRE_49 node _io_vcalloc_req_bits_T_638 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_639 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_640 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_641 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_642 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_643 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_644 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_645 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_646 = or(_io_vcalloc_req_bits_T_638, _io_vcalloc_req_bits_T_639) node _io_vcalloc_req_bits_T_647 = or(_io_vcalloc_req_bits_T_646, _io_vcalloc_req_bits_T_640) node _io_vcalloc_req_bits_T_648 = or(_io_vcalloc_req_bits_T_647, _io_vcalloc_req_bits_T_641) node _io_vcalloc_req_bits_T_649 = or(_io_vcalloc_req_bits_T_648, _io_vcalloc_req_bits_T_642) node _io_vcalloc_req_bits_T_650 = or(_io_vcalloc_req_bits_T_649, _io_vcalloc_req_bits_T_643) node _io_vcalloc_req_bits_T_651 = or(_io_vcalloc_req_bits_T_650, _io_vcalloc_req_bits_T_644) node _io_vcalloc_req_bits_T_652 = or(_io_vcalloc_req_bits_T_651, _io_vcalloc_req_bits_T_645) wire _io_vcalloc_req_bits_WIRE_50 : UInt<5> connect _io_vcalloc_req_bits_WIRE_50, _io_vcalloc_req_bits_T_652 connect _io_vcalloc_req_bits_WIRE_48.egress_node, _io_vcalloc_req_bits_WIRE_50 node _io_vcalloc_req_bits_T_653 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_654 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_655 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_656 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_657 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_658 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_659 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_660 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_661 = or(_io_vcalloc_req_bits_T_653, _io_vcalloc_req_bits_T_654) node _io_vcalloc_req_bits_T_662 = or(_io_vcalloc_req_bits_T_661, _io_vcalloc_req_bits_T_655) node _io_vcalloc_req_bits_T_663 = or(_io_vcalloc_req_bits_T_662, _io_vcalloc_req_bits_T_656) node _io_vcalloc_req_bits_T_664 = or(_io_vcalloc_req_bits_T_663, _io_vcalloc_req_bits_T_657) node _io_vcalloc_req_bits_T_665 = or(_io_vcalloc_req_bits_T_664, _io_vcalloc_req_bits_T_658) node _io_vcalloc_req_bits_T_666 = or(_io_vcalloc_req_bits_T_665, _io_vcalloc_req_bits_T_659) node _io_vcalloc_req_bits_T_667 = or(_io_vcalloc_req_bits_T_666, _io_vcalloc_req_bits_T_660) wire _io_vcalloc_req_bits_WIRE_51 : UInt<2> connect _io_vcalloc_req_bits_WIRE_51, _io_vcalloc_req_bits_T_667 connect _io_vcalloc_req_bits_WIRE_48.ingress_node_id, _io_vcalloc_req_bits_WIRE_51 node _io_vcalloc_req_bits_T_668 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_669 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_670 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_671 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_672 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_673 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_674 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_675 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_676 = or(_io_vcalloc_req_bits_T_668, _io_vcalloc_req_bits_T_669) node _io_vcalloc_req_bits_T_677 = or(_io_vcalloc_req_bits_T_676, _io_vcalloc_req_bits_T_670) node _io_vcalloc_req_bits_T_678 = or(_io_vcalloc_req_bits_T_677, _io_vcalloc_req_bits_T_671) node _io_vcalloc_req_bits_T_679 = or(_io_vcalloc_req_bits_T_678, _io_vcalloc_req_bits_T_672) node _io_vcalloc_req_bits_T_680 = or(_io_vcalloc_req_bits_T_679, _io_vcalloc_req_bits_T_673) node _io_vcalloc_req_bits_T_681 = or(_io_vcalloc_req_bits_T_680, _io_vcalloc_req_bits_T_674) node _io_vcalloc_req_bits_T_682 = or(_io_vcalloc_req_bits_T_681, _io_vcalloc_req_bits_T_675) wire _io_vcalloc_req_bits_WIRE_52 : UInt<5> connect _io_vcalloc_req_bits_WIRE_52, _io_vcalloc_req_bits_T_682 connect _io_vcalloc_req_bits_WIRE_48.ingress_node, _io_vcalloc_req_bits_WIRE_52 node _io_vcalloc_req_bits_T_683 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_684 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_685 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_686 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_687 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_688 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_689 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_690 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_691 = or(_io_vcalloc_req_bits_T_683, _io_vcalloc_req_bits_T_684) node _io_vcalloc_req_bits_T_692 = or(_io_vcalloc_req_bits_T_691, _io_vcalloc_req_bits_T_685) node _io_vcalloc_req_bits_T_693 = or(_io_vcalloc_req_bits_T_692, _io_vcalloc_req_bits_T_686) node _io_vcalloc_req_bits_T_694 = or(_io_vcalloc_req_bits_T_693, _io_vcalloc_req_bits_T_687) node _io_vcalloc_req_bits_T_695 = or(_io_vcalloc_req_bits_T_694, _io_vcalloc_req_bits_T_688) node _io_vcalloc_req_bits_T_696 = or(_io_vcalloc_req_bits_T_695, _io_vcalloc_req_bits_T_689) node _io_vcalloc_req_bits_T_697 = or(_io_vcalloc_req_bits_T_696, _io_vcalloc_req_bits_T_690) wire _io_vcalloc_req_bits_WIRE_53 : UInt<3> connect _io_vcalloc_req_bits_WIRE_53, _io_vcalloc_req_bits_T_697 connect _io_vcalloc_req_bits_WIRE_48.vnet_id, _io_vcalloc_req_bits_WIRE_53 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_48 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4` connect vcalloc_reqs[0].flow, states[0].flow node _T_38 = bits(vcalloc_sel, 0, 0) node _T_39 = and(vcalloc_vals[0], _T_38) node _T_40 = and(_T_39, io.vcalloc_req.ready) when _T_40 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].flow, states[1].flow node _T_41 = bits(vcalloc_sel, 1, 1) node _T_42 = and(vcalloc_vals[1], _T_41) node _T_43 = and(_T_42, io.vcalloc_req.ready) when _T_43 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].flow, states[2].flow node _T_44 = bits(vcalloc_sel, 2, 2) node _T_45 = and(vcalloc_vals[2], _T_44) node _T_46 = and(_T_45, io.vcalloc_req.ready) when _T_46 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].vc_sel.`4`, states[3].vc_sel.`4` connect vcalloc_reqs[3].flow, states[3].flow node _T_47 = bits(vcalloc_sel, 3, 3) node _T_48 = and(vcalloc_vals[3], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].vc_sel.`4`, states[4].vc_sel.`4` connect vcalloc_reqs[4].flow, states[4].flow node _T_50 = bits(vcalloc_sel, 4, 4) node _T_51 = and(vcalloc_vals[4], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].vc_sel.`4`, states[5].vc_sel.`4` connect vcalloc_reqs[5].flow, states[5].flow node _T_53 = bits(vcalloc_sel, 5, 5) node _T_54 = and(vcalloc_vals[5], _T_53) node _T_55 = and(_T_54, io.vcalloc_req.ready) when _T_55 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3` connect vcalloc_reqs[6].vc_sel.`4`, states[6].vc_sel.`4` connect vcalloc_reqs[6].flow, states[6].flow node _T_56 = bits(vcalloc_sel, 6, 6) node _T_57 = and(vcalloc_vals[6], _T_56) node _T_58 = and(_T_57, io.vcalloc_req.ready) when _T_58 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` connect vcalloc_reqs[7].vc_sel.`4`, states[7].vc_sel.`4` connect vcalloc_reqs[7].flow, states[7].flow node _T_59 = bits(vcalloc_sel, 7, 7) node _T_60 = and(vcalloc_vals[7], _T_59) node _T_61 = and(_T_60, io.vcalloc_req.ready) when _T_61 : connect states[7].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) connect io.debug.va_stall, _io_debug_va_stall_T_15 node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_62 : node _T_63 = bits(vcalloc_sel, 0, 0) when _T_63 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].g, UInt<3>(0h3) node _T_64 = eq(states[0].g, UInt<3>(0h2)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_64, UInt<1>(0h1), "") : assert_3 node _T_68 = bits(vcalloc_sel, 1, 1) when _T_68 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].g, UInt<3>(0h3) node _T_69 = eq(states[1].g, UInt<3>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_69, UInt<1>(0h1), "") : assert_4 node _T_73 = bits(vcalloc_sel, 2, 2) when _T_73 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].g, UInt<3>(0h3) node _T_74 = eq(states[2].g, UInt<3>(0h2)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_74, UInt<1>(0h1), "") : assert_5 node _T_78 = bits(vcalloc_sel, 3, 3) when _T_78 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[3].g, UInt<3>(0h3) node _T_79 = eq(states[3].g, UInt<3>(0h2)) node _T_80 = asUInt(reset) node _T_81 = eq(_T_80, UInt<1>(0h0)) when _T_81 : node _T_82 = eq(_T_79, UInt<1>(0h0)) when _T_82 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_79, UInt<1>(0h1), "") : assert_6 node _T_83 = bits(vcalloc_sel, 4, 4) when _T_83 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[4].g, UInt<3>(0h3) node _T_84 = eq(states[4].g, UInt<3>(0h2)) node _T_85 = asUInt(reset) node _T_86 = eq(_T_85, UInt<1>(0h0)) when _T_86 : node _T_87 = eq(_T_84, UInt<1>(0h0)) when _T_87 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_84, UInt<1>(0h1), "") : assert_7 node _T_88 = bits(vcalloc_sel, 5, 5) when _T_88 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[5].g, UInt<3>(0h3) node _T_89 = eq(states[5].g, UInt<3>(0h2)) node _T_90 = asUInt(reset) node _T_91 = eq(_T_90, UInt<1>(0h0)) when _T_91 : node _T_92 = eq(_T_89, UInt<1>(0h0)) when _T_92 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_89, UInt<1>(0h1), "") : assert_8 node _T_93 = bits(vcalloc_sel, 6, 6) when _T_93 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[6].g, UInt<3>(0h3) node _T_94 = eq(states[6].g, UInt<3>(0h2)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = bits(vcalloc_sel, 7, 7) when _T_98 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[7].g, UInt<3>(0h3) node _T_99 = eq(states[7].g, UInt<3>(0h2)) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 inst salloc_arb of SwitchArbiter_99 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0]) node credit_available_lo_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4]) node credit_available_hi_hi = cat(states[0].vc_sel.`0`[7], states[0].vc_sel.`0`[6]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0]) node credit_available_lo_hi_1 = cat(states[0].vc_sel.`1`[3], states[0].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[0].vc_sel.`1`[5], states[0].vc_sel.`1`[4]) node credit_available_hi_hi_1 = cat(states[0].vc_sel.`1`[7], states[0].vc_sel.`1`[6]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0]) node credit_available_lo_hi_2 = cat(states[0].vc_sel.`2`[3], states[0].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[0].vc_sel.`2`[5], states[0].vc_sel.`2`[4]) node credit_available_hi_hi_2 = cat(states[0].vc_sel.`2`[7], states[0].vc_sel.`2`[6]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_lo_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0]) node credit_available_lo_hi_3 = cat(states[0].vc_sel.`3`[3], states[0].vc_sel.`3`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(states[0].vc_sel.`3`[5], states[0].vc_sel.`3`[4]) node credit_available_hi_hi_3 = cat(states[0].vc_sel.`3`[7], states[0].vc_sel.`3`[6]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node credit_available_lo_lo_4 = cat(states[0].vc_sel.`4`[1], states[0].vc_sel.`4`[0]) node credit_available_lo_hi_4 = cat(states[0].vc_sel.`4`[3], states[0].vc_sel.`4`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(states[0].vc_sel.`4`[5], states[0].vc_sel.`4`[4]) node credit_available_hi_hi_4 = cat(states[0].vc_sel.`4`[7], states[0].vc_sel.`4`[6]) node credit_available_hi_4 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_5 = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_hi_5 = cat(_credit_available_T_4, _credit_available_T_3) node credit_available_hi_5 = cat(credit_available_hi_hi_5, _credit_available_T_2) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_6 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_6 = cat(credit_available_hi_hi_6, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_lo_6 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_6 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_7 = cat(credit_available_hi_hi_7, credit_available_hi_lo_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7) node credit_available_lo_lo_7 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_7 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_8 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_8 = cat(credit_available_hi_hi_8, credit_available_hi_lo_7) node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_lo_8 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_8 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_9 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_9 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_9 = cat(credit_available_hi_hi_9, credit_available_hi_lo_8) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9) node credit_available_lo_lo_9 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_9 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_10 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_10 = cat(credit_available_hi_hi_10, credit_available_hi_lo_9) node _credit_available_T_10 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_11 = cat(_credit_available_T_7, _credit_available_T_6) node credit_available_hi_hi_11 = cat(_credit_available_T_10, _credit_available_T_9) node credit_available_hi_11 = cat(credit_available_hi_hi_11, _credit_available_T_8) node _credit_available_T_11 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_12 = and(_credit_available_T_5, _credit_available_T_11) node credit_available = neq(_credit_available_T_12, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6] connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] connect salloc_arb.io.in[0].bits.vc_sel.`1`[3], states[0].vc_sel.`1`[3] connect salloc_arb.io.in[0].bits.vc_sel.`1`[4], states[0].vc_sel.`1`[4] connect salloc_arb.io.in[0].bits.vc_sel.`1`[5], states[0].vc_sel.`1`[5] connect salloc_arb.io.in[0].bits.vc_sel.`1`[6], states[0].vc_sel.`1`[6] connect salloc_arb.io.in[0].bits.vc_sel.`1`[7], states[0].vc_sel.`1`[7] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2] connect salloc_arb.io.in[0].bits.vc_sel.`2`[3], states[0].vc_sel.`2`[3] connect salloc_arb.io.in[0].bits.vc_sel.`2`[4], states[0].vc_sel.`2`[4] connect salloc_arb.io.in[0].bits.vc_sel.`2`[5], states[0].vc_sel.`2`[5] connect salloc_arb.io.in[0].bits.vc_sel.`2`[6], states[0].vc_sel.`2`[6] connect salloc_arb.io.in[0].bits.vc_sel.`2`[7], states[0].vc_sel.`2`[7] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1] connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2] connect salloc_arb.io.in[0].bits.vc_sel.`3`[3], states[0].vc_sel.`3`[3] connect salloc_arb.io.in[0].bits.vc_sel.`3`[4], states[0].vc_sel.`3`[4] connect salloc_arb.io.in[0].bits.vc_sel.`3`[5], states[0].vc_sel.`3`[5] connect salloc_arb.io.in[0].bits.vc_sel.`3`[6], states[0].vc_sel.`3`[6] connect salloc_arb.io.in[0].bits.vc_sel.`3`[7], states[0].vc_sel.`3`[7] connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0] connect salloc_arb.io.in[0].bits.vc_sel.`4`[1], states[0].vc_sel.`4`[1] connect salloc_arb.io.in[0].bits.vc_sel.`4`[2], states[0].vc_sel.`4`[2] connect salloc_arb.io.in[0].bits.vc_sel.`4`[3], states[0].vc_sel.`4`[3] connect salloc_arb.io.in[0].bits.vc_sel.`4`[4], states[0].vc_sel.`4`[4] connect salloc_arb.io.in[0].bits.vc_sel.`4`[5], states[0].vc_sel.`4`[5] connect salloc_arb.io.in[0].bits.vc_sel.`4`[6], states[0].vc_sel.`4`[6] connect salloc_arb.io.in[0].bits.vc_sel.`4`[7], states[0].vc_sel.`4`[7] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_103 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_104 = and(_T_103, input_buffer.io.deq[0].bits.tail) when _T_104 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_lo_10 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi_10 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_hi_12 = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) node credit_available_hi_12 = cat(credit_available_hi_hi_12, credit_available_hi_lo_10) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_lo_11 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_lo_hi_11 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) node credit_available_hi_hi_13 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) node credit_available_hi_13 = cat(credit_available_hi_hi_13, credit_available_hi_lo_11) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_lo_12 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo_hi_12 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) node credit_available_hi_hi_14 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) node credit_available_hi_14 = cat(credit_available_hi_hi_14, credit_available_hi_lo_12) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_lo_13 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) node credit_available_lo_hi_13 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4]) node credit_available_hi_hi_15 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6]) node credit_available_hi_15 = cat(credit_available_hi_hi_15, credit_available_hi_lo_13) node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15) node credit_available_lo_lo_14 = cat(states[1].vc_sel.`4`[1], states[1].vc_sel.`4`[0]) node credit_available_lo_hi_14 = cat(states[1].vc_sel.`4`[3], states[1].vc_sel.`4`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[1].vc_sel.`4`[5], states[1].vc_sel.`4`[4]) node credit_available_hi_hi_16 = cat(states[1].vc_sel.`4`[7], states[1].vc_sel.`4`[6]) node credit_available_hi_16 = cat(credit_available_hi_hi_16, credit_available_hi_lo_14) node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_17 = cat(_credit_available_T_14, _credit_available_T_13) node credit_available_hi_hi_17 = cat(_credit_available_T_17, _credit_available_T_16) node credit_available_hi_17 = cat(credit_available_hi_hi_17, _credit_available_T_15) node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_15 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_18 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_18 = cat(credit_available_hi_hi_18, credit_available_hi_lo_15) node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_16 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_19 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_19 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_19 = cat(credit_available_hi_hi_19, credit_available_hi_lo_16) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19) node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_17 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_20 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_20 = cat(credit_available_hi_hi_20, credit_available_hi_lo_17) node _credit_available_T_21 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_lo_18 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_18 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_21 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_21 = cat(credit_available_hi_hi_21, credit_available_hi_lo_18) node _credit_available_T_22 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_19 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_19 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_22 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_22 = cat(credit_available_hi_hi_22, credit_available_hi_lo_19) node _credit_available_T_23 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_23 = cat(_credit_available_T_20, _credit_available_T_19) node credit_available_hi_hi_23 = cat(_credit_available_T_23, _credit_available_T_22) node credit_available_hi_23 = cat(credit_available_hi_hi_23, _credit_available_T_21) node _credit_available_T_24 = cat(credit_available_hi_23, credit_available_lo_23) node _credit_available_T_25 = and(_credit_available_T_18, _credit_available_T_24) node credit_available_1 = neq(_credit_available_T_25, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3] connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4] connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5] connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6] connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.vc_sel.`4`[1], states[1].vc_sel.`4`[1] connect salloc_arb.io.in[1].bits.vc_sel.`4`[2], states[1].vc_sel.`4`[2] connect salloc_arb.io.in[1].bits.vc_sel.`4`[3], states[1].vc_sel.`4`[3] connect salloc_arb.io.in[1].bits.vc_sel.`4`[4], states[1].vc_sel.`4`[4] connect salloc_arb.io.in[1].bits.vc_sel.`4`[5], states[1].vc_sel.`4`[5] connect salloc_arb.io.in[1].bits.vc_sel.`4`[6], states[1].vc_sel.`4`[6] connect salloc_arb.io.in[1].bits.vc_sel.`4`[7], states[1].vc_sel.`4`[7] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_105 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_106 = and(_T_105, input_buffer.io.deq[1].bits.tail) when _T_106 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_20 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_20 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_hi_24 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) node credit_available_hi_24 = cat(credit_available_hi_hi_24, credit_available_hi_lo_20) node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_lo_21 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_21 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) node credit_available_hi_hi_25 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) node credit_available_hi_25 = cat(credit_available_hi_hi_25, credit_available_hi_lo_21) node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_22 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_22 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) node credit_available_hi_hi_26 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) node credit_available_hi_26 = cat(credit_available_hi_hi_26, credit_available_hi_lo_22) node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_lo_23 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0]) node credit_available_lo_hi_23 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4]) node credit_available_hi_hi_27 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6]) node credit_available_hi_27 = cat(credit_available_hi_hi_27, credit_available_hi_lo_23) node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27) node credit_available_lo_lo_24 = cat(states[2].vc_sel.`4`[1], states[2].vc_sel.`4`[0]) node credit_available_lo_hi_24 = cat(states[2].vc_sel.`4`[3], states[2].vc_sel.`4`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[2].vc_sel.`4`[5], states[2].vc_sel.`4`[4]) node credit_available_hi_hi_28 = cat(states[2].vc_sel.`4`[7], states[2].vc_sel.`4`[6]) node credit_available_hi_28 = cat(credit_available_hi_hi_28, credit_available_hi_lo_24) node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_29 = cat(_credit_available_T_27, _credit_available_T_26) node credit_available_hi_hi_29 = cat(_credit_available_T_30, _credit_available_T_29) node credit_available_hi_29 = cat(credit_available_hi_hi_29, _credit_available_T_28) node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29) node credit_available_lo_lo_25 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_25 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_30 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_30 = cat(credit_available_hi_hi_30, credit_available_hi_lo_25) node _credit_available_T_32 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_lo_26 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_26 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_31 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_31 = cat(credit_available_hi_hi_31, credit_available_hi_lo_26) node _credit_available_T_33 = cat(credit_available_hi_31, credit_available_lo_31) node credit_available_lo_lo_27 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_27 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_32 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_32 = cat(credit_available_hi_hi_32, credit_available_hi_lo_27) node _credit_available_T_34 = cat(credit_available_hi_32, credit_available_lo_32) node credit_available_lo_lo_28 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_28 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_33 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_33 = cat(credit_available_hi_hi_33, credit_available_hi_lo_28) node _credit_available_T_35 = cat(credit_available_hi_33, credit_available_lo_33) node credit_available_lo_lo_29 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_29 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_34 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_34 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_34 = cat(credit_available_hi_hi_34, credit_available_hi_lo_29) node _credit_available_T_36 = cat(credit_available_hi_34, credit_available_lo_34) node credit_available_lo_35 = cat(_credit_available_T_33, _credit_available_T_32) node credit_available_hi_hi_35 = cat(_credit_available_T_36, _credit_available_T_35) node credit_available_hi_35 = cat(credit_available_hi_hi_35, _credit_available_T_34) node _credit_available_T_37 = cat(credit_available_hi_35, credit_available_lo_35) node _credit_available_T_38 = and(_credit_available_T_31, _credit_available_T_37) node credit_available_2 = neq(_credit_available_T_38, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3] connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4] connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5] connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6] connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`4`[1], states[2].vc_sel.`4`[1] connect salloc_arb.io.in[2].bits.vc_sel.`4`[2], states[2].vc_sel.`4`[2] connect salloc_arb.io.in[2].bits.vc_sel.`4`[3], states[2].vc_sel.`4`[3] connect salloc_arb.io.in[2].bits.vc_sel.`4`[4], states[2].vc_sel.`4`[4] connect salloc_arb.io.in[2].bits.vc_sel.`4`[5], states[2].vc_sel.`4`[5] connect salloc_arb.io.in[2].bits.vc_sel.`4`[6], states[2].vc_sel.`4`[6] connect salloc_arb.io.in[2].bits.vc_sel.`4`[7], states[2].vc_sel.`4`[7] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_107 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_108 = and(_T_107, input_buffer.io.deq[2].bits.tail) when _T_108 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_30 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_30 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_hi_36 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) node credit_available_hi_36 = cat(credit_available_hi_hi_36, credit_available_hi_lo_30) node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36) node credit_available_lo_lo_31 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_31 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) node credit_available_hi_hi_37 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) node credit_available_hi_37 = cat(credit_available_hi_hi_37, credit_available_hi_lo_31) node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37) node credit_available_lo_lo_32 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_32 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) node credit_available_hi_hi_38 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) node credit_available_hi_38 = cat(credit_available_hi_hi_38, credit_available_hi_lo_32) node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38) node credit_available_lo_lo_33 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0]) node credit_available_lo_hi_33 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2]) node credit_available_lo_39 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4]) node credit_available_hi_hi_39 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6]) node credit_available_hi_39 = cat(credit_available_hi_hi_39, credit_available_hi_lo_33) node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39) node credit_available_lo_lo_34 = cat(states[3].vc_sel.`4`[1], states[3].vc_sel.`4`[0]) node credit_available_lo_hi_34 = cat(states[3].vc_sel.`4`[3], states[3].vc_sel.`4`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(states[3].vc_sel.`4`[5], states[3].vc_sel.`4`[4]) node credit_available_hi_hi_40 = cat(states[3].vc_sel.`4`[7], states[3].vc_sel.`4`[6]) node credit_available_hi_40 = cat(credit_available_hi_hi_40, credit_available_hi_lo_34) node _credit_available_T_43 = cat(credit_available_hi_40, credit_available_lo_40) node credit_available_lo_41 = cat(_credit_available_T_40, _credit_available_T_39) node credit_available_hi_hi_41 = cat(_credit_available_T_43, _credit_available_T_42) node credit_available_hi_41 = cat(credit_available_hi_hi_41, _credit_available_T_41) node _credit_available_T_44 = cat(credit_available_hi_41, credit_available_lo_41) node credit_available_lo_lo_35 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_35 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_42 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_42 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_42 = cat(credit_available_hi_hi_42, credit_available_hi_lo_35) node _credit_available_T_45 = cat(credit_available_hi_42, credit_available_lo_42) node credit_available_lo_lo_36 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_36 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_43 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_43 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_43 = cat(credit_available_hi_hi_43, credit_available_hi_lo_36) node _credit_available_T_46 = cat(credit_available_hi_43, credit_available_lo_43) node credit_available_lo_lo_37 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_37 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_44 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_44 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_44 = cat(credit_available_hi_hi_44, credit_available_hi_lo_37) node _credit_available_T_47 = cat(credit_available_hi_44, credit_available_lo_44) node credit_available_lo_lo_38 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_38 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_45 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_45 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_45 = cat(credit_available_hi_hi_45, credit_available_hi_lo_38) node _credit_available_T_48 = cat(credit_available_hi_45, credit_available_lo_45) node credit_available_lo_lo_39 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_39 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_46 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_46 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_46 = cat(credit_available_hi_hi_46, credit_available_hi_lo_39) node _credit_available_T_49 = cat(credit_available_hi_46, credit_available_lo_46) node credit_available_lo_47 = cat(_credit_available_T_46, _credit_available_T_45) node credit_available_hi_hi_47 = cat(_credit_available_T_49, _credit_available_T_48) node credit_available_hi_47 = cat(credit_available_hi_hi_47, _credit_available_T_47) node _credit_available_T_50 = cat(credit_available_hi_47, credit_available_lo_47) node _credit_available_T_51 = and(_credit_available_T_44, _credit_available_T_50) node credit_available_3 = neq(_credit_available_T_51, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1] connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2] connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3] connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4] connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5] connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6] connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7] connect salloc_arb.io.in[3].bits.vc_sel.`4`[0], states[3].vc_sel.`4`[0] connect salloc_arb.io.in[3].bits.vc_sel.`4`[1], states[3].vc_sel.`4`[1] connect salloc_arb.io.in[3].bits.vc_sel.`4`[2], states[3].vc_sel.`4`[2] connect salloc_arb.io.in[3].bits.vc_sel.`4`[3], states[3].vc_sel.`4`[3] connect salloc_arb.io.in[3].bits.vc_sel.`4`[4], states[3].vc_sel.`4`[4] connect salloc_arb.io.in[3].bits.vc_sel.`4`[5], states[3].vc_sel.`4`[5] connect salloc_arb.io.in[3].bits.vc_sel.`4`[6], states[3].vc_sel.`4`[6] connect salloc_arb.io.in[3].bits.vc_sel.`4`[7], states[3].vc_sel.`4`[7] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_109 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_110 = and(_T_109, input_buffer.io.deq[3].bits.tail) when _T_110 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_40 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_40 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) node credit_available_lo_48 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_hi_48 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) node credit_available_hi_48 = cat(credit_available_hi_hi_48, credit_available_hi_lo_40) node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48) node credit_available_lo_lo_41 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_41 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) node credit_available_lo_49 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) node credit_available_hi_hi_49 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) node credit_available_hi_49 = cat(credit_available_hi_hi_49, credit_available_hi_lo_41) node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49) node credit_available_lo_lo_42 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_42 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) node credit_available_lo_50 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) node credit_available_hi_lo_42 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) node credit_available_hi_hi_50 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) node credit_available_hi_50 = cat(credit_available_hi_hi_50, credit_available_hi_lo_42) node _credit_available_T_54 = cat(credit_available_hi_50, credit_available_lo_50) node credit_available_lo_lo_43 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0]) node credit_available_lo_hi_43 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2]) node credit_available_lo_51 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) node credit_available_hi_lo_43 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4]) node credit_available_hi_hi_51 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6]) node credit_available_hi_51 = cat(credit_available_hi_hi_51, credit_available_hi_lo_43) node _credit_available_T_55 = cat(credit_available_hi_51, credit_available_lo_51) node credit_available_lo_lo_44 = cat(states[4].vc_sel.`4`[1], states[4].vc_sel.`4`[0]) node credit_available_lo_hi_44 = cat(states[4].vc_sel.`4`[3], states[4].vc_sel.`4`[2]) node credit_available_lo_52 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) node credit_available_hi_lo_44 = cat(states[4].vc_sel.`4`[5], states[4].vc_sel.`4`[4]) node credit_available_hi_hi_52 = cat(states[4].vc_sel.`4`[7], states[4].vc_sel.`4`[6]) node credit_available_hi_52 = cat(credit_available_hi_hi_52, credit_available_hi_lo_44) node _credit_available_T_56 = cat(credit_available_hi_52, credit_available_lo_52) node credit_available_lo_53 = cat(_credit_available_T_53, _credit_available_T_52) node credit_available_hi_hi_53 = cat(_credit_available_T_56, _credit_available_T_55) node credit_available_hi_53 = cat(credit_available_hi_hi_53, _credit_available_T_54) node _credit_available_T_57 = cat(credit_available_hi_53, credit_available_lo_53) node credit_available_lo_lo_45 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_45 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_54 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) node credit_available_hi_lo_45 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_54 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_54 = cat(credit_available_hi_hi_54, credit_available_hi_lo_45) node _credit_available_T_58 = cat(credit_available_hi_54, credit_available_lo_54) node credit_available_lo_lo_46 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_46 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_55 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) node credit_available_hi_lo_46 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_55 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_55 = cat(credit_available_hi_hi_55, credit_available_hi_lo_46) node _credit_available_T_59 = cat(credit_available_hi_55, credit_available_lo_55) node credit_available_lo_lo_47 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_47 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_56 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) node credit_available_hi_lo_47 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_56 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_56 = cat(credit_available_hi_hi_56, credit_available_hi_lo_47) node _credit_available_T_60 = cat(credit_available_hi_56, credit_available_lo_56) node credit_available_lo_lo_48 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_48 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_57 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48) node credit_available_hi_lo_48 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_57 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_57 = cat(credit_available_hi_hi_57, credit_available_hi_lo_48) node _credit_available_T_61 = cat(credit_available_hi_57, credit_available_lo_57) node credit_available_lo_lo_49 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_49 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_58 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49) node credit_available_hi_lo_49 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_58 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_58 = cat(credit_available_hi_hi_58, credit_available_hi_lo_49) node _credit_available_T_62 = cat(credit_available_hi_58, credit_available_lo_58) node credit_available_lo_59 = cat(_credit_available_T_59, _credit_available_T_58) node credit_available_hi_hi_59 = cat(_credit_available_T_62, _credit_available_T_61) node credit_available_hi_59 = cat(credit_available_hi_hi_59, _credit_available_T_60) node _credit_available_T_63 = cat(credit_available_hi_59, credit_available_lo_59) node _credit_available_T_64 = and(_credit_available_T_57, _credit_available_T_63) node credit_available_4 = neq(_credit_available_T_64, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1] connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2] connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3] connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4] connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5] connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6] connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7] connect salloc_arb.io.in[4].bits.vc_sel.`4`[0], states[4].vc_sel.`4`[0] connect salloc_arb.io.in[4].bits.vc_sel.`4`[1], states[4].vc_sel.`4`[1] connect salloc_arb.io.in[4].bits.vc_sel.`4`[2], states[4].vc_sel.`4`[2] connect salloc_arb.io.in[4].bits.vc_sel.`4`[3], states[4].vc_sel.`4`[3] connect salloc_arb.io.in[4].bits.vc_sel.`4`[4], states[4].vc_sel.`4`[4] connect salloc_arb.io.in[4].bits.vc_sel.`4`[5], states[4].vc_sel.`4`[5] connect salloc_arb.io.in[4].bits.vc_sel.`4`[6], states[4].vc_sel.`4`[6] connect salloc_arb.io.in[4].bits.vc_sel.`4`[7], states[4].vc_sel.`4`[7] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_111 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_112 = and(_T_111, input_buffer.io.deq[4].bits.tail) when _T_112 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_50 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_50 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) node credit_available_lo_60 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50) node credit_available_hi_lo_50 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_hi_60 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) node credit_available_hi_60 = cat(credit_available_hi_hi_60, credit_available_hi_lo_50) node _credit_available_T_65 = cat(credit_available_hi_60, credit_available_lo_60) node credit_available_lo_lo_51 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_51 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) node credit_available_lo_61 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51) node credit_available_hi_lo_51 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) node credit_available_hi_hi_61 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) node credit_available_hi_61 = cat(credit_available_hi_hi_61, credit_available_hi_lo_51) node _credit_available_T_66 = cat(credit_available_hi_61, credit_available_lo_61) node credit_available_lo_lo_52 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_52 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) node credit_available_lo_62 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52) node credit_available_hi_lo_52 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) node credit_available_hi_hi_62 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) node credit_available_hi_62 = cat(credit_available_hi_hi_62, credit_available_hi_lo_52) node _credit_available_T_67 = cat(credit_available_hi_62, credit_available_lo_62) node credit_available_lo_lo_53 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0]) node credit_available_lo_hi_53 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2]) node credit_available_lo_63 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53) node credit_available_hi_lo_53 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4]) node credit_available_hi_hi_63 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6]) node credit_available_hi_63 = cat(credit_available_hi_hi_63, credit_available_hi_lo_53) node _credit_available_T_68 = cat(credit_available_hi_63, credit_available_lo_63) node credit_available_lo_lo_54 = cat(states[5].vc_sel.`4`[1], states[5].vc_sel.`4`[0]) node credit_available_lo_hi_54 = cat(states[5].vc_sel.`4`[3], states[5].vc_sel.`4`[2]) node credit_available_lo_64 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54) node credit_available_hi_lo_54 = cat(states[5].vc_sel.`4`[5], states[5].vc_sel.`4`[4]) node credit_available_hi_hi_64 = cat(states[5].vc_sel.`4`[7], states[5].vc_sel.`4`[6]) node credit_available_hi_64 = cat(credit_available_hi_hi_64, credit_available_hi_lo_54) node _credit_available_T_69 = cat(credit_available_hi_64, credit_available_lo_64) node credit_available_lo_65 = cat(_credit_available_T_66, _credit_available_T_65) node credit_available_hi_hi_65 = cat(_credit_available_T_69, _credit_available_T_68) node credit_available_hi_65 = cat(credit_available_hi_hi_65, _credit_available_T_67) node _credit_available_T_70 = cat(credit_available_hi_65, credit_available_lo_65) node credit_available_lo_lo_55 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_55 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_66 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55) node credit_available_hi_lo_55 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_66 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_66 = cat(credit_available_hi_hi_66, credit_available_hi_lo_55) node _credit_available_T_71 = cat(credit_available_hi_66, credit_available_lo_66) node credit_available_lo_lo_56 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_56 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_67 = cat(credit_available_lo_hi_56, credit_available_lo_lo_56) node credit_available_hi_lo_56 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_67 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_67 = cat(credit_available_hi_hi_67, credit_available_hi_lo_56) node _credit_available_T_72 = cat(credit_available_hi_67, credit_available_lo_67) node credit_available_lo_lo_57 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_57 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_68 = cat(credit_available_lo_hi_57, credit_available_lo_lo_57) node credit_available_hi_lo_57 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_68 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_68 = cat(credit_available_hi_hi_68, credit_available_hi_lo_57) node _credit_available_T_73 = cat(credit_available_hi_68, credit_available_lo_68) node credit_available_lo_lo_58 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_58 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_69 = cat(credit_available_lo_hi_58, credit_available_lo_lo_58) node credit_available_hi_lo_58 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_69 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_69 = cat(credit_available_hi_hi_69, credit_available_hi_lo_58) node _credit_available_T_74 = cat(credit_available_hi_69, credit_available_lo_69) node credit_available_lo_lo_59 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_59 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_70 = cat(credit_available_lo_hi_59, credit_available_lo_lo_59) node credit_available_hi_lo_59 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_70 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_70 = cat(credit_available_hi_hi_70, credit_available_hi_lo_59) node _credit_available_T_75 = cat(credit_available_hi_70, credit_available_lo_70) node credit_available_lo_71 = cat(_credit_available_T_72, _credit_available_T_71) node credit_available_hi_hi_71 = cat(_credit_available_T_75, _credit_available_T_74) node credit_available_hi_71 = cat(credit_available_hi_hi_71, _credit_available_T_73) node _credit_available_T_76 = cat(credit_available_hi_71, credit_available_lo_71) node _credit_available_T_77 = and(_credit_available_T_70, _credit_available_T_76) node credit_available_5 = neq(_credit_available_T_77, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1] connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2] connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3] connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4] connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5] connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6] connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7] connect salloc_arb.io.in[5].bits.vc_sel.`4`[0], states[5].vc_sel.`4`[0] connect salloc_arb.io.in[5].bits.vc_sel.`4`[1], states[5].vc_sel.`4`[1] connect salloc_arb.io.in[5].bits.vc_sel.`4`[2], states[5].vc_sel.`4`[2] connect salloc_arb.io.in[5].bits.vc_sel.`4`[3], states[5].vc_sel.`4`[3] connect salloc_arb.io.in[5].bits.vc_sel.`4`[4], states[5].vc_sel.`4`[4] connect salloc_arb.io.in[5].bits.vc_sel.`4`[5], states[5].vc_sel.`4`[5] connect salloc_arb.io.in[5].bits.vc_sel.`4`[6], states[5].vc_sel.`4`[6] connect salloc_arb.io.in[5].bits.vc_sel.`4`[7], states[5].vc_sel.`4`[7] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_113 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_114 = and(_T_113, input_buffer.io.deq[5].bits.tail) when _T_114 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_60 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_60 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) node credit_available_lo_72 = cat(credit_available_lo_hi_60, credit_available_lo_lo_60) node credit_available_hi_lo_60 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) node credit_available_hi_hi_72 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) node credit_available_hi_72 = cat(credit_available_hi_hi_72, credit_available_hi_lo_60) node _credit_available_T_78 = cat(credit_available_hi_72, credit_available_lo_72) node credit_available_lo_lo_61 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_61 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) node credit_available_lo_73 = cat(credit_available_lo_hi_61, credit_available_lo_lo_61) node credit_available_hi_lo_61 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) node credit_available_hi_hi_73 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) node credit_available_hi_73 = cat(credit_available_hi_hi_73, credit_available_hi_lo_61) node _credit_available_T_79 = cat(credit_available_hi_73, credit_available_lo_73) node credit_available_lo_lo_62 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_62 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) node credit_available_lo_74 = cat(credit_available_lo_hi_62, credit_available_lo_lo_62) node credit_available_hi_lo_62 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) node credit_available_hi_hi_74 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) node credit_available_hi_74 = cat(credit_available_hi_hi_74, credit_available_hi_lo_62) node _credit_available_T_80 = cat(credit_available_hi_74, credit_available_lo_74) node credit_available_lo_lo_63 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0]) node credit_available_lo_hi_63 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2]) node credit_available_lo_75 = cat(credit_available_lo_hi_63, credit_available_lo_lo_63) node credit_available_hi_lo_63 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4]) node credit_available_hi_hi_75 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6]) node credit_available_hi_75 = cat(credit_available_hi_hi_75, credit_available_hi_lo_63) node _credit_available_T_81 = cat(credit_available_hi_75, credit_available_lo_75) node credit_available_lo_lo_64 = cat(states[6].vc_sel.`4`[1], states[6].vc_sel.`4`[0]) node credit_available_lo_hi_64 = cat(states[6].vc_sel.`4`[3], states[6].vc_sel.`4`[2]) node credit_available_lo_76 = cat(credit_available_lo_hi_64, credit_available_lo_lo_64) node credit_available_hi_lo_64 = cat(states[6].vc_sel.`4`[5], states[6].vc_sel.`4`[4]) node credit_available_hi_hi_76 = cat(states[6].vc_sel.`4`[7], states[6].vc_sel.`4`[6]) node credit_available_hi_76 = cat(credit_available_hi_hi_76, credit_available_hi_lo_64) node _credit_available_T_82 = cat(credit_available_hi_76, credit_available_lo_76) node credit_available_lo_77 = cat(_credit_available_T_79, _credit_available_T_78) node credit_available_hi_hi_77 = cat(_credit_available_T_82, _credit_available_T_81) node credit_available_hi_77 = cat(credit_available_hi_hi_77, _credit_available_T_80) node _credit_available_T_83 = cat(credit_available_hi_77, credit_available_lo_77) node credit_available_lo_lo_65 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_65 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_78 = cat(credit_available_lo_hi_65, credit_available_lo_lo_65) node credit_available_hi_lo_65 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_78 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_78 = cat(credit_available_hi_hi_78, credit_available_hi_lo_65) node _credit_available_T_84 = cat(credit_available_hi_78, credit_available_lo_78) node credit_available_lo_lo_66 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_66 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_79 = cat(credit_available_lo_hi_66, credit_available_lo_lo_66) node credit_available_hi_lo_66 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_79 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_79 = cat(credit_available_hi_hi_79, credit_available_hi_lo_66) node _credit_available_T_85 = cat(credit_available_hi_79, credit_available_lo_79) node credit_available_lo_lo_67 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_67 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_80 = cat(credit_available_lo_hi_67, credit_available_lo_lo_67) node credit_available_hi_lo_67 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_80 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_80 = cat(credit_available_hi_hi_80, credit_available_hi_lo_67) node _credit_available_T_86 = cat(credit_available_hi_80, credit_available_lo_80) node credit_available_lo_lo_68 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_68 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_81 = cat(credit_available_lo_hi_68, credit_available_lo_lo_68) node credit_available_hi_lo_68 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_81 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_81 = cat(credit_available_hi_hi_81, credit_available_hi_lo_68) node _credit_available_T_87 = cat(credit_available_hi_81, credit_available_lo_81) node credit_available_lo_lo_69 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_69 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_82 = cat(credit_available_lo_hi_69, credit_available_lo_lo_69) node credit_available_hi_lo_69 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_82 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_82 = cat(credit_available_hi_hi_82, credit_available_hi_lo_69) node _credit_available_T_88 = cat(credit_available_hi_82, credit_available_lo_82) node credit_available_lo_83 = cat(_credit_available_T_85, _credit_available_T_84) node credit_available_hi_hi_83 = cat(_credit_available_T_88, _credit_available_T_87) node credit_available_hi_83 = cat(credit_available_hi_hi_83, _credit_available_T_86) node _credit_available_T_89 = cat(credit_available_hi_83, credit_available_lo_83) node _credit_available_T_90 = and(_credit_available_T_83, _credit_available_T_89) node credit_available_6 = neq(_credit_available_T_90, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_6) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0] connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1] connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2] connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3] connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4] connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5] connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6] connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7] connect salloc_arb.io.in[6].bits.vc_sel.`4`[0], states[6].vc_sel.`4`[0] connect salloc_arb.io.in[6].bits.vc_sel.`4`[1], states[6].vc_sel.`4`[1] connect salloc_arb.io.in[6].bits.vc_sel.`4`[2], states[6].vc_sel.`4`[2] connect salloc_arb.io.in[6].bits.vc_sel.`4`[3], states[6].vc_sel.`4`[3] connect salloc_arb.io.in[6].bits.vc_sel.`4`[4], states[6].vc_sel.`4`[4] connect salloc_arb.io.in[6].bits.vc_sel.`4`[5], states[6].vc_sel.`4`[5] connect salloc_arb.io.in[6].bits.vc_sel.`4`[6], states[6].vc_sel.`4`[6] connect salloc_arb.io.in[6].bits.vc_sel.`4`[7], states[6].vc_sel.`4`[7] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_115 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_116 = and(_T_115, input_buffer.io.deq[6].bits.tail) when _T_116 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_70 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_70 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) node credit_available_lo_84 = cat(credit_available_lo_hi_70, credit_available_lo_lo_70) node credit_available_hi_lo_70 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) node credit_available_hi_hi_84 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) node credit_available_hi_84 = cat(credit_available_hi_hi_84, credit_available_hi_lo_70) node _credit_available_T_91 = cat(credit_available_hi_84, credit_available_lo_84) node credit_available_lo_lo_71 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_71 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) node credit_available_lo_85 = cat(credit_available_lo_hi_71, credit_available_lo_lo_71) node credit_available_hi_lo_71 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) node credit_available_hi_hi_85 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) node credit_available_hi_85 = cat(credit_available_hi_hi_85, credit_available_hi_lo_71) node _credit_available_T_92 = cat(credit_available_hi_85, credit_available_lo_85) node credit_available_lo_lo_72 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_72 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) node credit_available_lo_86 = cat(credit_available_lo_hi_72, credit_available_lo_lo_72) node credit_available_hi_lo_72 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) node credit_available_hi_hi_86 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) node credit_available_hi_86 = cat(credit_available_hi_hi_86, credit_available_hi_lo_72) node _credit_available_T_93 = cat(credit_available_hi_86, credit_available_lo_86) node credit_available_lo_lo_73 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0]) node credit_available_lo_hi_73 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2]) node credit_available_lo_87 = cat(credit_available_lo_hi_73, credit_available_lo_lo_73) node credit_available_hi_lo_73 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4]) node credit_available_hi_hi_87 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6]) node credit_available_hi_87 = cat(credit_available_hi_hi_87, credit_available_hi_lo_73) node _credit_available_T_94 = cat(credit_available_hi_87, credit_available_lo_87) node credit_available_lo_lo_74 = cat(states[7].vc_sel.`4`[1], states[7].vc_sel.`4`[0]) node credit_available_lo_hi_74 = cat(states[7].vc_sel.`4`[3], states[7].vc_sel.`4`[2]) node credit_available_lo_88 = cat(credit_available_lo_hi_74, credit_available_lo_lo_74) node credit_available_hi_lo_74 = cat(states[7].vc_sel.`4`[5], states[7].vc_sel.`4`[4]) node credit_available_hi_hi_88 = cat(states[7].vc_sel.`4`[7], states[7].vc_sel.`4`[6]) node credit_available_hi_88 = cat(credit_available_hi_hi_88, credit_available_hi_lo_74) node _credit_available_T_95 = cat(credit_available_hi_88, credit_available_lo_88) node credit_available_lo_89 = cat(_credit_available_T_92, _credit_available_T_91) node credit_available_hi_hi_89 = cat(_credit_available_T_95, _credit_available_T_94) node credit_available_hi_89 = cat(credit_available_hi_hi_89, _credit_available_T_93) node _credit_available_T_96 = cat(credit_available_hi_89, credit_available_lo_89) node credit_available_lo_lo_75 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_75 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_90 = cat(credit_available_lo_hi_75, credit_available_lo_lo_75) node credit_available_hi_lo_75 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_90 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_90 = cat(credit_available_hi_hi_90, credit_available_hi_lo_75) node _credit_available_T_97 = cat(credit_available_hi_90, credit_available_lo_90) node credit_available_lo_lo_76 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_76 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_91 = cat(credit_available_lo_hi_76, credit_available_lo_lo_76) node credit_available_hi_lo_76 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_91 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_91 = cat(credit_available_hi_hi_91, credit_available_hi_lo_76) node _credit_available_T_98 = cat(credit_available_hi_91, credit_available_lo_91) node credit_available_lo_lo_77 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_77 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_92 = cat(credit_available_lo_hi_77, credit_available_lo_lo_77) node credit_available_hi_lo_77 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_92 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_92 = cat(credit_available_hi_hi_92, credit_available_hi_lo_77) node _credit_available_T_99 = cat(credit_available_hi_92, credit_available_lo_92) node credit_available_lo_lo_78 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_78 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_93 = cat(credit_available_lo_hi_78, credit_available_lo_lo_78) node credit_available_hi_lo_78 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_93 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_93 = cat(credit_available_hi_hi_93, credit_available_hi_lo_78) node _credit_available_T_100 = cat(credit_available_hi_93, credit_available_lo_93) node credit_available_lo_lo_79 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_79 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_94 = cat(credit_available_lo_hi_79, credit_available_lo_lo_79) node credit_available_hi_lo_79 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_94 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_94 = cat(credit_available_hi_hi_94, credit_available_hi_lo_79) node _credit_available_T_101 = cat(credit_available_hi_94, credit_available_lo_94) node credit_available_lo_95 = cat(_credit_available_T_98, _credit_available_T_97) node credit_available_hi_hi_95 = cat(_credit_available_T_101, _credit_available_T_100) node credit_available_hi_95 = cat(credit_available_hi_hi_95, _credit_available_T_99) node _credit_available_T_102 = cat(credit_available_hi_95, credit_available_lo_95) node _credit_available_T_103 = and(_credit_available_T_96, _credit_available_T_102) node credit_available_7 = neq(_credit_available_T_103, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_7) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1] connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2] connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3] connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4] connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5] connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6] connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7] connect salloc_arb.io.in[7].bits.vc_sel.`4`[0], states[7].vc_sel.`4`[0] connect salloc_arb.io.in[7].bits.vc_sel.`4`[1], states[7].vc_sel.`4`[1] connect salloc_arb.io.in[7].bits.vc_sel.`4`[2], states[7].vc_sel.`4`[2] connect salloc_arb.io.in[7].bits.vc_sel.`4`[3], states[7].vc_sel.`4`[3] connect salloc_arb.io.in[7].bits.vc_sel.`4`[4], states[7].vc_sel.`4`[4] connect salloc_arb.io.in[7].bits.vc_sel.`4`[5], states[7].vc_sel.`4`[5] connect salloc_arb.io.in[7].bits.vc_sel.`4`[6], states[7].vc_sel.`4`[6] connect salloc_arb.io.in[7].bits.vc_sel.`4`[7], states[7].vc_sel.`4`[7] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_117 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_118 = and(_T_117, input_buffer.io.deq[7].bits.tail) when _T_118 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_29 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_25 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _vc_sel_WIRE : UInt<1>[8] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_22 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_37 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_52 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_67 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_82 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_97 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_112 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_127 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_9 : UInt<1>[8] node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_142 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_157 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_172 connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_187 connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_202 connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_217 connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_232 connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_247 connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 connect vc_sel.`1`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_18 : UInt<1>[8] node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_262 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_277 connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_292 connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) wire _vc_sel_WIRE_22 : UInt<1> connect _vc_sel_WIRE_22, _vc_sel_T_307 connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_322 connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_337 connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_352 connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_367 connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 connect vc_sel.`2`, _vc_sel_WIRE_18 wire _vc_sel_WIRE_27 : UInt<1>[8] node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369) node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370) node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371) node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372) node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373) node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_382 connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28 node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384) node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385) node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386) node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387) node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388) node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389) node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_397 connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29 node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401) node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402) node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403) node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404) node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_412 connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30 node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_427 connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430) node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_442 connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32 node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444) node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445) node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446) node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447) node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448) node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449) node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450) wire _vc_sel_WIRE_33 : UInt<1> connect _vc_sel_WIRE_33, _vc_sel_T_457 connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33 node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459) node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460) node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461) node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462) node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463) node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464) node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465) wire _vc_sel_WIRE_34 : UInt<1> connect _vc_sel_WIRE_34, _vc_sel_T_472 connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34 node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477) node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478) node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479) node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480) wire _vc_sel_WIRE_35 : UInt<1> connect _vc_sel_WIRE_35, _vc_sel_T_487 connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35 connect vc_sel.`3`, _vc_sel_WIRE_27 wire _vc_sel_WIRE_36 : UInt<1>[8] node _vc_sel_T_488 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_489 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_490 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_491 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_492 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_493 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_494 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_495 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_496 = or(_vc_sel_T_488, _vc_sel_T_489) node _vc_sel_T_497 = or(_vc_sel_T_496, _vc_sel_T_490) node _vc_sel_T_498 = or(_vc_sel_T_497, _vc_sel_T_491) node _vc_sel_T_499 = or(_vc_sel_T_498, _vc_sel_T_492) node _vc_sel_T_500 = or(_vc_sel_T_499, _vc_sel_T_493) node _vc_sel_T_501 = or(_vc_sel_T_500, _vc_sel_T_494) node _vc_sel_T_502 = or(_vc_sel_T_501, _vc_sel_T_495) wire _vc_sel_WIRE_37 : UInt<1> connect _vc_sel_WIRE_37, _vc_sel_T_502 connect _vc_sel_WIRE_36[0], _vc_sel_WIRE_37 node _vc_sel_T_503 = mux(_vc_sel_T, states[0].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_504 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_505 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_506 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_507 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_508 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_509 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_510 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_511 = or(_vc_sel_T_503, _vc_sel_T_504) node _vc_sel_T_512 = or(_vc_sel_T_511, _vc_sel_T_505) node _vc_sel_T_513 = or(_vc_sel_T_512, _vc_sel_T_506) node _vc_sel_T_514 = or(_vc_sel_T_513, _vc_sel_T_507) node _vc_sel_T_515 = or(_vc_sel_T_514, _vc_sel_T_508) node _vc_sel_T_516 = or(_vc_sel_T_515, _vc_sel_T_509) node _vc_sel_T_517 = or(_vc_sel_T_516, _vc_sel_T_510) wire _vc_sel_WIRE_38 : UInt<1> connect _vc_sel_WIRE_38, _vc_sel_T_517 connect _vc_sel_WIRE_36[1], _vc_sel_WIRE_38 node _vc_sel_T_518 = mux(_vc_sel_T, states[0].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_519 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_520 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_521 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_522 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_523 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_524 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_525 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_526 = or(_vc_sel_T_518, _vc_sel_T_519) node _vc_sel_T_527 = or(_vc_sel_T_526, _vc_sel_T_520) node _vc_sel_T_528 = or(_vc_sel_T_527, _vc_sel_T_521) node _vc_sel_T_529 = or(_vc_sel_T_528, _vc_sel_T_522) node _vc_sel_T_530 = or(_vc_sel_T_529, _vc_sel_T_523) node _vc_sel_T_531 = or(_vc_sel_T_530, _vc_sel_T_524) node _vc_sel_T_532 = or(_vc_sel_T_531, _vc_sel_T_525) wire _vc_sel_WIRE_39 : UInt<1> connect _vc_sel_WIRE_39, _vc_sel_T_532 connect _vc_sel_WIRE_36[2], _vc_sel_WIRE_39 node _vc_sel_T_533 = mux(_vc_sel_T, states[0].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_534 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_535 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_536 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_537 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_538 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_539 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_540 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_541 = or(_vc_sel_T_533, _vc_sel_T_534) node _vc_sel_T_542 = or(_vc_sel_T_541, _vc_sel_T_535) node _vc_sel_T_543 = or(_vc_sel_T_542, _vc_sel_T_536) node _vc_sel_T_544 = or(_vc_sel_T_543, _vc_sel_T_537) node _vc_sel_T_545 = or(_vc_sel_T_544, _vc_sel_T_538) node _vc_sel_T_546 = or(_vc_sel_T_545, _vc_sel_T_539) node _vc_sel_T_547 = or(_vc_sel_T_546, _vc_sel_T_540) wire _vc_sel_WIRE_40 : UInt<1> connect _vc_sel_WIRE_40, _vc_sel_T_547 connect _vc_sel_WIRE_36[3], _vc_sel_WIRE_40 node _vc_sel_T_548 = mux(_vc_sel_T, states[0].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_549 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_550 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_551 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_552 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_553 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_554 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_555 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_556 = or(_vc_sel_T_548, _vc_sel_T_549) node _vc_sel_T_557 = or(_vc_sel_T_556, _vc_sel_T_550) node _vc_sel_T_558 = or(_vc_sel_T_557, _vc_sel_T_551) node _vc_sel_T_559 = or(_vc_sel_T_558, _vc_sel_T_552) node _vc_sel_T_560 = or(_vc_sel_T_559, _vc_sel_T_553) node _vc_sel_T_561 = or(_vc_sel_T_560, _vc_sel_T_554) node _vc_sel_T_562 = or(_vc_sel_T_561, _vc_sel_T_555) wire _vc_sel_WIRE_41 : UInt<1> connect _vc_sel_WIRE_41, _vc_sel_T_562 connect _vc_sel_WIRE_36[4], _vc_sel_WIRE_41 node _vc_sel_T_563 = mux(_vc_sel_T, states[0].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_564 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_565 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_566 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_567 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_568 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_569 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_570 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_571 = or(_vc_sel_T_563, _vc_sel_T_564) node _vc_sel_T_572 = or(_vc_sel_T_571, _vc_sel_T_565) node _vc_sel_T_573 = or(_vc_sel_T_572, _vc_sel_T_566) node _vc_sel_T_574 = or(_vc_sel_T_573, _vc_sel_T_567) node _vc_sel_T_575 = or(_vc_sel_T_574, _vc_sel_T_568) node _vc_sel_T_576 = or(_vc_sel_T_575, _vc_sel_T_569) node _vc_sel_T_577 = or(_vc_sel_T_576, _vc_sel_T_570) wire _vc_sel_WIRE_42 : UInt<1> connect _vc_sel_WIRE_42, _vc_sel_T_577 connect _vc_sel_WIRE_36[5], _vc_sel_WIRE_42 node _vc_sel_T_578 = mux(_vc_sel_T, states[0].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_579 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_580 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_581 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_582 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_583 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_584 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_585 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_586 = or(_vc_sel_T_578, _vc_sel_T_579) node _vc_sel_T_587 = or(_vc_sel_T_586, _vc_sel_T_580) node _vc_sel_T_588 = or(_vc_sel_T_587, _vc_sel_T_581) node _vc_sel_T_589 = or(_vc_sel_T_588, _vc_sel_T_582) node _vc_sel_T_590 = or(_vc_sel_T_589, _vc_sel_T_583) node _vc_sel_T_591 = or(_vc_sel_T_590, _vc_sel_T_584) node _vc_sel_T_592 = or(_vc_sel_T_591, _vc_sel_T_585) wire _vc_sel_WIRE_43 : UInt<1> connect _vc_sel_WIRE_43, _vc_sel_T_592 connect _vc_sel_WIRE_36[6], _vc_sel_WIRE_43 node _vc_sel_T_593 = mux(_vc_sel_T, states[0].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_594 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_595 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_596 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_597 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_598 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_599 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_600 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_601 = or(_vc_sel_T_593, _vc_sel_T_594) node _vc_sel_T_602 = or(_vc_sel_T_601, _vc_sel_T_595) node _vc_sel_T_603 = or(_vc_sel_T_602, _vc_sel_T_596) node _vc_sel_T_604 = or(_vc_sel_T_603, _vc_sel_T_597) node _vc_sel_T_605 = or(_vc_sel_T_604, _vc_sel_T_598) node _vc_sel_T_606 = or(_vc_sel_T_605, _vc_sel_T_599) node _vc_sel_T_607 = or(_vc_sel_T_606, _vc_sel_T_600) wire _vc_sel_WIRE_44 : UInt<1> connect _vc_sel_WIRE_44, _vc_sel_T_607 connect _vc_sel_WIRE_36[7], _vc_sel_WIRE_44 connect vc_sel.`4`, _vc_sel_WIRE_36 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6]) node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7]) node _channel_oh_T_24 = or(vc_sel.`4`[0], vc_sel.`4`[1]) node _channel_oh_T_25 = or(_channel_oh_T_24, vc_sel.`4`[2]) node _channel_oh_T_26 = or(_channel_oh_T_25, vc_sel.`4`[3]) node _channel_oh_T_27 = or(_channel_oh_T_26, vc_sel.`4`[4]) node _channel_oh_T_28 = or(_channel_oh_T_27, vc_sel.`4`[5]) node _channel_oh_T_29 = or(_channel_oh_T_28, vc_sel.`4`[6]) node channel_oh_4 = or(_channel_oh_T_29, vc_sel.`4`[7]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2]) node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3) node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4]) node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6]) node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3) node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node virt_channel_lo_lo_4 = cat(vc_sel.`4`[1], vc_sel.`4`[0]) node virt_channel_lo_hi_4 = cat(vc_sel.`4`[3], vc_sel.`4`[2]) node virt_channel_lo_12 = cat(virt_channel_lo_hi_4, virt_channel_lo_lo_4) node virt_channel_hi_lo_4 = cat(vc_sel.`4`[5], vc_sel.`4`[4]) node virt_channel_hi_hi_4 = cat(vc_sel.`4`[7], vc_sel.`4`[6]) node virt_channel_hi_12 = cat(virt_channel_hi_hi_4, virt_channel_hi_lo_4) node _virt_channel_T_32 = cat(virt_channel_hi_12, virt_channel_lo_12) node virt_channel_hi_13 = bits(_virt_channel_T_32, 7, 4) node virt_channel_lo_13 = bits(_virt_channel_T_32, 3, 0) node _virt_channel_T_33 = orr(virt_channel_hi_13) node _virt_channel_T_34 = or(virt_channel_hi_13, virt_channel_lo_13) node virt_channel_hi_14 = bits(_virt_channel_T_34, 3, 2) node virt_channel_lo_14 = bits(_virt_channel_T_34, 1, 0) node _virt_channel_T_35 = orr(virt_channel_hi_14) node _virt_channel_T_36 = or(virt_channel_hi_14, virt_channel_lo_14) node _virt_channel_T_37 = bits(_virt_channel_T_36, 1, 1) node _virt_channel_T_38 = cat(_virt_channel_T_35, _virt_channel_T_37) node _virt_channel_T_39 = cat(_virt_channel_T_33, _virt_channel_T_38) node _virt_channel_T_40 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_41 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_42 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_43 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0)) node _virt_channel_T_44 = mux(channel_oh_4, _virt_channel_T_39, UInt<1>(0h0)) node _virt_channel_T_45 = or(_virt_channel_T_40, _virt_channel_T_41) node _virt_channel_T_46 = or(_virt_channel_T_45, _virt_channel_T_42) node _virt_channel_T_47 = or(_virt_channel_T_46, _virt_channel_T_43) node _virt_channel_T_48 = or(_virt_channel_T_47, _virt_channel_T_44) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_48 node _T_119 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_119 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`1`[0], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[2], UInt<1>(0h0) connect states[0].vc_sel.`1`[3], UInt<1>(0h0) connect states[0].vc_sel.`1`[4], UInt<1>(0h0) connect states[0].vc_sel.`1`[5], UInt<1>(0h0) connect states[0].vc_sel.`1`[6], UInt<1>(0h0) connect states[0].vc_sel.`1`[7], UInt<1>(0h0) connect states[0].vc_sel.`2`[0], UInt<1>(0h0) connect states[0].vc_sel.`2`[1], UInt<1>(0h0) connect states[0].vc_sel.`2`[2], UInt<1>(0h0) connect states[0].vc_sel.`2`[3], UInt<1>(0h0) connect states[0].vc_sel.`2`[4], UInt<1>(0h0) connect states[0].vc_sel.`2`[5], UInt<1>(0h0) connect states[0].vc_sel.`2`[6], UInt<1>(0h0) connect states[0].vc_sel.`2`[7], UInt<1>(0h0) connect states[0].vc_sel.`3`[1], UInt<1>(0h0) connect states[0].vc_sel.`3`[2], UInt<1>(0h0) connect states[0].vc_sel.`3`[3], UInt<1>(0h0) connect states[0].vc_sel.`3`[4], UInt<1>(0h0) connect states[0].vc_sel.`3`[5], UInt<1>(0h0) connect states[0].vc_sel.`3`[6], UInt<1>(0h0) connect states[0].vc_sel.`3`[7], UInt<1>(0h0) connect states[0].vc_sel.`4`[1], UInt<1>(0h0) connect states[0].vc_sel.`4`[2], UInt<1>(0h0) connect states[0].vc_sel.`4`[3], UInt<1>(0h0) connect states[0].vc_sel.`4`[4], UInt<1>(0h0) connect states[0].vc_sel.`4`[5], UInt<1>(0h0) connect states[0].vc_sel.`4`[6], UInt<1>(0h0) connect states[0].vc_sel.`4`[7], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[5], UInt<1>(0h0) connect states[1].vc_sel.`1`[6], UInt<1>(0h0) connect states[1].vc_sel.`1`[7], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[3], UInt<1>(0h0) connect states[1].vc_sel.`2`[4], UInt<1>(0h0) connect states[1].vc_sel.`2`[5], UInt<1>(0h0) connect states[1].vc_sel.`2`[6], UInt<1>(0h0) connect states[1].vc_sel.`2`[7], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[2], UInt<1>(0h0) connect states[2].vc_sel.`1`[3], UInt<1>(0h0) connect states[2].vc_sel.`1`[4], UInt<1>(0h0) connect states[2].vc_sel.`1`[5], UInt<1>(0h0) connect states[2].vc_sel.`1`[6], UInt<1>(0h0) connect states[2].vc_sel.`1`[7], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[1], UInt<1>(0h0) connect states[2].vc_sel.`2`[2], UInt<1>(0h0) connect states[2].vc_sel.`2`[3], UInt<1>(0h0) connect states[2].vc_sel.`2`[4], UInt<1>(0h0) connect states[2].vc_sel.`2`[5], UInt<1>(0h0) connect states[2].vc_sel.`2`[6], UInt<1>(0h0) connect states[2].vc_sel.`2`[7], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[1], UInt<1>(0h0) connect states[3].vc_sel.`1`[2], UInt<1>(0h0) connect states[3].vc_sel.`1`[3], UInt<1>(0h0) connect states[3].vc_sel.`1`[4], UInt<1>(0h0) connect states[3].vc_sel.`1`[5], UInt<1>(0h0) connect states[3].vc_sel.`1`[6], UInt<1>(0h0) connect states[3].vc_sel.`1`[7], UInt<1>(0h0) connect states[3].vc_sel.`2`[0], UInt<1>(0h0) connect states[3].vc_sel.`2`[1], UInt<1>(0h0) connect states[3].vc_sel.`2`[2], UInt<1>(0h0) connect states[3].vc_sel.`2`[3], UInt<1>(0h0) connect states[3].vc_sel.`2`[4], UInt<1>(0h0) connect states[3].vc_sel.`2`[5], UInt<1>(0h0) connect states[3].vc_sel.`2`[6], UInt<1>(0h0) connect states[3].vc_sel.`2`[7], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[2], UInt<1>(0h0) connect states[4].vc_sel.`1`[3], UInt<1>(0h0) connect states[4].vc_sel.`1`[4], UInt<1>(0h0) connect states[4].vc_sel.`1`[5], UInt<1>(0h0) connect states[4].vc_sel.`1`[6], UInt<1>(0h0) connect states[4].vc_sel.`1`[7], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[1], UInt<1>(0h0) connect states[4].vc_sel.`2`[2], UInt<1>(0h0) connect states[4].vc_sel.`2`[3], UInt<1>(0h0) connect states[4].vc_sel.`2`[4], UInt<1>(0h0) connect states[4].vc_sel.`2`[5], UInt<1>(0h0) connect states[4].vc_sel.`2`[6], UInt<1>(0h0) connect states[4].vc_sel.`2`[7], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[1], UInt<1>(0h0) connect states[5].vc_sel.`1`[2], UInt<1>(0h0) connect states[5].vc_sel.`1`[3], UInt<1>(0h0) connect states[5].vc_sel.`1`[4], UInt<1>(0h0) connect states[5].vc_sel.`2`[0], UInt<1>(0h0) connect states[5].vc_sel.`2`[1], UInt<1>(0h0) connect states[5].vc_sel.`2`[2], UInt<1>(0h0) connect states[5].vc_sel.`2`[3], UInt<1>(0h0) connect states[5].vc_sel.`2`[4], UInt<1>(0h0) connect states[5].vc_sel.`2`[5], UInt<1>(0h0) connect states[5].vc_sel.`2`[6], UInt<1>(0h0) connect states[5].vc_sel.`2`[7], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[1], UInt<1>(0h0) connect states[6].vc_sel.`1`[2], UInt<1>(0h0) connect states[6].vc_sel.`1`[3], UInt<1>(0h0) connect states[6].vc_sel.`1`[4], UInt<1>(0h0) connect states[6].vc_sel.`2`[0], UInt<1>(0h0) connect states[6].vc_sel.`2`[1], UInt<1>(0h0) connect states[6].vc_sel.`2`[2], UInt<1>(0h0) connect states[6].vc_sel.`2`[3], UInt<1>(0h0) connect states[6].vc_sel.`2`[4], UInt<1>(0h0) connect states[6].vc_sel.`2`[5], UInt<1>(0h0) connect states[6].vc_sel.`2`[6], UInt<1>(0h0) connect states[6].vc_sel.`2`[7], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[1], UInt<1>(0h0) connect states[7].vc_sel.`1`[2], UInt<1>(0h0) connect states[7].vc_sel.`1`[3], UInt<1>(0h0) connect states[7].vc_sel.`1`[4], UInt<1>(0h0) connect states[7].vc_sel.`2`[0], UInt<1>(0h0) connect states[7].vc_sel.`2`[1], UInt<1>(0h0) connect states[7].vc_sel.`2`[2], UInt<1>(0h0) connect states[7].vc_sel.`2`[3], UInt<1>(0h0) connect states[7].vc_sel.`2`[4], UInt<1>(0h0) connect states[7].vc_sel.`2`[5], UInt<1>(0h0) connect states[7].vc_sel.`2`[6], UInt<1>(0h0) connect states[7].vc_sel.`2`[7], UInt<1>(0h0) node _T_120 = asUInt(reset) when _T_120 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0)	module InputUnit_34( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_1, // @[InputUnit.scala:170:14] input io_out_credit_available_4_2, // @[InputUnit.scala:170:14] input io_out_credit_available_4_3, // @[InputUnit.scala:170:14] input io_out_credit_available_4_4, // @[InputUnit.scala:170:14] input io_out_credit_available_4_5, // @[InputUnit.scala:170:14] input io_out_credit_available_4_6, // @[InputUnit.scala:170:14] input io_out_credit_available_4_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_3_3, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] \| vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 \| vcalloc_vals_1 \| vcalloc_vals_2 \| vcalloc_vals_3 \| vcalloc_vals_4 \| vcalloc_vals_5 \| vcalloc_vals_6 \| vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_17 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_27 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_17( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_27 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<4>(0h8)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<4>(0h9)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<4>(0ha)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<4>(0hb)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h1)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 3) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h7)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 node _source_ok_T_43 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[2]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[3]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[4]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[5]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_48, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<4>(0h8)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<4>(0h9)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<4>(0ha)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<4>(0hb)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<2>(0h2)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_77 = shr(io.in.a.bits.source, 3) node _T_78 = eq(_T_77, UInt<1>(0h1)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_90 = shr(io.in.a.bits.source, 3) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<3>(0h7)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _T_103 = and(_T_11, _T_24) node _T_104 = and(_T_103, _T_37) node _T_105 = and(_T_104, _T_50) node _T_106 = and(_T_105, _T_63) node _T_107 = and(_T_106, _T_76) node _T_108 = and(_T_107, _T_89) node _T_109 = and(_T_108, _T_102) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_109, UInt<1>(0h1), "") : assert_1 node _T_113 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_113 : node _T_114 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_115 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_116 = and(_T_114, _T_115) node _T_117 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<4>(0h8)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_7) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<4>(0h9)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_8) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<4>(0ha)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_9) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_136 = shr(io.in.a.bits.source, 2) node _T_137 = eq(_T_136, UInt<4>(0hb)) node _T_138 = leq(UInt<1>(0h0), uncommonBits_10) node _T_139 = and(_T_137, _T_138) node _T_140 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_141 = and(_T_139, _T_140) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_142 = shr(io.in.a.bits.source, 3) node _T_143 = eq(_T_142, UInt<2>(0h2)) node _T_144 = leq(UInt<1>(0h0), uncommonBits_11) node _T_145 = and(_T_143, _T_144) node _T_146 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_147 = and(_T_145, _T_146) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_148 = shr(io.in.a.bits.source, 3) node _T_149 = eq(_T_148, UInt<1>(0h1)) node _T_150 = leq(UInt<1>(0h0), uncommonBits_12) node _T_151 = and(_T_149, _T_150) node _T_152 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_153 = and(_T_151, _T_152) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_154 = shr(io.in.a.bits.source, 3) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = leq(UInt<1>(0h0), uncommonBits_13) node _T_157 = and(_T_155, _T_156) node _T_158 = leq(uncommonBits_13, UInt<3>(0h7)) node _T_159 = and(_T_157, _T_158) node _T_160 = or(_T_117, _T_123) node _T_161 = or(_T_160, _T_129) node _T_162 = or(_T_161, _T_135) node _T_163 = or(_T_162, _T_141) node _T_164 = or(_T_163, _T_147) node _T_165 = or(_T_164, _T_153) node _T_166 = or(_T_165, _T_159) node _T_167 = and(_T_116, _T_166) node _T_168 = or(UInt<1>(0h0), _T_167) node _T_169 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<14>(0h2000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<13>(0h1000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<17>(0h10000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_186 = cvt(_T_185) node _T_187 = and(_T_186, asSInt(UInt<18>(0h2f000))) node _T_188 = asSInt(_T_187) node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0))) node _T_190 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_191 = cvt(_T_190) node _T_192 = and(_T_191, asSInt(UInt<17>(0h10000))) node _T_193 = asSInt(_T_192) node _T_194 = eq(_T_193, asSInt(UInt<1>(0h0))) node _T_195 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_196 = cvt(_T_195) node _T_197 = and(_T_196, asSInt(UInt<13>(0h1000))) node _T_198 = asSInt(_T_197) node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0))) node _T_200 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_201 = cvt(_T_200) node _T_202 = and(_T_201, asSInt(UInt<27>(0h4000000))) node _T_203 = asSInt(_T_202) node _T_204 = eq(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_206 = cvt(_T_205) node _T_207 = and(_T_206, asSInt(UInt<13>(0h1000))) node _T_208 = asSInt(_T_207) node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0))) node _T_210 = or(_T_174, _T_179) node _T_211 = or(_T_210, _T_184) node _T_212 = or(_T_211, _T_189) node _T_213 = or(_T_212, _T_194) node _T_214 = or(_T_213, _T_199) node _T_215 = or(_T_214, _T_204) node _T_216 = or(_T_215, _T_209) node _T_217 = and(_T_169, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = and(_T_168, _T_218) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_219, UInt<1>(0h1), "") : assert_2 node _T_223 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<4>(0h8)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_14) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_230 = shr(io.in.a.bits.source, 2) node _T_231 = eq(_T_230, UInt<4>(0h9)) node _T_232 = leq(UInt<1>(0h0), uncommonBits_15) node _T_233 = and(_T_231, _T_232) node _T_234 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<4>(0ha)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_16) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<4>(0hb)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_17) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_248 = shr(io.in.a.bits.source, 3) node _T_249 = eq(_T_248, UInt<2>(0h2)) node _T_250 = leq(UInt<1>(0h0), uncommonBits_18) node _T_251 = and(_T_249, _T_250) node _T_252 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_253 = and(_T_251, _T_252) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_254 = shr(io.in.a.bits.source, 3) node _T_255 = eq(_T_254, UInt<1>(0h1)) node _T_256 = leq(UInt<1>(0h0), uncommonBits_19) node _T_257 = and(_T_255, _T_256) node _T_258 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_259 = and(_T_257, _T_258) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_260 = shr(io.in.a.bits.source, 3) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = leq(UInt<1>(0h0), uncommonBits_20) node _T_263 = and(_T_261, _T_262) node _T_264 = leq(uncommonBits_20, UInt<3>(0h7)) node _T_265 = and(_T_263, _T_264) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_223 connect _WIRE[1], _T_229 connect _WIRE[2], _T_235 connect _WIRE[3], _T_241 connect _WIRE[4], _T_247 connect _WIRE[5], _T_253 connect _WIRE[6], _T_259 connect _WIRE[7], _T_265 node _T_266 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_267 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_268 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_269 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_270 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_271 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_272 = mux(_WIRE[5], _T_266, UInt<1>(0h0)) node _T_273 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_274 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_275 = or(_T_267, _T_268) node _T_276 = or(_T_275, _T_269) node _T_277 = or(_T_276, _T_270) node _T_278 = or(_T_277, _T_271) node _T_279 = or(_T_278, _T_272) node _T_280 = or(_T_279, _T_273) node _T_281 = or(_T_280, _T_274) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_281 node _T_282 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_283 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_284 = and(_T_282, _T_283) node _T_285 = or(UInt<1>(0h0), _T_284) node _T_286 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<14>(0h2000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<18>(0h2f000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<17>(0h10000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<27>(0h4000000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<13>(0h1000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = or(_T_290, _T_295) node _T_327 = or(_T_326, _T_300) node _T_328 = or(_T_327, _T_305) node _T_329 = or(_T_328, _T_310) node _T_330 = or(_T_329, _T_315) node _T_331 = or(_T_330, _T_320) node _T_332 = or(_T_331, _T_325) node _T_333 = and(_T_285, _T_332) node _T_334 = or(UInt<1>(0h0), _T_333) node _T_335 = and(_WIRE_1, _T_334) node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_T_335, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_335, UInt<1>(0h1), "") : assert_3 node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(source_ok, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_342 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_342, UInt<1>(0h1), "") : assert_5 node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(is_aligned, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_349 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_349, UInt<1>(0h1), "") : assert_7 node _T_353 = not(io.in.a.bits.mask) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_354, UInt<1>(0h1), "") : assert_8 node _T_358 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_T_358, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_358, UInt<1>(0h1), "") : assert_9 node _T_362 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_362 : node _T_363 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_364 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_367 = shr(io.in.a.bits.source, 2) node _T_368 = eq(_T_367, UInt<4>(0h8)) node _T_369 = leq(UInt<1>(0h0), uncommonBits_21) node _T_370 = and(_T_368, _T_369) node _T_371 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_372 = and(_T_370, _T_371) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_373 = shr(io.in.a.bits.source, 2) node _T_374 = eq(_T_373, UInt<4>(0h9)) node _T_375 = leq(UInt<1>(0h0), uncommonBits_22) node _T_376 = and(_T_374, _T_375) node _T_377 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_378 = and(_T_376, _T_377) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_379 = shr(io.in.a.bits.source, 2) node _T_380 = eq(_T_379, UInt<4>(0ha)) node _T_381 = leq(UInt<1>(0h0), uncommonBits_23) node _T_382 = and(_T_380, _T_381) node _T_383 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_384 = and(_T_382, _T_383) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_385 = shr(io.in.a.bits.source, 2) node _T_386 = eq(_T_385, UInt<4>(0hb)) node _T_387 = leq(UInt<1>(0h0), uncommonBits_24) node _T_388 = and(_T_386, _T_387) node _T_389 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_390 = and(_T_388, _T_389) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_391 = shr(io.in.a.bits.source, 3) node _T_392 = eq(_T_391, UInt<2>(0h2)) node _T_393 = leq(UInt<1>(0h0), uncommonBits_25) node _T_394 = and(_T_392, _T_393) node _T_395 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_396 = and(_T_394, _T_395) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_397 = shr(io.in.a.bits.source, 3) node _T_398 = eq(_T_397, UInt<1>(0h1)) node _T_399 = leq(UInt<1>(0h0), uncommonBits_26) node _T_400 = and(_T_398, _T_399) node _T_401 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_402 = and(_T_400, _T_401) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_403 = shr(io.in.a.bits.source, 3) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = leq(UInt<1>(0h0), uncommonBits_27) node _T_406 = and(_T_404, _T_405) node _T_407 = leq(uncommonBits_27, UInt<3>(0h7)) node _T_408 = and(_T_406, _T_407) node _T_409 = or(_T_366, _T_372) node _T_410 = or(_T_409, _T_378) node _T_411 = or(_T_410, _T_384) node _T_412 = or(_T_411, _T_390) node _T_413 = or(_T_412, _T_396) node _T_414 = or(_T_413, _T_402) node _T_415 = or(_T_414, _T_408) node _T_416 = and(_T_365, _T_415) node _T_417 = or(UInt<1>(0h0), _T_416) node _T_418 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_419 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<14>(0h2000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<13>(0h1000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<17>(0h10000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<18>(0h2f000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<17>(0h10000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<13>(0h1000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_450 = cvt(_T_449) node _T_451 = and(_T_450, asSInt(UInt<27>(0h4000000))) node _T_452 = asSInt(_T_451) node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) node _T_454 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<13>(0h1000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = or(_T_423, _T_428) node _T_460 = or(_T_459, _T_433) node _T_461 = or(_T_460, _T_438) node _T_462 = or(_T_461, _T_443) node _T_463 = or(_T_462, _T_448) node _T_464 = or(_T_463, _T_453) node _T_465 = or(_T_464, _T_458) node _T_466 = and(_T_418, _T_465) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = and(_T_417, _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_468, UInt<1>(0h1), "") : assert_10 node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_473 = shr(io.in.a.bits.source, 2) node _T_474 = eq(_T_473, UInt<4>(0h8)) node _T_475 = leq(UInt<1>(0h0), uncommonBits_28) node _T_476 = and(_T_474, _T_475) node _T_477 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_478 = and(_T_476, _T_477) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_479 = shr(io.in.a.bits.source, 2) node _T_480 = eq(_T_479, UInt<4>(0h9)) node _T_481 = leq(UInt<1>(0h0), uncommonBits_29) node _T_482 = and(_T_480, _T_481) node _T_483 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_484 = and(_T_482, _T_483) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_485 = shr(io.in.a.bits.source, 2) node _T_486 = eq(_T_485, UInt<4>(0ha)) node _T_487 = leq(UInt<1>(0h0), uncommonBits_30) node _T_488 = and(_T_486, _T_487) node _T_489 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_490 = and(_T_488, _T_489) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_491 = shr(io.in.a.bits.source, 2) node _T_492 = eq(_T_491, UInt<4>(0hb)) node _T_493 = leq(UInt<1>(0h0), uncommonBits_31) node _T_494 = and(_T_492, _T_493) node _T_495 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_496 = and(_T_494, _T_495) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_497 = shr(io.in.a.bits.source, 3) node _T_498 = eq(_T_497, UInt<2>(0h2)) node _T_499 = leq(UInt<1>(0h0), uncommonBits_32) node _T_500 = and(_T_498, _T_499) node _T_501 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_502 = and(_T_500, _T_501) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_503 = shr(io.in.a.bits.source, 3) node _T_504 = eq(_T_503, UInt<1>(0h1)) node _T_505 = leq(UInt<1>(0h0), uncommonBits_33) node _T_506 = and(_T_504, _T_505) node _T_507 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_508 = and(_T_506, _T_507) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_509 = shr(io.in.a.bits.source, 3) node _T_510 = eq(_T_509, UInt<1>(0h0)) node _T_511 = leq(UInt<1>(0h0), uncommonBits_34) node _T_512 = and(_T_510, _T_511) node _T_513 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_514 = and(_T_512, _T_513) wire _WIRE_2 : UInt<1>[8] connect _WIRE_2[0], _T_472 connect _WIRE_2[1], _T_478 connect _WIRE_2[2], _T_484 connect _WIRE_2[3], _T_490 connect _WIRE_2[4], _T_496 connect _WIRE_2[5], _T_502 connect _WIRE_2[6], _T_508 connect _WIRE_2[7], _T_514 node _T_515 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_516 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_517 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_518 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_520 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_521 = mux(_WIRE_2[5], _T_515, UInt<1>(0h0)) node _T_522 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_524 = or(_T_516, _T_517) node _T_525 = or(_T_524, _T_518) node _T_526 = or(_T_525, _T_519) node _T_527 = or(_T_526, _T_520) node _T_528 = or(_T_527, _T_521) node _T_529 = or(_T_528, _T_522) node _T_530 = or(_T_529, _T_523) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_530 node _T_531 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_532 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_533 = and(_T_531, _T_532) node _T_534 = or(UInt<1>(0h0), _T_533) node _T_535 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_536 = cvt(_T_535) node _T_537 = and(_T_536, asSInt(UInt<14>(0h2000))) node _T_538 = asSInt(_T_537) node _T_539 = eq(_T_538, asSInt(UInt<1>(0h0))) node _T_540 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_541 = cvt(_T_540) node _T_542 = and(_T_541, asSInt(UInt<13>(0h1000))) node _T_543 = asSInt(_T_542) node _T_544 = eq(_T_543, asSInt(UInt<1>(0h0))) node _T_545 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_546 = cvt(_T_545) node _T_547 = and(_T_546, asSInt(UInt<17>(0h10000))) node _T_548 = asSInt(_T_547) node _T_549 = eq(_T_548, asSInt(UInt<1>(0h0))) node _T_550 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_551 = cvt(_T_550) node _T_552 = and(_T_551, asSInt(UInt<18>(0h2f000))) node _T_553 = asSInt(_T_552) node _T_554 = eq(_T_553, asSInt(UInt<1>(0h0))) node _T_555 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_556 = cvt(_T_555) node _T_557 = and(_T_556, asSInt(UInt<17>(0h10000))) node _T_558 = asSInt(_T_557) node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0))) node _T_560 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_561 = cvt(_T_560) node _T_562 = and(_T_561, asSInt(UInt<13>(0h1000))) node _T_563 = asSInt(_T_562) node _T_564 = eq(_T_563, asSInt(UInt<1>(0h0))) node _T_565 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_566 = cvt(_T_565) node _T_567 = and(_T_566, asSInt(UInt<27>(0h4000000))) node _T_568 = asSInt(_T_567) node _T_569 = eq(_T_568, asSInt(UInt<1>(0h0))) node _T_570 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_571 = cvt(_T_570) node _T_572 = and(_T_571, asSInt(UInt<13>(0h1000))) node _T_573 = asSInt(_T_572) node _T_574 = eq(_T_573, asSInt(UInt<1>(0h0))) node _T_575 = or(_T_539, _T_544) node _T_576 = or(_T_575, _T_549) node _T_577 = or(_T_576, _T_554) node _T_578 = or(_T_577, _T_559) node _T_579 = or(_T_578, _T_564) node _T_580 = or(_T_579, _T_569) node _T_581 = or(_T_580, _T_574) node _T_582 = and(_T_534, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = and(_WIRE_3, _T_583) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_584, UInt<1>(0h1), "") : assert_11 node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(source_ok, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_591 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(_T_591, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_591, UInt<1>(0h1), "") : assert_13 node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(is_aligned, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_598 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_598, UInt<1>(0h1), "") : assert_15 node _T_602 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_602, UInt<1>(0h1), "") : assert_16 node _T_606 = not(io.in.a.bits.mask) node _T_607 = eq(_T_606, UInt<1>(0h0)) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(_T_607, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_607, UInt<1>(0h1), "") : assert_17 node _T_611 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_611, UInt<1>(0h1), "") : assert_18 node _T_615 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<4>(0h8)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_35) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<4>(0h9)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_36) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<4>(0ha)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_37) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<4>(0hb)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_38) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_644 = shr(io.in.a.bits.source, 3) node _T_645 = eq(_T_644, UInt<2>(0h2)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_39) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_649 = and(_T_647, _T_648) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_650 = shr(io.in.a.bits.source, 3) node _T_651 = eq(_T_650, UInt<1>(0h1)) node _T_652 = leq(UInt<1>(0h0), uncommonBits_40) node _T_653 = and(_T_651, _T_652) node _T_654 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_655 = and(_T_653, _T_654) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_656 = shr(io.in.a.bits.source, 3) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = leq(UInt<1>(0h0), uncommonBits_41) node _T_659 = and(_T_657, _T_658) node _T_660 = leq(uncommonBits_41, UInt<3>(0h7)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(_T_619, _T_625) node _T_663 = or(_T_662, _T_631) node _T_664 = or(_T_663, _T_637) node _T_665 = or(_T_664, _T_643) node _T_666 = or(_T_665, _T_649) node _T_667 = or(_T_666, _T_655) node _T_668 = or(_T_667, _T_661) node _T_669 = and(_T_618, _T_668) node _T_670 = or(UInt<1>(0h0), _T_669) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_670, UInt<1>(0h1), "") : assert_19 node _T_674 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_675 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_676 = and(_T_674, _T_675) node _T_677 = or(UInt<1>(0h0), _T_676) node _T_678 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<13>(0h1000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = and(_T_677, _T_682) node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_685 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_686 = and(_T_684, _T_685) node _T_687 = or(UInt<1>(0h0), _T_686) node _T_688 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<14>(0h2000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<17>(0h10000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<18>(0h2f000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<17>(0h10000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<13>(0h1000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<27>(0h4000000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = or(_T_692, _T_697) node _T_724 = or(_T_723, _T_702) node _T_725 = or(_T_724, _T_707) node _T_726 = or(_T_725, _T_712) node _T_727 = or(_T_726, _T_717) node _T_728 = or(_T_727, _T_722) node _T_729 = and(_T_687, _T_728) node _T_730 = or(UInt<1>(0h0), _T_683) node _T_731 = or(_T_730, _T_729) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_731, UInt<1>(0h1), "") : assert_20 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(source_ok, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_741 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_741, UInt<1>(0h1), "") : assert_23 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_745, UInt<1>(0h1), "") : assert_24 node _T_749 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_749, UInt<1>(0h1), "") : assert_25 node _T_753 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<4>(0h8)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_42) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<4>(0h9)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_43) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<4>(0ha)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_44) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<4>(0hb)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_45) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_782 = shr(io.in.a.bits.source, 3) node _T_783 = eq(_T_782, UInt<2>(0h2)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_46) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_788 = shr(io.in.a.bits.source, 3) node _T_789 = eq(_T_788, UInt<1>(0h1)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_47) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_793 = and(_T_791, _T_792) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_794 = shr(io.in.a.bits.source, 3) node _T_795 = eq(_T_794, UInt<1>(0h0)) node _T_796 = leq(UInt<1>(0h0), uncommonBits_48) node _T_797 = and(_T_795, _T_796) node _T_798 = leq(uncommonBits_48, UInt<3>(0h7)) node _T_799 = and(_T_797, _T_798) node _T_800 = or(_T_757, _T_763) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_775) node _T_803 = or(_T_802, _T_781) node _T_804 = or(_T_803, _T_787) node _T_805 = or(_T_804, _T_793) node _T_806 = or(_T_805, _T_799) node _T_807 = and(_T_756, _T_806) node _T_808 = or(UInt<1>(0h0), _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<13>(0h1000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = and(_T_812, _T_817) node _T_819 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_820 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_821 = and(_T_819, _T_820) node _T_822 = or(UInt<1>(0h0), _T_821) node _T_823 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_824 = cvt(_T_823) node _T_825 = and(_T_824, asSInt(UInt<14>(0h2000))) node _T_826 = asSInt(_T_825) node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) node _T_828 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_829 = cvt(_T_828) node _T_830 = and(_T_829, asSInt(UInt<18>(0h2f000))) node _T_831 = asSInt(_T_830) node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) node _T_833 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_834 = cvt(_T_833) node _T_835 = and(_T_834, asSInt(UInt<17>(0h10000))) node _T_836 = asSInt(_T_835) node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0))) node _T_838 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_839 = cvt(_T_838) node _T_840 = and(_T_839, asSInt(UInt<13>(0h1000))) node _T_841 = asSInt(_T_840) node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) node _T_843 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<27>(0h4000000))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_849 = cvt(_T_848) node _T_850 = and(_T_849, asSInt(UInt<13>(0h1000))) node _T_851 = asSInt(_T_850) node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0))) node _T_853 = or(_T_827, _T_832) node _T_854 = or(_T_853, _T_837) node _T_855 = or(_T_854, _T_842) node _T_856 = or(_T_855, _T_847) node _T_857 = or(_T_856, _T_852) node _T_858 = and(_T_822, _T_857) node _T_859 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_860 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<17>(0h10000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = and(_T_859, _T_864) node _T_866 = or(UInt<1>(0h0), _T_818) node _T_867 = or(_T_866, _T_858) node _T_868 = or(_T_867, _T_865) node _T_869 = and(_T_808, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_869, UInt<1>(0h1), "") : assert_26 node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(source_ok, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(is_aligned, UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_879 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_880 = asUInt(reset) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(_T_879, UInt<1>(0h0)) when _T_882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_879, UInt<1>(0h1), "") : assert_29 node _T_883 = eq(io.in.a.bits.mask, mask) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_883, UInt<1>(0h1), "") : assert_30 node _T_887 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_887 : node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_892 = shr(io.in.a.bits.source, 2) node _T_893 = eq(_T_892, UInt<4>(0h8)) node _T_894 = leq(UInt<1>(0h0), uncommonBits_49) node _T_895 = and(_T_893, _T_894) node _T_896 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_897 = and(_T_895, _T_896) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_898 = shr(io.in.a.bits.source, 2) node _T_899 = eq(_T_898, UInt<4>(0h9)) node _T_900 = leq(UInt<1>(0h0), uncommonBits_50) node _T_901 = and(_T_899, _T_900) node _T_902 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_903 = and(_T_901, _T_902) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_904 = shr(io.in.a.bits.source, 2) node _T_905 = eq(_T_904, UInt<4>(0ha)) node _T_906 = leq(UInt<1>(0h0), uncommonBits_51) node _T_907 = and(_T_905, _T_906) node _T_908 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_909 = and(_T_907, _T_908) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_910 = shr(io.in.a.bits.source, 2) node _T_911 = eq(_T_910, UInt<4>(0hb)) node _T_912 = leq(UInt<1>(0h0), uncommonBits_52) node _T_913 = and(_T_911, _T_912) node _T_914 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_915 = and(_T_913, _T_914) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_916 = shr(io.in.a.bits.source, 3) node _T_917 = eq(_T_916, UInt<2>(0h2)) node _T_918 = leq(UInt<1>(0h0), uncommonBits_53) node _T_919 = and(_T_917, _T_918) node _T_920 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_921 = and(_T_919, _T_920) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_922 = shr(io.in.a.bits.source, 3) node _T_923 = eq(_T_922, UInt<1>(0h1)) node _T_924 = leq(UInt<1>(0h0), uncommonBits_54) node _T_925 = and(_T_923, _T_924) node _T_926 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_927 = and(_T_925, _T_926) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0) node _T_928 = shr(io.in.a.bits.source, 3) node _T_929 = eq(_T_928, UInt<1>(0h0)) node _T_930 = leq(UInt<1>(0h0), uncommonBits_55) node _T_931 = and(_T_929, _T_930) node _T_932 = leq(uncommonBits_55, UInt<3>(0h7)) node _T_933 = and(_T_931, _T_932) node _T_934 = or(_T_891, _T_897) node _T_935 = or(_T_934, _T_903) node _T_936 = or(_T_935, _T_909) node _T_937 = or(_T_936, _T_915) node _T_938 = or(_T_937, _T_921) node _T_939 = or(_T_938, _T_927) node _T_940 = or(_T_939, _T_933) node _T_941 = and(_T_890, _T_940) node _T_942 = or(UInt<1>(0h0), _T_941) node _T_943 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_944 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_945 = and(_T_943, _T_944) node _T_946 = or(UInt<1>(0h0), _T_945) node _T_947 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<13>(0h1000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = and(_T_946, _T_951) node _T_953 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_954 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_955 = and(_T_953, _T_954) node _T_956 = or(UInt<1>(0h0), _T_955) node _T_957 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_958 = cvt(_T_957) node _T_959 = and(_T_958, asSInt(UInt<14>(0h2000))) node _T_960 = asSInt(_T_959) node _T_961 = eq(_T_960, asSInt(UInt<1>(0h0))) node _T_962 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_963 = cvt(_T_962) node _T_964 = and(_T_963, asSInt(UInt<18>(0h2f000))) node _T_965 = asSInt(_T_964) node _T_966 = eq(_T_965, asSInt(UInt<1>(0h0))) node _T_967 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_968 = cvt(_T_967) node _T_969 = and(_T_968, asSInt(UInt<17>(0h10000))) node _T_970 = asSInt(_T_969) node _T_971 = eq(_T_970, asSInt(UInt<1>(0h0))) node _T_972 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_973 = cvt(_T_972) node _T_974 = and(_T_973, asSInt(UInt<13>(0h1000))) node _T_975 = asSInt(_T_974) node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0))) node _T_977 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<27>(0h4000000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = or(_T_961, _T_966) node _T_988 = or(_T_987, _T_971) node _T_989 = or(_T_988, _T_976) node _T_990 = or(_T_989, _T_981) node _T_991 = or(_T_990, _T_986) node _T_992 = and(_T_956, _T_991) node _T_993 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_994 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = and(_T_993, _T_998) node _T_1000 = or(UInt<1>(0h0), _T_952) node _T_1001 = or(_T_1000, _T_992) node _T_1002 = or(_T_1001, _T_999) node _T_1003 = and(_T_942, _T_1002) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_31 node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(source_ok, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(is_aligned, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1013 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_34 node _T_1017 = not(mask) node _T_1018 = and(io.in.a.bits.mask, _T_1017) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_35 node _T_1023 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1023 : node _T_1024 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1025 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1026 = and(_T_1024, _T_1025) node _T_1027 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1028 = shr(io.in.a.bits.source, 2) node _T_1029 = eq(_T_1028, UInt<4>(0h8)) node _T_1030 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1033 = and(_T_1031, _T_1032) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1034 = shr(io.in.a.bits.source, 2) node _T_1035 = eq(_T_1034, UInt<4>(0h9)) node _T_1036 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1037 = and(_T_1035, _T_1036) node _T_1038 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1039 = and(_T_1037, _T_1038) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1040 = shr(io.in.a.bits.source, 2) node _T_1041 = eq(_T_1040, UInt<4>(0ha)) node _T_1042 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1045 = and(_T_1043, _T_1044) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1046 = shr(io.in.a.bits.source, 2) node _T_1047 = eq(_T_1046, UInt<4>(0hb)) node _T_1048 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1051 = and(_T_1049, _T_1050) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0) node _T_1052 = shr(io.in.a.bits.source, 3) node _T_1053 = eq(_T_1052, UInt<2>(0h2)) node _T_1054 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1055 = and(_T_1053, _T_1054) node _T_1056 = leq(uncommonBits_60, UInt<3>(0h7)) node _T_1057 = and(_T_1055, _T_1056) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0) node _T_1058 = shr(io.in.a.bits.source, 3) node _T_1059 = eq(_T_1058, UInt<1>(0h1)) node _T_1060 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1061 = and(_T_1059, _T_1060) node _T_1062 = leq(uncommonBits_61, UInt<3>(0h7)) node _T_1063 = and(_T_1061, _T_1062) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0) node _T_1064 = shr(io.in.a.bits.source, 3) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) node _T_1066 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1067 = and(_T_1065, _T_1066) node _T_1068 = leq(uncommonBits_62, UInt<3>(0h7)) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = or(_T_1027, _T_1033) node _T_1071 = or(_T_1070, _T_1039) node _T_1072 = or(_T_1071, _T_1045) node _T_1073 = or(_T_1072, _T_1051) node _T_1074 = or(_T_1073, _T_1057) node _T_1075 = or(_T_1074, _T_1063) node _T_1076 = or(_T_1075, _T_1069) node _T_1077 = and(_T_1026, _T_1076) node _T_1078 = or(UInt<1>(0h0), _T_1077) node _T_1079 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1080 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1081 = and(_T_1079, _T_1080) node _T_1082 = or(UInt<1>(0h0), _T_1081) node _T_1083 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1084 = cvt(_T_1083) node _T_1085 = and(_T_1084, asSInt(UInt<14>(0h2000))) node _T_1086 = asSInt(_T_1085) node _T_1087 = eq(_T_1086, asSInt(UInt<1>(0h0))) node _T_1088 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1089 = cvt(_T_1088) node _T_1090 = and(_T_1089, asSInt(UInt<13>(0h1000))) node _T_1091 = asSInt(_T_1090) node _T_1092 = eq(_T_1091, asSInt(UInt<1>(0h0))) node _T_1093 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1094 = cvt(_T_1093) node _T_1095 = and(_T_1094, asSInt(UInt<18>(0h2f000))) node _T_1096 = asSInt(_T_1095) node _T_1097 = eq(_T_1096, asSInt(UInt<1>(0h0))) node _T_1098 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1099 = cvt(_T_1098) node _T_1100 = and(_T_1099, asSInt(UInt<17>(0h10000))) node _T_1101 = asSInt(_T_1100) node _T_1102 = eq(_T_1101, asSInt(UInt<1>(0h0))) node _T_1103 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1104 = cvt(_T_1103) node _T_1105 = and(_T_1104, asSInt(UInt<13>(0h1000))) node _T_1106 = asSInt(_T_1105) node _T_1107 = eq(_T_1106, asSInt(UInt<1>(0h0))) node _T_1108 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1109 = cvt(_T_1108) node _T_1110 = and(_T_1109, asSInt(UInt<27>(0h4000000))) node _T_1111 = asSInt(_T_1110) node _T_1112 = eq(_T_1111, asSInt(UInt<1>(0h0))) node _T_1113 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1114 = cvt(_T_1113) node _T_1115 = and(_T_1114, asSInt(UInt<13>(0h1000))) node _T_1116 = asSInt(_T_1115) node _T_1117 = eq(_T_1116, asSInt(UInt<1>(0h0))) node _T_1118 = or(_T_1087, _T_1092) node _T_1119 = or(_T_1118, _T_1097) node _T_1120 = or(_T_1119, _T_1102) node _T_1121 = or(_T_1120, _T_1107) node _T_1122 = or(_T_1121, _T_1112) node _T_1123 = or(_T_1122, _T_1117) node _T_1124 = and(_T_1082, _T_1123) node _T_1125 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1126 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1127 = cvt(_T_1126) node _T_1128 = and(_T_1127, asSInt(UInt<17>(0h10000))) node _T_1129 = asSInt(_T_1128) node _T_1130 = eq(_T_1129, asSInt(UInt<1>(0h0))) node _T_1131 = and(_T_1125, _T_1130) node _T_1132 = or(UInt<1>(0h0), _T_1124) node _T_1133 = or(_T_1132, _T_1131) node _T_1134 = and(_T_1078, _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_36 node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(source_ok, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(is_aligned, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1144 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_39 node _T_1148 = eq(io.in.a.bits.mask, mask) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_40 node _T_1152 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1152 : node _T_1153 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1154 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1157 = shr(io.in.a.bits.source, 2) node _T_1158 = eq(_T_1157, UInt<4>(0h8)) node _T_1159 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1160 = and(_T_1158, _T_1159) node _T_1161 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1162 = and(_T_1160, _T_1161) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_1163 = shr(io.in.a.bits.source, 2) node _T_1164 = eq(_T_1163, UInt<4>(0h9)) node _T_1165 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1166 = and(_T_1164, _T_1165) node _T_1167 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_1168 = and(_T_1166, _T_1167) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1169 = shr(io.in.a.bits.source, 2) node _T_1170 = eq(_T_1169, UInt<4>(0ha)) node _T_1171 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1172 = and(_T_1170, _T_1171) node _T_1173 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1174 = and(_T_1172, _T_1173) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1175 = shr(io.in.a.bits.source, 2) node _T_1176 = eq(_T_1175, UInt<4>(0hb)) node _T_1177 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1178 = and(_T_1176, _T_1177) node _T_1179 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1180 = and(_T_1178, _T_1179) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0) node _T_1181 = shr(io.in.a.bits.source, 3) node _T_1182 = eq(_T_1181, UInt<2>(0h2)) node _T_1183 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1184 = and(_T_1182, _T_1183) node _T_1185 = leq(uncommonBits_67, UInt<3>(0h7)) node _T_1186 = and(_T_1184, _T_1185) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0) node _T_1187 = shr(io.in.a.bits.source, 3) node _T_1188 = eq(_T_1187, UInt<1>(0h1)) node _T_1189 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1190 = and(_T_1188, _T_1189) node _T_1191 = leq(uncommonBits_68, UInt<3>(0h7)) node _T_1192 = and(_T_1190, _T_1191) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1193 = shr(io.in.a.bits.source, 3) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) node _T_1195 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1196 = and(_T_1194, _T_1195) node _T_1197 = leq(uncommonBits_69, UInt<3>(0h7)) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = or(_T_1156, _T_1162) node _T_1200 = or(_T_1199, _T_1168) node _T_1201 = or(_T_1200, _T_1174) node _T_1202 = or(_T_1201, _T_1180) node _T_1203 = or(_T_1202, _T_1186) node _T_1204 = or(_T_1203, _T_1192) node _T_1205 = or(_T_1204, _T_1198) node _T_1206 = and(_T_1155, _T_1205) node _T_1207 = or(UInt<1>(0h0), _T_1206) node _T_1208 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1209 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = or(UInt<1>(0h0), _T_1210) node _T_1212 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<14>(0h2000))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1218 = cvt(_T_1217) node _T_1219 = and(_T_1218, asSInt(UInt<13>(0h1000))) node _T_1220 = asSInt(_T_1219) node _T_1221 = eq(_T_1220, asSInt(UInt<1>(0h0))) node _T_1222 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<18>(0h2f000))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1228 = cvt(_T_1227) node _T_1229 = and(_T_1228, asSInt(UInt<17>(0h10000))) node _T_1230 = asSInt(_T_1229) node _T_1231 = eq(_T_1230, asSInt(UInt<1>(0h0))) node _T_1232 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1233 = cvt(_T_1232) node _T_1234 = and(_T_1233, asSInt(UInt<13>(0h1000))) node _T_1235 = asSInt(_T_1234) node _T_1236 = eq(_T_1235, asSInt(UInt<1>(0h0))) node _T_1237 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1238 = cvt(_T_1237) node _T_1239 = and(_T_1238, asSInt(UInt<27>(0h4000000))) node _T_1240 = asSInt(_T_1239) node _T_1241 = eq(_T_1240, asSInt(UInt<1>(0h0))) node _T_1242 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1243 = cvt(_T_1242) node _T_1244 = and(_T_1243, asSInt(UInt<13>(0h1000))) node _T_1245 = asSInt(_T_1244) node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0))) node _T_1247 = or(_T_1216, _T_1221) node _T_1248 = or(_T_1247, _T_1226) node _T_1249 = or(_T_1248, _T_1231) node _T_1250 = or(_T_1249, _T_1236) node _T_1251 = or(_T_1250, _T_1241) node _T_1252 = or(_T_1251, _T_1246) node _T_1253 = and(_T_1211, _T_1252) node _T_1254 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1255 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1256 = cvt(_T_1255) node _T_1257 = and(_T_1256, asSInt(UInt<17>(0h10000))) node _T_1258 = asSInt(_T_1257) node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0))) node _T_1260 = and(_T_1254, _T_1259) node _T_1261 = or(UInt<1>(0h0), _T_1253) node _T_1262 = or(_T_1261, _T_1260) node _T_1263 = and(_T_1207, _T_1262) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_41 node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(source_ok, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(is_aligned, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1273 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_44 node _T_1277 = eq(io.in.a.bits.mask, mask) node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(_T_1277, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1277, UInt<1>(0h1), "") : assert_45 node _T_1281 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1281 : node _T_1282 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1283 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1284 = and(_T_1282, _T_1283) node _T_1285 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1286 = shr(io.in.a.bits.source, 2) node _T_1287 = eq(_T_1286, UInt<4>(0h8)) node _T_1288 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1289 = and(_T_1287, _T_1288) node _T_1290 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1291 = and(_T_1289, _T_1290) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1292 = shr(io.in.a.bits.source, 2) node _T_1293 = eq(_T_1292, UInt<4>(0h9)) node _T_1294 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1297 = and(_T_1295, _T_1296) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1298 = shr(io.in.a.bits.source, 2) node _T_1299 = eq(_T_1298, UInt<4>(0ha)) node _T_1300 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1301 = and(_T_1299, _T_1300) node _T_1302 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1303 = and(_T_1301, _T_1302) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1304 = shr(io.in.a.bits.source, 2) node _T_1305 = eq(_T_1304, UInt<4>(0hb)) node _T_1306 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1307 = and(_T_1305, _T_1306) node _T_1308 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1309 = and(_T_1307, _T_1308) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1310 = shr(io.in.a.bits.source, 3) node _T_1311 = eq(_T_1310, UInt<2>(0h2)) node _T_1312 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1313 = and(_T_1311, _T_1312) node _T_1314 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1315 = and(_T_1313, _T_1314) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0) node _T_1316 = shr(io.in.a.bits.source, 3) node _T_1317 = eq(_T_1316, UInt<1>(0h1)) node _T_1318 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = leq(uncommonBits_75, UInt<3>(0h7)) node _T_1321 = and(_T_1319, _T_1320) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0) node _T_1322 = shr(io.in.a.bits.source, 3) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) node _T_1324 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = leq(uncommonBits_76, UInt<3>(0h7)) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = or(_T_1285, _T_1291) node _T_1329 = or(_T_1328, _T_1297) node _T_1330 = or(_T_1329, _T_1303) node _T_1331 = or(_T_1330, _T_1309) node _T_1332 = or(_T_1331, _T_1315) node _T_1333 = or(_T_1332, _T_1321) node _T_1334 = or(_T_1333, _T_1327) node _T_1335 = and(_T_1284, _T_1334) node _T_1336 = or(UInt<1>(0h0), _T_1335) node _T_1337 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1338 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1339 = and(_T_1337, _T_1338) node _T_1340 = or(UInt<1>(0h0), _T_1339) node _T_1341 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1342 = cvt(_T_1341) node _T_1343 = and(_T_1342, asSInt(UInt<13>(0h1000))) node _T_1344 = asSInt(_T_1343) node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) node _T_1346 = and(_T_1340, _T_1345) node _T_1347 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1348 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1349 = cvt(_T_1348) node _T_1350 = and(_T_1349, asSInt(UInt<14>(0h2000))) node _T_1351 = asSInt(_T_1350) node _T_1352 = eq(_T_1351, asSInt(UInt<1>(0h0))) node _T_1353 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1354 = cvt(_T_1353) node _T_1355 = and(_T_1354, asSInt(UInt<17>(0h10000))) node _T_1356 = asSInt(_T_1355) node _T_1357 = eq(_T_1356, asSInt(UInt<1>(0h0))) node _T_1358 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1359 = cvt(_T_1358) node _T_1360 = and(_T_1359, asSInt(UInt<18>(0h2f000))) node _T_1361 = asSInt(_T_1360) node _T_1362 = eq(_T_1361, asSInt(UInt<1>(0h0))) node _T_1363 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1364 = cvt(_T_1363) node _T_1365 = and(_T_1364, asSInt(UInt<17>(0h10000))) node _T_1366 = asSInt(_T_1365) node _T_1367 = eq(_T_1366, asSInt(UInt<1>(0h0))) node _T_1368 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1369 = cvt(_T_1368) node _T_1370 = and(_T_1369, asSInt(UInt<13>(0h1000))) node _T_1371 = asSInt(_T_1370) node _T_1372 = eq(_T_1371, asSInt(UInt<1>(0h0))) node _T_1373 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1374 = cvt(_T_1373) node _T_1375 = and(_T_1374, asSInt(UInt<27>(0h4000000))) node _T_1376 = asSInt(_T_1375) node _T_1377 = eq(_T_1376, asSInt(UInt<1>(0h0))) node _T_1378 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1379 = cvt(_T_1378) node _T_1380 = and(_T_1379, asSInt(UInt<13>(0h1000))) node _T_1381 = asSInt(_T_1380) node _T_1382 = eq(_T_1381, asSInt(UInt<1>(0h0))) node _T_1383 = or(_T_1352, _T_1357) node _T_1384 = or(_T_1383, _T_1362) node _T_1385 = or(_T_1384, _T_1367) node _T_1386 = or(_T_1385, _T_1372) node _T_1387 = or(_T_1386, _T_1377) node _T_1388 = or(_T_1387, _T_1382) node _T_1389 = and(_T_1347, _T_1388) node _T_1390 = or(UInt<1>(0h0), _T_1346) node _T_1391 = or(_T_1390, _T_1389) node _T_1392 = and(_T_1336, _T_1391) node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(_T_1392, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1392, UInt<1>(0h1), "") : assert_46 node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(source_ok, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(is_aligned, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1402 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_49 node _T_1406 = eq(io.in.a.bits.mask, mask) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_50 node _T_1410 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1414 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1415 = asUInt(reset) node _T_1416 = eq(_T_1415, UInt<1>(0h0)) when _T_1416 : node _T_1417 = eq(_T_1414, UInt<1>(0h0)) when _T_1417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1414, UInt<1>(0h1), "") : assert_52 node _source_ok_T_49 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_50 = shr(io.in.d.bits.source, 2) node _source_ok_T_51 = eq(_source_ok_T_50, UInt<4>(0h8)) node _source_ok_T_52 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_T_54 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_56 = shr(io.in.d.bits.source, 2) node _source_ok_T_57 = eq(_source_ok_T_56, UInt<4>(0h9)) node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_T_60 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_62 = shr(io.in.d.bits.source, 2) node _source_ok_T_63 = eq(_source_ok_T_62, UInt<4>(0ha)) node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_T_66 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_68 = shr(io.in.d.bits.source, 2) node _source_ok_T_69 = eq(_source_ok_T_68, UInt<4>(0hb)) node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_74 = shr(io.in.d.bits.source, 3) node _source_ok_T_75 = eq(_source_ok_T_74, UInt<2>(0h2)) node _source_ok_T_76 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_T_78 = leq(source_ok_uncommonBits_11, UInt<3>(0h7)) node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0) node _source_ok_T_80 = shr(io.in.d.bits.source, 3) node _source_ok_T_81 = eq(_source_ok_T_80, UInt<1>(0h1)) node _source_ok_T_82 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_T_84 = leq(source_ok_uncommonBits_12, UInt<3>(0h7)) node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0) node _source_ok_T_86 = shr(io.in.d.bits.source, 3) node _source_ok_T_87 = eq(_source_ok_T_86, UInt<1>(0h0)) node _source_ok_T_88 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_T_90 = leq(source_ok_uncommonBits_13, UInt<3>(0h7)) node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_49 connect _source_ok_WIRE_1[1], _source_ok_T_55 connect _source_ok_WIRE_1[2], _source_ok_T_61 connect _source_ok_WIRE_1[3], _source_ok_T_67 connect _source_ok_WIRE_1[4], _source_ok_T_73 connect _source_ok_WIRE_1[5], _source_ok_T_79 connect _source_ok_WIRE_1[6], _source_ok_T_85 connect _source_ok_WIRE_1[7], _source_ok_T_91 node _source_ok_T_92 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[2]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[3]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[4]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[5]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_97, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1418 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1418 : node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(source_ok_1, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1422 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1423 = asUInt(reset) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) when _T_1424 : node _T_1425 = eq(_T_1422, UInt<1>(0h0)) when _T_1425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1422, UInt<1>(0h1), "") : assert_54 node _T_1426 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1427 = asUInt(reset) node _T_1428 = eq(_T_1427, UInt<1>(0h0)) when _T_1428 : node _T_1429 = eq(_T_1426, UInt<1>(0h0)) when _T_1429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1426, UInt<1>(0h1), "") : assert_55 node _T_1430 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1431 = asUInt(reset) node _T_1432 = eq(_T_1431, UInt<1>(0h0)) when _T_1432 : node _T_1433 = eq(_T_1430, UInt<1>(0h0)) when _T_1433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1430, UInt<1>(0h1), "") : assert_56 node _T_1434 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(_T_1434, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1434, UInt<1>(0h1), "") : assert_57 node _T_1438 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1438 : node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(source_ok_1, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(sink_ok, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1445 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_60 node _T_1449 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1450 = asUInt(reset) node _T_1451 = eq(_T_1450, UInt<1>(0h0)) when _T_1451 : node _T_1452 = eq(_T_1449, UInt<1>(0h0)) when _T_1452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1449, UInt<1>(0h1), "") : assert_61 node _T_1453 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(_T_1453, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1453, UInt<1>(0h1), "") : assert_62 node _T_1457 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1458 = asUInt(reset) node _T_1459 = eq(_T_1458, UInt<1>(0h0)) when _T_1459 : node _T_1460 = eq(_T_1457, UInt<1>(0h0)) when _T_1460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1457, UInt<1>(0h1), "") : assert_63 node _T_1461 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1462 = or(UInt<1>(0h1), _T_1461) node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(_T_1462, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1462, UInt<1>(0h1), "") : assert_64 node _T_1466 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1466 : node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(source_ok_1, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(sink_ok, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1473 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(_T_1473, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1473, UInt<1>(0h1), "") : assert_67 node _T_1477 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1478 = asUInt(reset) node _T_1479 = eq(_T_1478, UInt<1>(0h0)) when _T_1479 : node _T_1480 = eq(_T_1477, UInt<1>(0h0)) when _T_1480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1477, UInt<1>(0h1), "") : assert_68 node _T_1481 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(_T_1481, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1481, UInt<1>(0h1), "") : assert_69 node _T_1485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1486 = or(_T_1485, io.in.d.bits.corrupt) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_70 node _T_1490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1491 = or(UInt<1>(0h1), _T_1490) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_71 node _T_1495 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1495 : node _T_1496 = asUInt(reset) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) when _T_1497 : node _T_1498 = eq(source_ok_1, UInt<1>(0h0)) when _T_1498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1500 = asUInt(reset) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) when _T_1501 : node _T_1502 = eq(_T_1499, UInt<1>(0h0)) when _T_1502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1499, UInt<1>(0h1), "") : assert_73 node _T_1503 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_74 node _T_1507 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1508 = or(UInt<1>(0h1), _T_1507) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_75 node _T_1512 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1512 : node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(source_ok_1, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1516 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_77 node _T_1520 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1521 = or(_T_1520, io.in.d.bits.corrupt) node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(_T_1521, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1521, UInt<1>(0h1), "") : assert_78 node _T_1525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1526 = or(UInt<1>(0h1), _T_1525) node _T_1527 = asUInt(reset) node _T_1528 = eq(_T_1527, UInt<1>(0h0)) when _T_1528 : node _T_1529 = eq(_T_1526, UInt<1>(0h0)) when _T_1529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1526, UInt<1>(0h1), "") : assert_79 node _T_1530 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1530 : node _T_1531 = asUInt(reset) node _T_1532 = eq(_T_1531, UInt<1>(0h0)) when _T_1532 : node _T_1533 = eq(source_ok_1, UInt<1>(0h0)) when _T_1533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1534 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_81 node _T_1538 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_82 node _T_1542 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1543 = or(UInt<1>(0h1), _T_1542) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<6>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1547 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(_T_1547, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1547, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1551 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(_T_1551, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1551, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1555 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1559 = eq(a_first, UInt<1>(0h0)) node _T_1560 = and(io.in.a.valid, _T_1559) when _T_1560 : node _T_1561 = eq(io.in.a.bits.opcode, opcode) node _T_1562 = asUInt(reset) node _T_1563 = eq(_T_1562, UInt<1>(0h0)) when _T_1563 : node _T_1564 = eq(_T_1561, UInt<1>(0h0)) when _T_1564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1561, UInt<1>(0h1), "") : assert_87 node _T_1565 = eq(io.in.a.bits.param, param) node _T_1566 = asUInt(reset) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) when _T_1567 : node _T_1568 = eq(_T_1565, UInt<1>(0h0)) when _T_1568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1565, UInt<1>(0h1), "") : assert_88 node _T_1569 = eq(io.in.a.bits.size, size) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_89 node _T_1573 = eq(io.in.a.bits.source, source) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_90 node _T_1577 = eq(io.in.a.bits.address, address) node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(_T_1577, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1577, UInt<1>(0h1), "") : assert_91 node _T_1581 = and(io.in.a.ready, io.in.a.valid) node _T_1582 = and(_T_1581, a_first) when _T_1582 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1583 = eq(d_first, UInt<1>(0h0)) node _T_1584 = and(io.in.d.valid, _T_1583) when _T_1584 : node _T_1585 = eq(io.in.d.bits.opcode, opcode_1) node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(_T_1585, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1585, UInt<1>(0h1), "") : assert_92 node _T_1589 = eq(io.in.d.bits.param, param_1) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_93 node _T_1593 = eq(io.in.d.bits.size, size_1) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_94 node _T_1597 = eq(io.in.d.bits.source, source_1) node _T_1598 = asUInt(reset) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) when _T_1599 : node _T_1600 = eq(_T_1597, UInt<1>(0h0)) when _T_1600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1597, UInt<1>(0h1), "") : assert_95 node _T_1601 = eq(io.in.d.bits.sink, sink) node _T_1602 = asUInt(reset) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) when _T_1603 : node _T_1604 = eq(_T_1601, UInt<1>(0h0)) when _T_1604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1601, UInt<1>(0h1), "") : assert_96 node _T_1605 = eq(io.in.d.bits.denied, denied) node _T_1606 = asUInt(reset) node _T_1607 = eq(_T_1606, UInt<1>(0h0)) when _T_1607 : node _T_1608 = eq(_T_1605, UInt<1>(0h0)) when _T_1608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1605, UInt<1>(0h1), "") : assert_97 node _T_1609 = and(io.in.d.ready, io.in.d.valid) node _T_1610 = and(_T_1609, d_first) when _T_1610 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<49>, clock, reset, UInt<49>(0h0) regreset inflight_opcodes : UInt<196>, clock, reset, UInt<196>(0h0) regreset inflight_sizes : UInt<392>, clock, reset, UInt<392>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<49> connect a_set, UInt<49>(0h0) wire a_set_wo_ready : UInt<49> connect a_set_wo_ready, UInt<49>(0h0) wire a_opcodes_set : UInt<196> connect a_opcodes_set, UInt<196>(0h0) wire a_sizes_set : UInt<392> connect a_sizes_set, UInt<392>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1611 = and(io.in.a.valid, a_first_1) node _T_1612 = and(_T_1611, UInt<1>(0h1)) when _T_1612 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1613 = and(io.in.a.ready, io.in.a.valid) node _T_1614 = and(_T_1613, a_first_1) node _T_1615 = and(_T_1614, UInt<1>(0h1)) when _T_1615 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1616 = dshr(inflight, io.in.a.bits.source) node _T_1617 = bits(_T_1616, 0, 0) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) node _T_1619 = asUInt(reset) node _T_1620 = eq(_T_1619, UInt<1>(0h0)) when _T_1620 : node _T_1621 = eq(_T_1618, UInt<1>(0h0)) when _T_1621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1618, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<49> connect d_clr, UInt<49>(0h0) wire d_clr_wo_ready : UInt<49> connect d_clr_wo_ready, UInt<49>(0h0) wire d_opcodes_clr : UInt<196> connect d_opcodes_clr, UInt<196>(0h0) wire d_sizes_clr : UInt<392> connect d_sizes_clr, UInt<392>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1622 = and(io.in.d.valid, d_first_1) node _T_1623 = and(_T_1622, UInt<1>(0h1)) node _T_1624 = eq(d_release_ack, UInt<1>(0h0)) node _T_1625 = and(_T_1623, _T_1624) when _T_1625 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1626 = and(io.in.d.ready, io.in.d.valid) node _T_1627 = and(_T_1626, d_first_1) node _T_1628 = and(_T_1627, UInt<1>(0h1)) node _T_1629 = eq(d_release_ack, UInt<1>(0h0)) node _T_1630 = and(_T_1628, _T_1629) when _T_1630 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1631 = and(io.in.d.valid, d_first_1) node _T_1632 = and(_T_1631, UInt<1>(0h1)) node _T_1633 = eq(d_release_ack, UInt<1>(0h0)) node _T_1634 = and(_T_1632, _T_1633) when _T_1634 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1635 = dshr(inflight, io.in.d.bits.source) node _T_1636 = bits(_T_1635, 0, 0) node _T_1637 = or(_T_1636, same_cycle_resp) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1641 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1642 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1643 = or(_T_1641, _T_1642) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_100 node _T_1647 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1648 = asUInt(reset) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(_T_1647, UInt<1>(0h0)) when _T_1650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1647, UInt<1>(0h1), "") : assert_101 else : node _T_1651 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1652 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1653 = or(_T_1651, _T_1652) node _T_1654 = asUInt(reset) node _T_1655 = eq(_T_1654, UInt<1>(0h0)) when _T_1655 : node _T_1656 = eq(_T_1653, UInt<1>(0h0)) when _T_1656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1653, UInt<1>(0h1), "") : assert_102 node _T_1657 = eq(io.in.d.bits.size, a_size_lookup) node _T_1658 = asUInt(reset) node _T_1659 = eq(_T_1658, UInt<1>(0h0)) when _T_1659 : node _T_1660 = eq(_T_1657, UInt<1>(0h0)) when _T_1660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1657, UInt<1>(0h1), "") : assert_103 node _T_1661 = and(io.in.d.valid, d_first_1) node _T_1662 = and(_T_1661, a_first_1) node _T_1663 = and(_T_1662, io.in.a.valid) node _T_1664 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1665 = and(_T_1663, _T_1664) node _T_1666 = eq(d_release_ack, UInt<1>(0h0)) node _T_1667 = and(_T_1665, _T_1666) when _T_1667 : node _T_1668 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1669 = or(_T_1668, io.in.a.ready) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_104 node _T_1673 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1674 = orr(a_set_wo_ready) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) node _T_1676 = or(_T_1673, _T_1675) node _T_1677 = asUInt(reset) node _T_1678 = eq(_T_1677, UInt<1>(0h0)) when _T_1678 : node _T_1679 = eq(_T_1676, UInt<1>(0h0)) when _T_1679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1676, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_38 node _T_1680 = orr(inflight) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) node _T_1682 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1683 = or(_T_1681, _T_1682) node _T_1684 = lt(watchdog, plusarg_reader.out) node _T_1685 = or(_T_1683, _T_1684) node _T_1686 = asUInt(reset) node _T_1687 = eq(_T_1686, UInt<1>(0h0)) when _T_1687 : node _T_1688 = eq(_T_1685, UInt<1>(0h0)) when _T_1688 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1685, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1689 = and(io.in.a.ready, io.in.a.valid) node _T_1690 = and(io.in.d.ready, io.in.d.valid) node _T_1691 = or(_T_1689, _T_1690) when _T_1691 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<49>, clock, reset, UInt<49>(0h0) regreset inflight_opcodes_1 : UInt<196>, clock, reset, UInt<196>(0h0) regreset inflight_sizes_1 : UInt<392>, clock, reset, UInt<392>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<49> connect c_set, UInt<49>(0h0) wire c_set_wo_ready : UInt<49> connect c_set_wo_ready, UInt<49>(0h0) wire c_opcodes_set : UInt<196> connect c_opcodes_set, UInt<196>(0h0) wire c_sizes_set : UInt<392> connect c_sizes_set, UInt<392>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1692 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1693 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1694 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = and(_T_1692, _T_1695) when _T_1696 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1697 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1698 = and(_T_1697, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1699 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1700 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = and(_T_1698, _T_1701) when _T_1702 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1703 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1704 = bits(_T_1703, 0, 0) node _T_1705 = eq(_T_1704, UInt<1>(0h0)) node _T_1706 = asUInt(reset) node _T_1707 = eq(_T_1706, UInt<1>(0h0)) when _T_1707 : node _T_1708 = eq(_T_1705, UInt<1>(0h0)) when _T_1708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1705, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<49> connect d_clr_1, UInt<49>(0h0) wire d_clr_wo_ready_1 : UInt<49> connect d_clr_wo_ready_1, UInt<49>(0h0) wire d_opcodes_clr_1 : UInt<196> connect d_opcodes_clr_1, UInt<196>(0h0) wire d_sizes_clr_1 : UInt<392> connect d_sizes_clr_1, UInt<392>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1709 = and(io.in.d.valid, d_first_2) node _T_1710 = and(_T_1709, UInt<1>(0h1)) node _T_1711 = and(_T_1710, d_release_ack_1) when _T_1711 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1712 = and(io.in.d.ready, io.in.d.valid) node _T_1713 = and(_T_1712, d_first_2) node _T_1714 = and(_T_1713, UInt<1>(0h1)) node _T_1715 = and(_T_1714, d_release_ack_1) when _T_1715 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1716 = and(io.in.d.valid, d_first_2) node _T_1717 = and(_T_1716, UInt<1>(0h1)) node _T_1718 = and(_T_1717, d_release_ack_1) when _T_1718 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1719 = dshr(inflight_1, io.in.d.bits.source) node _T_1720 = bits(_T_1719, 0, 0) node _T_1721 = or(_T_1720, same_cycle_resp_1) node _T_1722 = asUInt(reset) node _T_1723 = eq(_T_1722, UInt<1>(0h0)) when _T_1723 : node _T_1724 = eq(_T_1721, UInt<1>(0h0)) when _T_1724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1721, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1725 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1726 = asUInt(reset) node _T_1727 = eq(_T_1726, UInt<1>(0h0)) when _T_1727 : node _T_1728 = eq(_T_1725, UInt<1>(0h0)) when _T_1728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1725, UInt<1>(0h1), "") : assert_109 else : node _T_1729 = eq(io.in.d.bits.size, c_size_lookup) node _T_1730 = asUInt(reset) node _T_1731 = eq(_T_1730, UInt<1>(0h0)) when _T_1731 : node _T_1732 = eq(_T_1729, UInt<1>(0h0)) when _T_1732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1729, UInt<1>(0h1), "") : assert_110 node _T_1733 = and(io.in.d.valid, d_first_2) node _T_1734 = and(_T_1733, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1735 = and(_T_1734, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1736 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1737 = and(_T_1735, _T_1736) node _T_1738 = and(_T_1737, d_release_ack_1) node _T_1739 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1740 = and(_T_1738, _T_1739) when _T_1740 : node _T_1741 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<6>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1742 = or(_T_1741, _WIRE_27.ready) node _T_1743 = asUInt(reset) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) when _T_1744 : node _T_1745 = eq(_T_1742, UInt<1>(0h0)) when _T_1745 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1742, UInt<1>(0h1), "") : assert_111 node _T_1746 = orr(c_set_wo_ready) when _T_1746 : node _T_1747 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1748 = asUInt(reset) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) when _T_1749 : node _T_1750 = eq(_T_1747, UInt<1>(0h0)) when _T_1750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1747, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_39 node _T_1751 = orr(inflight_1) node _T_1752 = eq(_T_1751, UInt<1>(0h0)) node _T_1753 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1754 = or(_T_1752, _T_1753) node _T_1755 = lt(watchdog_1, plusarg_reader_1.out) node _T_1756 = or(_T_1754, _T_1755) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<6>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1760 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1761 = and(io.in.d.ready, io.in.d.valid) node _T_1762 = or(_T_1760, _T_1761) when _T_1762 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_40 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_41 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [391:0] c_sizes_set = 392'h0; // @[Monitor.scala:741:34] wire [195:0] c_opcodes_set = 196'h0; // @[Monitor.scala:740:34] wire [48:0] c_set = 49'h0; // @[Monitor.scala:738:34] wire [48:0] c_set_wo_ready = 49'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_37 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_48 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = io_in_d_bits_source_0 == 6'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_50 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_56 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_62 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_68 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_51 = _source_ok_T_50 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_57 = _source_ok_T_56 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_69 = _source_ok_T_68 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_74 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_80 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_86 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_75 = _source_ok_T_74 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_79; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_81 = _source_ok_T_80 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_87 = _source_ok_T_86 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_97 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1689 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1689; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1689; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1762 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1762; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1762; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1762; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [48:0] inflight; // @[Monitor.scala:614:27] reg [195:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [391:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [48:0] a_set; // @[Monitor.scala:626:34] wire [48:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [195:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [391:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [195:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [195:0] _a_opcode_lookup_T_6 = {192'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [195:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[195:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [391:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [391:0] _a_size_lookup_T_6 = {384'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [391:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[391:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire _T_1615 = _T_1689 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1615 ? _a_set_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1615 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1615 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1615 ? _a_opcodes_set_T_1[195:0] : 196'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1615 ? _a_sizes_set_T_1[391:0] : 392'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [48:0] d_clr; // @[Monitor.scala:664:34] wire [48:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [195:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [391:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1661 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1661 & ~d_release_ack ? _d_clr_wo_ready_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire _T_1630 = _T_1762 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1630 ? _d_clr_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1630 ? _d_opcodes_clr_T_5[195:0] : 196'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1630 ? _d_sizes_clr_T_5[391:0] : 392'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [48:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [48:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [48:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [195:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [195:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [195:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [391:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [391:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [391:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [48:0] inflight_1; // @[Monitor.scala:726:35] wire [48:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [195:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [195:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [391:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [391:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [195:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [195:0] _c_opcode_lookup_T_6 = {192'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [195:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[195:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [391:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [391:0] _c_size_lookup_T_6 = {384'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [391:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[391:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [48:0] d_clr_1; // @[Monitor.scala:774:34] wire [48:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [195:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [391:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1733 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1733 & d_release_ack_1 ? _d_clr_wo_ready_T_1[48:0] : 49'h0; // @[OneHot.scala:58:35] wire _T_1715 = _T_1762 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1715 ? _d_clr_T_1[48:0] : 49'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1715 ? _d_opcodes_clr_T_11[195:0] : 196'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1715 ? _d_sizes_clr_T_11[391:0] : 392'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [48:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [48:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [195:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [195:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [391:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [391:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_25 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut	module MulFullRawFN_25( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T \| _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 \| io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 \| io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 \| _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 \| notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 \| io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _T_889 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_890 = orr(a_set_wo_ready) node _T_891 = eq(_T_890, UInt<1>(0h0)) node _T_892 = or(_T_889, _T_891) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_892, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_97 node _T_896 = orr(inflight) node _T_897 = eq(_T_896, UInt<1>(0h0)) node _T_898 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_899 = or(_T_897, _T_898) node _T_900 = lt(watchdog, plusarg_reader.out) node _T_901 = or(_T_899, _T_900) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_901, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_905 = and(io.in.a.ready, io.in.a.valid) node _T_906 = and(io.in.d.ready, io.in.d.valid) node _T_907 = or(_T_905, _T_906) when _T_907 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_908 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_909 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_910 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_911 = and(_T_909, _T_910) node _T_912 = and(_T_908, _T_911) when _T_912 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_913 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_914 = and(_T_913, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_915 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_916 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_917 = and(_T_915, _T_916) node _T_918 = and(_T_914, _T_917) when _T_918 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_919 = dshr(inflight_1, _WIRE_15.bits.source) node _T_920 = bits(_T_919, 0, 0) node _T_921 = eq(_T_920, UInt<1>(0h0)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_921, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_928 = and(io.in.d.ready, io.in.d.valid) node _T_929 = and(_T_928, d_first_2) node _T_930 = and(_T_929, UInt<1>(0h1)) node _T_931 = and(_T_930, d_release_ack_1) when _T_931 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_932 = and(io.in.d.valid, d_first_2) node _T_933 = and(_T_932, UInt<1>(0h1)) node _T_934 = and(_T_933, d_release_ack_1) when _T_934 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_935 = dshr(inflight_1, io.in.d.bits.source) node _T_936 = bits(_T_935, 0, 0) node _T_937 = or(_T_936, same_cycle_resp_1) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_937, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_941 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_941, UInt<1>(0h1), "") : assert_109 else : node _T_945 = eq(io.in.d.bits.size, c_size_lookup) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_945, UInt<1>(0h1), "") : assert_110 node _T_949 = and(io.in.d.valid, d_first_2) node _T_950 = and(_T_949, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_951 = and(_T_950, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_952 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_953 = and(_T_951, _T_952) node _T_954 = and(_T_953, d_release_ack_1) node _T_955 = eq(c_probe_ack, UInt<1>(0h0)) node _T_956 = and(_T_954, _T_955) when _T_956 : node _T_957 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_958 = or(_T_957, _WIRE_23.ready) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_958, UInt<1>(0h1), "") : assert_111 node _T_962 = orr(c_set_wo_ready) when _T_962 : node _T_963 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_963, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_98 node _T_967 = orr(inflight_1) node _T_968 = eq(_T_967, UInt<1>(0h0)) node _T_969 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_970 = or(_T_968, _T_969) node _T_971 = lt(watchdog_1, plusarg_reader_1.out) node _T_972 = or(_T_970, _T_971) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_972, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_976 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_977 = and(io.in.d.ready, io.in.d.valid) node _T_978 = or(_T_976, _T_977) when _T_978 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_30 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}}, resp : { `2` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, `1` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, `0` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, channel_status : { flip `3` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5]}, out_allocs : { `3` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5]}} regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire in_arb_reqs : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}[3] wire in_arb_vals : UInt<1>[3] node in_arb_filter_hi = cat(in_arb_vals[2], in_arb_vals[1]) node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_vals[0]) node in_arb_filter_hi_1 = cat(in_arb_vals[2], in_arb_vals[1]) node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_vals[0]) node _in_arb_filter_T_2 = not(mask) node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2) node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3) node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0) node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1) node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2) node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3) node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4) node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5) node _in_arb_filter_T_11 = mux(_in_arb_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _in_arb_filter_T_12 = mux(_in_arb_filter_T_9, UInt<6>(0h10), _in_arb_filter_T_11) node _in_arb_filter_T_13 = mux(_in_arb_filter_T_8, UInt<6>(0h8), _in_arb_filter_T_12) node _in_arb_filter_T_14 = mux(_in_arb_filter_T_7, UInt<6>(0h4), _in_arb_filter_T_13) node _in_arb_filter_T_15 = mux(_in_arb_filter_T_6, UInt<6>(0h2), _in_arb_filter_T_14) node in_arb_filter = mux(_in_arb_filter_T_5, UInt<6>(0h1), _in_arb_filter_T_15) node _in_arb_sel_T = bits(in_arb_filter, 2, 0) node _in_arb_sel_T_1 = shr(in_arb_filter, 3) node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1) node _T = or(in_arb_vals[0], in_arb_vals[1]) node _T_1 = or(_T, in_arb_vals[2]) when _T_1 : node _mask_T = not(UInt<1>(0h0)) node _mask_T_1 = not(UInt<2>(0h0)) node _mask_T_2 = not(UInt<3>(0h0)) node _mask_T_3 = bits(in_arb_sel, 0, 0) node _mask_T_4 = bits(in_arb_sel, 1, 1) node _mask_T_5 = bits(in_arb_sel, 2, 2) node _mask_T_6 = mux(_mask_T_3, _mask_T, UInt<1>(0h0)) node _mask_T_7 = mux(_mask_T_4, _mask_T_1, UInt<1>(0h0)) node _mask_T_8 = mux(_mask_T_5, _mask_T_2, UInt<1>(0h0)) node _mask_T_9 = or(_mask_T_6, _mask_T_7) node _mask_T_10 = or(_mask_T_9, _mask_T_8) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_10 connect mask, _mask_WIRE node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T) connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1 node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T) connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1 node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T) connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1 node _in_arb_reqs_0_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_3_T_1 = and(io.req.`0`.bits.vc_sel.`0`[3], _in_arb_reqs_0_0_3_T) connect in_arb_reqs[0].`0`[3], _in_arb_reqs_0_0_3_T_1 node _in_arb_reqs_0_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_4_T_1 = and(io.req.`0`.bits.vc_sel.`0`[4], _in_arb_reqs_0_0_4_T) connect in_arb_reqs[0].`0`[4], _in_arb_reqs_0_0_4_T_1 node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T) connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1 node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T) connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1 node _in_arb_reqs_0_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_3_0_T_1 = and(io.req.`0`.bits.vc_sel.`3`[0], _in_arb_reqs_0_3_0_T) connect in_arb_reqs[0].`3`[0], _in_arb_reqs_0_3_0_T_1 node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1]) node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2]) node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T_1, in_arb_reqs[0].`0`[3]) node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`0`[4]) node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T_3, in_arb_reqs[0].`1`[0]) node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`2`[0]) node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`3`[0]) node _in_arb_vals_0_T_7 = and(io.req.`0`.valid, _in_arb_vals_0_T_6) connect in_arb_vals[0], _in_arb_vals_0_T_7 node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T) connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1 node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T) connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1 node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T) connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1 node _in_arb_reqs_1_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_3_T_1 = and(io.req.`1`.bits.vc_sel.`0`[3], _in_arb_reqs_1_0_3_T) connect in_arb_reqs[1].`0`[3], _in_arb_reqs_1_0_3_T_1 node _in_arb_reqs_1_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_4_T_1 = and(io.req.`1`.bits.vc_sel.`0`[4], _in_arb_reqs_1_0_4_T) connect in_arb_reqs[1].`0`[4], _in_arb_reqs_1_0_4_T_1 node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T) connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1 node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T) connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1 node _in_arb_reqs_1_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_3_0_T_1 = and(io.req.`1`.bits.vc_sel.`3`[0], _in_arb_reqs_1_3_0_T) connect in_arb_reqs[1].`3`[0], _in_arb_reqs_1_3_0_T_1 node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1]) node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2]) node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T_1, in_arb_reqs[1].`0`[3]) node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`0`[4]) node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T_3, in_arb_reqs[1].`1`[0]) node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`2`[0]) node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`3`[0]) node _in_arb_vals_1_T_7 = and(io.req.`1`.valid, _in_arb_vals_1_T_6) connect in_arb_vals[1], _in_arb_vals_1_T_7 node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T) connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1 node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T) connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1 node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T) connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1 node _in_arb_reqs_2_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_3_T_1 = and(io.req.`2`.bits.vc_sel.`0`[3], _in_arb_reqs_2_0_3_T) connect in_arb_reqs[2].`0`[3], _in_arb_reqs_2_0_3_T_1 node _in_arb_reqs_2_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_4_T_1 = and(io.req.`2`.bits.vc_sel.`0`[4], _in_arb_reqs_2_0_4_T) connect in_arb_reqs[2].`0`[4], _in_arb_reqs_2_0_4_T_1 node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T) connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1 node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T) connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1 node _in_arb_reqs_2_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_3_0_T_1 = and(io.req.`2`.bits.vc_sel.`3`[0], _in_arb_reqs_2_3_0_T) connect in_arb_reqs[2].`3`[0], _in_arb_reqs_2_3_0_T_1 node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1]) node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2]) node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T_1, in_arb_reqs[2].`0`[3]) node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`0`[4]) node _in_arb_vals_2_T_4 = or(_in_arb_vals_2_T_3, in_arb_reqs[2].`1`[0]) node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`2`[0]) node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, in_arb_reqs[2].`3`[0]) node _in_arb_vals_2_T_7 = and(io.req.`2`.valid, _in_arb_vals_2_T_6) connect in_arb_vals[2], _in_arb_vals_2_T_7 connect io.req.`0`.ready, UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h0) wire in_alloc : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]} node _in_flow_T = bits(in_arb_sel, 0, 0) node _in_flow_T_1 = bits(in_arb_sel, 1, 1) node _in_flow_T_2 = bits(in_arb_sel, 2, 2) wire in_flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _in_flow_T_3 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_4 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_5 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_6 = or(_in_flow_T_3, _in_flow_T_4) node _in_flow_T_7 = or(_in_flow_T_6, _in_flow_T_5) wire _in_flow_WIRE : UInt<2> connect _in_flow_WIRE, _in_flow_T_7 connect in_flow.egress_node_id, _in_flow_WIRE node _in_flow_T_8 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_9 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_10 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_11 = or(_in_flow_T_8, _in_flow_T_9) node _in_flow_T_12 = or(_in_flow_T_11, _in_flow_T_10) wire _in_flow_WIRE_1 : UInt<5> connect _in_flow_WIRE_1, _in_flow_T_12 connect in_flow.egress_node, _in_flow_WIRE_1 node _in_flow_T_13 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_14 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_15 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_16 = or(_in_flow_T_13, _in_flow_T_14) node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_15) wire _in_flow_WIRE_2 : UInt<2> connect _in_flow_WIRE_2, _in_flow_T_17 connect in_flow.ingress_node_id, _in_flow_WIRE_2 node _in_flow_T_18 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_19 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_20 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_21 = or(_in_flow_T_18, _in_flow_T_19) node _in_flow_T_22 = or(_in_flow_T_21, _in_flow_T_20) wire _in_flow_WIRE_3 : UInt<5> connect _in_flow_WIRE_3, _in_flow_T_22 connect in_flow.ingress_node, _in_flow_WIRE_3 node _in_flow_T_23 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_24 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_25 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_26 = or(_in_flow_T_23, _in_flow_T_24) node _in_flow_T_27 = or(_in_flow_T_26, _in_flow_T_25) wire _in_flow_WIRE_4 : UInt<3> connect _in_flow_WIRE_4, _in_flow_T_27 connect in_flow.vnet_id, _in_flow_WIRE_4 node _in_vc_T = bits(in_arb_sel, 0, 0) node _in_vc_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_T_3 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_4 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_5 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_6 = or(_in_vc_T_3, _in_vc_T_4) node _in_vc_T_7 = or(_in_vc_T_6, _in_vc_T_5) wire in_vc : UInt<3> connect in_vc, _in_vc_T_7 node _in_vc_sel_T = bits(in_arb_sel, 0, 0) node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2) wire in_vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]} wire _in_vc_sel_WIRE : UInt<1>[5] node _in_vc_sel_T_3 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_4 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_5 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_6 = or(_in_vc_sel_T_3, _in_vc_sel_T_4) node _in_vc_sel_T_7 = or(_in_vc_sel_T_6, _in_vc_sel_T_5) wire _in_vc_sel_WIRE_1 : UInt<1> connect _in_vc_sel_WIRE_1, _in_vc_sel_T_7 connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1 node _in_vc_sel_T_8 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_9 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_10 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_11 = or(_in_vc_sel_T_8, _in_vc_sel_T_9) node _in_vc_sel_T_12 = or(_in_vc_sel_T_11, _in_vc_sel_T_10) wire _in_vc_sel_WIRE_2 : UInt<1> connect _in_vc_sel_WIRE_2, _in_vc_sel_T_12 connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2 node _in_vc_sel_T_13 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_14 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_15 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_16 = or(_in_vc_sel_T_13, _in_vc_sel_T_14) node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_15) wire _in_vc_sel_WIRE_3 : UInt<1> connect _in_vc_sel_WIRE_3, _in_vc_sel_T_17 connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3 node _in_vc_sel_T_18 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_19 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_20 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_21 = or(_in_vc_sel_T_18, _in_vc_sel_T_19) node _in_vc_sel_T_22 = or(_in_vc_sel_T_21, _in_vc_sel_T_20) wire _in_vc_sel_WIRE_4 : UInt<1> connect _in_vc_sel_WIRE_4, _in_vc_sel_T_22 connect _in_vc_sel_WIRE[3], _in_vc_sel_WIRE_4 node _in_vc_sel_T_23 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_24 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_25 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_26 = or(_in_vc_sel_T_23, _in_vc_sel_T_24) node _in_vc_sel_T_27 = or(_in_vc_sel_T_26, _in_vc_sel_T_25) wire _in_vc_sel_WIRE_5 : UInt<1> connect _in_vc_sel_WIRE_5, _in_vc_sel_T_27 connect _in_vc_sel_WIRE[4], _in_vc_sel_WIRE_5 connect in_vc_sel.`0`, _in_vc_sel_WIRE wire _in_vc_sel_WIRE_6 : UInt<1>[1] node _in_vc_sel_T_28 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_29 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_30 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_31 = or(_in_vc_sel_T_28, _in_vc_sel_T_29) node _in_vc_sel_T_32 = or(_in_vc_sel_T_31, _in_vc_sel_T_30) wire _in_vc_sel_WIRE_7 : UInt<1> connect _in_vc_sel_WIRE_7, _in_vc_sel_T_32 connect _in_vc_sel_WIRE_6[0], _in_vc_sel_WIRE_7 connect in_vc_sel.`1`, _in_vc_sel_WIRE_6 wire _in_vc_sel_WIRE_8 : UInt<1>[1] node _in_vc_sel_T_33 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_34 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_35 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_36 = or(_in_vc_sel_T_33, _in_vc_sel_T_34) node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_35) wire _in_vc_sel_WIRE_9 : UInt<1> connect _in_vc_sel_WIRE_9, _in_vc_sel_T_37 connect _in_vc_sel_WIRE_8[0], _in_vc_sel_WIRE_9 connect in_vc_sel.`2`, _in_vc_sel_WIRE_8 wire _in_vc_sel_WIRE_10 : UInt<1>[1] node _in_vc_sel_T_38 = mux(_in_vc_sel_T, in_arb_reqs[0].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_39 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_40 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_41 = or(_in_vc_sel_T_38, _in_vc_sel_T_39) node _in_vc_sel_T_42 = or(_in_vc_sel_T_41, _in_vc_sel_T_40) wire _in_vc_sel_WIRE_11 : UInt<1> connect _in_vc_sel_WIRE_11, _in_vc_sel_T_42 connect _in_vc_sel_WIRE_10[0], _in_vc_sel_WIRE_11 connect in_vc_sel.`3`, _in_vc_sel_WIRE_10 node _T_2 = or(in_arb_vals[0], in_arb_vals[1]) node _T_3 = or(_T_2, in_arb_vals[2]) node hi = bits(in_arb_sel, 2, 2) node lo = bits(in_arb_sel, 1, 0) node _T_4 = orr(hi) node _T_5 = or(hi, lo) node _T_6 = bits(_T_5, 1, 1) node _T_7 = cat(_T_4, _T_6) node _T_8 = and(io.req.`0`.ready, io.req.`0`.valid) node _T_9 = and(io.req.`1`.ready, io.req.`1`.valid) node _T_10 = and(io.req.`2`.ready, io.req.`2`.valid) node _T_11 = or(_T_8, _T_9) node _T_12 = or(_T_11, _T_10) node lo_1 = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0]) node hi_hi = cat(in_vc_sel.`0`[4], in_vc_sel.`0`[3]) node hi_1 = cat(hi_hi, in_vc_sel.`0`[2]) node _T_13 = cat(hi_1, lo_1) node lo_2 = cat(in_vc_sel.`1`[0], _T_13) node hi_2 = cat(in_vc_sel.`3`[0], in_vc_sel.`2`[0]) node _T_14 = cat(hi_2, lo_2) regreset mask_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _full_T = not(mask_1) node _full_T_1 = and(_T_14, _full_T) node full = cat(_T_14, _full_T_1) node _oh_T = bits(full, 0, 0) node _oh_T_1 = bits(full, 1, 1) node _oh_T_2 = bits(full, 2, 2) node _oh_T_3 = bits(full, 3, 3) node _oh_T_4 = bits(full, 4, 4) node _oh_T_5 = bits(full, 5, 5) node _oh_T_6 = bits(full, 6, 6) node _oh_T_7 = bits(full, 7, 7) node _oh_T_8 = bits(full, 8, 8) node _oh_T_9 = bits(full, 9, 9) node _oh_T_10 = bits(full, 10, 10) node _oh_T_11 = bits(full, 11, 11) node _oh_T_12 = bits(full, 12, 12) node _oh_T_13 = bits(full, 13, 13) node _oh_T_14 = bits(full, 14, 14) node _oh_T_15 = bits(full, 15, 15) node _oh_T_16 = mux(_oh_T_15, UInt<16>(0h8000), UInt<16>(0h0)) node _oh_T_17 = mux(_oh_T_14, UInt<16>(0h4000), _oh_T_16) node _oh_T_18 = mux(_oh_T_13, UInt<16>(0h2000), _oh_T_17) node _oh_T_19 = mux(_oh_T_12, UInt<16>(0h1000), _oh_T_18) node _oh_T_20 = mux(_oh_T_11, UInt<16>(0h800), _oh_T_19) node _oh_T_21 = mux(_oh_T_10, UInt<16>(0h400), _oh_T_20) node _oh_T_22 = mux(_oh_T_9, UInt<16>(0h200), _oh_T_21) node _oh_T_23 = mux(_oh_T_8, UInt<16>(0h100), _oh_T_22) node _oh_T_24 = mux(_oh_T_7, UInt<16>(0h80), _oh_T_23) node _oh_T_25 = mux(_oh_T_6, UInt<16>(0h40), _oh_T_24) node _oh_T_26 = mux(_oh_T_5, UInt<16>(0h20), _oh_T_25) node _oh_T_27 = mux(_oh_T_4, UInt<16>(0h10), _oh_T_26) node _oh_T_28 = mux(_oh_T_3, UInt<16>(0h8), _oh_T_27) node _oh_T_29 = mux(_oh_T_2, UInt<16>(0h4), _oh_T_28) node _oh_T_30 = mux(_oh_T_1, UInt<16>(0h2), _oh_T_29) node oh = mux(_oh_T, UInt<16>(0h1), _oh_T_30) node _sel_T = bits(oh, 7, 0) node _sel_T_1 = shr(oh, 8) node sel = or(_sel_T, _sel_T_1) when _T_12 : node _mask_T_11 = bits(sel, 0, 0) node _mask_T_12 = not(UInt<1>(0h0)) node _mask_T_13 = bits(sel, 1, 1) node _mask_T_14 = not(UInt<2>(0h0)) node _mask_T_15 = bits(sel, 2, 2) node _mask_T_16 = not(UInt<3>(0h0)) node _mask_T_17 = bits(sel, 3, 3) node _mask_T_18 = not(UInt<4>(0h0)) node _mask_T_19 = bits(sel, 4, 4) node _mask_T_20 = not(UInt<5>(0h0)) node _mask_T_21 = bits(sel, 5, 5) node _mask_T_22 = not(UInt<6>(0h0)) node _mask_T_23 = bits(sel, 6, 6) node _mask_T_24 = not(UInt<7>(0h0)) node _mask_T_25 = bits(sel, 7, 7) node _mask_T_26 = not(UInt<8>(0h0)) node _mask_T_27 = mux(_mask_T_25, _mask_T_26, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_23, _mask_T_24, _mask_T_27) node _mask_T_29 = mux(_mask_T_21, _mask_T_22, _mask_T_28) node _mask_T_30 = mux(_mask_T_19, _mask_T_20, _mask_T_29) node _mask_T_31 = mux(_mask_T_17, _mask_T_18, _mask_T_30) node _mask_T_32 = mux(_mask_T_15, _mask_T_16, _mask_T_31) node _mask_T_33 = mux(_mask_T_13, _mask_T_14, _mask_T_32) node _mask_T_34 = mux(_mask_T_11, _mask_T_12, _mask_T_33) connect mask_1, _mask_T_34 wire _WIRE : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]} wire _WIRE_1 : UInt<8> connect _WIRE_1, sel node _T_15 = bits(_WIRE_1, 0, 0) connect _WIRE.`0`[0], _T_15 node _T_16 = bits(_WIRE_1, 1, 1) connect _WIRE.`0`[1], _T_16 node _T_17 = bits(_WIRE_1, 2, 2) connect _WIRE.`0`[2], _T_17 node _T_18 = bits(_WIRE_1, 3, 3) connect _WIRE.`0`[3], _T_18 node _T_19 = bits(_WIRE_1, 4, 4) connect _WIRE.`0`[4], _T_19 node _T_20 = bits(_WIRE_1, 5, 5) connect _WIRE.`1`[0], _T_20 node _T_21 = bits(_WIRE_1, 6, 6) connect _WIRE.`2`[0], _T_21 node _T_22 = bits(_WIRE_1, 7, 7) connect _WIRE.`3`[0], _T_22 wire _WIRE_2 : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]} connect _WIRE_2.`0`[0], UInt<1>(0h0) connect _WIRE_2.`0`[1], UInt<1>(0h0) connect _WIRE_2.`0`[2], UInt<1>(0h0) connect _WIRE_2.`0`[3], UInt<1>(0h0) connect _WIRE_2.`0`[4], UInt<1>(0h0) connect _WIRE_2.`1`[0], UInt<1>(0h0) connect _WIRE_2.`2`[0], UInt<1>(0h0) connect _WIRE_2.`3`[0], UInt<1>(0h0) node _T_23 = mux(_T_3, _WIRE, _WIRE_2) connect in_alloc.`0`, _T_23.`0` connect in_alloc.`1`, _T_23.`1` connect in_alloc.`2`, _T_23.`2` connect in_alloc.`3`, _T_23.`3` node _io_req_0_ready_T = bits(in_arb_sel, 0, 0) connect io.req.`0`.ready, _io_req_0_ready_T connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`0`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`0`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`0`.vc_sel.`3`[0], in_alloc.`3`[0] node lo_3 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0]) node hi_hi_1 = cat(io.resp.`0`.vc_sel.`0`[4], io.resp.`0`.vc_sel.`0`[3]) node hi_3 = cat(hi_hi_1, io.resp.`0`.vc_sel.`0`[2]) node _T_24 = cat(hi_3, lo_3) node lo_4 = cat(io.resp.`0`.vc_sel.`1`[0], _T_24) node hi_4 = cat(io.resp.`0`.vc_sel.`3`[0], io.resp.`0`.vc_sel.`2`[0]) node _T_25 = cat(hi_4, lo_4) node _T_26 = bits(_T_25, 0, 0) node _T_27 = bits(_T_25, 1, 1) node _T_28 = bits(_T_25, 2, 2) node _T_29 = bits(_T_25, 3, 3) node _T_30 = bits(_T_25, 4, 4) node _T_31 = bits(_T_25, 5, 5) node _T_32 = bits(_T_25, 6, 6) node _T_33 = bits(_T_25, 7, 7) node _T_34 = add(_T_26, _T_27) node _T_35 = bits(_T_34, 1, 0) node _T_36 = add(_T_28, _T_29) node _T_37 = bits(_T_36, 1, 0) node _T_38 = add(_T_35, _T_37) node _T_39 = bits(_T_38, 2, 0) node _T_40 = add(_T_30, _T_31) node _T_41 = bits(_T_40, 1, 0) node _T_42 = add(_T_32, _T_33) node _T_43 = bits(_T_42, 1, 0) node _T_44 = add(_T_41, _T_43) node _T_45 = bits(_T_44, 2, 0) node _T_46 = add(_T_39, _T_45) node _T_47 = bits(_T_46, 3, 0) node _T_48 = leq(_T_47, UInt<1>(0h1)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf assert(clock, _T_48, UInt<1>(0h1), "") : assert node _io_req_1_ready_T = bits(in_arb_sel, 1, 1) connect io.req.`1`.ready, _io_req_1_ready_T connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`1`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`1`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`1`.vc_sel.`3`[0], in_alloc.`3`[0] node lo_5 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0]) node hi_hi_2 = cat(io.resp.`1`.vc_sel.`0`[4], io.resp.`1`.vc_sel.`0`[3]) node hi_5 = cat(hi_hi_2, io.resp.`1`.vc_sel.`0`[2]) node _T_52 = cat(hi_5, lo_5) node lo_6 = cat(io.resp.`1`.vc_sel.`1`[0], _T_52) node hi_6 = cat(io.resp.`1`.vc_sel.`3`[0], io.resp.`1`.vc_sel.`2`[0]) node _T_53 = cat(hi_6, lo_6) node _T_54 = bits(_T_53, 0, 0) node _T_55 = bits(_T_53, 1, 1) node _T_56 = bits(_T_53, 2, 2) node _T_57 = bits(_T_53, 3, 3) node _T_58 = bits(_T_53, 4, 4) node _T_59 = bits(_T_53, 5, 5) node _T_60 = bits(_T_53, 6, 6) node _T_61 = bits(_T_53, 7, 7) node _T_62 = add(_T_54, _T_55) node _T_63 = bits(_T_62, 1, 0) node _T_64 = add(_T_56, _T_57) node _T_65 = bits(_T_64, 1, 0) node _T_66 = add(_T_63, _T_65) node _T_67 = bits(_T_66, 2, 0) node _T_68 = add(_T_58, _T_59) node _T_69 = bits(_T_68, 1, 0) node _T_70 = add(_T_60, _T_61) node _T_71 = bits(_T_70, 1, 0) node _T_72 = add(_T_69, _T_71) node _T_73 = bits(_T_72, 2, 0) node _T_74 = add(_T_67, _T_73) node _T_75 = bits(_T_74, 3, 0) node _T_76 = leq(_T_75, UInt<1>(0h1)) node _T_77 = asUInt(reset) node _T_78 = eq(_T_77, UInt<1>(0h0)) when _T_78 : node _T_79 = eq(_T_76, UInt<1>(0h0)) when _T_79 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1 assert(clock, _T_76, UInt<1>(0h1), "") : assert_1 node _io_req_2_ready_T = bits(in_arb_sel, 2, 2) connect io.req.`2`.ready, _io_req_2_ready_T connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`2`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`2`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`2`.vc_sel.`3`[0], in_alloc.`3`[0] node lo_7 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0]) node hi_hi_3 = cat(io.resp.`2`.vc_sel.`0`[4], io.resp.`2`.vc_sel.`0`[3]) node hi_7 = cat(hi_hi_3, io.resp.`2`.vc_sel.`0`[2]) node _T_80 = cat(hi_7, lo_7) node lo_8 = cat(io.resp.`2`.vc_sel.`1`[0], _T_80) node hi_8 = cat(io.resp.`2`.vc_sel.`3`[0], io.resp.`2`.vc_sel.`2`[0]) node _T_81 = cat(hi_8, lo_8) node _T_82 = bits(_T_81, 0, 0) node _T_83 = bits(_T_81, 1, 1) node _T_84 = bits(_T_81, 2, 2) node _T_85 = bits(_T_81, 3, 3) node _T_86 = bits(_T_81, 4, 4) node _T_87 = bits(_T_81, 5, 5) node _T_88 = bits(_T_81, 6, 6) node _T_89 = bits(_T_81, 7, 7) node _T_90 = add(_T_82, _T_83) node _T_91 = bits(_T_90, 1, 0) node _T_92 = add(_T_84, _T_85) node _T_93 = bits(_T_92, 1, 0) node _T_94 = add(_T_91, _T_93) node _T_95 = bits(_T_94, 2, 0) node _T_96 = add(_T_86, _T_87) node _T_97 = bits(_T_96, 1, 0) node _T_98 = add(_T_88, _T_89) node _T_99 = bits(_T_98, 1, 0) node _T_100 = add(_T_97, _T_99) node _T_101 = bits(_T_100, 2, 0) node _T_102 = add(_T_95, _T_101) node _T_103 = bits(_T_102, 3, 0) node _T_104 = leq(_T_103, UInt<1>(0h1)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2 assert(clock, _T_104, UInt<1>(0h1), "") : assert_2 connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0] connect io.out_allocs.`0`[0].flow, in_flow connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1] connect io.out_allocs.`0`[1].flow, in_flow connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2] connect io.out_allocs.`0`[2].flow, in_flow connect io.out_allocs.`0`[3].alloc, in_alloc.`0`[3] connect io.out_allocs.`0`[3].flow, in_flow connect io.out_allocs.`0`[4].alloc, in_alloc.`0`[4] connect io.out_allocs.`0`[4].flow, in_flow connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0] connect io.out_allocs.`1`[0].flow, in_flow connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0] connect io.out_allocs.`2`[0].flow, in_flow connect io.out_allocs.`3`[0].alloc, in_alloc.`3`[0] connect io.out_allocs.`3`[0].flow, in_flow	module RotatingSingleVCAllocator_30( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_1_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [2:0] mask; // @[SingleVCAllocator.scala:16:21] wire [2:0] _in_arb_filter_T_3 = {in_arb_vals_2, 1'h0, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [5:0] in_arb_filter = _in_arb_filter_T_3[0] ? 6'h1 : _in_arb_filter_T_3[1] ? 6'h2 : _in_arb_filter_T_3[2] ? 6'h4 : in_arb_vals_0 ? 6'h8 : {in_arb_vals_2, 5'h0}; // @[OneHot.scala:85:71] wire [2:0] in_arb_sel = in_arb_filter[2:0] \| in_arb_filter[5:3]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 \| in_arb_vals_2; // @[package.scala:81:59] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_1_0 \| in_arb_reqs_0_2_0 \| in_arb_reqs_0_3_0); // @[package.scala:81:59] wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_3_0 = io_req_2_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (io_req_2_bits_vc_sel_0_0 \| in_arb_reqs_2_0_1 \| io_req_2_bits_vc_sel_0_2 \| io_req_2_bits_vc_sel_0_3 \| io_req_2_bits_vc_sel_0_4 \| in_arb_reqs_2_1_0 \| in_arb_reqs_2_2_0 \| in_arb_reqs_2_3_0); // @[package.scala:81:59] wire _in_vc_sel_T_5 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_10 = in_arb_sel[2] & in_arb_reqs_2_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_15 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_20 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_25 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_32 = in_arb_sel[0] & in_arb_reqs_0_1_0 \| in_arb_sel[2] & in_arb_reqs_2_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_37 = in_arb_sel[0] & in_arb_reqs_0_2_0 \| in_arb_sel[2] & in_arb_reqs_2_2_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_42 = in_arb_sel[0] & in_arb_reqs_0_3_0 \| in_arb_sel[2] & in_arb_reqs_2_3_0; // @[Mux.scala:30:73, :32:36] reg [7:0] mask_1; // @[ISLIP.scala:17:25] wire [7:0] _full_T_1 = {_in_vc_sel_T_42, _in_vc_sel_T_37, _in_vc_sel_T_32, _in_vc_sel_T_25, _in_vc_sel_T_20, _in_vc_sel_T_15, _in_vc_sel_T_10, _in_vc_sel_T_5} & ~mask_1; // @[Mux.scala:30:73] wire [15:0] oh = _full_T_1[0] ? 16'h1 : _full_T_1[1] ? 16'h2 : _full_T_1[2] ? 16'h4 : _full_T_1[3] ? 16'h8 : _full_T_1[4] ? 16'h10 : _full_T_1[5] ? 16'h20 : _full_T_1[6] ? 16'h40 : _full_T_1[7] ? 16'h80 : _in_vc_sel_T_5 ? 16'h100 : _in_vc_sel_T_10 ? 16'h200 : _in_vc_sel_T_15 ? 16'h400 : _in_vc_sel_T_20 ? 16'h800 : _in_vc_sel_T_25 ? 16'h1000 : _in_vc_sel_T_32 ? 16'h2000 : _in_vc_sel_T_37 ? 16'h4000 : {_in_vc_sel_T_42, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] sel = oh[7:0] \| oh[15:8]; // @[Mux.scala:50:70] wire in_alloc_3_0 = _GEN & sel[7]; // @[package.scala:81:59] wire in_alloc_2_0 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59] wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_4 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}} wire _in_flight_WIRE : UInt<1>[8] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_41 = and(_T_39, _T_40) node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_45 = and(_T_43, _T_44) node _T_46 = or(_T_17, _T_24) node _T_47 = or(_T_46, _T_31) node _T_48 = or(_T_47, _T_38) node _T_49 = or(_T_48, _T_45) node _T_50 = or(_T_10, _T_49) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_50, UInt<1>(0h1), "") : assert_2 node _T_54 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_71 = and(_T_69, _T_70) node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_75 = and(_T_73, _T_74) node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_61, _T_68) node _T_91 = or(_T_90, _T_75) node _T_92 = or(_T_91, _T_82) node _T_93 = or(_T_92, _T_89) node _T_94 = or(_T_54, _T_93) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_94, UInt<1>(0h1), "") : assert_3 node _T_98 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_100 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_105 = and(_T_103, _T_104) node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_112 = and(_T_110, _T_111) node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_121 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_128 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_135 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_136 = and(_T_134, _T_135) node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_142 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_149 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_156 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(_T_105, _T_112) node _T_163 = or(_T_162, _T_119) node _T_164 = or(_T_163, _T_126) node _T_165 = or(_T_164, _T_133) node _T_166 = or(_T_165, _T_140) node _T_167 = or(_T_166, _T_147) node _T_168 = or(_T_167, _T_154) node _T_169 = or(_T_168, _T_161) node _T_170 = or(_T_98, _T_169) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_170, UInt<1>(0h1), "") : assert_4 node _T_174 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_176 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_179 = and(_T_177, _T_178) node _T_180 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_181 = and(_T_179, _T_180) node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_183 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_190 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_191 = and(_T_189, _T_190) node _T_192 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_193 = and(_T_191, _T_192) node _T_194 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_195 = and(_T_193, _T_194) node _T_196 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_197 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_204 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_205 = and(_T_203, _T_204) node _T_206 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_207 = and(_T_205, _T_206) node _T_208 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_211 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_212 = and(_T_210, _T_211) node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_214 = and(_T_212, _T_213) node _T_215 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_218 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_219 = and(_T_217, _T_218) node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_221 = and(_T_219, _T_220) node _T_222 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_225 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_226 = and(_T_224, _T_225) node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_232 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_233 = and(_T_231, _T_232) node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_235 = and(_T_233, _T_234) node _T_236 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_237 = and(_T_235, _T_236) node _T_238 = or(_T_181, _T_188) node _T_239 = or(_T_238, _T_195) node _T_240 = or(_T_239, _T_202) node _T_241 = or(_T_240, _T_209) node _T_242 = or(_T_241, _T_216) node _T_243 = or(_T_242, _T_223) node _T_244 = or(_T_243, _T_230) node _T_245 = or(_T_244, _T_237) node _T_246 = or(_T_174, _T_245) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_246, UInt<1>(0h1), "") : assert_5 node _T_250 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_255 = and(_T_253, _T_254) node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_257 = and(_T_255, _T_256) node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_269 = and(_T_267, _T_268) node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_273 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_278 = and(_T_276, _T_277) node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_280 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_285 = and(_T_283, _T_284) node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_287 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_292 = and(_T_290, _T_291) node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_294 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_297 = and(_T_295, _T_296) node _T_298 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_301 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_306 = and(_T_304, _T_305) node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_308 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_309 = and(_T_307, _T_308) node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_311 = and(_T_309, _T_310) node _T_312 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_313 = and(_T_311, _T_312) node _T_314 = or(_T_257, _T_264) node _T_315 = or(_T_314, _T_271) node _T_316 = or(_T_315, _T_278) node _T_317 = or(_T_316, _T_285) node _T_318 = or(_T_317, _T_292) node _T_319 = or(_T_318, _T_299) node _T_320 = or(_T_319, _T_306) node _T_321 = or(_T_320, _T_313) node _T_322 = or(_T_250, _T_321) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_322, UInt<1>(0h1), "") : assert_6 node _T_326 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_327 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_328 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_329 = and(_T_327, _T_328) node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_331 = and(_T_329, _T_330) node _T_332 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_335 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_338 = and(_T_336, _T_337) node _T_339 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_340 = and(_T_338, _T_339) node _T_341 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_342 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_345 = and(_T_343, _T_344) node _T_346 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_349 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_350 = and(_T_348, _T_349) node _T_351 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_356 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_357 = and(_T_355, _T_356) node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_359 = and(_T_357, _T_358) node _T_360 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_361 = and(_T_359, _T_360) node _T_362 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_363 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_364 = and(_T_362, _T_363) node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_370 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_371 = and(_T_369, _T_370) node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_373 = and(_T_371, _T_372) node _T_374 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) node _T_376 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_377 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_378 = and(_T_376, _T_377) node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_380 = and(_T_378, _T_379) node _T_381 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_384 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_385 = and(_T_383, _T_384) node _T_386 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_387 = and(_T_385, _T_386) node _T_388 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_389 = and(_T_387, _T_388) node _T_390 = or(_T_333, _T_340) node _T_391 = or(_T_390, _T_347) node _T_392 = or(_T_391, _T_354) node _T_393 = or(_T_392, _T_361) node _T_394 = or(_T_393, _T_368) node _T_395 = or(_T_394, _T_375) node _T_396 = or(_T_395, _T_382) node _T_397 = or(_T_396, _T_389) node _T_398 = or(_T_326, _T_397) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_398, UInt<1>(0h1), "") : assert_7 node _T_402 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_403 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_404 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_411 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_414 = and(_T_412, _T_413) node _T_415 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_416 = and(_T_414, _T_415) node _T_417 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_418 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_421 = and(_T_419, _T_420) node _T_422 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_423 = and(_T_421, _T_422) node _T_424 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_425 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_428 = and(_T_426, _T_427) node _T_429 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_430 = and(_T_428, _T_429) node _T_431 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_432 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_435 = and(_T_433, _T_434) node _T_436 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_437 = and(_T_435, _T_436) node _T_438 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_439 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_440 = and(_T_438, _T_439) node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_442 = and(_T_440, _T_441) node _T_443 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_446 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_449 = and(_T_447, _T_448) node _T_450 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_453 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_454 = and(_T_452, _T_453) node _T_455 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_456 = and(_T_454, _T_455) node _T_457 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_460 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_461 = and(_T_459, _T_460) node _T_462 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_463 = and(_T_461, _T_462) node _T_464 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(_T_409, _T_416) node _T_467 = or(_T_466, _T_423) node _T_468 = or(_T_467, _T_430) node _T_469 = or(_T_468, _T_437) node _T_470 = or(_T_469, _T_444) node _T_471 = or(_T_470, _T_451) node _T_472 = or(_T_471, _T_458) node _T_473 = or(_T_472, _T_465) node _T_474 = or(_T_402, _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_474, UInt<1>(0h1), "") : assert_8	module NoCMonitor_4( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_109 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_110 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [7:0] io_in_a_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_a_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [8:0] a_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a29d64s8k1z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_16 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a29d64s8k1z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a29d64s8k1z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_66 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_67 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBuffer_a29d64s8k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [7:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_16 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s8k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s8k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (2'h0), // @[Decoupled.scala:362:21] .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_denied (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (1'h0), // @[Decoupled.scala:362:21] .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IDPool_5 : input clock : Clock input reset : Reset output io : { flip free : { valid : UInt<1>, bits : UInt<3>}, alloc : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<3>}} regreset bitmap : UInt<8>, clock, reset, UInt<8>(0hff) regreset select : UInt<3>, clock, reset, UInt<3>(0h0) regreset valid : UInt<1>, clock, reset, UInt<1>(0h1) connect io.alloc.valid, valid connect io.alloc.bits, select node taken_shiftAmount = bits(io.alloc.bits, 2, 0) node _taken_T = dshl(UInt<1>(0h1), taken_shiftAmount) node _taken_T_1 = bits(_taken_T, 7, 0) node taken = mux(io.alloc.ready, _taken_T_1, UInt<1>(0h0)) node allocated_shiftAmount = bits(io.free.bits, 2, 0) node _allocated_T = dshl(UInt<1>(0h1), allocated_shiftAmount) node _allocated_T_1 = bits(_allocated_T, 7, 0) node allocated = mux(io.free.valid, _allocated_T_1, UInt<1>(0h0)) node _bitmap1_T = not(taken) node _bitmap1_T_1 = and(bitmap, _bitmap1_T) node bitmap1 = or(_bitmap1_T_1, allocated) node _select1_T = bits(bitmap1, 0, 0) node _select1_T_1 = bits(bitmap1, 1, 1) node _select1_T_2 = bits(bitmap1, 2, 2) node _select1_T_3 = bits(bitmap1, 3, 3) node _select1_T_4 = bits(bitmap1, 4, 4) node _select1_T_5 = bits(bitmap1, 5, 5) node _select1_T_6 = bits(bitmap1, 6, 6) node _select1_T_7 = bits(bitmap1, 7, 7) node _select1_T_8 = mux(_select1_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _select1_T_9 = mux(_select1_T_5, UInt<3>(0h5), _select1_T_8) node _select1_T_10 = mux(_select1_T_4, UInt<3>(0h4), _select1_T_9) node _select1_T_11 = mux(_select1_T_3, UInt<2>(0h3), _select1_T_10) node _select1_T_12 = mux(_select1_T_2, UInt<2>(0h2), _select1_T_11) node _select1_T_13 = mux(_select1_T_1, UInt<1>(0h1), _select1_T_12) node select1 = mux(_select1_T, UInt<1>(0h0), _select1_T_13) node _valid1_T = orr(bitmap) node _valid1_T_1 = bits(bitmap, 0, 0) node _valid1_T_2 = bits(bitmap, 1, 1) node _valid1_T_3 = bits(bitmap, 2, 2) node _valid1_T_4 = bits(bitmap, 3, 3) node _valid1_T_5 = bits(bitmap, 4, 4) node _valid1_T_6 = bits(bitmap, 5, 5) node _valid1_T_7 = bits(bitmap, 6, 6) node _valid1_T_8 = bits(bitmap, 7, 7) node _valid1_T_9 = add(_valid1_T_1, _valid1_T_2) node _valid1_T_10 = bits(_valid1_T_9, 1, 0) node _valid1_T_11 = add(_valid1_T_3, _valid1_T_4) node _valid1_T_12 = bits(_valid1_T_11, 1, 0) node _valid1_T_13 = add(_valid1_T_10, _valid1_T_12) node _valid1_T_14 = bits(_valid1_T_13, 2, 0) node _valid1_T_15 = add(_valid1_T_5, _valid1_T_6) node _valid1_T_16 = bits(_valid1_T_15, 1, 0) node _valid1_T_17 = add(_valid1_T_7, _valid1_T_8) node _valid1_T_18 = bits(_valid1_T_17, 1, 0) node _valid1_T_19 = add(_valid1_T_16, _valid1_T_18) node _valid1_T_20 = bits(_valid1_T_19, 2, 0) node _valid1_T_21 = add(_valid1_T_14, _valid1_T_20) node _valid1_T_22 = bits(_valid1_T_21, 3, 0) node _valid1_T_23 = eq(_valid1_T_22, UInt<1>(0h1)) node _valid1_T_24 = and(_valid1_T_23, io.alloc.ready) node _valid1_T_25 = eq(_valid1_T_24, UInt<1>(0h0)) node _valid1_T_26 = and(_valid1_T, _valid1_T_25) node valid1 = or(_valid1_T_26, io.free.valid) node _T = or(io.alloc.ready, io.free.valid) when _T : connect bitmap, bitmap1 connect valid, valid1 node _T_1 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_2 = and(_T_1, io.free.valid) node _T_3 = or(io.alloc.ready, _T_2) when _T_3 : connect select, select1 node _T_4 = eq(io.free.valid, UInt<1>(0h0)) node _T_5 = not(taken) node _T_6 = and(bitmap, _T_5) node _T_7 = dshr(_T_6, io.free.bits) node _T_8 = bits(_T_7, 0, 0) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_4, _T_9) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:44 assert (!io.free.valid \|\| !(bitmap & ~taken)(io.free.bits))\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _T_14 = orr(bitmap) node _T_15 = eq(valid, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:48 assert (valid === bitmap.orR)\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node _T_19 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_20 = and(_T_19, io.free.valid) node _T_21 = or(io.alloc.ready, _T_20) reg REG : UInt<1>, clock connect REG, _T_21 node _T_22 = and(io.alloc.valid, REG) when _T_22 : node _T_23 = bits(bitmap, 0, 0) node _T_24 = bits(bitmap, 1, 1) node _T_25 = bits(bitmap, 2, 2) node _T_26 = bits(bitmap, 3, 3) node _T_27 = bits(bitmap, 4, 4) node _T_28 = bits(bitmap, 5, 5) node _T_29 = bits(bitmap, 6, 6) node _T_30 = bits(bitmap, 7, 7) node _T_31 = mux(_T_29, UInt<3>(0h6), UInt<3>(0h7)) node _T_32 = mux(_T_28, UInt<3>(0h5), _T_31) node _T_33 = mux(_T_27, UInt<3>(0h4), _T_32) node _T_34 = mux(_T_26, UInt<2>(0h3), _T_33) node _T_35 = mux(_T_25, UInt<2>(0h2), _T_34) node _T_36 = mux(_T_24, UInt<1>(0h1), _T_35) node _T_37 = mux(_T_23, UInt<1>(0h0), _T_36) node _T_38 = eq(select, _T_37) node _T_39 = asUInt(reset) node _T_40 = eq(_T_39, UInt<1>(0h0)) when _T_40 : node _T_41 = eq(_T_38, UInt<1>(0h0)) when _T_41 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:52 assert (select === PriorityEncoder(bitmap))\n") : printf_2 assert(clock, _T_38, UInt<1>(0h1), "") : assert_2	module IDPool_5( // @[IDPool.scala:8:7] input clock, // @[IDPool.scala:8:7] input reset, // @[IDPool.scala:8:7] input io_free_valid, // @[IDPool.scala:12:14] input [2:0] io_free_bits, // @[IDPool.scala:12:14] input io_alloc_ready, // @[IDPool.scala:12:14] output io_alloc_valid, // @[IDPool.scala:12:14] output [2:0] io_alloc_bits // @[IDPool.scala:12:14] ); wire [2:0] io_alloc_bits_0; // @[IDPool.scala:8:7] wire io_free_valid_0 = io_free_valid; // @[IDPool.scala:8:7] wire [2:0] io_free_bits_0 = io_free_bits; // @[IDPool.scala:8:7] wire io_alloc_ready_0 = io_alloc_ready; // @[IDPool.scala:8:7] wire [2:0] allocated_shiftAmount = io_free_bits_0; // @[OneHot.scala:64:49] wire [2:0] taken_shiftAmount = io_alloc_bits_0; // @[OneHot.scala:64:49] wire io_alloc_valid_0; // @[IDPool.scala:8:7] reg [7:0] bitmap; // @[IDPool.scala:18:23] reg [2:0] select; // @[IDPool.scala:19:23] assign io_alloc_bits_0 = select; // @[IDPool.scala:8:7, :19:23] reg valid; // @[IDPool.scala:20:23] assign io_alloc_valid_0 = valid; // @[IDPool.scala:8:7, :20:23] wire [7:0] _taken_T = 8'h1 << taken_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _taken_T_1 = _taken_T; // @[OneHot.scala:65:{12,27}] wire [7:0] taken = io_alloc_ready_0 ? _taken_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _allocated_T = 8'h1 << allocated_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _allocated_T_1 = _allocated_T; // @[OneHot.scala:65:{12,27}] wire [7:0] allocated = io_free_valid_0 ? _allocated_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _bitmap1_T = ~taken; // @[IDPool.scala:25:19, :27:27] wire [7:0] _bitmap1_T_1 = bitmap & _bitmap1_T; // @[IDPool.scala:18:23, :27:{25,27}] wire [7:0] bitmap1 = _bitmap1_T_1 \| allocated; // @[IDPool.scala:26:22, :27:{25,35}] wire _select1_T = bitmap1[0]; // @[OneHot.scala:48:45] wire _select1_T_1 = bitmap1[1]; // @[OneHot.scala:48:45] wire _select1_T_2 = bitmap1[2]; // @[OneHot.scala:48:45] wire _select1_T_3 = bitmap1[3]; // @[OneHot.scala:48:45] wire _select1_T_4 = bitmap1[4]; // @[OneHot.scala:48:45] wire _select1_T_5 = bitmap1[5]; // @[OneHot.scala:48:45] wire _select1_T_6 = bitmap1[6]; // @[OneHot.scala:48:45] wire _select1_T_7 = bitmap1[7]; // @[OneHot.scala:48:45] wire [2:0] _select1_T_8 = {2'h3, ~_select1_T_6}; // @[OneHot.scala:48:45] wire [2:0] _select1_T_9 = _select1_T_5 ? 3'h5 : _select1_T_8; // @[OneHot.scala:48:45] wire [2:0] _select1_T_10 = _select1_T_4 ? 3'h4 : _select1_T_9; // @[OneHot.scala:48:45] wire [2:0] _select1_T_11 = _select1_T_3 ? 3'h3 : _select1_T_10; // @[OneHot.scala:48:45] wire [2:0] _select1_T_12 = _select1_T_2 ? 3'h2 : _select1_T_11; // @[OneHot.scala:48:45] wire [2:0] _select1_T_13 = _select1_T_1 ? 3'h1 : _select1_T_12; // @[OneHot.scala:48:45] wire [2:0] select1 = _select1_T ? 3'h0 : _select1_T_13; // @[OneHot.scala:48:45] wire _valid1_T = \|bitmap; // @[IDPool.scala:18:23, :29:28] wire _valid1_T_1 = bitmap[0]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_2 = bitmap[1]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_3 = bitmap[2]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_4 = bitmap[3]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_5 = bitmap[4]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_6 = bitmap[5]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_7 = bitmap[6]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_8 = bitmap[7]; // @[IDPool.scala:18:23, :29:46] wire [1:0] _valid1_T_9 = {1'h0, _valid1_T_1} + {1'h0, _valid1_T_2}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_10 = _valid1_T_9; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_11 = {1'h0, _valid1_T_3} + {1'h0, _valid1_T_4}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_12 = _valid1_T_11; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_13 = {1'h0, _valid1_T_10} + {1'h0, _valid1_T_12}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_14 = _valid1_T_13; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_15 = {1'h0, _valid1_T_5} + {1'h0, _valid1_T_6}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_16 = _valid1_T_15; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_17 = {1'h0, _valid1_T_7} + {1'h0, _valid1_T_8}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_18 = _valid1_T_17; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_19 = {1'h0, _valid1_T_16} + {1'h0, _valid1_T_18}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_20 = _valid1_T_19; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_21 = {1'h0, _valid1_T_14} + {1'h0, _valid1_T_20}; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_22 = _valid1_T_21; // @[IDPool.scala:29:46] wire _valid1_T_23 = _valid1_T_22 == 4'h1; // @[IDPool.scala:29:{46,55}] wire _valid1_T_24 = _valid1_T_23 & io_alloc_ready_0; // @[IDPool.scala:8:7, :29:{55,64}] wire _valid1_T_25 = ~_valid1_T_24; // @[IDPool.scala:29:{35,64}] wire _valid1_T_26 = _valid1_T & _valid1_T_25; // @[IDPool.scala:29:{28,32,35}] wire valid1 = _valid1_T_26 \| io_free_valid_0; // @[IDPool.scala:8:7, :29:32, :30:17] reg REG; // @[IDPool.scala:51:36]
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i64_e5_s11 : output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 63, 63) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32) node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33) node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34) node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35) node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36) node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37) node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38) node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39) node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40) node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41) node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42) node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43) node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44) node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45) node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46) node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47) node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48) node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49) node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50) node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51) node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52) node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53) node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54) node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55) node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56) node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57) node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58) node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59) node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60) node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61) node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62) node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63) node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f)) node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64) node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65) node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66) node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67) node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68) node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69) node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70) node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71) node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72) node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73) node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74) node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75) node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76) node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77) node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78) node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79) node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80) node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81) node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82) node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83) node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84) node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85) node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86) node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87) node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88) node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89) node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90) node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91) node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92) node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93) node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94) node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95) node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96) node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97) node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98) node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99) node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100) node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101) node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102) node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103) node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104) node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105) node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106) node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107) node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108) node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109) node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110) node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111) node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112) node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113) node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114) node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115) node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116) node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117) node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118) node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119) node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120) node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121) node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122) node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123) node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i64_e5_s11( // @[INToRecFN.scala:43:7] input io_signedIn, // @[INToRecFN.scala:46:16] input [63:0] io_in, // @[INToRecFN.scala:46:16] input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16] output [16:0] io_out, // @[INToRecFN.scala:46:16] output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16] ); wire intAsRawFloat_sign = io_signedIn & io_in[63]; // @[rawFloatFromIN.scala:51:{29,34}] wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? 64'h0 - io_in : io_in; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [5:0] intAsRawFloat_adjustedNormDist = intAsRawFloat_absIn[63] ? 6'h0 : intAsRawFloat_absIn[62] ? 6'h1 : intAsRawFloat_absIn[61] ? 6'h2 : intAsRawFloat_absIn[60] ? 6'h3 : intAsRawFloat_absIn[59] ? 6'h4 : intAsRawFloat_absIn[58] ? 6'h5 : intAsRawFloat_absIn[57] ? 6'h6 : intAsRawFloat_absIn[56] ? 6'h7 : intAsRawFloat_absIn[55] ? 6'h8 : intAsRawFloat_absIn[54] ? 6'h9 : intAsRawFloat_absIn[53] ? 6'hA : intAsRawFloat_absIn[52] ? 6'hB : intAsRawFloat_absIn[51] ? 6'hC : intAsRawFloat_absIn[50] ? 6'hD : intAsRawFloat_absIn[49] ? 6'hE : intAsRawFloat_absIn[48] ? 6'hF : intAsRawFloat_absIn[47] ? 6'h10 : intAsRawFloat_absIn[46] ? 6'h11 : intAsRawFloat_absIn[45] ? 6'h12 : intAsRawFloat_absIn[44] ? 6'h13 : intAsRawFloat_absIn[43] ? 6'h14 : intAsRawFloat_absIn[42] ? 6'h15 : intAsRawFloat_absIn[41] ? 6'h16 : intAsRawFloat_absIn[40] ? 6'h17 : intAsRawFloat_absIn[39] ? 6'h18 : intAsRawFloat_absIn[38] ? 6'h19 : intAsRawFloat_absIn[37] ? 6'h1A : intAsRawFloat_absIn[36] ? 6'h1B : intAsRawFloat_absIn[35] ? 6'h1C : intAsRawFloat_absIn[34] ? 6'h1D : intAsRawFloat_absIn[33] ? 6'h1E : intAsRawFloat_absIn[32] ? 6'h1F : intAsRawFloat_absIn[31] ? 6'h20 : intAsRawFloat_absIn[30] ? 6'h21 : intAsRawFloat_absIn[29] ? 6'h22 : intAsRawFloat_absIn[28] ? 6'h23 : intAsRawFloat_absIn[27] ? 6'h24 : intAsRawFloat_absIn[26] ? 6'h25 : intAsRawFloat_absIn[25] ? 6'h26 : intAsRawFloat_absIn[24] ? 6'h27 : intAsRawFloat_absIn[23] ? 6'h28 : intAsRawFloat_absIn[22] ? 6'h29 : intAsRawFloat_absIn[21] ? 6'h2A : intAsRawFloat_absIn[20] ? 6'h2B : intAsRawFloat_absIn[19] ? 6'h2C : intAsRawFloat_absIn[18] ? 6'h2D : intAsRawFloat_absIn[17] ? 6'h2E : intAsRawFloat_absIn[16] ? 6'h2F : intAsRawFloat_absIn[15] ? 6'h30 : intAsRawFloat_absIn[14] ? 6'h31 : intAsRawFloat_absIn[13] ? 6'h32 : intAsRawFloat_absIn[12] ? 6'h33 : intAsRawFloat_absIn[11] ? 6'h34 : intAsRawFloat_absIn[10] ? 6'h35 : intAsRawFloat_absIn[9] ? 6'h36 : intAsRawFloat_absIn[8] ? 6'h37 : intAsRawFloat_absIn[7] ? 6'h38 : intAsRawFloat_absIn[6] ? 6'h39 : intAsRawFloat_absIn[5] ? 6'h3A : intAsRawFloat_absIn[4] ? 6'h3B : intAsRawFloat_absIn[3] ? 6'h3C : intAsRawFloat_absIn[2] ? 6'h3D : {5'h1F, ~(intAsRawFloat_absIn[1])}; // @[Mux.scala:50:70] wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_absIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (~(_intAsRawFloat_sig_T[63])), // @[rawFloatFromIN.scala:56:{22,41}, :62:{23,28}] .io_in_sign (intAsRawFloat_sign), // @[rawFloatFromIN.scala:51:29] .io_in_sExp ({3'h2, ~intAsRawFloat_adjustedNormDist}), // @[Mux.scala:50:70] .io_in_sig ({1'h0, _intAsRawFloat_sig_T[63:0]}), // @[rawFloatFromIN.scala:52:31, :56:{22,41}, :65:20] .io_roundingMode (io_roundingMode), .io_out (io_out), .io_exceptionFlags (io_exceptionFlags) ); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_197 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_197( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_85 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_85( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_23 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_46 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_23 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id) node _T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0h8) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h3) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<2>(0h3), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<2> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0h8)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_16 = eq(UInt<5>(0h16), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(UInt<5>(0h17), io.in.bits.egress_id) when _T_17 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_18 = eq(UInt<5>(0h18), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(route_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_47 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_23 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_26 = and(vcalloc_q.io.enq.valid, _T_25) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_2 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_16 = or(_out_bundle_bits_out_virt_channel_T_15, _out_bundle_bits_out_virt_channel_T_13) node _out_bundle_bits_out_virt_channel_T_17 = or(_out_bundle_bits_out_virt_channel_T_16, _out_bundle_bits_out_virt_channel_T_14) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_17 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_23( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'h4; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'h6; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 4'h8; // @[IngressUnit.scala:30:72] wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {2'h0, {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, _route_buffer_io_enq_bits_flow_egress_node_id_T_1} \| {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_3}}}; // @[Mux.scala:30:73] wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_plic : input clock : Clock input reset : Reset output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fragmenter of TLFragmenter_PLIC connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect fragmenter.auto.anon_in, tlOut connect tlIn, auto.tl_in connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready extmodule plusarg_reader_52 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_53 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLInterconnectCoupler_cbus_to_plic( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_PLIC fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_366 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_366( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module SourceD_7 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<128>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, flip bs_rdat : { data : UInt<128>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, bs_wdat : { data : UInt<128>}, flip evict_req : { set : UInt<11>, way : UInt<4>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<11>, way : UInt<4>}, grant_safe : UInt<1>} wire s1_valid : UInt<1> wire s2_valid : UInt<1> wire s3_valid : UInt<1> wire s2_ready : UInt<1> wire s3_ready : UInt<1> wire s4_ready : UInt<1> regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _s1_req_reg_T = eq(busy, UInt<1>(0h0)) node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid) reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when _s1_req_reg_T_1 : connect s1_req_reg, io.req.bits node _s1_req_T = eq(busy, UInt<1>(0h0)) node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg) wire s1_x_bypass : UInt<2> node _s1_latch_bypass_T = or(busy, io.req.valid) node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0)) node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready) reg s1_latch_bypass : UInt<1>, clock connect s1_latch_bypass, _s1_latch_bypass_T_2 reg s1_bypass_r : UInt<2>, clock when s1_latch_bypass : connect s1_bypass_r, s1_x_bypass node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r) node _s1_mask_sizeOH_T = or(s1_req.size, UInt<4>(0h0)) node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 1, 0) node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount) node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 3, 0) node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<4>(0hf)) node s1_mask_sub_0_1 = geq(s1_req.size, UInt<3>(0h4)) node s1_mask_size = bits(s1_mask_sizeOH, 3, 3) node s1_mask_bit = bits(s1_req.offset, 3, 3) node s1_mask_nbit = eq(s1_mask_bit, UInt<1>(0h0)) node s1_mask_eq = and(UInt<1>(0h1), s1_mask_nbit) node _s1_mask_acc_T = and(s1_mask_size, s1_mask_eq) node s1_mask_acc = or(s1_mask_sub_0_1, _s1_mask_acc_T) node s1_mask_eq_1 = and(UInt<1>(0h1), s1_mask_bit) node _s1_mask_acc_T_1 = and(s1_mask_size, s1_mask_eq_1) node s1_mask_acc_1 = or(s1_mask_sub_0_1, _s1_mask_acc_T_1) node _s1_mask_T = cat(s1_mask_acc_1, s1_mask_acc) node _s1_mask_T_1 = not(s1_bypass) node s1_mask = and(_s1_mask_T, _s1_mask_T_1) node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6)) node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2)) node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1) node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7)) node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3) node _s1_need_r_T = orr(s1_mask) node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0]) node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5)) node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2) node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0)) node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4) node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0)) node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h3)) node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7) node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8) node _s1_valid_r_T = or(busy, io.req.valid) node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r) node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0)) node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2) node _s1_need_pb_T = bits(s1_req.opcode, 2, 2) node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0)) node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0) node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2) node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5)) node _s1_single_T_1 = or(_s1_single_T, s1_grant) node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6)) node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2) node s1_retires = eq(s1_single, UInt<1>(0h0)) node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size) node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0) node _s1_beats1_T_2 = not(_s1_beats1_T_1) node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 4) node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3) node _s1_beat_T = shr(s1_req.offset, 4) node s1_beat = or(_s1_beat_T, s1_counter) node s1_last = eq(s1_counter, s1_beats1) node s1_first = eq(s1_counter, UInt<1>(0h0)) node _T = eq(s1_latch_bypass, UInt<1>(0h0)) node _T_1 = or(busy, io.req.valid) node _T_2 = eq(s1_need_r, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) connect io.bs_radr.valid, s1_valid_r connect io.bs_radr.bits.noop, UInt<1>(0h0) connect io.bs_radr.bits.way, s1_req.way connect io.bs_radr.bits.set, s1_req.set connect io.bs_radr.bits.beat, s1_beat connect io.bs_radr.bits.mask, s1_mask node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_radr.valid, _T_4) inst queue of Queue3_BankedStoreInnerDecoded_7 connect queue.clock, clock connect queue.reset, reset node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid) reg queue_io_enq_valid_REG : UInt<1>, clock connect queue_io_enq_valid_REG, _queue_io_enq_valid_T reg queue_io_enq_valid_REG_1 : UInt<1>, clock connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG connect queue.io.enq.valid, queue_io_enq_valid_REG_1 connect queue.io.enq.bits.data, io.bs_rdat.data node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0)) node _T_7 = or(_T_6, queue.io.enq.ready) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid \|\| queue.io.enq.ready)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid) when _T_12 : connect s1_block_r, UInt<1>(0h1) when io.req.valid : connect busy, UInt<1>(0h1) node _T_13 = and(s1_valid, s2_ready) when _T_13 : node _s1_counter_T = add(s1_counter, UInt<1>(0h1)) node _s1_counter_T_1 = tail(_s1_counter_T, 1) connect s1_counter, _s1_counter_T_1 connect s1_block_r, UInt<1>(0h0) when s1_last : connect s1_counter, UInt<1>(0h0) connect busy, UInt<1>(0h0) node _T_14 = eq(s2_ready, UInt<1>(0h0)) node _T_15 = and(s1_valid, _T_14) node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _s1_valid_T = or(busy, io.req.valid) node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0)) node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready) node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2) connect s1_valid, _s1_valid_T_3 node s2_latch = and(s1_valid, s2_ready) regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_beat : UInt<2>, clock when s2_latch : connect s2_beat, s1_beat reg s2_bypass : UInt<2>, clock when s2_latch : connect s2_bypass, s1_bypass reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s2_latch : connect s2_req, s1_req reg s2_last : UInt<1>, clock when s2_latch : connect s2_last, s1_last reg s2_need_r : UInt<1>, clock when s2_latch : connect s2_need_r, s1_need_r reg s2_need_pb : UInt<1>, clock when s2_latch : connect s2_need_pb, s1_need_pb reg s2_retires : UInt<1>, clock when s2_latch : connect s2_retires, s1_retires node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0)) node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first) reg s2_need_d : UInt<1>, clock when s2_latch : connect s2_need_d, _s2_need_d_T_1 wire s2_pdata_raw : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>} reg s2_pdata_r : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s2_valid_pb : connect s2_pdata_r, s2_pdata_raw node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r) node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data) connect s2_pdata_raw.data, _s2_pdata_raw_data_T node _s2_pdata_raw_mask_T = not(UInt<16>(0h0)) node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T) connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1 node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt) connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0]) connect io.pb_pop.valid, _io_pb_pop_valid_T connect io.pb_pop.bits.index, s2_req.put connect io.pb_pop.bits.last, s2_last node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0)) node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T) connect io.rel_pop.valid, _io_rel_pop_valid_T_1 connect io.rel_pop.bits.index, s2_req.put connect io.rel_pop.bits.last, s2_last node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0)) node _T_17 = and(io.pb_pop.valid, _T_16) node _T_18 = eq(io.rel_pop.ready, UInt<1>(0h0)) node _T_19 = and(io.rel_pop.valid, _T_18) node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready) when pb_ready : connect s2_valid_pb, UInt<1>(0h0) node _T_20 = and(s2_valid, s3_ready) when _T_20 : connect s2_full, UInt<1>(0h0) when s2_latch : connect s2_valid_pb, s1_need_pb when s2_latch : connect s2_full, UInt<1>(0h1) node _T_21 = eq(s3_ready, UInt<1>(0h0)) node _T_22 = and(s2_valid, _T_21) node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_valid_T_1 = or(_s2_valid_T, pb_ready) node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1) connect s2_valid, _s2_valid_T_2 node _s2_ready_T = eq(s2_full, UInt<1>(0h0)) node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready) node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2) node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3) connect s2_ready, _s2_ready_T_4 node s3_latch = and(s2_valid, s3_ready) regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0) reg s3_beat : UInt<2>, clock when s3_latch : connect s3_beat, s2_beat reg s3_bypass : UInt<2>, clock when s3_latch : connect s3_bypass, s2_bypass reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s3_latch : connect s3_req, s2_req node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode) reg s3_last : UInt<1>, clock when s3_latch : connect s3_last, s2_last reg s3_pdata : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s3_latch : connect s3_pdata, s2_pdata reg s3_need_pb : UInt<1>, clock when s3_latch : connect s3_need_pb, s2_need_pb reg s3_retires : UInt<1>, clock when s3_latch : connect s3_retires, s2_retires reg s3_need_r : UInt<1>, clock when s3_latch : connect s3_need_r, s2_need_r node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6)) node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7)) node s3_acq = or(_s3_acq_T, _s3_acq_T_1) wire s3_bypass_data : UInt node _s3_rdata_T = bits(s3_bypass, 0, 0) node _s3_rdata_T_1 = bits(s3_bypass, 1, 1) node _s3_rdata_T_2 = bits(s3_bypass_data, 63, 0) node _s3_rdata_T_3 = bits(s3_bypass_data, 127, 64) node _s3_rdata_T_4 = bits(queue.io.deq.bits.data, 63, 0) node _s3_rdata_T_5 = bits(queue.io.deq.bits.data, 127, 64) node _s3_rdata_T_6 = mux(_s3_rdata_T, _s3_rdata_T_2, _s3_rdata_T_4) node _s3_rdata_T_7 = mux(_s3_rdata_T_1, _s3_rdata_T_3, _s3_rdata_T_5) node s3_rdata = cat(_s3_rdata_T_7, _s3_rdata_T_6) node _grant_T = eq(s3_req.param, UInt<2>(0h2)) node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5)) wire resp_opcode : UInt<3>[8] connect resp_opcode[0], UInt<1>(0h0) connect resp_opcode[1], UInt<1>(0h0) connect resp_opcode[2], UInt<1>(0h1) connect resp_opcode[3], UInt<1>(0h1) connect resp_opcode[4], UInt<1>(0h1) connect resp_opcode[5], UInt<2>(0h2) connect resp_opcode[6], grant connect resp_opcode[7], UInt<3>(0h4) wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect io.d, d connect d.valid, s3_valid_d node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6)) connect d.bits.opcode, _d_bits_opcode_T node _d_bits_param_T = and(s3_req.prio[0], s3_acq) node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0)) node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1)) node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0)) connect d.bits.param, _d_bits_param_T_3 connect d.bits.size, s3_req.size connect d.bits.source, s3_req.source connect d.bits.sink, s3_req.sink connect d.bits.denied, s3_req.bad connect d.bits.data, s3_rdata node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0) node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T) connect d.bits.corrupt, _d_bits_corrupt_T_1 node _queue_io_deq_ready_T = and(s3_valid, s4_ready) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _T_23 = eq(s3_full, UInt<1>(0h0)) node _T_24 = eq(s3_need_r, UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = or(_T_25, queue.io.deq.valid) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full \|\| !s3_need_r \|\| queue.io.deq.valid)\n") : printf_1 assert(clock, _T_26, UInt<1>(0h1), "") : assert_1 when d.ready : connect s3_valid_d, UInt<1>(0h0) node _T_30 = and(s3_valid, s4_ready) when _T_30 : connect s3_full, UInt<1>(0h0) when s3_latch : connect s3_valid_d, s2_need_d when s3_latch : connect s3_full, UInt<1>(0h1) node _T_31 = eq(s4_ready, UInt<1>(0h0)) node _T_32 = and(s3_valid, _T_31) node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0)) node _s3_valid_T_1 = or(_s3_valid_T, d.ready) node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1) connect s3_valid, _s3_valid_T_2 node _s3_ready_T = eq(s3_full, UInt<1>(0h0)) node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0)) node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready) node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2) node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3) connect s3_ready, _s3_ready_T_4 node _s4_latch_T = and(s3_valid, s3_retires) node s4_latch = and(_s4_latch_T, s4_ready) regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0) reg s4_beat : UInt<2>, clock when s4_latch : connect s4_beat, s3_beat reg s4_need_r : UInt<1>, clock when s4_latch : connect s4_need_r, s3_need_r reg s4_need_bs : UInt<1>, clock when s4_latch : connect s4_need_bs, s3_need_pb reg s4_need_pb : UInt<1>, clock when s4_latch : connect s4_need_pb, s3_need_pb reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s4_latch : connect s4_req, s3_req reg s4_adjusted_opcode : UInt<3>, clock when s4_latch : connect s4_adjusted_opcode, s3_adjusted_opcode reg s4_pdata : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s4_latch : connect s4_pdata, s3_pdata reg s4_rdata : UInt<128>, clock when s4_latch : connect s4_rdata, s3_rdata inst atomics of Atomics_7 connect atomics.clock, clock connect atomics.reset, reset connect atomics.io.write, s4_req.prio[2] connect atomics.io.a.opcode, s4_adjusted_opcode connect atomics.io.a.param, s4_req.param connect atomics.io.a.size, UInt<1>(0h0) connect atomics.io.a.source, UInt<1>(0h0) connect atomics.io.a.address, UInt<1>(0h0) connect atomics.io.a.mask, s4_pdata.mask connect atomics.io.a.data, s4_pdata.data invalidate atomics.io.a.corrupt connect atomics.io.data_in, s4_rdata node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs) connect io.bs_wadr.valid, _io_bs_wadr_valid_T connect io.bs_wadr.bits.noop, UInt<1>(0h0) connect io.bs_wadr.bits.way, s4_req.way connect io.bs_wadr.bits.set, s4_req.set connect io.bs_wadr.bits.beat, s4_beat node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0) node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1) node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2) node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3) node _io_bs_wadr_bits_mask_T_4 = bits(s4_pdata.mask, 4, 4) node _io_bs_wadr_bits_mask_T_5 = bits(s4_pdata.mask, 5, 5) node _io_bs_wadr_bits_mask_T_6 = bits(s4_pdata.mask, 6, 6) node _io_bs_wadr_bits_mask_T_7 = bits(s4_pdata.mask, 7, 7) node _io_bs_wadr_bits_mask_T_8 = bits(s4_pdata.mask, 8, 8) node _io_bs_wadr_bits_mask_T_9 = bits(s4_pdata.mask, 9, 9) node _io_bs_wadr_bits_mask_T_10 = bits(s4_pdata.mask, 10, 10) node _io_bs_wadr_bits_mask_T_11 = bits(s4_pdata.mask, 11, 11) node _io_bs_wadr_bits_mask_T_12 = bits(s4_pdata.mask, 12, 12) node _io_bs_wadr_bits_mask_T_13 = bits(s4_pdata.mask, 13, 13) node _io_bs_wadr_bits_mask_T_14 = bits(s4_pdata.mask, 14, 14) node _io_bs_wadr_bits_mask_T_15 = bits(s4_pdata.mask, 15, 15) node _io_bs_wadr_bits_mask_T_16 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1) node _io_bs_wadr_bits_mask_T_17 = or(_io_bs_wadr_bits_mask_T_16, _io_bs_wadr_bits_mask_T_2) node _io_bs_wadr_bits_mask_T_18 = or(_io_bs_wadr_bits_mask_T_17, _io_bs_wadr_bits_mask_T_3) node _io_bs_wadr_bits_mask_T_19 = or(_io_bs_wadr_bits_mask_T_18, _io_bs_wadr_bits_mask_T_4) node _io_bs_wadr_bits_mask_T_20 = or(_io_bs_wadr_bits_mask_T_19, _io_bs_wadr_bits_mask_T_5) node _io_bs_wadr_bits_mask_T_21 = or(_io_bs_wadr_bits_mask_T_20, _io_bs_wadr_bits_mask_T_6) node _io_bs_wadr_bits_mask_T_22 = or(_io_bs_wadr_bits_mask_T_21, _io_bs_wadr_bits_mask_T_7) node _io_bs_wadr_bits_mask_T_23 = or(_io_bs_wadr_bits_mask_T_8, _io_bs_wadr_bits_mask_T_9) node _io_bs_wadr_bits_mask_T_24 = or(_io_bs_wadr_bits_mask_T_23, _io_bs_wadr_bits_mask_T_10) node _io_bs_wadr_bits_mask_T_25 = or(_io_bs_wadr_bits_mask_T_24, _io_bs_wadr_bits_mask_T_11) node _io_bs_wadr_bits_mask_T_26 = or(_io_bs_wadr_bits_mask_T_25, _io_bs_wadr_bits_mask_T_12) node _io_bs_wadr_bits_mask_T_27 = or(_io_bs_wadr_bits_mask_T_26, _io_bs_wadr_bits_mask_T_13) node _io_bs_wadr_bits_mask_T_28 = or(_io_bs_wadr_bits_mask_T_27, _io_bs_wadr_bits_mask_T_14) node _io_bs_wadr_bits_mask_T_29 = or(_io_bs_wadr_bits_mask_T_28, _io_bs_wadr_bits_mask_T_15) node _io_bs_wadr_bits_mask_T_30 = cat(_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22) connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_30 connect io.bs_wdat.data, atomics.io.data_out node _T_33 = and(s4_full, s4_need_pb) node _T_34 = and(_T_33, s4_pdata.corrupt) node _T_35 = eq(_T_34, UInt<1>(0h0)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2 assert(clock, _T_35, UInt<1>(0h1), "") : assert_2 node _T_39 = eq(io.bs_wadr.ready, UInt<1>(0h0)) node _T_40 = and(io.bs_wadr.valid, _T_39) node _T_41 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_42 = and(s4_req.prio[0], _T_41) node _T_43 = eq(s4_req.param, UInt<3>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_46 = and(s4_req.prio[0], _T_45) node _T_47 = eq(s4_req.param, UInt<3>(0h1)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_50 = and(s4_req.prio[0], _T_49) node _T_51 = eq(s4_req.param, UInt<3>(0h2)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_54 = and(s4_req.prio[0], _T_53) node _T_55 = eq(s4_req.param, UInt<3>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_58 = and(s4_req.prio[0], _T_57) node _T_59 = eq(s4_req.param, UInt<3>(0h4)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_62 = and(s4_req.prio[0], _T_61) node _T_63 = eq(s4_req.param, UInt<3>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_66 = and(s4_req.prio[0], _T_65) node _T_67 = eq(s4_req.param, UInt<3>(0h1)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_70 = and(s4_req.prio[0], _T_69) node _T_71 = eq(s4_req.param, UInt<3>(0h2)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_74 = and(s4_req.prio[0], _T_73) node _T_75 = eq(s4_req.param, UInt<3>(0h3)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(s4_need_bs, UInt<1>(0h0)) node _T_78 = or(io.bs_wadr.ready, _T_77) when _T_78 : connect s4_full, UInt<1>(0h0) when s4_latch : connect s4_full, UInt<1>(0h1) node _s4_ready_T = eq(s3_retires, UInt<1>(0h0)) node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0)) node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1) node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready) node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0)) node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4) connect s4_ready, _s4_ready_T_5 node _retire_T = eq(s4_need_bs, UInt<1>(0h0)) node _retire_T_1 = or(io.bs_wadr.ready, _retire_T) node retire = and(s4_full, _retire_T_1) reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when retire : connect s5_req, s4_req reg s5_beat : UInt<2>, clock when retire : connect s5_beat, s4_beat reg s5_dat : UInt<128>, clock when retire : connect s5_dat, atomics.io.data_out reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when retire : connect s6_req, s5_req reg s6_beat : UInt<2>, clock when retire : connect s6_beat, s5_beat reg s6_dat : UInt<128>, clock when retire : connect s6_dat, s5_dat reg s7_dat : UInt<128>, clock when retire : connect s7_dat, s6_dat node pre_s3_req = mux(s3_latch, s2_req, s3_req) node pre_s4_req = mux(s4_latch, s3_req, s4_req) node pre_s5_req = mux(retire, s4_req, s5_req) node pre_s6_req = mux(retire, s5_req, s6_req) node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat) node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat) node pre_s5_beat = mux(retire, s4_beat, s5_beat) node pre_s6_beat = mux(retire, s5_beat, s6_beat) node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat) node pre_s6_dat = mux(retire, s5_dat, s6_dat) node pre_s7_dat = mux(retire, s6_dat, s7_dat) node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0)) node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T) node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0)) node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full) node pre_s4_full = or(s4_latch, _pre_s4_full_T_3) node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set) node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way) node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1) node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat) node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3) node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full) node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set) node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way) node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1) node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat) node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3) node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set) node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way) node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1) node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat) node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3) node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<4>(0h0)) node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 1, 0) node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount) node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 3, 0) node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_4_bypass_sub_0_1 = geq(pre_s4_req.size, UInt<3>(0h4)) node pre_s3_4_bypass_size = bits(pre_s3_4_bypass_sizeOH, 3, 3) node pre_s3_4_bypass_bit = bits(pre_s4_req.offset, 3, 3) node pre_s3_4_bypass_nbit = eq(pre_s3_4_bypass_bit, UInt<1>(0h0)) node pre_s3_4_bypass_eq = and(UInt<1>(0h1), pre_s3_4_bypass_nbit) node _pre_s3_4_bypass_acc_T = and(pre_s3_4_bypass_size, pre_s3_4_bypass_eq) node pre_s3_4_bypass_acc = or(pre_s3_4_bypass_sub_0_1, _pre_s3_4_bypass_acc_T) node pre_s3_4_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_4_bypass_bit) node _pre_s3_4_bypass_acc_T_1 = and(pre_s3_4_bypass_size, pre_s3_4_bypass_eq_1) node pre_s3_4_bypass_acc_1 = or(pre_s3_4_bypass_sub_0_1, _pre_s3_4_bypass_acc_T_1) node _pre_s3_4_bypass_T = cat(pre_s3_4_bypass_acc_1, pre_s3_4_bypass_acc) node pre_s3_4_bypass = mux(pre_s3_4_match, _pre_s3_4_bypass_T, UInt<1>(0h0)) node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<4>(0h0)) node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 1, 0) node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount) node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 3, 0) node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_5_bypass_sub_0_1 = geq(pre_s5_req.size, UInt<3>(0h4)) node pre_s3_5_bypass_size = bits(pre_s3_5_bypass_sizeOH, 3, 3) node pre_s3_5_bypass_bit = bits(pre_s5_req.offset, 3, 3) node pre_s3_5_bypass_nbit = eq(pre_s3_5_bypass_bit, UInt<1>(0h0)) node pre_s3_5_bypass_eq = and(UInt<1>(0h1), pre_s3_5_bypass_nbit) node _pre_s3_5_bypass_acc_T = and(pre_s3_5_bypass_size, pre_s3_5_bypass_eq) node pre_s3_5_bypass_acc = or(pre_s3_5_bypass_sub_0_1, _pre_s3_5_bypass_acc_T) node pre_s3_5_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_5_bypass_bit) node _pre_s3_5_bypass_acc_T_1 = and(pre_s3_5_bypass_size, pre_s3_5_bypass_eq_1) node pre_s3_5_bypass_acc_1 = or(pre_s3_5_bypass_sub_0_1, _pre_s3_5_bypass_acc_T_1) node _pre_s3_5_bypass_T = cat(pre_s3_5_bypass_acc_1, pre_s3_5_bypass_acc) node pre_s3_5_bypass = mux(pre_s3_5_match, _pre_s3_5_bypass_T, UInt<1>(0h0)) node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<4>(0h0)) node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 1, 0) node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount) node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 3, 0) node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_6_bypass_sub_0_1 = geq(pre_s6_req.size, UInt<3>(0h4)) node pre_s3_6_bypass_size = bits(pre_s3_6_bypass_sizeOH, 3, 3) node pre_s3_6_bypass_bit = bits(pre_s6_req.offset, 3, 3) node pre_s3_6_bypass_nbit = eq(pre_s3_6_bypass_bit, UInt<1>(0h0)) node pre_s3_6_bypass_eq = and(UInt<1>(0h1), pre_s3_6_bypass_nbit) node _pre_s3_6_bypass_acc_T = and(pre_s3_6_bypass_size, pre_s3_6_bypass_eq) node pre_s3_6_bypass_acc = or(pre_s3_6_bypass_sub_0_1, _pre_s3_6_bypass_acc_T) node pre_s3_6_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_6_bypass_bit) node _pre_s3_6_bypass_acc_T_1 = and(pre_s3_6_bypass_size, pre_s3_6_bypass_eq_1) node pre_s3_6_bypass_acc_1 = or(pre_s3_6_bypass_sub_0_1, _pre_s3_6_bypass_acc_T_1) node _pre_s3_6_bypass_T = cat(pre_s3_6_bypass_acc_1, pre_s3_6_bypass_acc) node pre_s3_6_bypass = mux(pre_s3_6_match, _pre_s3_6_bypass_T, UInt<1>(0h0)) reg s3_bypass_data_REG : UInt, clock connect s3_bypass_data_REG, pre_s3_4_bypass node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0) node _s3_bypass_data_T_1 = bits(pre_s3_6_bypass, 1, 1) node _s3_bypass_data_T_2 = bits(pre_s6_dat, 63, 0) node _s3_bypass_data_T_3 = bits(pre_s6_dat, 127, 64) node _s3_bypass_data_T_4 = bits(pre_s7_dat, 63, 0) node _s3_bypass_data_T_5 = bits(pre_s7_dat, 127, 64) node _s3_bypass_data_T_6 = mux(_s3_bypass_data_T, _s3_bypass_data_T_2, _s3_bypass_data_T_4) node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_1, _s3_bypass_data_T_3, _s3_bypass_data_T_5) node _s3_bypass_data_T_8 = cat(_s3_bypass_data_T_7, _s3_bypass_data_T_6) node _s3_bypass_data_T_9 = bits(pre_s3_5_bypass, 0, 0) node _s3_bypass_data_T_10 = bits(pre_s3_5_bypass, 1, 1) node _s3_bypass_data_T_11 = bits(pre_s5_dat, 63, 0) node _s3_bypass_data_T_12 = bits(pre_s5_dat, 127, 64) node _s3_bypass_data_T_13 = bits(_s3_bypass_data_T_8, 63, 0) node _s3_bypass_data_T_14 = bits(_s3_bypass_data_T_8, 127, 64) node _s3_bypass_data_T_15 = mux(_s3_bypass_data_T_9, _s3_bypass_data_T_11, _s3_bypass_data_T_13) node _s3_bypass_data_T_16 = mux(_s3_bypass_data_T_10, _s3_bypass_data_T_12, _s3_bypass_data_T_14) node _s3_bypass_data_T_17 = cat(_s3_bypass_data_T_16, _s3_bypass_data_T_15) reg s3_bypass_data_REG_1 : UInt, clock connect s3_bypass_data_REG_1, _s3_bypass_data_T_17 node _s3_bypass_data_T_18 = bits(s3_bypass_data_REG, 0, 0) node _s3_bypass_data_T_19 = bits(s3_bypass_data_REG, 1, 1) node _s3_bypass_data_T_20 = bits(atomics.io.data_out, 63, 0) node _s3_bypass_data_T_21 = bits(atomics.io.data_out, 127, 64) node _s3_bypass_data_T_22 = bits(s3_bypass_data_REG_1, 63, 0) node _s3_bypass_data_T_23 = bits(s3_bypass_data_REG_1, 127, 64) node _s3_bypass_data_T_24 = mux(_s3_bypass_data_T_18, _s3_bypass_data_T_20, _s3_bypass_data_T_22) node _s3_bypass_data_T_25 = mux(_s3_bypass_data_T_19, _s3_bypass_data_T_21, _s3_bypass_data_T_23) node _s3_bypass_data_T_26 = cat(_s3_bypass_data_T_25, _s3_bypass_data_T_24) connect s3_bypass_data, _s3_bypass_data_T_26 node _s1_2_match_T = eq(s2_req.set, s1_req.set) node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way) node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1) node _s1_2_match_T_3 = eq(s2_beat, s1_beat) node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3) node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full) node s1_2_match = and(_s1_2_match_T_5, s2_retires) node _s1_3_match_T = eq(s3_req.set, s1_req.set) node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way) node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1) node _s1_3_match_T_3 = eq(s3_beat, s1_beat) node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3) node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full) node s1_3_match = and(_s1_3_match_T_5, s3_retires) node _s1_4_match_T = eq(s4_req.set, s1_req.set) node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way) node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1) node _s1_4_match_T_3 = eq(s4_beat, s1_beat) node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3) node s1_4_match = and(_s1_4_match_T_4, s4_full) node s2 = eq(s1_2_match, UInt<1>(0h1)) node s3 = eq(s1_3_match, UInt<1>(0h0)) node s4 = eq(s1_4_match, UInt<1>(0h0)) node _T_79 = and(io.req.valid, s2) node _T_80 = and(_T_79, s3) node _T_81 = and(_T_80, s4) node s2_1 = eq(s1_2_match, UInt<1>(0h1)) node s3_1 = eq(s1_3_match, UInt<1>(0h0)) node s4_1 = eq(s1_4_match, UInt<1>(0h0)) node _T_82 = and(io.req.valid, s2_1) node _T_83 = and(_T_82, s3_1) node _T_84 = and(_T_83, s4_1) node s2_2 = eq(s1_2_match, UInt<1>(0h1)) node s3_2 = eq(s1_3_match, UInt<1>(0h0)) node s4_2 = eq(s1_4_match, UInt<1>(0h0)) node _T_85 = and(io.req.valid, s2_2) node _T_86 = and(_T_85, s3_2) node _T_87 = and(_T_86, s4_2) node s2_3 = eq(s1_2_match, UInt<1>(0h1)) node s3_3 = eq(s1_3_match, UInt<1>(0h0)) node s4_3 = eq(s1_4_match, UInt<1>(0h0)) node _T_88 = and(io.req.valid, s2_3) node _T_89 = and(_T_88, s3_3) node _T_90 = and(_T_89, s4_3) node s2_4 = eq(s1_2_match, UInt<1>(0h1)) node s3_4 = eq(s1_3_match, UInt<1>(0h0)) node s4_4 = eq(s1_4_match, UInt<1>(0h0)) node _T_91 = and(io.req.valid, s2_4) node _T_92 = and(_T_91, s3_4) node _T_93 = and(_T_92, s4_4) node s2_5 = eq(s1_2_match, UInt<1>(0h1)) node s3_5 = eq(s1_3_match, UInt<1>(0h0)) node s4_5 = eq(s1_4_match, UInt<1>(0h0)) node _T_94 = and(io.req.valid, s2_5) node _T_95 = and(_T_94, s3_5) node _T_96 = and(_T_95, s4_5) node s2_6 = eq(s1_2_match, UInt<1>(0h1)) node s3_6 = eq(s1_3_match, UInt<1>(0h0)) node s4_6 = eq(s1_4_match, UInt<1>(0h0)) node _T_97 = and(io.req.valid, s2_6) node _T_98 = and(_T_97, s3_6) node _T_99 = and(_T_98, s4_6) node s2_7 = eq(s1_2_match, UInt<1>(0h1)) node s3_7 = eq(s1_3_match, UInt<1>(0h0)) node s4_7 = eq(s1_4_match, UInt<1>(0h0)) node _T_100 = and(io.req.valid, s2_7) node _T_101 = and(_T_100, s3_7) node _T_102 = and(_T_101, s4_7) node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<4>(0h0)) node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 1, 0) node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount) node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 3, 0) node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_2_bypass_sub_0_1 = geq(s2_req.size, UInt<3>(0h4)) node s1_2_bypass_size = bits(s1_2_bypass_sizeOH, 3, 3) node s1_2_bypass_bit = bits(s2_req.offset, 3, 3) node s1_2_bypass_nbit = eq(s1_2_bypass_bit, UInt<1>(0h0)) node s1_2_bypass_eq = and(UInt<1>(0h1), s1_2_bypass_nbit) node _s1_2_bypass_acc_T = and(s1_2_bypass_size, s1_2_bypass_eq) node s1_2_bypass_acc = or(s1_2_bypass_sub_0_1, _s1_2_bypass_acc_T) node s1_2_bypass_eq_1 = and(UInt<1>(0h1), s1_2_bypass_bit) node _s1_2_bypass_acc_T_1 = and(s1_2_bypass_size, s1_2_bypass_eq_1) node s1_2_bypass_acc_1 = or(s1_2_bypass_sub_0_1, _s1_2_bypass_acc_T_1) node _s1_2_bypass_T = cat(s1_2_bypass_acc_1, s1_2_bypass_acc) node s1_2_bypass = mux(s1_2_match, _s1_2_bypass_T, UInt<1>(0h0)) node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<4>(0h0)) node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 1, 0) node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount) node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 3, 0) node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_3_bypass_sub_0_1 = geq(s3_req.size, UInt<3>(0h4)) node s1_3_bypass_size = bits(s1_3_bypass_sizeOH, 3, 3) node s1_3_bypass_bit = bits(s3_req.offset, 3, 3) node s1_3_bypass_nbit = eq(s1_3_bypass_bit, UInt<1>(0h0)) node s1_3_bypass_eq = and(UInt<1>(0h1), s1_3_bypass_nbit) node _s1_3_bypass_acc_T = and(s1_3_bypass_size, s1_3_bypass_eq) node s1_3_bypass_acc = or(s1_3_bypass_sub_0_1, _s1_3_bypass_acc_T) node s1_3_bypass_eq_1 = and(UInt<1>(0h1), s1_3_bypass_bit) node _s1_3_bypass_acc_T_1 = and(s1_3_bypass_size, s1_3_bypass_eq_1) node s1_3_bypass_acc_1 = or(s1_3_bypass_sub_0_1, _s1_3_bypass_acc_T_1) node _s1_3_bypass_T = cat(s1_3_bypass_acc_1, s1_3_bypass_acc) node s1_3_bypass = mux(s1_3_match, _s1_3_bypass_T, UInt<1>(0h0)) node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<4>(0h0)) node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 1, 0) node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount) node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 3, 0) node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_4_bypass_sub_0_1 = geq(s4_req.size, UInt<3>(0h4)) node s1_4_bypass_size = bits(s1_4_bypass_sizeOH, 3, 3) node s1_4_bypass_bit = bits(s4_req.offset, 3, 3) node s1_4_bypass_nbit = eq(s1_4_bypass_bit, UInt<1>(0h0)) node s1_4_bypass_eq = and(UInt<1>(0h1), s1_4_bypass_nbit) node _s1_4_bypass_acc_T = and(s1_4_bypass_size, s1_4_bypass_eq) node s1_4_bypass_acc = or(s1_4_bypass_sub_0_1, _s1_4_bypass_acc_T) node s1_4_bypass_eq_1 = and(UInt<1>(0h1), s1_4_bypass_bit) node _s1_4_bypass_acc_T_1 = and(s1_4_bypass_size, s1_4_bypass_eq_1) node s1_4_bypass_acc_1 = or(s1_4_bypass_sub_0_1, _s1_4_bypass_acc_T_1) node _s1_4_bypass_T = cat(s1_4_bypass_acc_1, s1_4_bypass_acc) node s1_4_bypass = mux(s1_4_match, _s1_4_bypass_T, UInt<1>(0h0)) node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass) node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass) connect s1_x_bypass, _s1_x_bypass_T_1 node _io_evict_safe_T = eq(busy, UInt<1>(0h0)) node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way) node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1) node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set) node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3) node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way) node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6) node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set) node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8) node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9) node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way) node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12) node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set) node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14) node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15) node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way) node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18) node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set) node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20) node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21) connect io.evict_safe, _io_evict_safe_T_22 node _io_grant_safe_T = eq(busy, UInt<1>(0h0)) node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way) node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1) node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set) node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3) node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way) node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6) node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set) node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8) node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9) node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way) node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12) node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set) node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14) node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15) node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way) node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18) node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set) node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20) node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21) connect io.grant_safe, _io_grant_safe_T_22	module SourceD_7( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [5:0] io_req_bits_source, // @[SourceD.scala:50:14] input [8:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [10:0] io_req_bits_set, // @[SourceD.scala:50:14] input [3:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [3:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [5:0] io_d_bits_source, // @[SourceD.scala:50:14] output [3:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [127:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [15:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] input io_rel_pop_ready, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_rel_beat_data, // @[SourceD.scala:50:14] input io_rel_beat_corrupt, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [3:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [10:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [127:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [3:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [10:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [127:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [10:0] io_evict_req_set, // @[SourceD.scala:50:14] input [3:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [10:0] io_grant_req_set, // @[SourceD.scala:50:14] input [3:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [127:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire [127:0] _queue_io_deq_bits_data; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [3:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [3:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [15:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [127:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [10:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [3:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [10:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [3:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire s1_mask_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_5_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_6_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_2_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_3_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [15:0] _s2_pdata_raw_mask_T = 16'hFFFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [5:0] d_bits_source; // @[SourceD.scala:218:15] wire [3:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [127:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [3:0] s1_req_way; // @[SourceD.scala:88:19] wire [10:0] s1_req_set; // @[SourceD.scala:88:19] wire [1:0] s1_beat; // @[SourceD.scala:102:56] wire [1:0] s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire [1:0] _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:275:30] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [3:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [127:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [10:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [10:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [127:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [1:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [8:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [10:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [3:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [3:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [8:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [3:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire [1:0] _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire [1:0] s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy \| io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 \| s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg [1:0] s1_bypass_r; // @[SourceD.scala:91:62] wire [1:0] s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [3:0] _s1_mask_sizeOH_T = {1'h0, s1_req_size}; // @[Misc.scala:202:34] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire s1_mask_sub_0_1 = s1_req_size[2]; // @[Misc.scala:206:21] wire s1_mask_bit = s1_req_offset[3]; // @[Misc.scala:210:26] wire s1_mask_eq_1 = s1_mask_bit; // @[Misc.scala:210:26, :214:27] wire s1_mask_nbit = ~s1_mask_bit; // @[Misc.scala:210:26, :211:20] wire s1_mask_eq = s1_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _s1_mask_acc_T = s1_mask_eq; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc = s1_mask_sub_0_1 \| _s1_mask_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _s1_mask_acc_T_1 = s1_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc_1 = s1_mask_sub_0_1 \| _s1_mask_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire [1:0] _s1_mask_T = {s1_mask_acc_1, s1_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] _s1_mask_T_1 = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T & _s1_mask_T_1; // @[Misc.scala:222:10] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 \| _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T = \|s1_mask; // @[SourceD.scala:92:76, :94:27] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = \|s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 \| _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T \| s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [1:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:4]; // @[package.scala:243:46] wire [1:0] s1_beats1 = s1_single ? 2'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [1:0] _s1_beat_T = s1_req_offset[5:4]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T \| s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 2'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [2:0] _s1_counter_T = {1'h0, s1_counter} + 3'h1; // @[SourceD.scala:86:27, :130:30] wire [1:0] _s1_counter_T_1 = _s1_counter_T[1:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 \| io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [1:0] s2_beat; // @[SourceD.scala:149:26] reg [1:0] s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] reg [5:0] s2_req_source; // @[SourceD.scala:151:25] reg [8:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [10:0] s2_req_set; // @[SourceD.scala:151:25] reg [3:0] s2_req_sink; // @[SourceD.scala:151:25] reg [3:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T \| s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [127:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [15:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [127:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [15:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [127:0] s2_pdata_r_data; // @[package.scala:88:63] reg [15:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [127:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [15:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 16'hFFFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T \| pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 \| pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T \| _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [1:0] s3_beat; // @[SourceD.scala:192:26] wire [1:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg [1:0] s3_bypass; // @[SourceD.scala:193:28] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] reg [5:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [8:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [10:0] s3_req_set; // @[SourceD.scala:194:25] reg [3:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [3:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [8:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [10:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [3:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [3:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [127:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [15:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T \| _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [127:0] _s3_bypass_data_T_26; // @[package.scala:45:27] wire [127:0] s3_bypass_data; // @[SourceD.scala:206:28] wire _s3_rdata_T = s3_bypass[0]; // @[SourceD.scala:193:28, :208:78] wire _s3_rdata_T_1 = s3_bypass[1]; // @[SourceD.scala:193:28, :208:78] wire [63:0] _s3_rdata_T_2 = s3_bypass_data[63:0]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_3 = s3_bypass_data[127:64]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_4 = _queue_io_deq_bits_data[63:0]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_5 = _queue_io_deq_bits_data[127:64]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_6 = _s3_rdata_T ? _s3_rdata_T_2 : _s3_rdata_T_4; // @[SourceD.scala:207:78, :208:78, :210:75] wire [63:0] _s3_rdata_T_7 = _s3_rdata_T_1 ? _s3_rdata_T_3 : _s3_rdata_T_5; // @[SourceD.scala:207:78, :208:78, :210:75] wire [127:0] s3_rdata = {_s3_rdata_T_7, _s3_rdata_T_6}; // @[package.scala:45:27] assign d_bits_data = s3_rdata; // @[package.scala:45:27] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = \|s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T \| d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 \| d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T \| _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [1:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [1:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] reg [5:0] s4_req_source; // @[SourceD.scala:253:25] reg [8:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [10:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [3:0] s4_req_sink; // @[SourceD.scala:253:25] reg [3:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [8:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [10:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [3:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [3:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [127:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [15:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [127:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = s4_pdata_mask[8]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_9 = s4_pdata_mask[9]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_10 = s4_pdata_mask[10]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_11 = s4_pdata_mask[11]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_12 = s4_pdata_mask[12]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_13 = s4_pdata_mask[13]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_14 = s4_pdata_mask[14]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_15 = s4_pdata_mask[15]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_16 = _io_bs_wadr_bits_mask_T \| _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_17 = _io_bs_wadr_bits_mask_T_16 \| _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_18 = _io_bs_wadr_bits_mask_T_17 \| _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_19 = _io_bs_wadr_bits_mask_T_18 \| _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_20 = _io_bs_wadr_bits_mask_T_19 \| _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_21 = _io_bs_wadr_bits_mask_T_20 \| _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_22 = _io_bs_wadr_bits_mask_T_21 \| _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_23 = _io_bs_wadr_bits_mask_T_8 \| _io_bs_wadr_bits_mask_T_9; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_24 = _io_bs_wadr_bits_mask_T_23 \| _io_bs_wadr_bits_mask_T_10; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_25 = _io_bs_wadr_bits_mask_T_24 \| _io_bs_wadr_bits_mask_T_11; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_26 = _io_bs_wadr_bits_mask_T_25 \| _io_bs_wadr_bits_mask_T_12; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_27 = _io_bs_wadr_bits_mask_T_26 \| _io_bs_wadr_bits_mask_T_13; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_28 = _io_bs_wadr_bits_mask_T_27 \| _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_29 = _io_bs_wadr_bits_mask_T_28 \| _io_bs_wadr_bits_mask_T_15; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_30 = {_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22}; // @[SourceD.scala:275:{30,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:48:7, :275:30]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_226 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_226( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<12>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<12>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<12>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<12>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<12>, source : UInt<5>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<12>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<2>, clock reg probes_toN : UInt<2>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<4>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 3, 0) node _req_clientBit_T = shr(request.source, 4) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<1>(0h1)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<4>(0h8)) node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<4>(0h0)) node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 3, 0) node _req_clientBit_T_6 = shr(request.source, 4) node _req_clientBit_T_7 = eq(_req_clientBit_T_6, UInt<1>(0h0)) node _req_clientBit_T_8 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1) node _req_clientBit_T_9 = and(_req_clientBit_T_7, _req_clientBit_T_8) node _req_clientBit_T_10 = leq(req_clientBit_uncommonBits_1, UInt<4>(0h8)) node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10) node req_clientBit = cat(_req_clientBit_T_11, _req_clientBit_T_5) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,false,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,false,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,false,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,false,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(_T_110, UInt<1>(0h0)) node _T_112 = asUInt(reset) node _T_113 = eq(_T_112, UInt<1>(0h0)) when _T_113 : node _T_114 = eq(_T_111, UInt<1>(0h0)) when _T_114 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_111, UInt<1>(0h1), "") : assert_14 node _T_115 = eq(before, UInt<4>(0h8)) node _T_116 = eq(after, UInt<3>(0h5)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_118, UInt<1>(0h1), "") : assert_15 node _T_122 = eq(before, UInt<4>(0h8)) node _T_123 = eq(after, UInt<3>(0h4)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_125, UInt<1>(0h1), "") : assert_16 node _T_129 = eq(before, UInt<4>(0h8)) node _T_130 = eq(after, UInt<3>(0h6)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(_T_131, UInt<1>(0h0)) node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_T_132, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_132, UInt<1>(0h1), "") : assert_17 node _T_136 = eq(before, UInt<4>(0h8)) node _T_137 = eq(after, UInt<2>(0h3)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(before, UInt<4>(0h8)) node _T_140 = eq(after, UInt<2>(0h2)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(_T_141, UInt<1>(0h0)) node _T_143 = asUInt(reset) node _T_144 = eq(_T_143, UInt<1>(0h0)) when _T_144 : node _T_145 = eq(_T_142, UInt<1>(0h0)) when _T_145 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_142, UInt<1>(0h1), "") : assert_18 node _T_146 = eq(before, UInt<1>(0h1)) node _T_147 = eq(after, UInt<4>(0h8)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_149, UInt<1>(0h1), "") : assert_19 node _T_153 = eq(before, UInt<1>(0h1)) node _T_154 = eq(after, UInt<1>(0h0)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(_T_155, UInt<1>(0h0)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_156, UInt<1>(0h1), "") : assert_20 node _T_160 = eq(before, UInt<1>(0h1)) node _T_161 = eq(after, UInt<3>(0h7)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(_T_162, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_163, UInt<1>(0h1), "") : assert_21 node _T_167 = eq(before, UInt<1>(0h1)) node _T_168 = eq(after, UInt<3>(0h5)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_170, UInt<1>(0h1), "") : assert_22 node _T_174 = eq(before, UInt<1>(0h1)) node _T_175 = eq(after, UInt<3>(0h4)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = asUInt(reset) node _T_179 = eq(_T_178, UInt<1>(0h0)) when _T_179 : node _T_180 = eq(_T_177, UInt<1>(0h0)) when _T_180 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_177, UInt<1>(0h1), "") : assert_23 node _T_181 = eq(before, UInt<1>(0h1)) node _T_182 = eq(after, UInt<3>(0h6)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(_T_183, UInt<1>(0h0)) node _T_185 = asUInt(reset) node _T_186 = eq(_T_185, UInt<1>(0h0)) when _T_186 : node _T_187 = eq(_T_184, UInt<1>(0h0)) when _T_187 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_184, UInt<1>(0h1), "") : assert_24 node _T_188 = eq(before, UInt<1>(0h1)) node _T_189 = eq(after, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(_T_190, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(before, UInt<1>(0h1)) node _T_196 = eq(after, UInt<2>(0h2)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = asUInt(reset) node _T_200 = eq(_T_199, UInt<1>(0h0)) when _T_200 : node _T_201 = eq(_T_198, UInt<1>(0h0)) when _T_201 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_198, UInt<1>(0h1), "") : assert_26 node _T_202 = eq(before, UInt<1>(0h0)) node _T_203 = eq(after, UInt<4>(0h8)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(_T_204, UInt<1>(0h0)) node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(_T_205, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_205, UInt<1>(0h1), "") : assert_27 node _T_209 = eq(before, UInt<1>(0h0)) node _T_210 = eq(after, UInt<1>(0h1)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(_T_211, UInt<1>(0h0)) node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(_T_212, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_212, UInt<1>(0h1), "") : assert_28 node _T_216 = eq(before, UInt<1>(0h0)) node _T_217 = eq(after, UInt<3>(0h7)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(_T_218, UInt<1>(0h0)) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_219, UInt<1>(0h1), "") : assert_29 node _T_223 = eq(before, UInt<1>(0h0)) node _T_224 = eq(after, UInt<3>(0h5)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(_T_225, UInt<1>(0h0)) node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(_T_226, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_226, UInt<1>(0h1), "") : assert_30 node _T_230 = eq(before, UInt<1>(0h0)) node _T_231 = eq(after, UInt<3>(0h6)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_233, UInt<1>(0h1), "") : assert_31 node _T_237 = eq(before, UInt<1>(0h0)) node _T_238 = eq(after, UInt<3>(0h4)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(_T_239, UInt<1>(0h0)) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_240, UInt<1>(0h1), "") : assert_32 node _T_244 = eq(before, UInt<1>(0h0)) node _T_245 = eq(after, UInt<2>(0h3)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(_T_246, UInt<1>(0h0)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_247, UInt<1>(0h1), "") : assert_33 node _T_251 = eq(before, UInt<1>(0h0)) node _T_252 = eq(after, UInt<2>(0h2)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_254, UInt<1>(0h1), "") : assert_34 node _T_258 = eq(before, UInt<3>(0h7)) node _T_259 = eq(after, UInt<4>(0h8)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_T_261, UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_261, UInt<1>(0h1), "") : assert_35 node _T_265 = eq(before, UInt<3>(0h7)) node _T_266 = eq(after, UInt<1>(0h1)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_268, UInt<1>(0h1), "") : assert_36 node _T_272 = eq(before, UInt<3>(0h7)) node _T_273 = eq(after, UInt<1>(0h0)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_275, UInt<1>(0h1), "") : assert_37 node _T_279 = eq(before, UInt<3>(0h7)) node _T_280 = eq(after, UInt<3>(0h5)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_282, UInt<1>(0h1), "") : assert_38 node _T_286 = eq(before, UInt<3>(0h7)) node _T_287 = eq(after, UInt<3>(0h6)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = asUInt(reset) node _T_291 = eq(_T_290, UInt<1>(0h0)) when _T_291 : node _T_292 = eq(_T_289, UInt<1>(0h0)) when _T_292 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_289, UInt<1>(0h1), "") : assert_39 node _T_293 = eq(before, UInt<3>(0h7)) node _T_294 = eq(after, UInt<3>(0h4)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(_T_295, UInt<1>(0h0)) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_296, UInt<1>(0h1), "") : assert_40 node _T_300 = eq(before, UInt<3>(0h7)) node _T_301 = eq(after, UInt<2>(0h3)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(before, UInt<3>(0h7)) node _T_304 = eq(after, UInt<2>(0h2)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(_T_305, UInt<1>(0h0)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_306, UInt<1>(0h1), "") : assert_41 node _T_310 = eq(before, UInt<3>(0h5)) node _T_311 = eq(after, UInt<4>(0h8)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_313, UInt<1>(0h1), "") : assert_42 node _T_317 = eq(before, UInt<3>(0h5)) node _T_318 = eq(after, UInt<1>(0h1)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(_T_319, UInt<1>(0h0)) node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_T_320, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_320, UInt<1>(0h1), "") : assert_43 node _T_324 = eq(before, UInt<3>(0h5)) node _T_325 = eq(after, UInt<1>(0h0)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(_T_326, UInt<1>(0h0)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_327, UInt<1>(0h1), "") : assert_44 node _T_331 = eq(before, UInt<3>(0h5)) node _T_332 = eq(after, UInt<3>(0h7)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(before, UInt<3>(0h5)) node _T_335 = eq(after, UInt<3>(0h6)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_337, UInt<1>(0h1), "") : assert_45 node _T_341 = eq(before, UInt<3>(0h5)) node _T_342 = eq(after, UInt<3>(0h4)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(_T_343, UInt<1>(0h0)) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_344, UInt<1>(0h1), "") : assert_46 node _T_348 = eq(before, UInt<3>(0h5)) node _T_349 = eq(after, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _T_351 = eq(before, UInt<3>(0h5)) node _T_352 = eq(after, UInt<2>(0h2)) node _T_353 = and(_T_351, _T_352) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_354, UInt<1>(0h1), "") : assert_47 node _T_358 = eq(before, UInt<3>(0h6)) node _T_359 = eq(after, UInt<4>(0h8)) node _T_360 = and(_T_358, _T_359) node _T_361 = eq(_T_360, UInt<1>(0h0)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_361, UInt<1>(0h1), "") : assert_48 node _T_365 = eq(before, UInt<3>(0h6)) node _T_366 = eq(after, UInt<1>(0h1)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(_T_367, UInt<1>(0h0)) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_368, UInt<1>(0h1), "") : assert_49 node _T_372 = eq(before, UInt<3>(0h6)) node _T_373 = eq(after, UInt<1>(0h0)) node _T_374 = and(_T_372, _T_373) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_375, UInt<1>(0h1), "") : assert_50 node _T_379 = eq(before, UInt<3>(0h6)) node _T_380 = eq(after, UInt<3>(0h7)) node _T_381 = and(_T_379, _T_380) node _T_382 = eq(_T_381, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_382, UInt<1>(0h1), "") : assert_51 node _T_386 = eq(before, UInt<3>(0h6)) node _T_387 = eq(after, UInt<3>(0h5)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(_T_388, UInt<1>(0h0)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_389, UInt<1>(0h1), "") : assert_52 node _T_393 = eq(before, UInt<3>(0h6)) node _T_394 = eq(after, UInt<3>(0h4)) node _T_395 = and(_T_393, _T_394) node _T_396 = eq(_T_395, UInt<1>(0h0)) node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(_T_396, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_396, UInt<1>(0h1), "") : assert_53 node _T_400 = eq(before, UInt<3>(0h6)) node _T_401 = eq(after, UInt<2>(0h3)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(_T_402, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_403, UInt<1>(0h1), "") : assert_54 node _T_407 = eq(before, UInt<3>(0h6)) node _T_408 = eq(after, UInt<2>(0h2)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(before, UInt<3>(0h4)) node _T_411 = eq(after, UInt<4>(0h8)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(_T_412, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_413, UInt<1>(0h1), "") : assert_55 node _T_417 = eq(before, UInt<3>(0h4)) node _T_418 = eq(after, UInt<1>(0h1)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(_T_419, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_420, UInt<1>(0h1), "") : assert_56 node _T_424 = eq(before, UInt<3>(0h4)) node _T_425 = eq(after, UInt<1>(0h0)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_427, UInt<1>(0h1), "") : assert_57 node _T_431 = eq(before, UInt<3>(0h4)) node _T_432 = eq(after, UInt<3>(0h7)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(_T_433, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_434, UInt<1>(0h1), "") : assert_58 node _T_438 = eq(before, UInt<3>(0h4)) node _T_439 = eq(after, UInt<3>(0h5)) node _T_440 = and(_T_438, _T_439) node _T_441 = eq(_T_440, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_441, UInt<1>(0h1), "") : assert_59 node _T_445 = eq(before, UInt<3>(0h4)) node _T_446 = eq(after, UInt<3>(0h6)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(before, UInt<3>(0h4)) node _T_449 = eq(after, UInt<2>(0h3)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(_T_450, UInt<1>(0h0)) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_451, UInt<1>(0h1), "") : assert_60 node _T_455 = eq(before, UInt<3>(0h4)) node _T_456 = eq(after, UInt<2>(0h2)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(before, UInt<2>(0h3)) node _T_459 = eq(after, UInt<4>(0h8)) node _T_460 = and(_T_458, _T_459) node _T_461 = eq(_T_460, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_461, UInt<1>(0h1), "") : assert_61 node _T_465 = eq(before, UInt<2>(0h3)) node _T_466 = eq(after, UInt<1>(0h1)) node _T_467 = and(_T_465, _T_466) node _T_468 = eq(_T_467, UInt<1>(0h0)) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_468, UInt<1>(0h1), "") : assert_62 node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<1>(0h0)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_475, UInt<1>(0h1), "") : assert_63 node _T_479 = eq(before, UInt<2>(0h3)) node _T_480 = eq(after, UInt<3>(0h7)) node _T_481 = and(_T_479, _T_480) node _T_482 = eq(before, UInt<2>(0h3)) node _T_483 = eq(after, UInt<3>(0h5)) node _T_484 = and(_T_482, _T_483) node _T_485 = eq(before, UInt<2>(0h3)) node _T_486 = eq(after, UInt<3>(0h6)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(before, UInt<2>(0h3)) node _T_489 = eq(after, UInt<3>(0h4)) node _T_490 = and(_T_488, _T_489) node _T_491 = eq(before, UInt<2>(0h3)) node _T_492 = eq(after, UInt<2>(0h2)) node _T_493 = and(_T_491, _T_492) node _T_494 = eq(before, UInt<2>(0h2)) node _T_495 = eq(after, UInt<4>(0h8)) node _T_496 = and(_T_494, _T_495) node _T_497 = eq(_T_496, UInt<1>(0h0)) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_497, UInt<1>(0h1), "") : assert_64 node _T_501 = eq(before, UInt<2>(0h2)) node _T_502 = eq(after, UInt<1>(0h1)) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(_T_503, UInt<1>(0h0)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_504, UInt<1>(0h1), "") : assert_65 node _T_508 = eq(before, UInt<2>(0h2)) node _T_509 = eq(after, UInt<1>(0h0)) node _T_510 = and(_T_508, _T_509) node _T_511 = eq(_T_510, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_511, UInt<1>(0h1), "") : assert_66 node _T_515 = eq(before, UInt<2>(0h2)) node _T_516 = eq(after, UInt<3>(0h7)) node _T_517 = and(_T_515, _T_516) node _T_518 = eq(_T_517, UInt<1>(0h0)) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_518, UInt<1>(0h1), "") : assert_67 node _T_522 = eq(before, UInt<2>(0h2)) node _T_523 = eq(after, UInt<3>(0h5)) node _T_524 = and(_T_522, _T_523) node _T_525 = eq(_T_524, UInt<1>(0h0)) node _T_526 = asUInt(reset) node _T_527 = eq(_T_526, UInt<1>(0h0)) when _T_527 : node _T_528 = eq(_T_525, UInt<1>(0h0)) when _T_528 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_68 assert(clock, _T_525, UInt<1>(0h1), "") : assert_68 node _T_529 = eq(before, UInt<2>(0h2)) node _T_530 = eq(after, UInt<3>(0h6)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(before, UInt<2>(0h2)) node _T_533 = eq(after, UInt<3>(0h4)) node _T_534 = and(_T_532, _T_533) node _T_535 = eq(before, UInt<2>(0h2)) node _T_536 = eq(after, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(_T_537, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_69 assert(clock, _T_538, UInt<1>(0h1), "") : assert_69 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<4>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 3, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 4) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<1>(0h1)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<4>(0h8)) node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4) node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<4>(0h0)) node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 3, 0) node _probe_bit_T_6 = shr(io.sinkc.bits.source, 4) node _probe_bit_T_7 = eq(_probe_bit_T_6, UInt<1>(0h0)) node _probe_bit_T_8 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1) node _probe_bit_T_9 = and(_probe_bit_T_7, _probe_bit_T_8) node _probe_bit_T_10 = leq(probe_bit_uncommonBits_1, UInt<4>(0h8)) node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10) node probe_bit = cat(_probe_bit_T_11, _probe_bit_T_5) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_542 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_543 = and(probe_toN, _T_542) node _T_544 = eq(probe_toN, UInt<1>(0h0)) node _T_545 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_546 = and(_T_544, _T_545) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_547 = eq(set_pprobeack, UInt<1>(0h0)) node _T_548 = and(_T_547, w_rprobeackfirst) node _T_549 = and(set_pprobeack, w_rprobeackfirst) node _T_550 = neq(meta.state, UInt<2>(0h0)) node _T_551 = eq(io.sinkc.bits.tag, meta.tag) node _T_552 = and(_T_550, _T_551) node _T_553 = and(_T_552, io.sinkc.bits.data) when _T_553 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_554 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_555 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_556 = or(_T_554, _T_555) when _T_556 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_557 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_558 = eq(request.offset, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) node _T_560 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_561 = neq(request.offset, UInt<1>(0h0)) node _T_562 = and(_T_560, _T_561) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_563 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_563 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<4>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 3, 0) node _new_clientBit_T = shr(new_request.source, 4) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<1>(0h1)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<4>(0h8)) node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<4>(0h0)) node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 3, 0) node _new_clientBit_T_6 = shr(new_request.source, 4) node _new_clientBit_T_7 = eq(_new_clientBit_T_6, UInt<1>(0h0)) node _new_clientBit_T_8 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1) node _new_clientBit_T_9 = and(_new_clientBit_T_7, _new_clientBit_T_8) node _new_clientBit_T_10 = leq(new_clientBit_uncommonBits_1, UInt<4>(0h8)) node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10) node new_clientBit = cat(_new_clientBit_T_11, _new_clientBit_T_5) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_564 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_564 : node _T_565 = eq(prior, UInt<4>(0h8)) node _T_566 = eq(prior, UInt<1>(0h1)) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_70 assert(clock, _T_567, UInt<1>(0h1), "") : assert_70 node _T_571 = eq(prior, UInt<1>(0h0)) node _T_572 = eq(_T_571, UInt<1>(0h0)) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_71 assert(clock, _T_572, UInt<1>(0h1), "") : assert_71 node _T_576 = eq(prior, UInt<3>(0h7)) node _T_577 = eq(prior, UInt<3>(0h5)) node _T_578 = eq(prior, UInt<3>(0h4)) node _T_579 = eq(prior, UInt<3>(0h6)) node _T_580 = eq(prior, UInt<2>(0h3)) node _T_581 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_582 = eq(request_valid, UInt<1>(0h0)) node _T_583 = and(io.schedule.ready, io.schedule.valid) node _T_584 = and(no_wait, _T_583) node _T_585 = or(_T_582, _T_584) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_72 assert(clock, _T_585, UInt<1>(0h1), "") : assert_72 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_589 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_590 = or(io.directory.valid, _T_589) when _T_590 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_591 = and(new_request.prio[2], UInt<1>(0h1)) when _T_591 : connect s_execute, UInt<1>(0h0) node _T_592 = bits(new_request.opcode, 0, 0) node _T_593 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_594 = and(_T_592, _T_593) when _T_594 : connect s_writeback, UInt<1>(0h0) node _T_595 = eq(new_request.param, UInt<3>(0h0)) node _T_596 = eq(new_request.param, UInt<3>(0h4)) node _T_597 = or(_T_595, _T_596) node _T_598 = eq(new_meta.state, UInt<2>(0h2)) node _T_599 = and(_T_597, _T_598) when _T_599 : connect s_writeback, UInt<1>(0h0) node _T_600 = eq(new_request.param, UInt<3>(0h1)) node _T_601 = eq(new_request.param, UInt<3>(0h2)) node _T_602 = or(_T_600, _T_601) node _T_603 = eq(new_request.param, UInt<3>(0h5)) node _T_604 = or(_T_602, _T_603) node _T_605 = and(new_meta.clients, new_clientBit) node _T_606 = neq(_T_605, UInt<1>(0h0)) node _T_607 = and(_T_604, _T_606) when _T_607 : connect s_writeback, UInt<1>(0h0) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(new_meta.hit, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_73 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_73 else : node _T_611 = and(new_request.control, UInt<1>(0h1)) when _T_611 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_612 = neq(new_meta.clients, UInt<1>(0h0)) node _T_613 = and(UInt<1>(0h1), _T_612) when _T_613 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_614 = eq(new_meta.hit, UInt<1>(0h0)) node _T_615 = neq(new_meta.state, UInt<2>(0h0)) node _T_616 = and(_T_614, _T_615) when _T_616 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_617 = neq(new_meta.clients, UInt<1>(0h0)) node _T_618 = and(UInt<1>(0h1), _T_617) when _T_618 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_619 = eq(new_meta.hit, UInt<1>(0h0)) node _T_620 = eq(new_meta.state, UInt<2>(0h1)) node _T_621 = and(_T_620, new_needT) node _T_622 = or(_T_619, _T_621) when _T_622 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_623 = eq(new_meta.state, UInt<2>(0h2)) node _T_624 = or(new_needT, _T_623) node _T_625 = and(new_meta.hit, _T_624) node _T_626 = not(new_skipProbe) node _T_627 = and(new_meta.clients, _T_626) node _T_628 = neq(_T_627, UInt<1>(0h0)) node _T_629 = and(_T_625, _T_628) node _T_630 = and(UInt<1>(0h1), _T_629) when _T_630 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_631 = eq(new_request.opcode, UInt<3>(0h6)) node _T_632 = eq(new_request.opcode, UInt<3>(0h7)) node _T_633 = or(_T_631, _T_632) when _T_633 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_634 = bits(new_request.opcode, 2, 2) node _T_635 = eq(_T_634, UInt<1>(0h0)) node _T_636 = and(_T_635, new_meta.hit) node _T_637 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_638 = and(_T_636, _T_637) when _T_638 : connect s_writeback, UInt<1>(0h0)	module MSHR_5( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [4:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [11:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [11:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [11:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [4:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [11:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [4:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [11:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [11:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [4:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [11:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [11:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [11:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [4:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [11:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [1:0] _io_schedule_bits_b_bits_clients_T = 2'h3; // @[MSHR.scala:289:53] wire [1:0] _last_probe_T_1 = 2'h3; // @[MSHR.scala:459:66] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] excluded_client = 2'h0; // @[MSHR.scala:279:28] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire [11:0] invalid_tag = 12'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [4:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [11:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [11:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [11:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [4:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [4:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [11:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [4:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [4:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [4:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [4:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [11:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire [1:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [11:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [11:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [3:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T = request_source[4]; // @[Parameters.scala:54:10] wire _req_clientBit_T_6 = request_source[4]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_7 = ~_req_clientBit_T_6; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 12'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [3:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10] wire _probe_bit_T_6 = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_7 = ~_probe_bit_T_6; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_10 = probe_bit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48] wire [1:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [11:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [4:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [11:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [4:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [4:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_631 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_631; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_631; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [3:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T = new_request_source[4]; // @[Parameters.scala:54:10] wire _new_clientBit_T_6 = new_request_source[4]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_7 = ~_new_clientBit_T_6; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_590 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_86 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<10>(0h200))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = and(_T_19, _T_24) node _T_26 = or(UInt<1>(0h0), _T_25) node _T_27 = and(_T_18, _T_26) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_33 = and(_T_31, _T_32) node _T_34 = or(UInt<1>(0h0), _T_33) node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<10>(0h200))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = and(_T_34, _T_39) node _T_41 = or(UInt<1>(0h0), _T_40) node _T_42 = and(UInt<1>(0h0), _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_42, UInt<1>(0h1), "") : assert_3 node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_49, UInt<1>(0h1), "") : assert_5 node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(is_aligned, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_56, UInt<1>(0h1), "") : assert_7 node _T_60 = not(io.in.a.bits.mask) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_61, UInt<1>(0h1), "") : assert_8 node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_69 : node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_71 = and(UInt<1>(0h0), _T_70) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<10>(0h200))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = and(_T_73, _T_78) node _T_80 = or(UInt<1>(0h0), _T_79) node _T_81 = and(_T_72, _T_80) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_81, UInt<1>(0h1), "") : assert_10 node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_87 = and(_T_85, _T_86) node _T_88 = or(UInt<1>(0h0), _T_87) node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<10>(0h200))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = and(_T_88, _T_93) node _T_95 = or(UInt<1>(0h0), _T_94) node _T_96 = and(UInt<1>(0h0), _T_95) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_96, UInt<1>(0h1), "") : assert_11 node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_103, UInt<1>(0h1), "") : assert_13 node _T_107 = asUInt(reset) node _T_108 = eq(_T_107, UInt<1>(0h0)) when _T_108 : node _T_109 = eq(is_aligned, UInt<1>(0h0)) when _T_109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_110, UInt<1>(0h1), "") : assert_15 node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_114, UInt<1>(0h1), "") : assert_16 node _T_118 = not(io.in.a.bits.mask) node _T_119 = eq(_T_118, UInt<1>(0h0)) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_119, UInt<1>(0h1), "") : assert_17 node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_T_123, UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_123, UInt<1>(0h1), "") : assert_18 node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_127 : node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_130 = and(_T_128, _T_129) node _T_131 = or(UInt<1>(0h0), _T_130) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_131, UInt<1>(0h1), "") : assert_19 node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_137 = and(_T_135, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<10>(0h200))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = and(_T_138, _T_143) node _T_145 = or(UInt<1>(0h0), _T_144) node _T_146 = asUInt(reset) node _T_147 = eq(_T_146, UInt<1>(0h0)) when _T_147 : node _T_148 = eq(_T_145, UInt<1>(0h0)) when _T_148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_145, UInt<1>(0h1), "") : assert_20 node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(is_aligned, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_155, UInt<1>(0h1), "") : assert_23 node _T_159 = eq(io.in.a.bits.mask, mask) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_159, UInt<1>(0h1), "") : assert_24 node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_163, UInt<1>(0h1), "") : assert_25 node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = or(UInt<1>(0h0), _T_170) node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_174 = and(_T_172, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<10>(0h200))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = and(_T_175, _T_180) node _T_182 = or(UInt<1>(0h0), _T_181) node _T_183 = and(_T_171, _T_182) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_183, UInt<1>(0h1), "") : assert_26 node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(is_aligned, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_193, UInt<1>(0h1), "") : assert_29 node _T_197 = eq(io.in.a.bits.mask, mask) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_197, UInt<1>(0h1), "") : assert_30 node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_201 : node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_203 = and(UInt<1>(0h0), _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_207 = and(_T_205, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<10>(0h200))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = and(_T_208, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(_T_204, _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_216, UInt<1>(0h1), "") : assert_31 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(is_aligned, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(_T_226, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_226, UInt<1>(0h1), "") : assert_34 node _T_230 = not(mask) node _T_231 = and(io.in.a.bits.mask, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_232, UInt<1>(0h1), "") : assert_35 node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_236 : node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_238 = and(UInt<1>(0h0), _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<10>(0h200))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = and(_T_240, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = and(_T_239, _T_247) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_248, UInt<1>(0h1), "") : assert_36 node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(is_aligned, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_258, UInt<1>(0h1), "") : assert_39 node _T_262 = eq(io.in.a.bits.mask, mask) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_262, UInt<1>(0h1), "") : assert_40 node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_266 : node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_268 = and(UInt<1>(0h0), _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<10>(0h200))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = and(_T_270, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = and(_T_269, _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_278, UInt<1>(0h1), "") : assert_41 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(is_aligned, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_288, UInt<1>(0h1), "") : assert_44 node _T_292 = eq(io.in.a.bits.mask, mask) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_292, UInt<1>(0h1), "") : assert_45 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_296 : node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_298 = and(UInt<1>(0h0), _T_297) node _T_299 = or(UInt<1>(0h0), _T_298) node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<10>(0h200))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = and(_T_300, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = and(_T_299, _T_307) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_308, UInt<1>(0h1), "") : assert_46 node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(is_aligned, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_318, UInt<1>(0h1), "") : assert_49 node _T_322 = eq(io.in.a.bits.mask, mask) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_322, UInt<1>(0h1), "") : assert_50 node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_327 = asUInt(reset) node _T_328 = eq(_T_327, UInt<1>(0h0)) when _T_328 : node _T_329 = eq(_T_326, UInt<1>(0h0)) when _T_329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_326, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_331 = asUInt(reset) node _T_332 = eq(_T_331, UInt<1>(0h0)) when _T_332 : node _T_333 = eq(_T_330, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_330, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_334 : node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_338, UInt<1>(0h1), "") : assert_54 node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_342, UInt<1>(0h1), "") : assert_55 node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_346, UInt<1>(0h1), "") : assert_56 node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(_T_350, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_350, UInt<1>(0h1), "") : assert_57 node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_354 : node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(sink_ok, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_361, UInt<1>(0h1), "") : assert_60 node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_365, UInt<1>(0h1), "") : assert_61 node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_369, UInt<1>(0h1), "") : assert_62 node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_373, UInt<1>(0h1), "") : assert_63 node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_378 = or(UInt<1>(0h1), _T_377) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_378, UInt<1>(0h1), "") : assert_64 node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_382 : node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(sink_ok, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_389, UInt<1>(0h1), "") : assert_67 node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_393, UInt<1>(0h1), "") : assert_68 node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_397, UInt<1>(0h1), "") : assert_69 node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_402 = or(_T_401, io.in.d.bits.corrupt) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_402, UInt<1>(0h1), "") : assert_70 node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_407 = or(UInt<1>(0h1), _T_406) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_407, UInt<1>(0h1), "") : assert_71 node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_411 : node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_415, UInt<1>(0h1), "") : assert_73 node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_419, UInt<1>(0h1), "") : assert_74 node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_424 = or(UInt<1>(0h1), _T_423) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_424, UInt<1>(0h1), "") : assert_75 node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_428 : node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_432, UInt<1>(0h1), "") : assert_77 node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_437 = or(_T_436, io.in.d.bits.corrupt) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_437, UInt<1>(0h1), "") : assert_78 node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_442 = or(UInt<1>(0h1), _T_441) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_442, UInt<1>(0h1), "") : assert_79 node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_450, UInt<1>(0h1), "") : assert_81 node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_454, UInt<1>(0h1), "") : assert_82 node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_459 = or(UInt<1>(0h1), _T_458) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_459, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_463, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_467, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_471, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_475 = eq(a_first, UInt<1>(0h0)) node _T_476 = and(io.in.a.valid, _T_475) when _T_476 : node _T_477 = eq(io.in.a.bits.opcode, opcode) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_477, UInt<1>(0h1), "") : assert_87 node _T_481 = eq(io.in.a.bits.param, param) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_481, UInt<1>(0h1), "") : assert_88 node _T_485 = eq(io.in.a.bits.size, size) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_485, UInt<1>(0h1), "") : assert_89 node _T_489 = eq(io.in.a.bits.source, source) node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_T_489, UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_489, UInt<1>(0h1), "") : assert_90 node _T_493 = eq(io.in.a.bits.address, address) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_493, UInt<1>(0h1), "") : assert_91 node _T_497 = and(io.in.a.ready, io.in.a.valid) node _T_498 = and(_T_497, a_first) when _T_498 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_499 = eq(d_first, UInt<1>(0h0)) node _T_500 = and(io.in.d.valid, _T_499) when _T_500 : node _T_501 = eq(io.in.d.bits.opcode, opcode_1) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_501, UInt<1>(0h1), "") : assert_92 node _T_505 = eq(io.in.d.bits.param, param_1) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_505, UInt<1>(0h1), "") : assert_93 node _T_509 = eq(io.in.d.bits.size, size_1) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_509, UInt<1>(0h1), "") : assert_94 node _T_513 = eq(io.in.d.bits.source, source_1) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_513, UInt<1>(0h1), "") : assert_95 node _T_517 = eq(io.in.d.bits.sink, sink) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_517, UInt<1>(0h1), "") : assert_96 node _T_521 = eq(io.in.d.bits.denied, denied) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_521, UInt<1>(0h1), "") : assert_97 node _T_525 = and(io.in.d.ready, io.in.d.valid) node _T_526 = and(_T_525, d_first) when _T_526 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_527 = and(io.in.a.valid, a_first_1) node _T_528 = and(_T_527, UInt<1>(0h1)) when _T_528 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_529 = and(io.in.a.ready, io.in.a.valid) node _T_530 = and(_T_529, a_first_1) node _T_531 = and(_T_530, UInt<1>(0h1)) when _T_531 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_532 = dshr(inflight, io.in.a.bits.source) node _T_533 = bits(_T_532, 0, 0) node _T_534 = eq(_T_533, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_534, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_538 = and(io.in.d.valid, d_first_1) node _T_539 = and(_T_538, UInt<1>(0h1)) node _T_540 = eq(d_release_ack, UInt<1>(0h0)) node _T_541 = and(_T_539, _T_540) when _T_541 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_542 = and(io.in.d.ready, io.in.d.valid) node _T_543 = and(_T_542, d_first_1) node _T_544 = and(_T_543, UInt<1>(0h1)) node _T_545 = eq(d_release_ack, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) when _T_546 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_551 = dshr(inflight, io.in.d.bits.source) node _T_552 = bits(_T_551, 0, 0) node _T_553 = or(_T_552, same_cycle_resp) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_553, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_559 = or(_T_557, _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_559, UInt<1>(0h1), "") : assert_100 node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_563, UInt<1>(0h1), "") : assert_101 else : node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_569 = or(_T_567, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_569, UInt<1>(0h1), "") : assert_102 node _T_573 = eq(io.in.d.bits.size, a_size_lookup) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_573, UInt<1>(0h1), "") : assert_103 node _T_577 = and(io.in.d.valid, d_first_1) node _T_578 = and(_T_577, a_first_1) node _T_579 = and(_T_578, io.in.a.valid) node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_581 = and(_T_579, _T_580) node _T_582 = eq(d_release_ack, UInt<1>(0h0)) node _T_583 = and(_T_581, _T_582) when _T_583 : node _T_584 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_585 = or(_T_584, io.in.a.ready) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_585, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_206 node _T_589 = orr(inflight) node _T_590 = eq(_T_589, UInt<1>(0h0)) node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_592 = or(_T_590, _T_591) node _T_593 = lt(watchdog, plusarg_reader.out) node _T_594 = or(_T_592, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_594, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_598 = and(io.in.a.ready, io.in.a.valid) node _T_599 = and(io.in.d.ready, io.in.d.valid) node _T_600 = or(_T_598, _T_599) when _T_600 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_601 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_604 = and(_T_602, _T_603) node _T_605 = and(_T_601, _T_604) when _T_605 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_607 = and(_T_606, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_610 = and(_T_608, _T_609) node _T_611 = and(_T_607, _T_610) when _T_611 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_612 = dshr(inflight_1, _WIRE_15.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = eq(_T_613, UInt<1>(0h0)) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_614, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_618 = and(io.in.d.valid, d_first_2) node _T_619 = and(_T_618, UInt<1>(0h1)) node _T_620 = and(_T_619, d_release_ack_1) when _T_620 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_621 = and(io.in.d.ready, io.in.d.valid) node _T_622 = and(_T_621, d_first_2) node _T_623 = and(_T_622, UInt<1>(0h1)) node _T_624 = and(_T_623, d_release_ack_1) when _T_624 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_625 = and(io.in.d.valid, d_first_2) node _T_626 = and(_T_625, UInt<1>(0h1)) node _T_627 = and(_T_626, d_release_ack_1) when _T_627 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_628 = dshr(inflight_1, io.in.d.bits.source) node _T_629 = bits(_T_628, 0, 0) node _T_630 = or(_T_629, same_cycle_resp_1) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_630, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_634, UInt<1>(0h1), "") : assert_108 else : node _T_638 = eq(io.in.d.bits.size, c_size_lookup) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_638, UInt<1>(0h1), "") : assert_109 node _T_642 = and(io.in.d.valid, d_first_2) node _T_643 = and(_T_642, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_644 = and(_T_643, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_646 = and(_T_644, _T_645) node _T_647 = and(_T_646, d_release_ack_1) node _T_648 = eq(c_probe_ack, UInt<1>(0h0)) node _T_649 = and(_T_647, _T_648) when _T_649 : node _T_650 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_651 = or(_T_650, _WIRE_23.ready) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_651, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_207 node _T_655 = orr(inflight_1) node _T_656 = eq(_T_655, UInt<1>(0h0)) node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_658 = or(_T_656, _T_657) node _T_659 = lt(watchdog_1, plusarg_reader_1.out) node _T_660 = or(_T_658, _T_659) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_660, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_665 = and(io.in.d.ready, io.in.d.valid) node _T_666 = or(_T_664, _T_665) when _T_666 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_86( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_21 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<3>(0h6)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_39 = shr(io.in.a.bits.source, 3) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<3>(0h4)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<3>(0h4)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[18] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_36 connect _source_ok_WIRE[12], _source_ok_T_37 connect _source_ok_WIRE[13], _source_ok_T_38 connect _source_ok_WIRE[14], _source_ok_T_44 connect _source_ok_WIRE[15], _source_ok_T_45 connect _source_ok_WIRE[16], _source_ok_T_46 connect _source_ok_WIRE[17], _source_ok_T_47 node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[7]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[8]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[9]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[10]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[11]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[12]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[13]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[14]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[15]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[16]) node source_ok = or(_source_ok_T_63, _source_ok_WIRE[17]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_112 = shr(io.in.a.bits.source, 3) node _T_113 = eq(_T_112, UInt<3>(0h6)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_120 = cvt(_T_119) node _T_121 = and(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = asSInt(_T_121) node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = or(_T_118, _T_123) node _T_125 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_126 = eq(_T_125, UInt<1>(0h0)) node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = or(_T_126, _T_131) node _T_133 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<1>(0h0))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = or(_T_134, _T_139) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_141 = shr(io.in.a.bits.source, 3) node _T_142 = eq(_T_141, UInt<3>(0h4)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_5) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(_T_146, UInt<1>(0h0)) node _T_148 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_149 = cvt(_T_148) node _T_150 = and(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = asSInt(_T_150) node _T_152 = eq(_T_151, asSInt(UInt<1>(0h0))) node _T_153 = or(_T_147, _T_152) node _T_154 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = or(_T_155, _T_160) node _T_162 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_163 = eq(_T_162, UInt<1>(0h0)) node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = or(_T_163, _T_168) node _T_170 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_171 = eq(_T_170, UInt<1>(0h0)) node _T_172 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = or(_T_171, _T_176) node _T_178 = and(_T_11, _T_24) node _T_179 = and(_T_178, _T_37) node _T_180 = and(_T_179, _T_50) node _T_181 = and(_T_180, _T_63) node _T_182 = and(_T_181, _T_71) node _T_183 = and(_T_182, _T_79) node _T_184 = and(_T_183, _T_87) node _T_185 = and(_T_184, _T_95) node _T_186 = and(_T_185, _T_103) node _T_187 = and(_T_186, _T_111) node _T_188 = and(_T_187, _T_124) node _T_189 = and(_T_188, _T_132) node _T_190 = and(_T_189, _T_140) node _T_191 = and(_T_190, _T_153) node _T_192 = and(_T_191, _T_161) node _T_193 = and(_T_192, _T_169) node _T_194 = and(_T_193, _T_177) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_194, UInt<1>(0h1), "") : assert_1 node _T_198 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_198 : node _T_199 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_200 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_201 = and(_T_199, _T_200) node _T_202 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_203 = shr(io.in.a.bits.source, 2) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = leq(UInt<1>(0h0), uncommonBits_6) node _T_206 = and(_T_204, _T_205) node _T_207 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_208 = and(_T_206, _T_207) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_209 = shr(io.in.a.bits.source, 2) node _T_210 = eq(_T_209, UInt<1>(0h1)) node _T_211 = leq(UInt<1>(0h0), uncommonBits_7) node _T_212 = and(_T_210, _T_211) node _T_213 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_214 = and(_T_212, _T_213) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_215 = shr(io.in.a.bits.source, 2) node _T_216 = eq(_T_215, UInt<2>(0h2)) node _T_217 = leq(UInt<1>(0h0), uncommonBits_8) node _T_218 = and(_T_216, _T_217) node _T_219 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_220 = and(_T_218, _T_219) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_221 = shr(io.in.a.bits.source, 2) node _T_222 = eq(_T_221, UInt<2>(0h3)) node _T_223 = leq(UInt<1>(0h0), uncommonBits_9) node _T_224 = and(_T_222, _T_223) node _T_225 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_226 = and(_T_224, _T_225) node _T_227 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_228 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_229 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_230 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_231 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_233 = shr(io.in.a.bits.source, 3) node _T_234 = eq(_T_233, UInt<3>(0h6)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_10) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_241 = shr(io.in.a.bits.source, 3) node _T_242 = eq(_T_241, UInt<3>(0h4)) node _T_243 = leq(UInt<1>(0h0), uncommonBits_11) node _T_244 = and(_T_242, _T_243) node _T_245 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_250 = or(_T_202, _T_208) node _T_251 = or(_T_250, _T_214) node _T_252 = or(_T_251, _T_220) node _T_253 = or(_T_252, _T_226) node _T_254 = or(_T_253, _T_227) node _T_255 = or(_T_254, _T_228) node _T_256 = or(_T_255, _T_229) node _T_257 = or(_T_256, _T_230) node _T_258 = or(_T_257, _T_231) node _T_259 = or(_T_258, _T_232) node _T_260 = or(_T_259, _T_238) node _T_261 = or(_T_260, _T_239) node _T_262 = or(_T_261, _T_240) node _T_263 = or(_T_262, _T_246) node _T_264 = or(_T_263, _T_247) node _T_265 = or(_T_264, _T_248) node _T_266 = or(_T_265, _T_249) node _T_267 = and(_T_201, _T_266) node _T_268 = or(UInt<1>(0h0), _T_267) node _T_269 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_270 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_271 = cvt(_T_270) node _T_272 = and(_T_271, asSInt(UInt<14>(0h2000))) node _T_273 = asSInt(_T_272) node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0))) node _T_275 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_276 = cvt(_T_275) node _T_277 = and(_T_276, asSInt(UInt<13>(0h1000))) node _T_278 = asSInt(_T_277) node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0))) node _T_280 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_281 = cvt(_T_280) node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000))) node _T_283 = asSInt(_T_282) node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_286 = cvt(_T_285) node _T_287 = and(_T_286, asSInt(UInt<18>(0h2f000))) node _T_288 = asSInt(_T_287) node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) node _T_290 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<17>(0h10000))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_296 = cvt(_T_295) node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000))) node _T_298 = asSInt(_T_297) node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0))) node _T_300 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<27>(0h4000000))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_306 = cvt(_T_305) node _T_307 = and(_T_306, asSInt(UInt<13>(0h1000))) node _T_308 = asSInt(_T_307) node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0))) node _T_310 = or(_T_274, _T_279) node _T_311 = or(_T_310, _T_284) node _T_312 = or(_T_311, _T_289) node _T_313 = or(_T_312, _T_294) node _T_314 = or(_T_313, _T_299) node _T_315 = or(_T_314, _T_304) node _T_316 = or(_T_315, _T_309) node _T_317 = and(_T_269, _T_316) node _T_318 = or(UInt<1>(0h0), _T_317) node _T_319 = and(_T_268, _T_318) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_319, UInt<1>(0h1), "") : assert_2 node _T_323 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_324 = shr(io.in.a.bits.source, 2) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = leq(UInt<1>(0h0), uncommonBits_12) node _T_327 = and(_T_325, _T_326) node _T_328 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_329 = and(_T_327, _T_328) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_330 = shr(io.in.a.bits.source, 2) node _T_331 = eq(_T_330, UInt<1>(0h1)) node _T_332 = leq(UInt<1>(0h0), uncommonBits_13) node _T_333 = and(_T_331, _T_332) node _T_334 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_335 = and(_T_333, _T_334) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_336 = shr(io.in.a.bits.source, 2) node _T_337 = eq(_T_336, UInt<2>(0h2)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_14) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_342 = shr(io.in.a.bits.source, 2) node _T_343 = eq(_T_342, UInt<2>(0h3)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_15) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_350 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_351 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_352 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_353 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_354 = shr(io.in.a.bits.source, 3) node _T_355 = eq(_T_354, UInt<3>(0h6)) node _T_356 = leq(UInt<1>(0h0), uncommonBits_16) node _T_357 = and(_T_355, _T_356) node _T_358 = leq(uncommonBits_16, UInt<3>(0h4)) node _T_359 = and(_T_357, _T_358) node _T_360 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_361 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_362 = shr(io.in.a.bits.source, 3) node _T_363 = eq(_T_362, UInt<3>(0h4)) node _T_364 = leq(UInt<1>(0h0), uncommonBits_17) node _T_365 = and(_T_363, _T_364) node _T_366 = leq(uncommonBits_17, UInt<3>(0h4)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_369 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_370 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[18] connect _WIRE[0], _T_323 connect _WIRE[1], _T_329 connect _WIRE[2], _T_335 connect _WIRE[3], _T_341 connect _WIRE[4], _T_347 connect _WIRE[5], _T_348 connect _WIRE[6], _T_349 connect _WIRE[7], _T_350 connect _WIRE[8], _T_351 connect _WIRE[9], _T_352 connect _WIRE[10], _T_353 connect _WIRE[11], _T_359 connect _WIRE[12], _T_360 connect _WIRE[13], _T_361 connect _WIRE[14], _T_367 connect _WIRE[15], _T_368 connect _WIRE[16], _T_369 connect _WIRE[17], _T_370 node _T_371 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_372 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_373 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_374 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_375 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_376 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_377 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_380 = mux(_WIRE[5], _T_371, UInt<1>(0h0)) node _T_381 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_383 = mux(_WIRE[8], _T_372, UInt<1>(0h0)) node _T_384 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_385 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = mux(_WIRE[11], _T_373, UInt<1>(0h0)) node _T_387 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_388 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_389 = mux(_WIRE[14], _T_374, UInt<1>(0h0)) node _T_390 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_391 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_392 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_393 = or(_T_375, _T_376) node _T_394 = or(_T_393, _T_377) node _T_395 = or(_T_394, _T_378) node _T_396 = or(_T_395, _T_379) node _T_397 = or(_T_396, _T_380) node _T_398 = or(_T_397, _T_381) node _T_399 = or(_T_398, _T_382) node _T_400 = or(_T_399, _T_383) node _T_401 = or(_T_400, _T_384) node _T_402 = or(_T_401, _T_385) node _T_403 = or(_T_402, _T_386) node _T_404 = or(_T_403, _T_387) node _T_405 = or(_T_404, _T_388) node _T_406 = or(_T_405, _T_389) node _T_407 = or(_T_406, _T_390) node _T_408 = or(_T_407, _T_391) node _T_409 = or(_T_408, _T_392) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_409 node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_412 = and(_T_410, _T_411) node _T_413 = or(UInt<1>(0h0), _T_412) node _T_414 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<14>(0h2000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<18>(0h2f000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<17>(0h10000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<13>(0h1000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<27>(0h4000000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_450 = cvt(_T_449) node _T_451 = and(_T_450, asSInt(UInt<13>(0h1000))) node _T_452 = asSInt(_T_451) node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) node _T_454 = or(_T_418, _T_423) node _T_455 = or(_T_454, _T_428) node _T_456 = or(_T_455, _T_433) node _T_457 = or(_T_456, _T_438) node _T_458 = or(_T_457, _T_443) node _T_459 = or(_T_458, _T_448) node _T_460 = or(_T_459, _T_453) node _T_461 = and(_T_413, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = and(_WIRE_1, _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_463, UInt<1>(0h1), "") : assert_3 node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(source_ok, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_470 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(_T_470, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_470, UInt<1>(0h1), "") : assert_5 node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(is_aligned, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_477 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_477, UInt<1>(0h1), "") : assert_7 node _T_481 = not(io.in.a.bits.mask) node _T_482 = eq(_T_481, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_482, UInt<1>(0h1), "") : assert_8 node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_486, UInt<1>(0h1), "") : assert_9 node _T_490 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_490 : node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_493 = and(_T_491, _T_492) node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_495 = shr(io.in.a.bits.source, 2) node _T_496 = eq(_T_495, UInt<1>(0h0)) node _T_497 = leq(UInt<1>(0h0), uncommonBits_18) node _T_498 = and(_T_496, _T_497) node _T_499 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_500 = and(_T_498, _T_499) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_501 = shr(io.in.a.bits.source, 2) node _T_502 = eq(_T_501, UInt<1>(0h1)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_19) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<2>(0h2)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_20) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<2>(0h3)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_21) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_520 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_521 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_524 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 2, 0) node _T_525 = shr(io.in.a.bits.source, 3) node _T_526 = eq(_T_525, UInt<3>(0h6)) node _T_527 = leq(UInt<1>(0h0), uncommonBits_22) node _T_528 = and(_T_526, _T_527) node _T_529 = leq(uncommonBits_22, UInt<3>(0h4)) node _T_530 = and(_T_528, _T_529) node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 2, 0) node _T_533 = shr(io.in.a.bits.source, 3) node _T_534 = eq(_T_533, UInt<3>(0h4)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_23) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_23, UInt<3>(0h4)) node _T_538 = and(_T_536, _T_537) node _T_539 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_540 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_541 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_542 = or(_T_494, _T_500) node _T_543 = or(_T_542, _T_506) node _T_544 = or(_T_543, _T_512) node _T_545 = or(_T_544, _T_518) node _T_546 = or(_T_545, _T_519) node _T_547 = or(_T_546, _T_520) node _T_548 = or(_T_547, _T_521) node _T_549 = or(_T_548, _T_522) node _T_550 = or(_T_549, _T_523) node _T_551 = or(_T_550, _T_524) node _T_552 = or(_T_551, _T_530) node _T_553 = or(_T_552, _T_531) node _T_554 = or(_T_553, _T_532) node _T_555 = or(_T_554, _T_538) node _T_556 = or(_T_555, _T_539) node _T_557 = or(_T_556, _T_540) node _T_558 = or(_T_557, _T_541) node _T_559 = and(_T_493, _T_558) node _T_560 = or(UInt<1>(0h0), _T_559) node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_562 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<14>(0h2000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_568 = cvt(_T_567) node _T_569 = and(_T_568, asSInt(UInt<13>(0h1000))) node _T_570 = asSInt(_T_569) node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0))) node _T_572 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<17>(0h10000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_578 = cvt(_T_577) node _T_579 = and(_T_578, asSInt(UInt<18>(0h2f000))) node _T_580 = asSInt(_T_579) node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0))) node _T_582 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_583 = cvt(_T_582) node _T_584 = and(_T_583, asSInt(UInt<17>(0h10000))) node _T_585 = asSInt(_T_584) node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0))) node _T_587 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_588 = cvt(_T_587) node _T_589 = and(_T_588, asSInt(UInt<13>(0h1000))) node _T_590 = asSInt(_T_589) node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0))) node _T_592 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_593 = cvt(_T_592) node _T_594 = and(_T_593, asSInt(UInt<27>(0h4000000))) node _T_595 = asSInt(_T_594) node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0))) node _T_597 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_598 = cvt(_T_597) node _T_599 = and(_T_598, asSInt(UInt<13>(0h1000))) node _T_600 = asSInt(_T_599) node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0))) node _T_602 = or(_T_566, _T_571) node _T_603 = or(_T_602, _T_576) node _T_604 = or(_T_603, _T_581) node _T_605 = or(_T_604, _T_586) node _T_606 = or(_T_605, _T_591) node _T_607 = or(_T_606, _T_596) node _T_608 = or(_T_607, _T_601) node _T_609 = and(_T_561, _T_608) node _T_610 = or(UInt<1>(0h0), _T_609) node _T_611 = and(_T_560, _T_610) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_611, UInt<1>(0h1), "") : assert_10 node _T_615 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_616 = shr(io.in.a.bits.source, 2) node _T_617 = eq(_T_616, UInt<1>(0h0)) node _T_618 = leq(UInt<1>(0h0), uncommonBits_24) node _T_619 = and(_T_617, _T_618) node _T_620 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_621 = and(_T_619, _T_620) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_622 = shr(io.in.a.bits.source, 2) node _T_623 = eq(_T_622, UInt<1>(0h1)) node _T_624 = leq(UInt<1>(0h0), uncommonBits_25) node _T_625 = and(_T_623, _T_624) node _T_626 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_627 = and(_T_625, _T_626) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_628 = shr(io.in.a.bits.source, 2) node _T_629 = eq(_T_628, UInt<2>(0h2)) node _T_630 = leq(UInt<1>(0h0), uncommonBits_26) node _T_631 = and(_T_629, _T_630) node _T_632 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_633 = and(_T_631, _T_632) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_634 = shr(io.in.a.bits.source, 2) node _T_635 = eq(_T_634, UInt<2>(0h3)) node _T_636 = leq(UInt<1>(0h0), uncommonBits_27) node _T_637 = and(_T_635, _T_636) node _T_638 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_639 = and(_T_637, _T_638) node _T_640 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_641 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_642 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_643 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_644 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_645 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 2, 0) node _T_646 = shr(io.in.a.bits.source, 3) node _T_647 = eq(_T_646, UInt<3>(0h6)) node _T_648 = leq(UInt<1>(0h0), uncommonBits_28) node _T_649 = and(_T_647, _T_648) node _T_650 = leq(uncommonBits_28, UInt<3>(0h4)) node _T_651 = and(_T_649, _T_650) node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_653 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_654 = shr(io.in.a.bits.source, 3) node _T_655 = eq(_T_654, UInt<3>(0h4)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_29) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_659 = and(_T_657, _T_658) node _T_660 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_661 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_662 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[18] connect _WIRE_2[0], _T_615 connect _WIRE_2[1], _T_621 connect _WIRE_2[2], _T_627 connect _WIRE_2[3], _T_633 connect _WIRE_2[4], _T_639 connect _WIRE_2[5], _T_640 connect _WIRE_2[6], _T_641 connect _WIRE_2[7], _T_642 connect _WIRE_2[8], _T_643 connect _WIRE_2[9], _T_644 connect _WIRE_2[10], _T_645 connect _WIRE_2[11], _T_651 connect _WIRE_2[12], _T_652 connect _WIRE_2[13], _T_653 connect _WIRE_2[14], _T_659 connect _WIRE_2[15], _T_660 connect _WIRE_2[16], _T_661 connect _WIRE_2[17], _T_662 node _T_663 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_664 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_665 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_666 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_667 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_668 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_669 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_670 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_671 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_672 = mux(_WIRE_2[5], _T_663, UInt<1>(0h0)) node _T_673 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_674 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = mux(_WIRE_2[8], _T_664, UInt<1>(0h0)) node _T_676 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_678 = mux(_WIRE_2[11], _T_665, UInt<1>(0h0)) node _T_679 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_680 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_681 = mux(_WIRE_2[14], _T_666, UInt<1>(0h0)) node _T_682 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_683 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_684 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_685 = or(_T_667, _T_668) node _T_686 = or(_T_685, _T_669) node _T_687 = or(_T_686, _T_670) node _T_688 = or(_T_687, _T_671) node _T_689 = or(_T_688, _T_672) node _T_690 = or(_T_689, _T_673) node _T_691 = or(_T_690, _T_674) node _T_692 = or(_T_691, _T_675) node _T_693 = or(_T_692, _T_676) node _T_694 = or(_T_693, _T_677) node _T_695 = or(_T_694, _T_678) node _T_696 = or(_T_695, _T_679) node _T_697 = or(_T_696, _T_680) node _T_698 = or(_T_697, _T_681) node _T_699 = or(_T_698, _T_682) node _T_700 = or(_T_699, _T_683) node _T_701 = or(_T_700, _T_684) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_701 node _T_702 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_703 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_704 = and(_T_702, _T_703) node _T_705 = or(UInt<1>(0h0), _T_704) node _T_706 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<14>(0h2000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<13>(0h1000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<18>(0h2f000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<27>(0h4000000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = or(_T_710, _T_715) node _T_747 = or(_T_746, _T_720) node _T_748 = or(_T_747, _T_725) node _T_749 = or(_T_748, _T_730) node _T_750 = or(_T_749, _T_735) node _T_751 = or(_T_750, _T_740) node _T_752 = or(_T_751, _T_745) node _T_753 = and(_T_705, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = and(_WIRE_3, _T_754) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_755, UInt<1>(0h1), "") : assert_11 node _T_759 = asUInt(reset) node _T_760 = eq(_T_759, UInt<1>(0h0)) when _T_760 : node _T_761 = eq(source_ok, UInt<1>(0h0)) when _T_761 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_762 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_762, UInt<1>(0h1), "") : assert_13 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(is_aligned, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_769 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_769, UInt<1>(0h1), "") : assert_15 node _T_773 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_773, UInt<1>(0h1), "") : assert_16 node _T_777 = not(io.in.a.bits.mask) node _T_778 = eq(_T_777, UInt<1>(0h0)) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_778, UInt<1>(0h1), "") : assert_17 node _T_782 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_782, UInt<1>(0h1), "") : assert_18 node _T_786 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_786 : node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_789 = and(_T_787, _T_788) node _T_790 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_791 = shr(io.in.a.bits.source, 2) node _T_792 = eq(_T_791, UInt<1>(0h0)) node _T_793 = leq(UInt<1>(0h0), uncommonBits_30) node _T_794 = and(_T_792, _T_793) node _T_795 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_796 = and(_T_794, _T_795) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_797 = shr(io.in.a.bits.source, 2) node _T_798 = eq(_T_797, UInt<1>(0h1)) node _T_799 = leq(UInt<1>(0h0), uncommonBits_31) node _T_800 = and(_T_798, _T_799) node _T_801 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_802 = and(_T_800, _T_801) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_803 = shr(io.in.a.bits.source, 2) node _T_804 = eq(_T_803, UInt<2>(0h2)) node _T_805 = leq(UInt<1>(0h0), uncommonBits_32) node _T_806 = and(_T_804, _T_805) node _T_807 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_808 = and(_T_806, _T_807) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<2>(0h3)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_33) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _T_815 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_816 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_817 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_818 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_819 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_820 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_821 = shr(io.in.a.bits.source, 3) node _T_822 = eq(_T_821, UInt<3>(0h6)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_34) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_826 = and(_T_824, _T_825) node _T_827 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_828 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 2, 0) node _T_829 = shr(io.in.a.bits.source, 3) node _T_830 = eq(_T_829, UInt<3>(0h4)) node _T_831 = leq(UInt<1>(0h0), uncommonBits_35) node _T_832 = and(_T_830, _T_831) node _T_833 = leq(uncommonBits_35, UInt<3>(0h4)) node _T_834 = and(_T_832, _T_833) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_837 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_838 = or(_T_790, _T_796) node _T_839 = or(_T_838, _T_802) node _T_840 = or(_T_839, _T_808) node _T_841 = or(_T_840, _T_814) node _T_842 = or(_T_841, _T_815) node _T_843 = or(_T_842, _T_816) node _T_844 = or(_T_843, _T_817) node _T_845 = or(_T_844, _T_818) node _T_846 = or(_T_845, _T_819) node _T_847 = or(_T_846, _T_820) node _T_848 = or(_T_847, _T_826) node _T_849 = or(_T_848, _T_827) node _T_850 = or(_T_849, _T_828) node _T_851 = or(_T_850, _T_834) node _T_852 = or(_T_851, _T_835) node _T_853 = or(_T_852, _T_836) node _T_854 = or(_T_853, _T_837) node _T_855 = and(_T_789, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(_T_856, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_856, UInt<1>(0h1), "") : assert_19 node _T_860 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_861 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_862 = and(_T_860, _T_861) node _T_863 = or(UInt<1>(0h0), _T_862) node _T_864 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<13>(0h1000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = and(_T_863, _T_868) node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_872 = and(_T_870, _T_871) node _T_873 = or(UInt<1>(0h0), _T_872) node _T_874 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<14>(0h2000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<18>(0h2f000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<17>(0h10000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = or(_T_878, _T_883) node _T_910 = or(_T_909, _T_888) node _T_911 = or(_T_910, _T_893) node _T_912 = or(_T_911, _T_898) node _T_913 = or(_T_912, _T_903) node _T_914 = or(_T_913, _T_908) node _T_915 = and(_T_873, _T_914) node _T_916 = or(UInt<1>(0h0), _T_869) node _T_917 = or(_T_916, _T_915) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_917, UInt<1>(0h1), "") : assert_20 node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(source_ok, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(is_aligned, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_927 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(_T_927, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_927, UInt<1>(0h1), "") : assert_23 node _T_931 = eq(io.in.a.bits.mask, mask) node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(_T_931, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_931, UInt<1>(0h1), "") : assert_24 node _T_935 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_935, UInt<1>(0h1), "") : assert_25 node _T_939 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_939 : node _T_940 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_941 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_942 = and(_T_940, _T_941) node _T_943 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_944 = shr(io.in.a.bits.source, 2) node _T_945 = eq(_T_944, UInt<1>(0h0)) node _T_946 = leq(UInt<1>(0h0), uncommonBits_36) node _T_947 = and(_T_945, _T_946) node _T_948 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_949 = and(_T_947, _T_948) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_950 = shr(io.in.a.bits.source, 2) node _T_951 = eq(_T_950, UInt<1>(0h1)) node _T_952 = leq(UInt<1>(0h0), uncommonBits_37) node _T_953 = and(_T_951, _T_952) node _T_954 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_955 = and(_T_953, _T_954) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_956 = shr(io.in.a.bits.source, 2) node _T_957 = eq(_T_956, UInt<2>(0h2)) node _T_958 = leq(UInt<1>(0h0), uncommonBits_38) node _T_959 = and(_T_957, _T_958) node _T_960 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_961 = and(_T_959, _T_960) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_962 = shr(io.in.a.bits.source, 2) node _T_963 = eq(_T_962, UInt<2>(0h3)) node _T_964 = leq(UInt<1>(0h0), uncommonBits_39) node _T_965 = and(_T_963, _T_964) node _T_966 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_967 = and(_T_965, _T_966) node _T_968 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_969 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_970 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_971 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_972 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_973 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_974 = shr(io.in.a.bits.source, 3) node _T_975 = eq(_T_974, UInt<3>(0h6)) node _T_976 = leq(UInt<1>(0h0), uncommonBits_40) node _T_977 = and(_T_975, _T_976) node _T_978 = leq(uncommonBits_40, UInt<3>(0h4)) node _T_979 = and(_T_977, _T_978) node _T_980 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_981 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_982 = shr(io.in.a.bits.source, 3) node _T_983 = eq(_T_982, UInt<3>(0h4)) node _T_984 = leq(UInt<1>(0h0), uncommonBits_41) node _T_985 = and(_T_983, _T_984) node _T_986 = leq(uncommonBits_41, UInt<3>(0h4)) node _T_987 = and(_T_985, _T_986) node _T_988 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_989 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_990 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_991 = or(_T_943, _T_949) node _T_992 = or(_T_991, _T_955) node _T_993 = or(_T_992, _T_961) node _T_994 = or(_T_993, _T_967) node _T_995 = or(_T_994, _T_968) node _T_996 = or(_T_995, _T_969) node _T_997 = or(_T_996, _T_970) node _T_998 = or(_T_997, _T_971) node _T_999 = or(_T_998, _T_972) node _T_1000 = or(_T_999, _T_973) node _T_1001 = or(_T_1000, _T_979) node _T_1002 = or(_T_1001, _T_980) node _T_1003 = or(_T_1002, _T_981) node _T_1004 = or(_T_1003, _T_987) node _T_1005 = or(_T_1004, _T_988) node _T_1006 = or(_T_1005, _T_989) node _T_1007 = or(_T_1006, _T_990) node _T_1008 = and(_T_942, _T_1007) node _T_1009 = or(UInt<1>(0h0), _T_1008) node _T_1010 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1011 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1012 = and(_T_1010, _T_1011) node _T_1013 = or(UInt<1>(0h0), _T_1012) node _T_1014 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<13>(0h1000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = and(_T_1013, _T_1018) node _T_1020 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1021 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1022 = and(_T_1020, _T_1021) node _T_1023 = or(UInt<1>(0h0), _T_1022) node _T_1024 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<14>(0h2000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1030 = cvt(_T_1029) node _T_1031 = and(_T_1030, asSInt(UInt<18>(0h2f000))) node _T_1032 = asSInt(_T_1031) node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0))) node _T_1034 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1035 = cvt(_T_1034) node _T_1036 = and(_T_1035, asSInt(UInt<17>(0h10000))) node _T_1037 = asSInt(_T_1036) node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0))) node _T_1039 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1040 = cvt(_T_1039) node _T_1041 = and(_T_1040, asSInt(UInt<13>(0h1000))) node _T_1042 = asSInt(_T_1041) node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) node _T_1044 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1045 = cvt(_T_1044) node _T_1046 = and(_T_1045, asSInt(UInt<27>(0h4000000))) node _T_1047 = asSInt(_T_1046) node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) node _T_1049 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1050 = cvt(_T_1049) node _T_1051 = and(_T_1050, asSInt(UInt<13>(0h1000))) node _T_1052 = asSInt(_T_1051) node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = or(_T_1028, _T_1033) node _T_1055 = or(_T_1054, _T_1038) node _T_1056 = or(_T_1055, _T_1043) node _T_1057 = or(_T_1056, _T_1048) node _T_1058 = or(_T_1057, _T_1053) node _T_1059 = and(_T_1023, _T_1058) node _T_1060 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1061 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1062 = cvt(_T_1061) node _T_1063 = and(_T_1062, asSInt(UInt<17>(0h10000))) node _T_1064 = asSInt(_T_1063) node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0))) node _T_1066 = and(_T_1060, _T_1065) node _T_1067 = or(UInt<1>(0h0), _T_1019) node _T_1068 = or(_T_1067, _T_1059) node _T_1069 = or(_T_1068, _T_1066) node _T_1070 = and(_T_1009, _T_1069) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_26 node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(source_ok, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(is_aligned, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1080 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_29 node _T_1084 = eq(io.in.a.bits.mask, mask) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_30 node _T_1088 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1088 : node _T_1089 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1090 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1091 = and(_T_1089, _T_1090) node _T_1092 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1093 = shr(io.in.a.bits.source, 2) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) node _T_1095 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1098 = and(_T_1096, _T_1097) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1099 = shr(io.in.a.bits.source, 2) node _T_1100 = eq(_T_1099, UInt<1>(0h1)) node _T_1101 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1104 = and(_T_1102, _T_1103) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1105 = shr(io.in.a.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h2)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1111 = shr(io.in.a.bits.source, 2) node _T_1112 = eq(_T_1111, UInt<2>(0h3)) node _T_1113 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1114 = and(_T_1112, _T_1113) node _T_1115 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1116 = and(_T_1114, _T_1115) node _T_1117 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1118 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1119 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1120 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1121 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1122 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_1123 = shr(io.in.a.bits.source, 3) node _T_1124 = eq(_T_1123, UInt<3>(0h6)) node _T_1125 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1126 = and(_T_1124, _T_1125) node _T_1127 = leq(uncommonBits_46, UInt<3>(0h4)) node _T_1128 = and(_T_1126, _T_1127) node _T_1129 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1130 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_1131 = shr(io.in.a.bits.source, 3) node _T_1132 = eq(_T_1131, UInt<3>(0h4)) node _T_1133 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1134 = and(_T_1132, _T_1133) node _T_1135 = leq(uncommonBits_47, UInt<3>(0h4)) node _T_1136 = and(_T_1134, _T_1135) node _T_1137 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1138 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1139 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1140 = or(_T_1092, _T_1098) node _T_1141 = or(_T_1140, _T_1104) node _T_1142 = or(_T_1141, _T_1110) node _T_1143 = or(_T_1142, _T_1116) node _T_1144 = or(_T_1143, _T_1117) node _T_1145 = or(_T_1144, _T_1118) node _T_1146 = or(_T_1145, _T_1119) node _T_1147 = or(_T_1146, _T_1120) node _T_1148 = or(_T_1147, _T_1121) node _T_1149 = or(_T_1148, _T_1122) node _T_1150 = or(_T_1149, _T_1128) node _T_1151 = or(_T_1150, _T_1129) node _T_1152 = or(_T_1151, _T_1130) node _T_1153 = or(_T_1152, _T_1136) node _T_1154 = or(_T_1153, _T_1137) node _T_1155 = or(_T_1154, _T_1138) node _T_1156 = or(_T_1155, _T_1139) node _T_1157 = and(_T_1091, _T_1156) node _T_1158 = or(UInt<1>(0h0), _T_1157) node _T_1159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1160 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1161 = and(_T_1159, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1164 = cvt(_T_1163) node _T_1165 = and(_T_1164, asSInt(UInt<13>(0h1000))) node _T_1166 = asSInt(_T_1165) node _T_1167 = eq(_T_1166, asSInt(UInt<1>(0h0))) node _T_1168 = and(_T_1162, _T_1167) node _T_1169 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1170 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1171 = and(_T_1169, _T_1170) node _T_1172 = or(UInt<1>(0h0), _T_1171) node _T_1173 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1174 = cvt(_T_1173) node _T_1175 = and(_T_1174, asSInt(UInt<14>(0h2000))) node _T_1176 = asSInt(_T_1175) node _T_1177 = eq(_T_1176, asSInt(UInt<1>(0h0))) node _T_1178 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1179 = cvt(_T_1178) node _T_1180 = and(_T_1179, asSInt(UInt<18>(0h2f000))) node _T_1181 = asSInt(_T_1180) node _T_1182 = eq(_T_1181, asSInt(UInt<1>(0h0))) node _T_1183 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1184 = cvt(_T_1183) node _T_1185 = and(_T_1184, asSInt(UInt<17>(0h10000))) node _T_1186 = asSInt(_T_1185) node _T_1187 = eq(_T_1186, asSInt(UInt<1>(0h0))) node _T_1188 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1189 = cvt(_T_1188) node _T_1190 = and(_T_1189, asSInt(UInt<13>(0h1000))) node _T_1191 = asSInt(_T_1190) node _T_1192 = eq(_T_1191, asSInt(UInt<1>(0h0))) node _T_1193 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1194 = cvt(_T_1193) node _T_1195 = and(_T_1194, asSInt(UInt<27>(0h4000000))) node _T_1196 = asSInt(_T_1195) node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0))) node _T_1198 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1199 = cvt(_T_1198) node _T_1200 = and(_T_1199, asSInt(UInt<13>(0h1000))) node _T_1201 = asSInt(_T_1200) node _T_1202 = eq(_T_1201, asSInt(UInt<1>(0h0))) node _T_1203 = or(_T_1177, _T_1182) node _T_1204 = or(_T_1203, _T_1187) node _T_1205 = or(_T_1204, _T_1192) node _T_1206 = or(_T_1205, _T_1197) node _T_1207 = or(_T_1206, _T_1202) node _T_1208 = and(_T_1172, _T_1207) node _T_1209 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1210 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<17>(0h10000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = and(_T_1209, _T_1214) node _T_1216 = or(UInt<1>(0h0), _T_1168) node _T_1217 = or(_T_1216, _T_1208) node _T_1218 = or(_T_1217, _T_1215) node _T_1219 = and(_T_1158, _T_1218) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_31 node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(source_ok, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(is_aligned, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1229 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_34 node _T_1233 = not(mask) node _T_1234 = and(io.in.a.bits.mask, _T_1233) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_35 node _T_1239 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1239 : node _T_1240 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1241 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1242 = and(_T_1240, _T_1241) node _T_1243 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1244 = shr(io.in.a.bits.source, 2) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) node _T_1246 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1247 = and(_T_1245, _T_1246) node _T_1248 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1249 = and(_T_1247, _T_1248) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1250 = shr(io.in.a.bits.source, 2) node _T_1251 = eq(_T_1250, UInt<1>(0h1)) node _T_1252 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1253 = and(_T_1251, _T_1252) node _T_1254 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1255 = and(_T_1253, _T_1254) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1256 = shr(io.in.a.bits.source, 2) node _T_1257 = eq(_T_1256, UInt<2>(0h2)) node _T_1258 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1259 = and(_T_1257, _T_1258) node _T_1260 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1261 = and(_T_1259, _T_1260) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1262 = shr(io.in.a.bits.source, 2) node _T_1263 = eq(_T_1262, UInt<2>(0h3)) node _T_1264 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1265 = and(_T_1263, _T_1264) node _T_1266 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1267 = and(_T_1265, _T_1266) node _T_1268 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1269 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1270 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1271 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1272 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1273 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 2, 0) node _T_1274 = shr(io.in.a.bits.source, 3) node _T_1275 = eq(_T_1274, UInt<3>(0h6)) node _T_1276 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1277 = and(_T_1275, _T_1276) node _T_1278 = leq(uncommonBits_52, UInt<3>(0h4)) node _T_1279 = and(_T_1277, _T_1278) node _T_1280 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1281 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_1282 = shr(io.in.a.bits.source, 3) node _T_1283 = eq(_T_1282, UInt<3>(0h4)) node _T_1284 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1285 = and(_T_1283, _T_1284) node _T_1286 = leq(uncommonBits_53, UInt<3>(0h4)) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1289 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1290 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1291 = or(_T_1243, _T_1249) node _T_1292 = or(_T_1291, _T_1255) node _T_1293 = or(_T_1292, _T_1261) node _T_1294 = or(_T_1293, _T_1267) node _T_1295 = or(_T_1294, _T_1268) node _T_1296 = or(_T_1295, _T_1269) node _T_1297 = or(_T_1296, _T_1270) node _T_1298 = or(_T_1297, _T_1271) node _T_1299 = or(_T_1298, _T_1272) node _T_1300 = or(_T_1299, _T_1273) node _T_1301 = or(_T_1300, _T_1279) node _T_1302 = or(_T_1301, _T_1280) node _T_1303 = or(_T_1302, _T_1281) node _T_1304 = or(_T_1303, _T_1287) node _T_1305 = or(_T_1304, _T_1288) node _T_1306 = or(_T_1305, _T_1289) node _T_1307 = or(_T_1306, _T_1290) node _T_1308 = and(_T_1242, _T_1307) node _T_1309 = or(UInt<1>(0h0), _T_1308) node _T_1310 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1311 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1312 = and(_T_1310, _T_1311) node _T_1313 = or(UInt<1>(0h0), _T_1312) node _T_1314 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1315 = cvt(_T_1314) node _T_1316 = and(_T_1315, asSInt(UInt<15>(0h5000))) node _T_1317 = asSInt(_T_1316) node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0))) node _T_1319 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1320 = cvt(_T_1319) node _T_1321 = and(_T_1320, asSInt(UInt<13>(0h1000))) node _T_1322 = asSInt(_T_1321) node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0))) node _T_1324 = or(_T_1318, _T_1323) node _T_1325 = and(_T_1313, _T_1324) node _T_1326 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1327 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1328 = cvt(_T_1327) node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000))) node _T_1330 = asSInt(_T_1329) node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) node _T_1332 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<17>(0h10000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1338 = cvt(_T_1337) node _T_1339 = and(_T_1338, asSInt(UInt<18>(0h2f000))) node _T_1340 = asSInt(_T_1339) node _T_1341 = eq(_T_1340, asSInt(UInt<1>(0h0))) node _T_1342 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1343 = cvt(_T_1342) node _T_1344 = and(_T_1343, asSInt(UInt<17>(0h10000))) node _T_1345 = asSInt(_T_1344) node _T_1346 = eq(_T_1345, asSInt(UInt<1>(0h0))) node _T_1347 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1348 = cvt(_T_1347) node _T_1349 = and(_T_1348, asSInt(UInt<13>(0h1000))) node _T_1350 = asSInt(_T_1349) node _T_1351 = eq(_T_1350, asSInt(UInt<1>(0h0))) node _T_1352 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1353 = cvt(_T_1352) node _T_1354 = and(_T_1353, asSInt(UInt<27>(0h4000000))) node _T_1355 = asSInt(_T_1354) node _T_1356 = eq(_T_1355, asSInt(UInt<1>(0h0))) node _T_1357 = or(_T_1331, _T_1336) node _T_1358 = or(_T_1357, _T_1341) node _T_1359 = or(_T_1358, _T_1346) node _T_1360 = or(_T_1359, _T_1351) node _T_1361 = or(_T_1360, _T_1356) node _T_1362 = and(_T_1326, _T_1361) node _T_1363 = or(UInt<1>(0h0), _T_1325) node _T_1364 = or(_T_1363, _T_1362) node _T_1365 = and(_T_1309, _T_1364) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_36 node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(source_ok, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(is_aligned, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1375 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_39 node _T_1379 = eq(io.in.a.bits.mask, mask) node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(_T_1379, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1379, UInt<1>(0h1), "") : assert_40 node _T_1383 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1383 : node _T_1384 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1385 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1386 = and(_T_1384, _T_1385) node _T_1387 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1388 = shr(io.in.a.bits.source, 2) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) node _T_1390 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1391 = and(_T_1389, _T_1390) node _T_1392 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1393 = and(_T_1391, _T_1392) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1394 = shr(io.in.a.bits.source, 2) node _T_1395 = eq(_T_1394, UInt<1>(0h1)) node _T_1396 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1397 = and(_T_1395, _T_1396) node _T_1398 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1399 = and(_T_1397, _T_1398) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1400 = shr(io.in.a.bits.source, 2) node _T_1401 = eq(_T_1400, UInt<2>(0h2)) node _T_1402 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1403 = and(_T_1401, _T_1402) node _T_1404 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1405 = and(_T_1403, _T_1404) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1406 = shr(io.in.a.bits.source, 2) node _T_1407 = eq(_T_1406, UInt<2>(0h3)) node _T_1408 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1409 = and(_T_1407, _T_1408) node _T_1410 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1411 = and(_T_1409, _T_1410) node _T_1412 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1413 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1414 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1415 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1416 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1417 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 2, 0) node _T_1418 = shr(io.in.a.bits.source, 3) node _T_1419 = eq(_T_1418, UInt<3>(0h6)) node _T_1420 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1421 = and(_T_1419, _T_1420) node _T_1422 = leq(uncommonBits_58, UInt<3>(0h4)) node _T_1423 = and(_T_1421, _T_1422) node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0) node _T_1426 = shr(io.in.a.bits.source, 3) node _T_1427 = eq(_T_1426, UInt<3>(0h4)) node _T_1428 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1429 = and(_T_1427, _T_1428) node _T_1430 = leq(uncommonBits_59, UInt<3>(0h4)) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1433 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1434 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1435 = or(_T_1387, _T_1393) node _T_1436 = or(_T_1435, _T_1399) node _T_1437 = or(_T_1436, _T_1405) node _T_1438 = or(_T_1437, _T_1411) node _T_1439 = or(_T_1438, _T_1412) node _T_1440 = or(_T_1439, _T_1413) node _T_1441 = or(_T_1440, _T_1414) node _T_1442 = or(_T_1441, _T_1415) node _T_1443 = or(_T_1442, _T_1416) node _T_1444 = or(_T_1443, _T_1417) node _T_1445 = or(_T_1444, _T_1423) node _T_1446 = or(_T_1445, _T_1424) node _T_1447 = or(_T_1446, _T_1425) node _T_1448 = or(_T_1447, _T_1431) node _T_1449 = or(_T_1448, _T_1432) node _T_1450 = or(_T_1449, _T_1433) node _T_1451 = or(_T_1450, _T_1434) node _T_1452 = and(_T_1386, _T_1451) node _T_1453 = or(UInt<1>(0h0), _T_1452) node _T_1454 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1455 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1456 = and(_T_1454, _T_1455) node _T_1457 = or(UInt<1>(0h0), _T_1456) node _T_1458 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1459 = cvt(_T_1458) node _T_1460 = and(_T_1459, asSInt(UInt<15>(0h5000))) node _T_1461 = asSInt(_T_1460) node _T_1462 = eq(_T_1461, asSInt(UInt<1>(0h0))) node _T_1463 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1464 = cvt(_T_1463) node _T_1465 = and(_T_1464, asSInt(UInt<13>(0h1000))) node _T_1466 = asSInt(_T_1465) node _T_1467 = eq(_T_1466, asSInt(UInt<1>(0h0))) node _T_1468 = or(_T_1462, _T_1467) node _T_1469 = and(_T_1457, _T_1468) node _T_1470 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1471 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1472 = cvt(_T_1471) node _T_1473 = and(_T_1472, asSInt(UInt<13>(0h1000))) node _T_1474 = asSInt(_T_1473) node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0))) node _T_1476 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<17>(0h10000))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1482 = cvt(_T_1481) node _T_1483 = and(_T_1482, asSInt(UInt<18>(0h2f000))) node _T_1484 = asSInt(_T_1483) node _T_1485 = eq(_T_1484, asSInt(UInt<1>(0h0))) node _T_1486 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1487 = cvt(_T_1486) node _T_1488 = and(_T_1487, asSInt(UInt<17>(0h10000))) node _T_1489 = asSInt(_T_1488) node _T_1490 = eq(_T_1489, asSInt(UInt<1>(0h0))) node _T_1491 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1492 = cvt(_T_1491) node _T_1493 = and(_T_1492, asSInt(UInt<13>(0h1000))) node _T_1494 = asSInt(_T_1493) node _T_1495 = eq(_T_1494, asSInt(UInt<1>(0h0))) node _T_1496 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1497 = cvt(_T_1496) node _T_1498 = and(_T_1497, asSInt(UInt<27>(0h4000000))) node _T_1499 = asSInt(_T_1498) node _T_1500 = eq(_T_1499, asSInt(UInt<1>(0h0))) node _T_1501 = or(_T_1475, _T_1480) node _T_1502 = or(_T_1501, _T_1485) node _T_1503 = or(_T_1502, _T_1490) node _T_1504 = or(_T_1503, _T_1495) node _T_1505 = or(_T_1504, _T_1500) node _T_1506 = and(_T_1470, _T_1505) node _T_1507 = or(UInt<1>(0h0), _T_1469) node _T_1508 = or(_T_1507, _T_1506) node _T_1509 = and(_T_1453, _T_1508) node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(_T_1509, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1509, UInt<1>(0h1), "") : assert_41 node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(source_ok, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(is_aligned, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1519 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_44 node _T_1523 = eq(io.in.a.bits.mask, mask) node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(_T_1523, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1523, UInt<1>(0h1), "") : assert_45 node _T_1527 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1527 : node _T_1528 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1529 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1530 = and(_T_1528, _T_1529) node _T_1531 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1532 = shr(io.in.a.bits.source, 2) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) node _T_1534 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1535 = and(_T_1533, _T_1534) node _T_1536 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1537 = and(_T_1535, _T_1536) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1538 = shr(io.in.a.bits.source, 2) node _T_1539 = eq(_T_1538, UInt<1>(0h1)) node _T_1540 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1541 = and(_T_1539, _T_1540) node _T_1542 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1543 = and(_T_1541, _T_1542) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1544 = shr(io.in.a.bits.source, 2) node _T_1545 = eq(_T_1544, UInt<2>(0h2)) node _T_1546 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1547 = and(_T_1545, _T_1546) node _T_1548 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1549 = and(_T_1547, _T_1548) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1550 = shr(io.in.a.bits.source, 2) node _T_1551 = eq(_T_1550, UInt<2>(0h3)) node _T_1552 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1553 = and(_T_1551, _T_1552) node _T_1554 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1555 = and(_T_1553, _T_1554) node _T_1556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0) node _T_1562 = shr(io.in.a.bits.source, 3) node _T_1563 = eq(_T_1562, UInt<3>(0h6)) node _T_1564 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1565 = and(_T_1563, _T_1564) node _T_1566 = leq(uncommonBits_64, UInt<3>(0h4)) node _T_1567 = and(_T_1565, _T_1566) node _T_1568 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1569 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 2, 0) node _T_1570 = shr(io.in.a.bits.source, 3) node _T_1571 = eq(_T_1570, UInt<3>(0h4)) node _T_1572 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1573 = and(_T_1571, _T_1572) node _T_1574 = leq(uncommonBits_65, UInt<3>(0h4)) node _T_1575 = and(_T_1573, _T_1574) node _T_1576 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1578 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1579 = or(_T_1531, _T_1537) node _T_1580 = or(_T_1579, _T_1543) node _T_1581 = or(_T_1580, _T_1549) node _T_1582 = or(_T_1581, _T_1555) node _T_1583 = or(_T_1582, _T_1556) node _T_1584 = or(_T_1583, _T_1557) node _T_1585 = or(_T_1584, _T_1558) node _T_1586 = or(_T_1585, _T_1559) node _T_1587 = or(_T_1586, _T_1560) node _T_1588 = or(_T_1587, _T_1561) node _T_1589 = or(_T_1588, _T_1567) node _T_1590 = or(_T_1589, _T_1568) node _T_1591 = or(_T_1590, _T_1569) node _T_1592 = or(_T_1591, _T_1575) node _T_1593 = or(_T_1592, _T_1576) node _T_1594 = or(_T_1593, _T_1577) node _T_1595 = or(_T_1594, _T_1578) node _T_1596 = and(_T_1530, _T_1595) node _T_1597 = or(UInt<1>(0h0), _T_1596) node _T_1598 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1599 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1600 = and(_T_1598, _T_1599) node _T_1601 = or(UInt<1>(0h0), _T_1600) node _T_1602 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = and(_T_1601, _T_1606) node _T_1608 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1609 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1610 = cvt(_T_1609) node _T_1611 = and(_T_1610, asSInt(UInt<14>(0h2000))) node _T_1612 = asSInt(_T_1611) node _T_1613 = eq(_T_1612, asSInt(UInt<1>(0h0))) node _T_1614 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1615 = cvt(_T_1614) node _T_1616 = and(_T_1615, asSInt(UInt<17>(0h10000))) node _T_1617 = asSInt(_T_1616) node _T_1618 = eq(_T_1617, asSInt(UInt<1>(0h0))) node _T_1619 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1620 = cvt(_T_1619) node _T_1621 = and(_T_1620, asSInt(UInt<18>(0h2f000))) node _T_1622 = asSInt(_T_1621) node _T_1623 = eq(_T_1622, asSInt(UInt<1>(0h0))) node _T_1624 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1625 = cvt(_T_1624) node _T_1626 = and(_T_1625, asSInt(UInt<17>(0h10000))) node _T_1627 = asSInt(_T_1626) node _T_1628 = eq(_T_1627, asSInt(UInt<1>(0h0))) node _T_1629 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1630 = cvt(_T_1629) node _T_1631 = and(_T_1630, asSInt(UInt<13>(0h1000))) node _T_1632 = asSInt(_T_1631) node _T_1633 = eq(_T_1632, asSInt(UInt<1>(0h0))) node _T_1634 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1635 = cvt(_T_1634) node _T_1636 = and(_T_1635, asSInt(UInt<27>(0h4000000))) node _T_1637 = asSInt(_T_1636) node _T_1638 = eq(_T_1637, asSInt(UInt<1>(0h0))) node _T_1639 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1640 = cvt(_T_1639) node _T_1641 = and(_T_1640, asSInt(UInt<13>(0h1000))) node _T_1642 = asSInt(_T_1641) node _T_1643 = eq(_T_1642, asSInt(UInt<1>(0h0))) node _T_1644 = or(_T_1613, _T_1618) node _T_1645 = or(_T_1644, _T_1623) node _T_1646 = or(_T_1645, _T_1628) node _T_1647 = or(_T_1646, _T_1633) node _T_1648 = or(_T_1647, _T_1638) node _T_1649 = or(_T_1648, _T_1643) node _T_1650 = and(_T_1608, _T_1649) node _T_1651 = or(UInt<1>(0h0), _T_1607) node _T_1652 = or(_T_1651, _T_1650) node _T_1653 = and(_T_1597, _T_1652) node _T_1654 = asUInt(reset) node _T_1655 = eq(_T_1654, UInt<1>(0h0)) when _T_1655 : node _T_1656 = eq(_T_1653, UInt<1>(0h0)) when _T_1656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1653, UInt<1>(0h1), "") : assert_46 node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(source_ok, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1660 = asUInt(reset) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(is_aligned, UInt<1>(0h0)) when _T_1662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1663 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_49 node _T_1667 = eq(io.in.a.bits.mask, mask) node _T_1668 = asUInt(reset) node _T_1669 = eq(_T_1668, UInt<1>(0h0)) when _T_1669 : node _T_1670 = eq(_T_1667, UInt<1>(0h0)) when _T_1670 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1667, UInt<1>(0h1), "") : assert_50 node _T_1671 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1672 = asUInt(reset) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(_T_1671, UInt<1>(0h0)) when _T_1674 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1671, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1675 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(_T_1675, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1675, UInt<1>(0h1), "") : assert_52 node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_65 = shr(io.in.d.bits.source, 2) node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h0)) node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_71 = shr(io.in.d.bits.source, 2) node _source_ok_T_72 = eq(_source_ok_T_71, UInt<1>(0h1)) node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 2) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h2)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_83 = shr(io.in.d.bits.source, 2) node _source_ok_T_84 = eq(_source_ok_T_83, UInt<2>(0h3)) node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) node _source_ok_T_87 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 2, 0) node _source_ok_T_95 = shr(io.in.d.bits.source, 3) node _source_ok_T_96 = eq(_source_ok_T_95, UInt<3>(0h6)) node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_T_99 = leq(source_ok_uncommonBits_10, UInt<3>(0h4)) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 3) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_11, UInt<3>(0h4)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[18] connect _source_ok_WIRE_1[0], _source_ok_T_64 connect _source_ok_WIRE_1[1], _source_ok_T_70 connect _source_ok_WIRE_1[2], _source_ok_T_76 connect _source_ok_WIRE_1[3], _source_ok_T_82 connect _source_ok_WIRE_1[4], _source_ok_T_88 connect _source_ok_WIRE_1[5], _source_ok_T_89 connect _source_ok_WIRE_1[6], _source_ok_T_90 connect _source_ok_WIRE_1[7], _source_ok_T_91 connect _source_ok_WIRE_1[8], _source_ok_T_92 connect _source_ok_WIRE_1[9], _source_ok_T_93 connect _source_ok_WIRE_1[10], _source_ok_T_94 connect _source_ok_WIRE_1[11], _source_ok_T_100 connect _source_ok_WIRE_1[12], _source_ok_T_101 connect _source_ok_WIRE_1[13], _source_ok_T_102 connect _source_ok_WIRE_1[14], _source_ok_T_108 connect _source_ok_WIRE_1[15], _source_ok_T_109 connect _source_ok_WIRE_1[16], _source_ok_T_110 connect _source_ok_WIRE_1[17], _source_ok_T_111 node _source_ok_T_112 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[2]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[3]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[4]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[5]) node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[6]) node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[7]) node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[8]) node _source_ok_T_120 = or(_source_ok_T_119, _source_ok_WIRE_1[9]) node _source_ok_T_121 = or(_source_ok_T_120, _source_ok_WIRE_1[10]) node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_1[11]) node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_1[12]) node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_1[13]) node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_1[14]) node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_1[15]) node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_1[16]) node source_ok_1 = or(_source_ok_T_127, _source_ok_WIRE_1[17]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1679 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1679 : node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(source_ok_1, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1683 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_54 node _T_1687 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_55 node _T_1691 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_56 node _T_1695 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_57 node _T_1699 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1699 : node _T_1700 = asUInt(reset) node _T_1701 = eq(_T_1700, UInt<1>(0h0)) when _T_1701 : node _T_1702 = eq(source_ok_1, UInt<1>(0h0)) when _T_1702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1703 = asUInt(reset) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) when _T_1704 : node _T_1705 = eq(sink_ok, UInt<1>(0h0)) when _T_1705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1706 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1707 = asUInt(reset) node _T_1708 = eq(_T_1707, UInt<1>(0h0)) when _T_1708 : node _T_1709 = eq(_T_1706, UInt<1>(0h0)) when _T_1709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1706, UInt<1>(0h1), "") : assert_60 node _T_1710 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1711 = asUInt(reset) node _T_1712 = eq(_T_1711, UInt<1>(0h0)) when _T_1712 : node _T_1713 = eq(_T_1710, UInt<1>(0h0)) when _T_1713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1710, UInt<1>(0h1), "") : assert_61 node _T_1714 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_62 node _T_1718 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1719 = asUInt(reset) node _T_1720 = eq(_T_1719, UInt<1>(0h0)) when _T_1720 : node _T_1721 = eq(_T_1718, UInt<1>(0h0)) when _T_1721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1718, UInt<1>(0h1), "") : assert_63 node _T_1722 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1723 = or(UInt<1>(0h1), _T_1722) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_64 node _T_1727 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1727 : node _T_1728 = asUInt(reset) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) when _T_1729 : node _T_1730 = eq(source_ok_1, UInt<1>(0h0)) when _T_1730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1731 = asUInt(reset) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) when _T_1732 : node _T_1733 = eq(sink_ok, UInt<1>(0h0)) when _T_1733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1734 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1735 = asUInt(reset) node _T_1736 = eq(_T_1735, UInt<1>(0h0)) when _T_1736 : node _T_1737 = eq(_T_1734, UInt<1>(0h0)) when _T_1737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1734, UInt<1>(0h1), "") : assert_67 node _T_1738 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1739 = asUInt(reset) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) when _T_1740 : node _T_1741 = eq(_T_1738, UInt<1>(0h0)) when _T_1741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1738, UInt<1>(0h1), "") : assert_68 node _T_1742 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1743 = asUInt(reset) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) when _T_1744 : node _T_1745 = eq(_T_1742, UInt<1>(0h0)) when _T_1745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1742, UInt<1>(0h1), "") : assert_69 node _T_1746 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1747 = or(_T_1746, io.in.d.bits.corrupt) node _T_1748 = asUInt(reset) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) when _T_1749 : node _T_1750 = eq(_T_1747, UInt<1>(0h0)) when _T_1750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1747, UInt<1>(0h1), "") : assert_70 node _T_1751 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1752 = or(UInt<1>(0h1), _T_1751) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_71 node _T_1756 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1756 : node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(source_ok_1, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1760 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1761 = asUInt(reset) node _T_1762 = eq(_T_1761, UInt<1>(0h0)) when _T_1762 : node _T_1763 = eq(_T_1760, UInt<1>(0h0)) when _T_1763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1760, UInt<1>(0h1), "") : assert_73 node _T_1764 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1765 = asUInt(reset) node _T_1766 = eq(_T_1765, UInt<1>(0h0)) when _T_1766 : node _T_1767 = eq(_T_1764, UInt<1>(0h0)) when _T_1767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1764, UInt<1>(0h1), "") : assert_74 node _T_1768 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1769 = or(UInt<1>(0h1), _T_1768) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_75 node _T_1773 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1773 : node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(source_ok_1, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1777 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1778 = asUInt(reset) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) when _T_1779 : node _T_1780 = eq(_T_1777, UInt<1>(0h0)) when _T_1780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1777, UInt<1>(0h1), "") : assert_77 node _T_1781 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1782 = or(_T_1781, io.in.d.bits.corrupt) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_78 node _T_1786 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1787 = or(UInt<1>(0h1), _T_1786) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_79 node _T_1791 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1791 : node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(source_ok_1, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1795 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_81 node _T_1799 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_82 node _T_1803 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1804 = or(UInt<1>(0h1), _T_1803) node _T_1805 = asUInt(reset) node _T_1806 = eq(_T_1805, UInt<1>(0h0)) when _T_1806 : node _T_1807 = eq(_T_1804, UInt<1>(0h0)) when _T_1807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1804, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1808 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1809 = asUInt(reset) node _T_1810 = eq(_T_1809, UInt<1>(0h0)) when _T_1810 : node _T_1811 = eq(_T_1808, UInt<1>(0h0)) when _T_1811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1808, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1812 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1813 = asUInt(reset) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) when _T_1814 : node _T_1815 = eq(_T_1812, UInt<1>(0h0)) when _T_1815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1812, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1816 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1817 = asUInt(reset) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(_T_1816, UInt<1>(0h0)) when _T_1819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1816, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1820 = eq(a_first, UInt<1>(0h0)) node _T_1821 = and(io.in.a.valid, _T_1820) when _T_1821 : node _T_1822 = eq(io.in.a.bits.opcode, opcode) node _T_1823 = asUInt(reset) node _T_1824 = eq(_T_1823, UInt<1>(0h0)) when _T_1824 : node _T_1825 = eq(_T_1822, UInt<1>(0h0)) when _T_1825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1822, UInt<1>(0h1), "") : assert_87 node _T_1826 = eq(io.in.a.bits.param, param) node _T_1827 = asUInt(reset) node _T_1828 = eq(_T_1827, UInt<1>(0h0)) when _T_1828 : node _T_1829 = eq(_T_1826, UInt<1>(0h0)) when _T_1829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1826, UInt<1>(0h1), "") : assert_88 node _T_1830 = eq(io.in.a.bits.size, size) node _T_1831 = asUInt(reset) node _T_1832 = eq(_T_1831, UInt<1>(0h0)) when _T_1832 : node _T_1833 = eq(_T_1830, UInt<1>(0h0)) when _T_1833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1830, UInt<1>(0h1), "") : assert_89 node _T_1834 = eq(io.in.a.bits.source, source) node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(_T_1834, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1834, UInt<1>(0h1), "") : assert_90 node _T_1838 = eq(io.in.a.bits.address, address) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_91 node _T_1842 = and(io.in.a.ready, io.in.a.valid) node _T_1843 = and(_T_1842, a_first) when _T_1843 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1844 = eq(d_first, UInt<1>(0h0)) node _T_1845 = and(io.in.d.valid, _T_1844) when _T_1845 : node _T_1846 = eq(io.in.d.bits.opcode, opcode_1) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_92 node _T_1850 = eq(io.in.d.bits.param, param_1) node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(_T_1850, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1850, UInt<1>(0h1), "") : assert_93 node _T_1854 = eq(io.in.d.bits.size, size_1) node _T_1855 = asUInt(reset) node _T_1856 = eq(_T_1855, UInt<1>(0h0)) when _T_1856 : node _T_1857 = eq(_T_1854, UInt<1>(0h0)) when _T_1857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1854, UInt<1>(0h1), "") : assert_94 node _T_1858 = eq(io.in.d.bits.source, source_1) node _T_1859 = asUInt(reset) node _T_1860 = eq(_T_1859, UInt<1>(0h0)) when _T_1860 : node _T_1861 = eq(_T_1858, UInt<1>(0h0)) when _T_1861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1858, UInt<1>(0h1), "") : assert_95 node _T_1862 = eq(io.in.d.bits.sink, sink) node _T_1863 = asUInt(reset) node _T_1864 = eq(_T_1863, UInt<1>(0h0)) when _T_1864 : node _T_1865 = eq(_T_1862, UInt<1>(0h0)) when _T_1865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1862, UInt<1>(0h1), "") : assert_96 node _T_1866 = eq(io.in.d.bits.denied, denied) node _T_1867 = asUInt(reset) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) when _T_1868 : node _T_1869 = eq(_T_1866, UInt<1>(0h0)) when _T_1869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1866, UInt<1>(0h1), "") : assert_97 node _T_1870 = and(io.in.d.ready, io.in.d.valid) node _T_1871 = and(_T_1870, d_first) when _T_1871 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<1032> connect a_sizes_set, UInt<1032>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1872 = and(io.in.a.valid, a_first_1) node _T_1873 = and(_T_1872, UInt<1>(0h1)) when _T_1873 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1874 = and(io.in.a.ready, io.in.a.valid) node _T_1875 = and(_T_1874, a_first_1) node _T_1876 = and(_T_1875, UInt<1>(0h1)) when _T_1876 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1877 = dshr(inflight, io.in.a.bits.source) node _T_1878 = bits(_T_1877, 0, 0) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<1032> connect d_sizes_clr, UInt<1032>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1883 = and(io.in.d.valid, d_first_1) node _T_1884 = and(_T_1883, UInt<1>(0h1)) node _T_1885 = eq(d_release_ack, UInt<1>(0h0)) node _T_1886 = and(_T_1884, _T_1885) when _T_1886 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1887 = and(io.in.d.ready, io.in.d.valid) node _T_1888 = and(_T_1887, d_first_1) node _T_1889 = and(_T_1888, UInt<1>(0h1)) node _T_1890 = eq(d_release_ack, UInt<1>(0h0)) node _T_1891 = and(_T_1889, _T_1890) when _T_1891 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1892 = and(io.in.d.valid, d_first_1) node _T_1893 = and(_T_1892, UInt<1>(0h1)) node _T_1894 = eq(d_release_ack, UInt<1>(0h0)) node _T_1895 = and(_T_1893, _T_1894) when _T_1895 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1896 = dshr(inflight, io.in.d.bits.source) node _T_1897 = bits(_T_1896, 0, 0) node _T_1898 = or(_T_1897, same_cycle_resp) node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(_T_1898, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1898, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1902 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1903 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1904 = or(_T_1902, _T_1903) node _T_1905 = asUInt(reset) node _T_1906 = eq(_T_1905, UInt<1>(0h0)) when _T_1906 : node _T_1907 = eq(_T_1904, UInt<1>(0h0)) when _T_1907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1904, UInt<1>(0h1), "") : assert_100 node _T_1908 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(_T_1908, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1908, UInt<1>(0h1), "") : assert_101 else : node _T_1912 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1913 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1914 = or(_T_1912, _T_1913) node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(_T_1914, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1914, UInt<1>(0h1), "") : assert_102 node _T_1918 = eq(io.in.d.bits.size, a_size_lookup) node _T_1919 = asUInt(reset) node _T_1920 = eq(_T_1919, UInt<1>(0h0)) when _T_1920 : node _T_1921 = eq(_T_1918, UInt<1>(0h0)) when _T_1921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1918, UInt<1>(0h1), "") : assert_103 node _T_1922 = and(io.in.d.valid, d_first_1) node _T_1923 = and(_T_1922, a_first_1) node _T_1924 = and(_T_1923, io.in.a.valid) node _T_1925 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1926 = and(_T_1924, _T_1925) node _T_1927 = eq(d_release_ack, UInt<1>(0h0)) node _T_1928 = and(_T_1926, _T_1927) when _T_1928 : node _T_1929 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1930 = or(_T_1929, io.in.a.ready) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_42 node _T_1934 = orr(inflight) node _T_1935 = eq(_T_1934, UInt<1>(0h0)) node _T_1936 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1937 = or(_T_1935, _T_1936) node _T_1938 = lt(watchdog, plusarg_reader.out) node _T_1939 = or(_T_1937, _T_1938) node _T_1940 = asUInt(reset) node _T_1941 = eq(_T_1940, UInt<1>(0h0)) when _T_1941 : node _T_1942 = eq(_T_1939, UInt<1>(0h0)) when _T_1942 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1939, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1943 = and(io.in.a.ready, io.in.a.valid) node _T_1944 = and(io.in.d.ready, io.in.d.valid) node _T_1945 = or(_T_1943, _T_1944) when _T_1945 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<1032> connect c_sizes_set, UInt<1032>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1946 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1947 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1948 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1949 = and(_T_1947, _T_1948) node _T_1950 = and(_T_1946, _T_1949) when _T_1950 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1951 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1952 = and(_T_1951, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1953 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1954 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1955 = and(_T_1953, _T_1954) node _T_1956 = and(_T_1952, _T_1955) when _T_1956 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1957 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1958 = bits(_T_1957, 0, 0) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) node _T_1960 = asUInt(reset) node _T_1961 = eq(_T_1960, UInt<1>(0h0)) when _T_1961 : node _T_1962 = eq(_T_1959, UInt<1>(0h0)) when _T_1962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1959, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<1032> connect d_sizes_clr_1, UInt<1032>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1963 = and(io.in.d.valid, d_first_2) node _T_1964 = and(_T_1963, UInt<1>(0h1)) node _T_1965 = and(_T_1964, d_release_ack_1) when _T_1965 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1966 = and(io.in.d.ready, io.in.d.valid) node _T_1967 = and(_T_1966, d_first_2) node _T_1968 = and(_T_1967, UInt<1>(0h1)) node _T_1969 = and(_T_1968, d_release_ack_1) when _T_1969 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1970 = and(io.in.d.valid, d_first_2) node _T_1971 = and(_T_1970, UInt<1>(0h1)) node _T_1972 = and(_T_1971, d_release_ack_1) when _T_1972 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1973 = dshr(inflight_1, io.in.d.bits.source) node _T_1974 = bits(_T_1973, 0, 0) node _T_1975 = or(_T_1974, same_cycle_resp_1) node _T_1976 = asUInt(reset) node _T_1977 = eq(_T_1976, UInt<1>(0h0)) when _T_1977 : node _T_1978 = eq(_T_1975, UInt<1>(0h0)) when _T_1978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1975, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1979 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1980 = asUInt(reset) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) when _T_1981 : node _T_1982 = eq(_T_1979, UInt<1>(0h0)) when _T_1982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1979, UInt<1>(0h1), "") : assert_108 else : node _T_1983 = eq(io.in.d.bits.size, c_size_lookup) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_109 node _T_1987 = and(io.in.d.valid, d_first_2) node _T_1988 = and(_T_1987, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1989 = and(_T_1988, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1990 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1991 = and(_T_1989, _T_1990) node _T_1992 = and(_T_1991, d_release_ack_1) node _T_1993 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1994 = and(_T_1992, _T_1993) when _T_1994 : node _T_1995 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1996 = or(_T_1995, _WIRE_27.ready) node _T_1997 = asUInt(reset) node _T_1998 = eq(_T_1997, UInt<1>(0h0)) when _T_1998 : node _T_1999 = eq(_T_1996, UInt<1>(0h0)) when _T_1999 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1996, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_43 node _T_2000 = orr(inflight_1) node _T_2001 = eq(_T_2000, UInt<1>(0h0)) node _T_2002 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2003 = or(_T_2001, _T_2002) node _T_2004 = lt(watchdog_1, plusarg_reader_1.out) node _T_2005 = or(_T_2003, _T_2004) node _T_2006 = asUInt(reset) node _T_2007 = eq(_T_2006, UInt<1>(0h0)) when _T_2007 : node _T_2008 = eq(_T_2005, UInt<1>(0h0)) when _T_2008 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2005, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2009 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2010 = and(io.in.d.ready, io.in.d.valid) node _T_2011 = or(_T_2009, _T_2010) when _T_2011 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_21( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 \| _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 \| _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 \| _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_63 \| _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31] wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_117 = _source_ok_T_116 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_118 = _source_ok_T_117 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_119 = _source_ok_T_118 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_120 = _source_ok_T_119 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_121 = _source_ok_T_120 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_122 = _source_ok_T_121 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_123 = _source_ok_T_122 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_124 = _source_ok_T_123 \| _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_125 = _source_ok_T_124 \| _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_126 = _source_ok_T_125 \| _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_127 = _source_ok_T_126 \| _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_127 \| _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _T_1943 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1943; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1943; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_2011 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2011; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2011; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2011; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1876 = _T_1943 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1876 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1876 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1876 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1876 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1876 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1922 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1922 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1891 = _T_2011 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1891 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1891 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1891 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1031:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1987 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1987 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1969 = _T_2011 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1969 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1969 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1969 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_522 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_522( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}} wire _in_flight_WIRE : UInt<1>[8] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_38 = and(_T_36, _T_37) node _T_39 = or(_T_17, _T_24) node _T_40 = or(_T_39, _T_31) node _T_41 = or(_T_40, _T_38) node _T_42 = or(_T_10, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 node _T_46 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_69 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_74 = and(_T_72, _T_73) node _T_75 = or(_T_53, _T_60) node _T_76 = or(_T_75, _T_67) node _T_77 = or(_T_76, _T_74) node _T_78 = or(_T_46, _T_77) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_89 = and(_T_87, _T_88) node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_105 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_110 = and(_T_108, _T_109) node _T_111 = or(_T_89, _T_96) node _T_112 = or(_T_111, _T_103) node _T_113 = or(_T_112, _T_110) node _T_114 = or(_T_82, _T_113) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_114, UInt<1>(0h1), "") : assert_4 node _T_118 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_119 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_120 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_121 = and(_T_119, _T_120) node _T_122 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_123 = and(_T_121, _T_122) node _T_124 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_125 = and(_T_123, _T_124) node _T_126 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_127 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_134 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_139 = and(_T_137, _T_138) node _T_140 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_141 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_142 = and(_T_140, _T_141) node _T_143 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_146 = and(_T_144, _T_145) node _T_147 = or(_T_125, _T_132) node _T_148 = or(_T_147, _T_139) node _T_149 = or(_T_148, _T_146) node _T_150 = or(_T_118, _T_149) node _T_151 = asUInt(reset) node _T_152 = eq(_T_151, UInt<1>(0h0)) when _T_152 : node _T_153 = eq(_T_150, UInt<1>(0h0)) when _T_153 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_150, UInt<1>(0h1), "") : assert_5 node _T_154 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_156 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_163 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_170 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_177 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_184 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_191 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_194 = and(_T_192, _T_193) node _T_195 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_196 = and(_T_194, _T_195) node _T_197 = or(_T_161, _T_168) node _T_198 = or(_T_197, _T_175) node _T_199 = or(_T_198, _T_182) node _T_200 = or(_T_199, _T_189) node _T_201 = or(_T_200, _T_196) node _T_202 = or(_T_154, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_202, UInt<1>(0h1), "") : assert_6 node _T_206 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_207 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_208 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_215 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_222 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_229 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_236 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_243 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_244 = and(_T_242, _T_243) node _T_245 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_248 = and(_T_246, _T_247) node _T_249 = or(_T_213, _T_220) node _T_250 = or(_T_249, _T_227) node _T_251 = or(_T_250, _T_234) node _T_252 = or(_T_251, _T_241) node _T_253 = or(_T_252, _T_248) node _T_254 = or(_T_206, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_254, UInt<1>(0h1), "") : assert_7 node _T_258 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_259 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_260 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_261 = and(_T_259, _T_260) node _T_262 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_263 = and(_T_261, _T_262) node _T_264 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_267 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_268 = and(_T_266, _T_267) node _T_269 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_272 = and(_T_270, _T_271) node _T_273 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_274 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_279 = and(_T_277, _T_278) node _T_280 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_281 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_282 = and(_T_280, _T_281) node _T_283 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_284 = and(_T_282, _T_283) node _T_285 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_286 = and(_T_284, _T_285) node _T_287 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_288 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _T_290 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_291 = and(_T_289, _T_290) node _T_292 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_295 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_300 = and(_T_298, _T_299) node _T_301 = or(_T_265, _T_272) node _T_302 = or(_T_301, _T_279) node _T_303 = or(_T_302, _T_286) node _T_304 = or(_T_303, _T_293) node _T_305 = or(_T_304, _T_300) node _T_306 = or(_T_258, _T_305) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_306, UInt<1>(0h1), "") : assert_8	module NoCMonitor_16( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module PE_290 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_34 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_290( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_34 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_429 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_429( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module LoopMatmulLdA : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { max_i : UInt<16>, max_k : UInt<16>, pad_i : UInt<2>, pad_k : UInt<2>, dram_addr : UInt<40>, dram_stride : UInt<40>, transpose : UInt<1>, addr_start : UInt<14>, loop_id : UInt<1>, is_resadd : UInt<1>}}, cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, i : UInt<16>, k : UInt<16>, idle : UInt<1>, flip rob_overloaded : UInt<1>, loop_id : UInt<1>} regreset state : UInt<1>, clock, reset, UInt<1>(0h0) reg req : { max_i : UInt<16>, max_k : UInt<16>, pad_i : UInt<2>, pad_k : UInt<2>, dram_addr : UInt<40>, dram_stride : UInt<40>, transpose : UInt<1>, addr_start : UInt<14>, loop_id : UInt<1>, is_resadd : UInt<1>}, clock reg i : UInt<16>, clock reg k : UInt<16>, clock node row_iterator = mux(req.transpose, k, i) node col_iterator = mux(req.transpose, i, k) node max_row_iterator = mux(req.transpose, req.max_k, req.max_i) node max_col_iterator = mux(req.transpose, req.max_i, req.max_k) node row_pad = mux(req.transpose, req.pad_k, req.pad_i) node col_pad = mux(req.transpose, req.pad_i, req.pad_k) node max_col_dim = mux(req.transpose, req.max_i, req.max_k) node _max_blocks_T = leq(max_col_dim, UInt<3>(0h4)) node max_blocks = mux(_max_blocks_T, max_col_dim, UInt<3>(0h4)) node _dram_offset_T = mul(row_iterator, req.dram_stride) node _dram_offset_T_1 = add(_dram_offset_T, col_iterator) node _dram_offset_T_2 = tail(_dram_offset_T_1, 1) node _dram_offset_T_3 = mul(_dram_offset_T_2, UInt<3>(0h4)) node dram_offset = mul(_dram_offset_T_3, UInt<3>(0h4)) node _dram_addr_T = and(dram_offset, UInt<32>(0hffffffff)) node _dram_addr_T_1 = add(req.dram_addr, _dram_addr_T) node dram_addr = tail(_dram_addr_T_1, 1) node _sp_addr_T = mul(row_iterator, max_col_iterator) node _sp_addr_T_1 = add(_sp_addr_T, col_iterator) node _sp_addr_T_2 = tail(_sp_addr_T_1, 1) node _sp_addr_T_3 = mul(_sp_addr_T_2, UInt<3>(0h4)) node _sp_addr_T_4 = add(req.addr_start, _sp_addr_T_3) node sp_addr = tail(_sp_addr_T_4, 1) node _blocks_T = add(col_iterator, max_blocks) node _blocks_T_1 = tail(_blocks_T, 1) node _blocks_T_2 = leq(_blocks_T_1, max_col_iterator) node _blocks_T_3 = sub(max_col_iterator, col_iterator) node _blocks_T_4 = tail(_blocks_T_3, 1) node blocks = mux(_blocks_T_2, max_blocks, _blocks_T_4) node _cols_T = mul(blocks, UInt<3>(0h4)) node _cols_T_1 = add(col_iterator, blocks) node _cols_T_2 = tail(_cols_T_1, 1) node _cols_T_3 = geq(_cols_T_2, max_col_iterator) node _cols_T_4 = mux(_cols_T_3, col_pad, UInt<1>(0h0)) node _cols_T_5 = sub(_cols_T, _cols_T_4) node cols = tail(_cols_T_5, 1) node _rows_T = sub(max_row_iterator, UInt<1>(0h1)) node _rows_T_1 = tail(_rows_T, 1) node _rows_T_2 = eq(row_iterator, _rows_T_1) node _rows_T_3 = mux(_rows_T_2, row_pad, UInt<1>(0h0)) node _rows_T_4 = sub(UInt<3>(0h4), _rows_T_3) node rows = tail(_rows_T_4, 1) wire mvin_cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} invalidate mvin_cmd.status.uie invalidate mvin_cmd.status.sie invalidate mvin_cmd.status.hie invalidate mvin_cmd.status.mie invalidate mvin_cmd.status.upie invalidate mvin_cmd.status.spie invalidate mvin_cmd.status.ube invalidate mvin_cmd.status.mpie invalidate mvin_cmd.status.spp invalidate mvin_cmd.status.vs invalidate mvin_cmd.status.mpp invalidate mvin_cmd.status.fs invalidate mvin_cmd.status.xs invalidate mvin_cmd.status.mprv invalidate mvin_cmd.status.sum invalidate mvin_cmd.status.mxr invalidate mvin_cmd.status.tvm invalidate mvin_cmd.status.tw invalidate mvin_cmd.status.tsr invalidate mvin_cmd.status.zero1 invalidate mvin_cmd.status.sd_rv32 invalidate mvin_cmd.status.uxl invalidate mvin_cmd.status.sxl invalidate mvin_cmd.status.sbe invalidate mvin_cmd.status.mbe invalidate mvin_cmd.status.gva invalidate mvin_cmd.status.mpv invalidate mvin_cmd.status.zero2 invalidate mvin_cmd.status.sd invalidate mvin_cmd.status.v invalidate mvin_cmd.status.prv invalidate mvin_cmd.status.dv invalidate mvin_cmd.status.dprv invalidate mvin_cmd.status.isa invalidate mvin_cmd.status.wfi invalidate mvin_cmd.status.cease invalidate mvin_cmd.status.debug invalidate mvin_cmd.rs2 invalidate mvin_cmd.rs1 invalidate mvin_cmd.inst.opcode invalidate mvin_cmd.inst.rd invalidate mvin_cmd.inst.xs2 invalidate mvin_cmd.inst.xs1 invalidate mvin_cmd.inst.xd invalidate mvin_cmd.inst.rs1 invalidate mvin_cmd.inst.rs2 invalidate mvin_cmd.inst.funct connect mvin_cmd.inst.funct, UInt<2>(0h2) connect mvin_cmd.rs1, dram_addr wire mvin_cmd_rs2 : { _spacer2 : UInt<13>, num_rows : UInt<3>, _spacer1 : UInt<11>, num_cols : UInt<5>, _spacer0 : UInt<0>, local_addr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}} invalidate mvin_cmd_rs2.local_addr.data invalidate mvin_cmd_rs2.local_addr.garbage_bit invalidate mvin_cmd_rs2.local_addr.garbage invalidate mvin_cmd_rs2.local_addr.norm_cmd invalidate mvin_cmd_rs2.local_addr.read_full_acc_row invalidate mvin_cmd_rs2.local_addr.accumulate invalidate mvin_cmd_rs2.local_addr.is_acc_addr invalidate mvin_cmd_rs2._spacer0 invalidate mvin_cmd_rs2.num_cols invalidate mvin_cmd_rs2._spacer1 invalidate mvin_cmd_rs2.num_rows invalidate mvin_cmd_rs2._spacer2 connect mvin_cmd_rs2.num_rows, rows connect mvin_cmd_rs2.num_cols, cols wire _mvin_cmd_rs2_local_addr_result_result_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _mvin_cmd_rs2_local_addr_result_result_WIRE_1 : UInt<32> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_1, sp_addr node _mvin_cmd_rs2_local_addr_result_result_T = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 13, 0) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.data, _mvin_cmd_rs2_local_addr_result_result_T node _mvin_cmd_rs2_local_addr_result_result_T_1 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 14, 14) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.garbage_bit, _mvin_cmd_rs2_local_addr_result_result_T_1 node _mvin_cmd_rs2_local_addr_result_result_T_2 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 25, 15) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.garbage, _mvin_cmd_rs2_local_addr_result_result_T_2 node _mvin_cmd_rs2_local_addr_result_result_T_3 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 28, 26) wire _mvin_cmd_rs2_local_addr_result_result_WIRE_2 : UInt<3> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_2, _mvin_cmd_rs2_local_addr_result_result_T_3 wire _mvin_cmd_rs2_local_addr_result_result_WIRE_3 : UInt<3> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_3, _mvin_cmd_rs2_local_addr_result_result_WIRE_2 connect _mvin_cmd_rs2_local_addr_result_result_WIRE.norm_cmd, _mvin_cmd_rs2_local_addr_result_result_WIRE_3 node _mvin_cmd_rs2_local_addr_result_result_T_4 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 29, 29) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.read_full_acc_row, _mvin_cmd_rs2_local_addr_result_result_T_4 node _mvin_cmd_rs2_local_addr_result_result_T_5 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 30, 30) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.accumulate, _mvin_cmd_rs2_local_addr_result_result_T_5 node _mvin_cmd_rs2_local_addr_result_result_T_6 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 31, 31) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.is_acc_addr, _mvin_cmd_rs2_local_addr_result_result_T_6 wire mvin_cmd_rs2_local_addr_result_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvin_cmd_rs2_local_addr_result_result, _mvin_cmd_rs2_local_addr_result_result_WIRE connect mvin_cmd_rs2_local_addr_result_result.garbage, UInt<1>(0h0) wire mvin_cmd_rs2_local_addr_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvin_cmd_rs2_local_addr_result, mvin_cmd_rs2_local_addr_result_result connect mvin_cmd_rs2_local_addr_result.is_acc_addr, UInt<1>(0h0) connect mvin_cmd_rs2_local_addr_result.accumulate, UInt<1>(0h0) connect mvin_cmd_rs2_local_addr_result.read_full_acc_row, UInt<1>(0h0) connect mvin_cmd_rs2.local_addr, mvin_cmd_rs2_local_addr_result node _mvin_cmd_rs2_T = asUInt(mvin_cmd_rs2.local_addr.norm_cmd) node mvin_cmd_rs2_lo_hi = cat(mvin_cmd_rs2.local_addr.garbage, mvin_cmd_rs2.local_addr.garbage_bit) node mvin_cmd_rs2_lo = cat(mvin_cmd_rs2_lo_hi, mvin_cmd_rs2.local_addr.data) node mvin_cmd_rs2_hi_lo = cat(mvin_cmd_rs2.local_addr.read_full_acc_row, _mvin_cmd_rs2_T) node mvin_cmd_rs2_hi_hi = cat(mvin_cmd_rs2.local_addr.is_acc_addr, mvin_cmd_rs2.local_addr.accumulate) node mvin_cmd_rs2_hi = cat(mvin_cmd_rs2_hi_hi, mvin_cmd_rs2_hi_lo) node _mvin_cmd_rs2_T_1 = cat(mvin_cmd_rs2_hi, mvin_cmd_rs2_lo) node mvin_cmd_rs2_lo_hi_1 = cat(mvin_cmd_rs2.num_cols, mvin_cmd_rs2._spacer0) node mvin_cmd_rs2_lo_1 = cat(mvin_cmd_rs2_lo_hi_1, _mvin_cmd_rs2_T_1) node mvin_cmd_rs2_hi_hi_1 = cat(mvin_cmd_rs2._spacer2, mvin_cmd_rs2.num_rows) node mvin_cmd_rs2_hi_1 = cat(mvin_cmd_rs2_hi_hi_1, mvin_cmd_rs2._spacer1) node _mvin_cmd_rs2_T_2 = cat(mvin_cmd_rs2_hi_1, mvin_cmd_rs2_lo_1) connect mvin_cmd.rs2, _mvin_cmd_rs2_T_2 when req.is_resadd : wire _mvin_cmd_rs2_local_addr_result_result_WIRE_4 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _mvin_cmd_rs2_local_addr_result_result_WIRE_5 : UInt<32> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_5, sp_addr node _mvin_cmd_rs2_local_addr_result_result_T_7 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 13, 0) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.data, _mvin_cmd_rs2_local_addr_result_result_T_7 node _mvin_cmd_rs2_local_addr_result_result_T_8 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 14, 14) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.garbage_bit, _mvin_cmd_rs2_local_addr_result_result_T_8 node _mvin_cmd_rs2_local_addr_result_result_T_9 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 25, 15) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.garbage, _mvin_cmd_rs2_local_addr_result_result_T_9 node _mvin_cmd_rs2_local_addr_result_result_T_10 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 28, 26) wire _mvin_cmd_rs2_local_addr_result_result_WIRE_6 : UInt<3> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_6, _mvin_cmd_rs2_local_addr_result_result_T_10 wire _mvin_cmd_rs2_local_addr_result_result_WIRE_7 : UInt<3> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_7, _mvin_cmd_rs2_local_addr_result_result_WIRE_6 connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.norm_cmd, _mvin_cmd_rs2_local_addr_result_result_WIRE_7 node _mvin_cmd_rs2_local_addr_result_result_T_11 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 29, 29) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.read_full_acc_row, _mvin_cmd_rs2_local_addr_result_result_T_11 node _mvin_cmd_rs2_local_addr_result_result_T_12 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 30, 30) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.accumulate, _mvin_cmd_rs2_local_addr_result_result_T_12 node _mvin_cmd_rs2_local_addr_result_result_T_13 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 31, 31) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.is_acc_addr, _mvin_cmd_rs2_local_addr_result_result_T_13 wire mvin_cmd_rs2_local_addr_result_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvin_cmd_rs2_local_addr_result_result_1, _mvin_cmd_rs2_local_addr_result_result_WIRE_4 connect mvin_cmd_rs2_local_addr_result_result_1.garbage, UInt<1>(0h0) wire mvin_cmd_rs2_local_addr_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvin_cmd_rs2_local_addr_result_1, mvin_cmd_rs2_local_addr_result_result_1 connect mvin_cmd_rs2_local_addr_result_1.is_acc_addr, UInt<1>(0h1) connect mvin_cmd_rs2_local_addr_result_1.accumulate, UInt<1>(0h0) connect mvin_cmd_rs2_local_addr_result_1.read_full_acc_row, UInt<1>(0h0) connect mvin_cmd_rs2.local_addr, mvin_cmd_rs2_local_addr_result_1 node _io_req_ready_T = eq(state, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T connect io.i, i connect io.k, k node _io_idle_T = eq(state, UInt<1>(0h0)) connect io.idle, _io_idle_T node _io_cmd_valid_T = neq(state, UInt<1>(0h0)) node _io_cmd_valid_T_1 = eq(io.rob_overloaded, UInt<1>(0h0)) node _io_cmd_valid_T_2 = and(_io_cmd_valid_T, _io_cmd_valid_T_1) node _io_cmd_valid_T_3 = neq(req.dram_addr, UInt<1>(0h0)) node _io_cmd_valid_T_4 = and(_io_cmd_valid_T_2, _io_cmd_valid_T_3) connect io.cmd.valid, _io_cmd_valid_T_4 connect io.cmd.bits, mvin_cmd connect io.loop_id, req.loop_id node _T = eq(req.dram_addr, UInt<1>(0h0)) when _T : connect state, UInt<1>(0h0) else : node _T_1 = and(io.cmd.ready, io.cmd.valid) when _T_1 : node i_blocks = mux(req.transpose, max_blocks, UInt<1>(0h1)) node k_blocks = mux(req.transpose, UInt<1>(0h1), max_blocks) node _next_i_max_T = sub(req.max_i, UInt<1>(0h1)) node next_i_max = tail(_next_i_max_T, 1) node _next_i_T = add(i, i_blocks) node _next_i_T_1 = tail(_next_i_T, 1) node _next_i_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _next_i_T_3 = add(i, i_blocks) node _next_i_T_4 = gt(_next_i_T_3, next_i_max) node _next_i_T_5 = mux(_next_i_T_4, UInt<1>(0h0), _next_i_T_1) node next_i = mux(_next_i_T_2, i, _next_i_T_5) node _next_k_T = eq(next_i, UInt<1>(0h0)) node _next_k_max_T = sub(req.max_k, UInt<1>(0h1)) node next_k_max = tail(_next_k_max_T, 1) node _next_k_T_1 = add(k, k_blocks) node _next_k_T_2 = tail(_next_k_T_1, 1) node _next_k_T_3 = eq(_next_k_T, UInt<1>(0h0)) node _next_k_T_4 = add(k, k_blocks) node _next_k_T_5 = gt(_next_k_T_4, next_k_max) node _next_k_T_6 = mux(_next_k_T_5, UInt<1>(0h0), _next_k_T_2) node next_k = mux(_next_k_T_3, k, _next_k_T_6) connect i, next_i connect k, next_k node _T_2 = eq(next_i, UInt<1>(0h0)) node _T_3 = eq(next_k, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect state, UInt<1>(0h0) node _T_5 = and(io.req.ready, io.req.valid) when _T_5 : connect req, io.req.bits connect state, UInt<1>(0h1) connect i, UInt<1>(0h0) connect k, UInt<1>(0h0)	module LoopMatmulLdA( // @[LoopMatmul.scala:28:7] input clock, // @[LoopMatmul.scala:28:7] input reset, // @[LoopMatmul.scala:28:7] output io_req_ready, // @[LoopMatmul.scala:31:14] input io_req_valid, // @[LoopMatmul.scala:31:14] input [15:0] io_req_bits_max_i, // @[LoopMatmul.scala:31:14] input [15:0] io_req_bits_max_k, // @[LoopMatmul.scala:31:14] input [1:0] io_req_bits_pad_i, // @[LoopMatmul.scala:31:14] input [1:0] io_req_bits_pad_k, // @[LoopMatmul.scala:31:14] input [39:0] io_req_bits_dram_addr, // @[LoopMatmul.scala:31:14] input [39:0] io_req_bits_dram_stride, // @[LoopMatmul.scala:31:14] input io_req_bits_transpose, // @[LoopMatmul.scala:31:14] input [13:0] io_req_bits_addr_start, // @[LoopMatmul.scala:31:14] input io_req_bits_loop_id, // @[LoopMatmul.scala:31:14] input io_req_bits_is_resadd, // @[LoopMatmul.scala:31:14] input io_cmd_ready, // @[LoopMatmul.scala:31:14] output io_cmd_valid, // @[LoopMatmul.scala:31:14] output [63:0] io_cmd_bits_rs1, // @[LoopMatmul.scala:31:14] output [63:0] io_cmd_bits_rs2, // @[LoopMatmul.scala:31:14] output [15:0] io_i, // @[LoopMatmul.scala:31:14] output [15:0] io_k, // @[LoopMatmul.scala:31:14] output io_idle, // @[LoopMatmul.scala:31:14] input io_rob_overloaded, // @[LoopMatmul.scala:31:14] output io_loop_id // @[LoopMatmul.scala:31:14] ); wire _mvin_cmd_rs2_local_addr_result_result_WIRE_4_is_acc_addr; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_4_accumulate; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_4_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_4_norm_cmd; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_4_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_4_data; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37] wire [4:0] mvin_cmd_rs2_num_cols; // @[LoopMatmul.scala:78:26] wire [2:0] mvin_cmd_rs2_local_addr_norm_cmd; // @[LoopMatmul.scala:78:26] wire io_req_valid_0 = io_req_valid; // @[LoopMatmul.scala:28:7] wire [15:0] io_req_bits_max_i_0 = io_req_bits_max_i; // @[LoopMatmul.scala:28:7] wire [15:0] io_req_bits_max_k_0 = io_req_bits_max_k; // @[LoopMatmul.scala:28:7] wire [1:0] io_req_bits_pad_i_0 = io_req_bits_pad_i; // @[LoopMatmul.scala:28:7] wire [1:0] io_req_bits_pad_k_0 = io_req_bits_pad_k; // @[LoopMatmul.scala:28:7] wire [39:0] io_req_bits_dram_addr_0 = io_req_bits_dram_addr; // @[LoopMatmul.scala:28:7] wire [39:0] io_req_bits_dram_stride_0 = io_req_bits_dram_stride; // @[LoopMatmul.scala:28:7] wire io_req_bits_transpose_0 = io_req_bits_transpose; // @[LoopMatmul.scala:28:7] wire [13:0] io_req_bits_addr_start_0 = io_req_bits_addr_start; // @[LoopMatmul.scala:28:7] wire io_req_bits_loop_id_0 = io_req_bits_loop_id; // @[LoopMatmul.scala:28:7] wire io_req_bits_is_resadd_0 = io_req_bits_is_resadd; // @[LoopMatmul.scala:28:7] wire io_cmd_ready_0 = io_cmd_ready; // @[LoopMatmul.scala:28:7] wire io_rob_overloaded_0 = io_rob_overloaded; // @[LoopMatmul.scala:28:7] wire [12:0] mvin_cmd_rs2__spacer2 = 13'h0; // @[LoopMatmul.scala:78:26] wire mvin_cmd_rs2_local_addr_result_1_is_acc_addr = 1'h1; // @[LocalAddr.scala:129:26] wire [10:0] mvin_cmd_rs2__spacer1 = 11'h0; // @[LoopMatmul.scala:78:26] wire [10:0] mvin_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopMatmul.scala:78:26] wire [10:0] mvin_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] mvin_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:116:26] wire [10:0] mvin_cmd_rs2_local_addr_result_result_1_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] mvin_cmd_rs2_local_addr_result_1_garbage = 11'h0; // @[LocalAddr.scala:129:26] wire [7:0] io_cmd_bits_status_zero1 = 8'h0; // @[LoopMatmul.scala:28:7] wire [7:0] mvin_cmd_status_zero1 = 8'h0; // @[LoopMatmul.scala:73:22] wire [22:0] io_cmd_bits_status_zero2 = 23'h0; // @[LoopMatmul.scala:28:7] wire [22:0] mvin_cmd_status_zero2 = 23'h0; // @[LoopMatmul.scala:73:22] wire [1:0] io_cmd_bits_status_dprv = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_prv = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_sxl = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_uxl = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_xs = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_fs = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_mpp = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_vs = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] mvin_cmd_status_dprv = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_prv = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_sxl = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_uxl = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_xs = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_fs = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_mpp = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_vs = 2'h0; // @[LoopMatmul.scala:73:22] wire [31:0] io_cmd_bits_status_isa = 32'h0; // @[LoopMatmul.scala:28:7] wire [31:0] mvin_cmd_status_isa = 32'h0; // @[LoopMatmul.scala:73:22] wire [6:0] io_cmd_bits_inst_opcode = 7'h0; // @[LoopMatmul.scala:28:7] wire [6:0] mvin_cmd_inst_opcode = 7'h0; // @[LoopMatmul.scala:73:22] wire io_cmd_bits_inst_xd = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_inst_xs1 = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_inst_xs2 = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_debug = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_cease = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_wfi = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_dv = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_v = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_sd = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mpv = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_gva = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mbe = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_sbe = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_tsr = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_tw = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_tvm = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mxr = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_sum = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mprv = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_spp = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mpie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_ube = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_spie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_upie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_hie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_sie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_uie = 1'h0; // @[LoopMatmul.scala:28:7] wire mvin_cmd_inst_xd = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_inst_xs1 = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_inst_xs2 = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_debug = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_cease = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_wfi = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_dv = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_v = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_sd = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mpv = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_gva = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mbe = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_sbe = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_tsr = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_tw = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_tvm = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mxr = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_sum = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mprv = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_spp = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mpie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_ube = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_spie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_upie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_hie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_sie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_uie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopMatmul.scala:78:26] wire mvin_cmd_rs2_local_addr_read_full_acc_row = 1'h0; // @[LoopMatmul.scala:78:26] wire mvin_cmd_rs2_local_addr_result_is_acc_addr = 1'h0; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_result_read_full_acc_row = 1'h0; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_result_1_accumulate = 1'h0; // @[LocalAddr.scala:129:26] wire mvin_cmd_rs2_local_addr_result_1_read_full_acc_row = 1'h0; // @[LocalAddr.scala:129:26] wire _next_i_T_2 = 1'h0; // @[Util.scala:42:8] wire [4:0] io_cmd_bits_inst_rs2 = 5'h0; // @[LoopMatmul.scala:28:7] wire [4:0] io_cmd_bits_inst_rs1 = 5'h0; // @[LoopMatmul.scala:28:7] wire [4:0] io_cmd_bits_inst_rd = 5'h0; // @[LoopMatmul.scala:28:7] wire [4:0] mvin_cmd_inst_rs2 = 5'h0; // @[LoopMatmul.scala:73:22] wire [4:0] mvin_cmd_inst_rs1 = 5'h0; // @[LoopMatmul.scala:73:22] wire [4:0] mvin_cmd_inst_rd = 5'h0; // @[LoopMatmul.scala:73:22] wire [6:0] io_cmd_bits_inst_funct = 7'h2; // @[LoopMatmul.scala:28:7] wire [6:0] mvin_cmd_inst_funct = 7'h2; // @[LoopMatmul.scala:73:22] wire _io_req_ready_T; // @[LoopMatmul.scala:88:25] wire _io_cmd_valid_T_4; // @[LoopMatmul.scala:93:56] wire [63:0] mvin_cmd_rs1; // @[LoopMatmul.scala:73:22] wire [63:0] mvin_cmd_rs2; // @[LoopMatmul.scala:73:22] wire _io_idle_T; // @[LoopMatmul.scala:91:20] wire io_req_ready_0; // @[LoopMatmul.scala:28:7] wire [63:0] io_cmd_bits_rs1_0; // @[LoopMatmul.scala:28:7] wire [63:0] io_cmd_bits_rs2_0; // @[LoopMatmul.scala:28:7] wire io_cmd_valid_0; // @[LoopMatmul.scala:28:7] wire [15:0] io_i_0; // @[LoopMatmul.scala:28:7] wire [15:0] io_k_0; // @[LoopMatmul.scala:28:7] wire io_idle_0; // @[LoopMatmul.scala:28:7] wire io_loop_id_0; // @[LoopMatmul.scala:28:7] reg state; // @[LoopMatmul.scala:45:22] wire _io_cmd_valid_T = state; // @[LoopMatmul.scala:45:22, :93:25] reg [15:0] req_max_i; // @[LoopMatmul.scala:47:16] reg [15:0] req_max_k; // @[LoopMatmul.scala:47:16] reg [1:0] req_pad_i; // @[LoopMatmul.scala:47:16] reg [1:0] req_pad_k; // @[LoopMatmul.scala:47:16] reg [39:0] req_dram_addr; // @[LoopMatmul.scala:47:16] reg [39:0] req_dram_stride; // @[LoopMatmul.scala:47:16] reg req_transpose; // @[LoopMatmul.scala:47:16] reg [13:0] req_addr_start; // @[LoopMatmul.scala:47:16] reg req_loop_id; // @[LoopMatmul.scala:47:16] assign io_loop_id_0 = req_loop_id; // @[LoopMatmul.scala:28:7, :47:16] reg req_is_resadd; // @[LoopMatmul.scala:47:16] wire mvin_cmd_rs2_local_addr_is_acc_addr = req_is_resadd; // @[LoopMatmul.scala:47:16, :78:26] reg [15:0] i; // @[LoopMatmul.scala:49:14] assign io_i_0 = i; // @[LoopMatmul.scala:28:7, :49:14] reg [15:0] k; // @[LoopMatmul.scala:50:14] assign io_k_0 = k; // @[LoopMatmul.scala:28:7, :50:14] wire [15:0] row_iterator = req_transpose ? k : i; // @[LoopMatmul.scala:47:16, :49:14, :50:14, :52:25] wire [15:0] col_iterator = req_transpose ? i : k; // @[LoopMatmul.scala:47:16, :49:14, :50:14, :53:25] wire [15:0] max_row_iterator = req_transpose ? req_max_k : req_max_i; // @[LoopMatmul.scala:47:16, :55:29] wire [15:0] _GEN = req_transpose ? req_max_i : req_max_k; // @[LoopMatmul.scala:47:16, :56:29] wire [15:0] max_col_iterator; // @[LoopMatmul.scala:56:29] assign max_col_iterator = _GEN; // @[LoopMatmul.scala:56:29] wire [15:0] max_col_dim; // @[LoopMatmul.scala:61:24] assign max_col_dim = _GEN; // @[LoopMatmul.scala:56:29, :61:24] wire [1:0] row_pad = req_transpose ? req_pad_k : req_pad_i; // @[LoopMatmul.scala:47:16, :58:20] wire [1:0] col_pad = req_transpose ? req_pad_i : req_pad_k; // @[LoopMatmul.scala:47:16, :59:20] wire _max_blocks_T = max_col_dim < 16'h5; // @[LoopMatmul.scala:61:24, :62:36] wire [15:0] max_blocks = _max_blocks_T ? max_col_dim : 16'h4; // @[LoopMatmul.scala:61:24, :62:{23,36}] wire [55:0] _dram_offset_T = {40'h0, row_iterator} * {16'h0, req_dram_stride}; // @[LoopMatmul.scala:47:16, :52:25, :66:35] wire [56:0] _dram_offset_T_1 = {1'h0, _dram_offset_T} + {41'h0, col_iterator}; // @[LoopMatmul.scala:53:25, :66:{35,53}] wire [55:0] _dram_offset_T_2 = _dram_offset_T_1[55:0]; // @[LoopMatmul.scala:66:53] wire [58:0] _dram_offset_T_3 = {1'h0, _dram_offset_T_2, 2'h0}; // @[LoopMatmul.scala:66:{53,69}] wire [61:0] dram_offset = {1'h0, _dram_offset_T_3, 2'h0}; // @[LoopMatmul.scala:66:{69,84}] wire [61:0] _dram_addr_T = {30'h0, dram_offset[31:0]}; // @[LoopMatmul.scala:66:84, :1139:17] wire [62:0] _dram_addr_T_1 = {23'h0, req_dram_addr} + {1'h0, _dram_addr_T}; // @[LoopMatmul.scala:47:16, :67:33, :1139:17] wire [61:0] dram_addr = _dram_addr_T_1[61:0]; // @[LoopMatmul.scala:67:33] wire [31:0] _sp_addr_T = {16'h0, row_iterator} * {16'h0, max_col_iterator}; // @[LoopMatmul.scala:52:25, :56:29, :68:47] wire [32:0] _sp_addr_T_1 = {1'h0, _sp_addr_T} + {17'h0, col_iterator}; // @[LoopMatmul.scala:53:25, :68:{47,66}] wire [31:0] _sp_addr_T_2 = _sp_addr_T_1[31:0]; // @[LoopMatmul.scala:68:66] wire [34:0] _sp_addr_T_3 = {1'h0, _sp_addr_T_2, 2'h0}; // @[LoopMatmul.scala:68:{66,82}] wire [35:0] _sp_addr_T_4 = {22'h0, req_addr_start} + {1'h0, _sp_addr_T_3}; // @[LoopMatmul.scala:47:16, :68:{31,82}] wire [34:0] sp_addr = _sp_addr_T_4[34:0]; // @[LoopMatmul.scala:68:31] wire [16:0] _GEN_0 = {1'h0, col_iterator}; // @[LoopMatmul.scala:53:25, :69:33] wire [16:0] _blocks_T = _GEN_0 + {1'h0, max_blocks}; // @[LoopMatmul.scala:62:23, :69:33] wire [15:0] _blocks_T_1 = _blocks_T[15:0]; // @[LoopMatmul.scala:69:33] wire _blocks_T_2 = _blocks_T_1 <= max_col_iterator; // @[LoopMatmul.scala:56:29, :69:{33,46}] wire [16:0] _blocks_T_3 = {1'h0, max_col_iterator} - _GEN_0; // @[LoopMatmul.scala:56:29, :69:{33,95}] wire [15:0] _blocks_T_4 = _blocks_T_3[15:0]; // @[LoopMatmul.scala:69:95] wire [15:0] blocks = _blocks_T_2 ? max_blocks : _blocks_T_4; // @[LoopMatmul.scala:62:23, :69:{19,46,95}] wire [18:0] _cols_T = {1'h0, blocks, 2'h0}; // @[LoopMatmul.scala:69:19, :70:22] wire [16:0] _cols_T_1 = _GEN_0 + {1'h0, blocks}; // @[LoopMatmul.scala:69:{19,33}, :70:57] wire [15:0] _cols_T_2 = _cols_T_1[15:0]; // @[LoopMatmul.scala:70:57] wire _cols_T_3 = _cols_T_2 >= max_col_iterator; // @[LoopMatmul.scala:56:29, :70:{57,66}] wire [1:0] _cols_T_4 = _cols_T_3 ? col_pad : 2'h0; // @[LoopMatmul.scala:59:20, :70:{43,66}] wire [19:0] _cols_T_5 = {1'h0, _cols_T} - {18'h0, _cols_T_4}; // @[LoopMatmul.scala:70:{22,38,43}] wire [18:0] cols = _cols_T_5[18:0]; // @[LoopMatmul.scala:70:38] wire [16:0] _rows_T = {1'h0, max_row_iterator} - 17'h1; // @[LoopMatmul.scala:55:29, :71:66] wire [15:0] _rows_T_1 = _rows_T[15:0]; // @[LoopMatmul.scala:71:66] wire _rows_T_2 = row_iterator == _rows_T_1; // @[LoopMatmul.scala:52:25, :71:{46,66}] wire [1:0] _rows_T_3 = _rows_T_2 ? row_pad : 2'h0; // @[LoopMatmul.scala:58:20, :71:{32,46}] wire [3:0] _rows_T_4 = 4'h4 - {2'h0, _rows_T_3}; // @[LoopMatmul.scala:71:{27,32}] wire [2:0] rows = _rows_T_4[2:0]; // @[LoopMatmul.scala:71:27] wire [2:0] mvin_cmd_rs2_num_rows = rows; // @[LoopMatmul.scala:71:27, :78:26] assign io_cmd_bits_rs1_0 = mvin_cmd_rs1; // @[LoopMatmul.scala:28:7, :73:22] wire [63:0] _mvin_cmd_rs2_T_2; // @[LoopMatmul.scala:83:32] assign io_cmd_bits_rs2_0 = mvin_cmd_rs2; // @[LoopMatmul.scala:28:7, :73:22] assign mvin_cmd_rs1 = {2'h0, dram_addr}; // @[LoopMatmul.scala:67:33, :73:22, :76:16] wire [4:0] mvin_cmd_rs2_lo_hi_1 = mvin_cmd_rs2_num_cols; // @[LoopMatmul.scala:78:26, :83:32] wire [2:0] _mvin_cmd_rs2_T = mvin_cmd_rs2_local_addr_norm_cmd; // @[LoopMatmul.scala:78:26, :83:32] wire mvin_cmd_rs2_local_addr_garbage_bit; // @[LoopMatmul.scala:78:26] wire [13:0] mvin_cmd_rs2_local_addr_data; // @[LoopMatmul.scala:78:26] assign mvin_cmd_rs2_num_cols = cols[4:0]; // @[LoopMatmul.scala:70:38, :78:26, :81:25] wire _mvin_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_accumulate = _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] mvin_cmd_rs2_local_addr_result_result_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] mvin_cmd_rs2_local_addr_result_result_data = _mvin_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}] wire [31:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_1 = sp_addr[31:0]; // @[LoopMatmul.scala:68:31] wire [31:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_5 = sp_addr[31:0]; // @[LoopMatmul.scala:68:31] assign _mvin_cmd_rs2_local_addr_result_result_T = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_data = _mvin_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_1 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_2 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage = _mvin_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_T_3 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_2 = _mvin_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_3 = _mvin_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_4 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_5 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate = _mvin_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_6 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire [2:0] mvin_cmd_rs2_local_addr_result_norm_cmd = mvin_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :116:26] wire mvin_cmd_rs2_local_addr_result_garbage_bit = mvin_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :116:26] wire [13:0] mvin_cmd_rs2_local_addr_result_data = mvin_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :116:26] wire [11:0] mvin_cmd_rs2_lo_hi = {11'h0, mvin_cmd_rs2_local_addr_garbage_bit}; // @[LoopMatmul.scala:78:26, :83:32] wire [25:0] mvin_cmd_rs2_lo = {mvin_cmd_rs2_lo_hi, mvin_cmd_rs2_local_addr_data}; // @[LoopMatmul.scala:78:26, :83:32] wire [3:0] mvin_cmd_rs2_hi_lo = {1'h0, _mvin_cmd_rs2_T}; // @[LoopMatmul.scala:83:32] wire [1:0] mvin_cmd_rs2_hi_hi = {mvin_cmd_rs2_local_addr_is_acc_addr, 1'h0}; // @[LoopMatmul.scala:78:26, :83:32] wire [5:0] mvin_cmd_rs2_hi = {mvin_cmd_rs2_hi_hi, mvin_cmd_rs2_hi_lo}; // @[LoopMatmul.scala:83:32] wire [31:0] _mvin_cmd_rs2_T_1 = {mvin_cmd_rs2_hi, mvin_cmd_rs2_lo}; // @[LoopMatmul.scala:83:32] wire [36:0] mvin_cmd_rs2_lo_1 = {mvin_cmd_rs2_lo_hi_1, _mvin_cmd_rs2_T_1}; // @[LoopMatmul.scala:83:32] wire [15:0] mvin_cmd_rs2_hi_hi_1 = {13'h0, mvin_cmd_rs2_num_rows}; // @[LoopMatmul.scala:78:26, :83:32] wire [26:0] mvin_cmd_rs2_hi_1 = {mvin_cmd_rs2_hi_hi_1, 11'h0}; // @[LoopMatmul.scala:83:32] assign _mvin_cmd_rs2_T_2 = {mvin_cmd_rs2_hi_1, mvin_cmd_rs2_lo_1}; // @[LoopMatmul.scala:83:32] assign mvin_cmd_rs2 = _mvin_cmd_rs2_T_2; // @[LoopMatmul.scala:73:22, :83:32] wire _mvin_cmd_rs2_local_addr_result_result_T_13; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_T_12; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_1_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_11; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_1_accumulate = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_7; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_1_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_T_9; // @[LocalAddr.scala:108:37] wire [2:0] mvin_cmd_rs2_local_addr_result_result_1_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_8; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_T_7; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_1_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] mvin_cmd_rs2_local_addr_result_result_1_data = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_data; // @[LocalAddr.scala:108:{26,37}] assign _mvin_cmd_rs2_local_addr_result_result_T_7 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[13:0]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_data = _mvin_cmd_rs2_local_addr_result_result_T_7; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_8 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[14]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_T_8; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_9 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_4_garbage = _mvin_cmd_rs2_local_addr_result_result_T_9; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_T_10 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_6 = _mvin_cmd_rs2_local_addr_result_result_T_10; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_7 = _mvin_cmd_rs2_local_addr_result_result_WIRE_6; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_7; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_11 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[29]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_T_11; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_12 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[30]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_accumulate = _mvin_cmd_rs2_local_addr_result_result_T_12; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_13 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[31]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_T_13; // @[LocalAddr.scala:108:37] wire [2:0] mvin_cmd_rs2_local_addr_result_1_norm_cmd = mvin_cmd_rs2_local_addr_result_result_1_norm_cmd; // @[LocalAddr.scala:108:26, :129:26] wire mvin_cmd_rs2_local_addr_result_1_garbage_bit = mvin_cmd_rs2_local_addr_result_result_1_garbage_bit; // @[LocalAddr.scala:108:26, :129:26] wire [13:0] mvin_cmd_rs2_local_addr_result_1_data = mvin_cmd_rs2_local_addr_result_result_1_data; // @[LocalAddr.scala:108:26, :129:26] assign mvin_cmd_rs2_local_addr_norm_cmd = req_is_resadd ? mvin_cmd_rs2_local_addr_result_1_norm_cmd : mvin_cmd_rs2_local_addr_result_norm_cmd; // @[LoopMatmul.scala:47:16, :78:26, :82:27, :84:22, :85:29] assign mvin_cmd_rs2_local_addr_garbage_bit = req_is_resadd ? mvin_cmd_rs2_local_addr_result_1_garbage_bit : mvin_cmd_rs2_local_addr_result_garbage_bit; // @[LoopMatmul.scala:47:16, :78:26, :82:27, :84:22, :85:29] assign mvin_cmd_rs2_local_addr_data = req_is_resadd ? mvin_cmd_rs2_local_addr_result_1_data : mvin_cmd_rs2_local_addr_result_data; // @[LoopMatmul.scala:47:16, :78:26, :82:27, :84:22, :85:29] assign _io_req_ready_T = ~state; // @[LoopMatmul.scala:45:22, :88:25] assign io_req_ready_0 = _io_req_ready_T; // @[LoopMatmul.scala:28:7, :88:25] assign _io_idle_T = ~state; // @[LoopMatmul.scala:45:22, :88:25, :91:20] assign io_idle_0 = _io_idle_T; // @[LoopMatmul.scala:28:7, :91:20] wire _io_cmd_valid_T_1 = ~io_rob_overloaded_0; // @[LoopMatmul.scala:28:7, :93:37] wire _io_cmd_valid_T_2 = _io_cmd_valid_T & _io_cmd_valid_T_1; // @[LoopMatmul.scala:93:{25,34,37}] wire _io_cmd_valid_T_3 = \|req_dram_addr; // @[LoopMatmul.scala:47:16, :93:73] assign _io_cmd_valid_T_4 = _io_cmd_valid_T_2 & _io_cmd_valid_T_3; // @[LoopMatmul.scala:93:{34,56,73}] assign io_cmd_valid_0 = _io_cmd_valid_T_4; // @[LoopMatmul.scala:28:7, :93:56] wire [15:0] i_blocks = req_transpose ? max_blocks : 16'h1; // @[LoopMatmul.scala:47:16, :62:23, :102:23] wire [15:0] k_blocks = req_transpose ? 16'h1 : max_blocks; // @[LoopMatmul.scala:47:16, :62:23, :103:23] wire [16:0] _next_i_max_T = {1'h0, req_max_i} - 17'h1; // @[Util.scala:39:28] wire [15:0] next_i_max = _next_i_max_T[15:0]; // @[Util.scala:39:28] wire [16:0] _GEN_1 = {1'h0, i} + {1'h0, i_blocks}; // @[Util.scala:41:15] wire [16:0] _next_i_T; // @[Util.scala:41:15] assign _next_i_T = _GEN_1; // @[Util.scala:41:15] wire [16:0] _next_i_T_3; // @[Util.scala:43:11] assign _next_i_T_3 = _GEN_1; // @[Util.scala:41:15, :43:11] wire [15:0] _next_i_T_1 = _next_i_T[15:0]; // @[Util.scala:41:15] wire _next_i_T_4 = _next_i_T_3 > {1'h0, next_i_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_i_T_5 = _next_i_T_4 ? 16'h0 : _next_i_T_1; // @[Mux.scala:126:16] wire [15:0] next_i = _next_i_T_5; // @[Mux.scala:126:16] wire _next_k_T = next_i == 16'h0; // @[Mux.scala:126:16] wire [16:0] _next_k_max_T = {1'h0, req_max_k} - 17'h1; // @[Util.scala:39:28] wire [15:0] next_k_max = _next_k_max_T[15:0]; // @[Util.scala:39:28] wire [16:0] _GEN_2 = {1'h0, k} + {1'h0, k_blocks}; // @[Util.scala:41:15] wire [16:0] _next_k_T_1; // @[Util.scala:41:15] assign _next_k_T_1 = _GEN_2; // @[Util.scala:41:15] wire [16:0] _next_k_T_4; // @[Util.scala:43:11] assign _next_k_T_4 = _GEN_2; // @[Util.scala:41:15, :43:11] wire [15:0] _next_k_T_2 = _next_k_T_1[15:0]; // @[Util.scala:41:15] wire _next_k_T_3 = ~_next_k_T; // @[Util.scala:42:8] wire _next_k_T_5 = _next_k_T_4 > {1'h0, next_k_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_k_T_6 = _next_k_T_5 ? 16'h0 : _next_k_T_2; // @[Mux.scala:126:16] wire [15:0] next_k = _next_k_T_3 ? k : _next_k_T_6; // @[Mux.scala:126:16] wire _T_1 = io_cmd_ready_0 & io_cmd_valid_0; // @[Decoupled.scala:51:35] wire _T_5 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[LoopMatmul.scala:28:7] if (reset) // @[LoopMatmul.scala:28:7] state <= 1'h0; // @[LoopMatmul.scala:45:22] else // @[LoopMatmul.scala:28:7] state <= _T_5 \| ~(~(\|req_dram_addr) \| _T_1 & _next_k_T & next_k == 16'h0) & state; // @[Mux.scala:126:16] if (_T_5) begin // @[Decoupled.scala:51:35] req_max_i <= io_req_bits_max_i_0; // @[LoopMatmul.scala:28:7, :47:16] req_max_k <= io_req_bits_max_k_0; // @[LoopMatmul.scala:28:7, :47:16] req_pad_i <= io_req_bits_pad_i_0; // @[LoopMatmul.scala:28:7, :47:16] req_pad_k <= io_req_bits_pad_k_0; // @[LoopMatmul.scala:28:7, :47:16] req_dram_addr <= io_req_bits_dram_addr_0; // @[LoopMatmul.scala:28:7, :47:16] req_dram_stride <= io_req_bits_dram_stride_0; // @[LoopMatmul.scala:28:7, :47:16] req_transpose <= io_req_bits_transpose_0; // @[LoopMatmul.scala:28:7, :47:16] req_addr_start <= io_req_bits_addr_start_0; // @[LoopMatmul.scala:28:7, :47:16] req_loop_id <= io_req_bits_loop_id_0; // @[LoopMatmul.scala:28:7, :47:16] req_is_resadd <= io_req_bits_is_resadd_0; // @[LoopMatmul.scala:28:7, :47:16] i <= 16'h0; // @[LoopMatmul.scala:49:14] k <= 16'h0; // @[LoopMatmul.scala:50:14] end else if ((\|req_dram_addr) & _T_1) begin // @[Decoupled.scala:51:35] i <= next_i; // @[Mux.scala:126:16] k <= next_k; // @[Mux.scala:126:16] end always @(posedge) assign io_req_ready = io_req_ready_0; // @[LoopMatmul.scala:28:7] assign io_cmd_valid = io_cmd_valid_0; // @[LoopMatmul.scala:28:7] assign io_cmd_bits_rs1 = io_cmd_bits_rs1_0; // @[LoopMatmul.scala:28:7] assign io_cmd_bits_rs2 = io_cmd_bits_rs2_0; // @[LoopMatmul.scala:28:7] assign io_i = io_i_0; // @[LoopMatmul.scala:28:7] assign io_k = io_k_0; // @[LoopMatmul.scala:28:7] assign io_idle = io_idle_0; // @[LoopMatmul.scala:28:7] assign io_loop_id = io_loop_id_0; // @[LoopMatmul.scala:28:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<7>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<7>(0h40)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<7>(0h40)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<7>(0h40)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_5( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 7'h40; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 7'h40; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_54 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_54( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCManagerControl_1 : input clock : Clock input reset : Reset output auto : { flip ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip mgr_busy : UInt<1>, flip rocc_busy : UInt<1>} wire ctrlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate ctrlNodeIn.d.bits.corrupt invalidate ctrlNodeIn.d.bits.data invalidate ctrlNodeIn.d.bits.denied invalidate ctrlNodeIn.d.bits.sink invalidate ctrlNodeIn.d.bits.source invalidate ctrlNodeIn.d.bits.size invalidate ctrlNodeIn.d.bits.param invalidate ctrlNodeIn.d.bits.opcode invalidate ctrlNodeIn.d.valid invalidate ctrlNodeIn.d.ready invalidate ctrlNodeIn.a.bits.corrupt invalidate ctrlNodeIn.a.bits.data invalidate ctrlNodeIn.a.bits.mask invalidate ctrlNodeIn.a.bits.address invalidate ctrlNodeIn.a.bits.source invalidate ctrlNodeIn.a.bits.size invalidate ctrlNodeIn.a.bits.param invalidate ctrlNodeIn.a.bits.opcode invalidate ctrlNodeIn.a.valid invalidate ctrlNodeIn.a.ready inst monitor of TLMonitor_78 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, ctrlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, ctrlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, ctrlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, ctrlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, ctrlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, ctrlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, ctrlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, ctrlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, ctrlNodeIn.d.valid connect monitor.io.in.d.ready, ctrlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, ctrlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, ctrlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, ctrlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, ctrlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, ctrlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, ctrlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, ctrlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, ctrlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, ctrlNodeIn.a.valid connect monitor.io.in.a.ready, ctrlNodeIn.a.ready connect ctrlNodeIn, auto.ctrl_in wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}} node _in_bits_read_T = eq(ctrlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(ctrlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, ctrlNodeIn.a.bits.data connect in.bits.mask, ctrlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, ctrlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, ctrlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}} connect out_front.bits, in.bits inst out_back_front_q of Queue1_RegMapperInput_i9_m8_2 connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front node out_maskMatch = not(UInt<9>(0h1)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[2] wire out_wivalid : UInt<1>[2] wire out_roready : UInt<1>[2] wire out_woready : UInt<1>[2] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_4 = bits(out_back_front_q.io.deq.bits.data, 7, 0) node _out_T_5 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_6 = and(UInt<1>(0h1), out_f_roready) node _out_T_7 = eq(out_rimask, UInt<1>(0h0)) node _out_T_8 = eq(out_wimask, UInt<1>(0h0)) node _out_T_9 = eq(out_romask, UInt<1>(0h0)) node _out_T_10 = eq(out_womask, UInt<1>(0h0)) node _out_T_11 = or(io.mgr_busy, UInt<8>(0h0)) node _out_T_12 = bits(_out_T_11, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 7, 0) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 7, 0) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 7, 0) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 7, 0) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_13 = bits(out_back_front_q.io.deq.bits.data, 7, 0) node _out_T_14 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_15 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_16 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_17 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_18 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_19 = eq(out_womask_1, UInt<1>(0h0)) node _out_T_20 = or(io.rocc_busy, UInt<8>(0h0)) node _out_T_21 = bits(_out_T_20, 7, 0) node out_iindex = bits(out_front.bits.index, 0, 0) node _out_iindex_T = bits(out_front.bits.index, 1, 1) node _out_iindex_T_1 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_2 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_3 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_4 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_5 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_6 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_7 = bits(out_front.bits.index, 8, 8) node out_oindex = bits(out_back_front_q.io.deq.bits.index, 0, 0) node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 1, 1) node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 2, 2) node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 3, 3) node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 4, 4) node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 5, 5) node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 6, 6) node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 7, 7) node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 8, 8) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) node _out_rifireMux_T_10 = geq(out_iindex, UInt<2>(0h2)) wire _out_rifireMux_WIRE : UInt<1>[2] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 node out_rifireMux = mux(_out_rifireMux_T_10, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) node _out_wifireMux_T_11 = geq(out_iindex, UInt<2>(0h2)) wire _out_wifireMux_WIRE : UInt<1>[2] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 node out_wifireMux = mux(_out_wifireMux_T_11, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) node _out_rofireMux_T_10 = geq(out_oindex, UInt<2>(0h2)) wire _out_rofireMux_WIRE : UInt<1>[2] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 node out_rofireMux = mux(_out_rofireMux_T_10, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) node _out_wofireMux_T_11 = geq(out_oindex, UInt<2>(0h2)) wire _out_wofireMux_WIRE : UInt<1>[2] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 node out_wofireMux = mux(_out_wofireMux_T_11, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_back_front_q.io.deq.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE : UInt<1>[2] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE_1 : UInt<8>[2] connect _out_out_bits_data_WIRE_1[0], _out_T_12 connect _out_out_bits_data_WIRE_1[1], _out_T_21 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_back_front_q.io.deq.bits.extra connect in.valid, ctrlNodeIn.a.valid connect ctrlNodeIn.a.ready, in.ready connect ctrlNodeIn.d.valid, out.valid connect out.ready, ctrlNodeIn.d.ready wire ctrlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect ctrlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect ctrlNodeIn_d_bits_d.param, UInt<1>(0h0) connect ctrlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect ctrlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect ctrlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect ctrlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate ctrlNodeIn_d_bits_d.data connect ctrlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect ctrlNodeIn.d.bits.corrupt, ctrlNodeIn_d_bits_d.corrupt connect ctrlNodeIn.d.bits.data, ctrlNodeIn_d_bits_d.data connect ctrlNodeIn.d.bits.denied, ctrlNodeIn_d_bits_d.denied connect ctrlNodeIn.d.bits.sink, ctrlNodeIn_d_bits_d.sink connect ctrlNodeIn.d.bits.source, ctrlNodeIn_d_bits_d.source connect ctrlNodeIn.d.bits.size, ctrlNodeIn_d_bits_d.size connect ctrlNodeIn.d.bits.param, ctrlNodeIn_d_bits_d.param connect ctrlNodeIn.d.bits.opcode, ctrlNodeIn_d_bits_d.opcode connect ctrlNodeIn.d.bits.data, out.bits.data node _ctrlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect ctrlNodeIn.d.bits.opcode, _ctrlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module ReRoCCManagerControl_1( // @[Control.scala:49:9] input clock, // @[Control.scala:49:9] input reset, // @[Control.scala:49:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_mgr_busy, // @[Control.scala:50:16] input io_rocc_busy // @[Control.scala:50:16] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [6:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:49:9] wire [6:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:49:9] wire [11:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:49:9] wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:49:9] wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:49:9] wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:49:9] wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:49:9] wire io_mgr_busy_0 = io_mgr_busy; // @[Control.scala:49:9] wire io_rocc_busy_0 = io_rocc_busy; // @[Control.scala:49:9] wire [8:0] out_maskMatch = 9'h1FE; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] ctrlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] ctrlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:49:9] wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:49:9] wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:49:9] wire ctrlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire ctrlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire ctrlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_10 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_11 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_10 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_11 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire ctrlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire ctrlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire ctrlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:49:9] wire ctrlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] ctrlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] ctrlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire ctrlNodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:49:9] wire [6:0] ctrlNodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:49:9] wire [11:0] ctrlNodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:49:9] wire [7:0] ctrlNodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:49:9] wire [63:0] ctrlNodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:49:9] wire ctrlNodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:49:9] wire ctrlNodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:49:9] wire ctrlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] ctrlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] ctrlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] ctrlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] ctrlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_ctrl_in_a_ready_0; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:49:9] wire [6:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:49:9] wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:49:9] wire auto_ctrl_in_d_valid_0; // @[Control.scala:49:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_ctrl_in_a_ready_0 = ctrlNodeIn_a_ready; // @[Control.scala:49:9] wire in_valid = ctrlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [2:0] in_bits_extra_tlrr_extra_size = ctrlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [6:0] in_bits_extra_tlrr_extra_source = ctrlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = ctrlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = ctrlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = ctrlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_valid_0 = ctrlNodeIn_d_valid; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_opcode_0 = ctrlNodeIn_d_bits_opcode; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_size_0 = ctrlNodeIn_d_bits_size; // @[Control.scala:49:9] wire [6:0] ctrlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_source_0 = ctrlNodeIn_d_bits_source; // @[Control.scala:49:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_bits_data_0 = ctrlNodeIn_d_bits_data; // @[Control.scala:49:9] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] _in_bits_index_T; // @[Edges.scala:192:34] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [2:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = ctrlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T = ctrlNodeIn_a_bits_address[11:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T; // @[RegisterRouter.scala:73:18] wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _ctrlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign ctrlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [2:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index & 9'h1FE; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1FE; // @[RegisterRouter.scala:87:24] wire _GEN = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_13 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_7 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11 = {7'h0, io_mgr_busy_0}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12 = _out_T_11; // @[RegisterRouter.scala:87:24] wire [7:0] _out_out_bits_data_WIRE_1_0 = _out_T_12; // @[MuxLiteral.scala:49:48] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_14 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_15 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_16 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_20 = {7'h0, io_rocc_busy_0}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_21 = _out_T_20; // @[RegisterRouter.scala:87:24] wire [7:0] _out_out_bits_data_WIRE_1_1 = _out_T_21; // @[MuxLiteral.scala:49:48] wire out_iindex = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire out_oindex = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_frontSel_T = 2'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire _GEN_1 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _GEN_2 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = out_oindex ? _out_out_bits_data_WIRE_1 : _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire [7:0] _out_out_bits_data_T_3 = out_oindex ? _out_out_bits_data_WIRE_1_1 : _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] wire [7:0] _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 8'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = {56'h0, _out_out_bits_data_T_4}; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_bits_size = ctrlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign ctrlNodeIn_d_bits_source = ctrlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign ctrlNodeIn_d_bits_opcode = {2'h0, _ctrlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_78 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (ctrlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (ctrlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (ctrlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (ctrlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (ctrlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (ctrlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (ctrlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (ctrlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (ctrlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (ctrlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (ctrlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (ctrlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (ctrlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (ctrlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (ctrlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (ctrlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_RegMapperInput_i9_m8_2 out_back_front_q ( // @[RegisterRouter.scala:87:24] .clock (clock), .reset (reset), .io_enq_ready (out_front_ready), .io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24] .io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24] .io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24] .io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24] .io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24] .io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24] .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source), .io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size) ); // @[RegisterRouter.scala:87:24] assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:49:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_253 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_270 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_253( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_270 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) wire _source_ok_WIRE : UInt<1>[5] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 node _source_ok_T_25 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_26 = or(_source_ok_T_25, _source_ok_WIRE[2]) node _source_ok_T_27 = or(_source_ok_T_26, _source_ok_WIRE[3]) node source_ok = or(_source_ok_T_27, _source_ok_WIRE[4]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = and(_T_11, _T_24) node _T_65 = and(_T_64, _T_37) node _T_66 = and(_T_65, _T_50) node _T_67 = and(_T_66, _T_63) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_67, UInt<1>(0h1), "") : assert_1 node _T_71 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_71 : node _T_72 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_73 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_76 = shr(io.in.a.bits.source, 2) node _T_77 = eq(_T_76, UInt<1>(0h0)) node _T_78 = leq(UInt<1>(0h0), uncommonBits_4) node _T_79 = and(_T_77, _T_78) node _T_80 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_81 = and(_T_79, _T_80) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_82 = shr(io.in.a.bits.source, 2) node _T_83 = eq(_T_82, UInt<1>(0h1)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_5) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_87 = and(_T_85, _T_86) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_88 = shr(io.in.a.bits.source, 2) node _T_89 = eq(_T_88, UInt<2>(0h2)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_6) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_93 = and(_T_91, _T_92) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_94 = shr(io.in.a.bits.source, 2) node _T_95 = eq(_T_94, UInt<2>(0h3)) node _T_96 = leq(UInt<1>(0h0), uncommonBits_7) node _T_97 = and(_T_95, _T_96) node _T_98 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(_T_75, _T_81) node _T_101 = or(_T_100, _T_87) node _T_102 = or(_T_101, _T_93) node _T_103 = or(_T_102, _T_99) node _T_104 = and(_T_74, _T_103) node _T_105 = or(UInt<1>(0h0), _T_104) node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<13>(0h1000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<18>(0h2f000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<13>(0h1000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<27>(0h4000000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<13>(0h1000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = or(_T_111, _T_116) node _T_148 = or(_T_147, _T_121) node _T_149 = or(_T_148, _T_126) node _T_150 = or(_T_149, _T_131) node _T_151 = or(_T_150, _T_136) node _T_152 = or(_T_151, _T_141) node _T_153 = or(_T_152, _T_146) node _T_154 = and(_T_106, _T_153) node _T_155 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_156 = or(UInt<1>(0h0), _T_155) node _T_157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<29>(0h10000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = and(_T_156, _T_167) node _T_169 = or(UInt<1>(0h0), _T_154) node _T_170 = or(_T_169, _T_168) node _T_171 = and(_T_105, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_171, UInt<1>(0h1), "") : assert_2 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<14>(0h2000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<13>(0h1000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<17>(0h10000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<18>(0h2f000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<13>(0h1000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<17>(0h10000))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<27>(0h4000000))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_220 = cvt(_T_219) node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000))) node _T_222 = asSInt(_T_221) node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0))) node _T_224 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_225 = cvt(_T_224) node _T_226 = and(_T_225, asSInt(UInt<29>(0h10000000))) node _T_227 = asSInt(_T_226) node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = or(_T_183, _T_188) node _T_230 = or(_T_229, _T_193) node _T_231 = or(_T_230, _T_198) node _T_232 = or(_T_231, _T_203) node _T_233 = or(_T_232, _T_208) node _T_234 = or(_T_233, _T_213) node _T_235 = or(_T_234, _T_218) node _T_236 = or(_T_235, _T_223) node _T_237 = or(_T_236, _T_228) node _T_238 = and(_T_178, _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = and(UInt<1>(0h0), _T_239) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_240, UInt<1>(0h1), "") : assert_3 node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(source_ok, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_247 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_247, UInt<1>(0h1), "") : assert_5 node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(is_aligned, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_254 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_254, UInt<1>(0h1), "") : assert_7 node _T_258 = not(io.in.a.bits.mask) node _T_259 = eq(_T_258, UInt<1>(0h0)) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_259, UInt<1>(0h1), "") : assert_8 node _T_263 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_263, UInt<1>(0h1), "") : assert_9 node _T_267 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_267 : node _T_268 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_269 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_8) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h1)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_9) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h2)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_10) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h3)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_11) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _T_296 = or(_T_271, _T_277) node _T_297 = or(_T_296, _T_283) node _T_298 = or(_T_297, _T_289) node _T_299 = or(_T_298, _T_295) node _T_300 = and(_T_270, _T_299) node _T_301 = or(UInt<1>(0h0), _T_300) node _T_302 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_303 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<14>(0h2000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<17>(0h10000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<18>(0h2f000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<27>(0h4000000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_307, _T_312) node _T_344 = or(_T_343, _T_317) node _T_345 = or(_T_344, _T_322) node _T_346 = or(_T_345, _T_327) node _T_347 = or(_T_346, _T_332) node _T_348 = or(_T_347, _T_337) node _T_349 = or(_T_348, _T_342) node _T_350 = and(_T_302, _T_349) node _T_351 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_359 = cvt(_T_358) node _T_360 = and(_T_359, asSInt(UInt<29>(0h10000000))) node _T_361 = asSInt(_T_360) node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) node _T_363 = or(_T_357, _T_362) node _T_364 = and(_T_352, _T_363) node _T_365 = or(UInt<1>(0h0), _T_350) node _T_366 = or(_T_365, _T_364) node _T_367 = and(_T_301, _T_366) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_367, UInt<1>(0h1), "") : assert_10 node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<14>(0h2000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_386 = cvt(_T_385) node _T_387 = and(_T_386, asSInt(UInt<17>(0h10000))) node _T_388 = asSInt(_T_387) node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0))) node _T_390 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_391 = cvt(_T_390) node _T_392 = and(_T_391, asSInt(UInt<18>(0h2f000))) node _T_393 = asSInt(_T_392) node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0))) node _T_395 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<17>(0h10000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<17>(0h10000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_411 = cvt(_T_410) node _T_412 = and(_T_411, asSInt(UInt<27>(0h4000000))) node _T_413 = asSInt(_T_412) node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0))) node _T_415 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_416 = cvt(_T_415) node _T_417 = and(_T_416, asSInt(UInt<13>(0h1000))) node _T_418 = asSInt(_T_417) node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0))) node _T_420 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_421 = cvt(_T_420) node _T_422 = and(_T_421, asSInt(UInt<29>(0h10000000))) node _T_423 = asSInt(_T_422) node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0))) node _T_425 = or(_T_379, _T_384) node _T_426 = or(_T_425, _T_389) node _T_427 = or(_T_426, _T_394) node _T_428 = or(_T_427, _T_399) node _T_429 = or(_T_428, _T_404) node _T_430 = or(_T_429, _T_409) node _T_431 = or(_T_430, _T_414) node _T_432 = or(_T_431, _T_419) node _T_433 = or(_T_432, _T_424) node _T_434 = and(_T_374, _T_433) node _T_435 = or(UInt<1>(0h0), _T_434) node _T_436 = and(UInt<1>(0h0), _T_435) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_436, UInt<1>(0h1), "") : assert_11 node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(source_ok, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_443 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_443, UInt<1>(0h1), "") : assert_13 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(is_aligned, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_450 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_450, UInt<1>(0h1), "") : assert_15 node _T_454 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_454, UInt<1>(0h1), "") : assert_16 node _T_458 = not(io.in.a.bits.mask) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_459, UInt<1>(0h1), "") : assert_17 node _T_463 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_463, UInt<1>(0h1), "") : assert_18 node _T_467 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_467 : node _T_468 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_469 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_470 = and(_T_468, _T_469) node _T_471 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_472 = shr(io.in.a.bits.source, 2) node _T_473 = eq(_T_472, UInt<1>(0h0)) node _T_474 = leq(UInt<1>(0h0), uncommonBits_12) node _T_475 = and(_T_473, _T_474) node _T_476 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_477 = and(_T_475, _T_476) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_478 = shr(io.in.a.bits.source, 2) node _T_479 = eq(_T_478, UInt<1>(0h1)) node _T_480 = leq(UInt<1>(0h0), uncommonBits_13) node _T_481 = and(_T_479, _T_480) node _T_482 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_483 = and(_T_481, _T_482) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<2>(0h2)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_14) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<2>(0h3)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_15) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(_T_471, _T_477) node _T_497 = or(_T_496, _T_483) node _T_498 = or(_T_497, _T_489) node _T_499 = or(_T_498, _T_495) node _T_500 = and(_T_470, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_501, UInt<1>(0h1), "") : assert_19 node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = or(UInt<1>(0h0), _T_507) node _T_509 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<13>(0h1000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = and(_T_508, _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<14>(0h2000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<17>(0h10000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<18>(0h2f000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<17>(0h10000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<17>(0h10000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<27>(0h4000000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<29>(0h10000000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = or(_T_523, _T_528) node _T_565 = or(_T_564, _T_533) node _T_566 = or(_T_565, _T_538) node _T_567 = or(_T_566, _T_543) node _T_568 = or(_T_567, _T_548) node _T_569 = or(_T_568, _T_553) node _T_570 = or(_T_569, _T_558) node _T_571 = or(_T_570, _T_563) node _T_572 = and(_T_518, _T_571) node _T_573 = or(UInt<1>(0h0), _T_514) node _T_574 = or(_T_573, _T_572) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_574, UInt<1>(0h1), "") : assert_20 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(source_ok, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(is_aligned, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_584 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_584, UInt<1>(0h1), "") : assert_23 node _T_588 = eq(io.in.a.bits.mask, mask) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_588, UInt<1>(0h1), "") : assert_24 node _T_592 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_593 = asUInt(reset) node _T_594 = eq(_T_593, UInt<1>(0h0)) when _T_594 : node _T_595 = eq(_T_592, UInt<1>(0h0)) when _T_595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_592, UInt<1>(0h1), "") : assert_25 node _T_596 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_596 : node _T_597 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_598 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_601 = shr(io.in.a.bits.source, 2) node _T_602 = eq(_T_601, UInt<1>(0h0)) node _T_603 = leq(UInt<1>(0h0), uncommonBits_16) node _T_604 = and(_T_602, _T_603) node _T_605 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_606 = and(_T_604, _T_605) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_607 = shr(io.in.a.bits.source, 2) node _T_608 = eq(_T_607, UInt<1>(0h1)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_17) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_613 = shr(io.in.a.bits.source, 2) node _T_614 = eq(_T_613, UInt<2>(0h2)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_18) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_619 = shr(io.in.a.bits.source, 2) node _T_620 = eq(_T_619, UInt<2>(0h3)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_19) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_624 = and(_T_622, _T_623) node _T_625 = or(_T_600, _T_606) node _T_626 = or(_T_625, _T_612) node _T_627 = or(_T_626, _T_618) node _T_628 = or(_T_627, _T_624) node _T_629 = and(_T_599, _T_628) node _T_630 = or(UInt<1>(0h0), _T_629) node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = and(_T_634, _T_639) node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_643 = and(_T_641, _T_642) node _T_644 = or(UInt<1>(0h0), _T_643) node _T_645 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<14>(0h2000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<18>(0h2f000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<17>(0h10000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<27>(0h4000000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<13>(0h1000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<29>(0h10000000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = or(_T_649, _T_654) node _T_686 = or(_T_685, _T_659) node _T_687 = or(_T_686, _T_664) node _T_688 = or(_T_687, _T_669) node _T_689 = or(_T_688, _T_674) node _T_690 = or(_T_689, _T_679) node _T_691 = or(_T_690, _T_684) node _T_692 = and(_T_644, _T_691) node _T_693 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<17>(0h10000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = and(_T_693, _T_698) node _T_700 = or(UInt<1>(0h0), _T_640) node _T_701 = or(_T_700, _T_692) node _T_702 = or(_T_701, _T_699) node _T_703 = and(_T_630, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_703, UInt<1>(0h1), "") : assert_26 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_713 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_713, UInt<1>(0h1), "") : assert_29 node _T_717 = eq(io.in.a.bits.mask, mask) node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(_T_717, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_717, UInt<1>(0h1), "") : assert_30 node _T_721 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_721 : node _T_722 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_723 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_726 = shr(io.in.a.bits.source, 2) node _T_727 = eq(_T_726, UInt<1>(0h0)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_20) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_731 = and(_T_729, _T_730) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_732 = shr(io.in.a.bits.source, 2) node _T_733 = eq(_T_732, UInt<1>(0h1)) node _T_734 = leq(UInt<1>(0h0), uncommonBits_21) node _T_735 = and(_T_733, _T_734) node _T_736 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_737 = and(_T_735, _T_736) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_738 = shr(io.in.a.bits.source, 2) node _T_739 = eq(_T_738, UInt<2>(0h2)) node _T_740 = leq(UInt<1>(0h0), uncommonBits_22) node _T_741 = and(_T_739, _T_740) node _T_742 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_743 = and(_T_741, _T_742) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_744 = shr(io.in.a.bits.source, 2) node _T_745 = eq(_T_744, UInt<2>(0h3)) node _T_746 = leq(UInt<1>(0h0), uncommonBits_23) node _T_747 = and(_T_745, _T_746) node _T_748 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(_T_725, _T_731) node _T_751 = or(_T_750, _T_737) node _T_752 = or(_T_751, _T_743) node _T_753 = or(_T_752, _T_749) node _T_754 = and(_T_724, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = and(_T_759, _T_764) node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_768 = and(_T_766, _T_767) node _T_769 = or(UInt<1>(0h0), _T_768) node _T_770 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<14>(0h2000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<18>(0h2f000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<13>(0h1000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<27>(0h4000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<29>(0h10000000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = or(_T_774, _T_779) node _T_811 = or(_T_810, _T_784) node _T_812 = or(_T_811, _T_789) node _T_813 = or(_T_812, _T_794) node _T_814 = or(_T_813, _T_799) node _T_815 = or(_T_814, _T_804) node _T_816 = or(_T_815, _T_809) node _T_817 = and(_T_769, _T_816) node _T_818 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_819 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<17>(0h10000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = and(_T_818, _T_823) node _T_825 = or(UInt<1>(0h0), _T_765) node _T_826 = or(_T_825, _T_817) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_828, UInt<1>(0h1), "") : assert_31 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(source_ok, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_838 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_838, UInt<1>(0h1), "") : assert_34 node _T_842 = not(mask) node _T_843 = and(io.in.a.bits.mask, _T_842) node _T_844 = eq(_T_843, UInt<1>(0h0)) node _T_845 = asUInt(reset) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(_T_844, UInt<1>(0h0)) when _T_847 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_844, UInt<1>(0h1), "") : assert_35 node _T_848 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_848 : node _T_849 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_850 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_851 = and(_T_849, _T_850) node _T_852 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h0)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_24) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<1>(0h1)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_25) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_865 = shr(io.in.a.bits.source, 2) node _T_866 = eq(_T_865, UInt<2>(0h2)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_26) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_870 = and(_T_868, _T_869) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_871 = shr(io.in.a.bits.source, 2) node _T_872 = eq(_T_871, UInt<2>(0h3)) node _T_873 = leq(UInt<1>(0h0), uncommonBits_27) node _T_874 = and(_T_872, _T_873) node _T_875 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_876 = and(_T_874, _T_875) node _T_877 = or(_T_852, _T_858) node _T_878 = or(_T_877, _T_864) node _T_879 = or(_T_878, _T_870) node _T_880 = or(_T_879, _T_876) node _T_881 = and(_T_851, _T_880) node _T_882 = or(UInt<1>(0h0), _T_881) node _T_883 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_884 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _T_886 = or(UInt<1>(0h0), _T_885) node _T_887 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_888 = cvt(_T_887) node _T_889 = and(_T_888, asSInt(UInt<14>(0h2000))) node _T_890 = asSInt(_T_889) node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0))) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<18>(0h2f000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<17>(0h10000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_908 = cvt(_T_907) node _T_909 = and(_T_908, asSInt(UInt<13>(0h1000))) node _T_910 = asSInt(_T_909) node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0))) node _T_912 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_913 = cvt(_T_912) node _T_914 = and(_T_913, asSInt(UInt<27>(0h4000000))) node _T_915 = asSInt(_T_914) node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0))) node _T_917 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = or(_T_891, _T_896) node _T_923 = or(_T_922, _T_901) node _T_924 = or(_T_923, _T_906) node _T_925 = or(_T_924, _T_911) node _T_926 = or(_T_925, _T_916) node _T_927 = or(_T_926, _T_921) node _T_928 = and(_T_886, _T_927) node _T_929 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_930 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_931 = cvt(_T_930) node _T_932 = and(_T_931, asSInt(UInt<17>(0h10000))) node _T_933 = asSInt(_T_932) node _T_934 = eq(_T_933, asSInt(UInt<1>(0h0))) node _T_935 = and(_T_929, _T_934) node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_938 = and(_T_936, _T_937) node _T_939 = or(UInt<1>(0h0), _T_938) node _T_940 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_941 = cvt(_T_940) node _T_942 = and(_T_941, asSInt(UInt<17>(0h10000))) node _T_943 = asSInt(_T_942) node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0))) node _T_945 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<29>(0h10000000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = or(_T_944, _T_949) node _T_951 = and(_T_939, _T_950) node _T_952 = or(UInt<1>(0h0), _T_928) node _T_953 = or(_T_952, _T_935) node _T_954 = or(_T_953, _T_951) node _T_955 = and(_T_882, _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_955, UInt<1>(0h1), "") : assert_36 node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(source_ok, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(is_aligned, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_965 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_965, UInt<1>(0h1), "") : assert_39 node _T_969 = eq(io.in.a.bits.mask, mask) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_969, UInt<1>(0h1), "") : assert_40 node _T_973 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_973 : node _T_974 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_975 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_976 = and(_T_974, _T_975) node _T_977 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_978 = shr(io.in.a.bits.source, 2) node _T_979 = eq(_T_978, UInt<1>(0h0)) node _T_980 = leq(UInt<1>(0h0), uncommonBits_28) node _T_981 = and(_T_979, _T_980) node _T_982 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_983 = and(_T_981, _T_982) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_984 = shr(io.in.a.bits.source, 2) node _T_985 = eq(_T_984, UInt<1>(0h1)) node _T_986 = leq(UInt<1>(0h0), uncommonBits_29) node _T_987 = and(_T_985, _T_986) node _T_988 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_989 = and(_T_987, _T_988) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_990 = shr(io.in.a.bits.source, 2) node _T_991 = eq(_T_990, UInt<2>(0h2)) node _T_992 = leq(UInt<1>(0h0), uncommonBits_30) node _T_993 = and(_T_991, _T_992) node _T_994 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_995 = and(_T_993, _T_994) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<2>(0h3)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_31) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _T_1002 = or(_T_977, _T_983) node _T_1003 = or(_T_1002, _T_989) node _T_1004 = or(_T_1003, _T_995) node _T_1005 = or(_T_1004, _T_1001) node _T_1006 = and(_T_976, _T_1005) node _T_1007 = or(UInt<1>(0h0), _T_1006) node _T_1008 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1009 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1010 = and(_T_1008, _T_1009) node _T_1011 = or(UInt<1>(0h0), _T_1010) node _T_1012 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<14>(0h2000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1023 = cvt(_T_1022) node _T_1024 = and(_T_1023, asSInt(UInt<18>(0h2f000))) node _T_1025 = asSInt(_T_1024) node _T_1026 = eq(_T_1025, asSInt(UInt<1>(0h0))) node _T_1027 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1028 = cvt(_T_1027) node _T_1029 = and(_T_1028, asSInt(UInt<17>(0h10000))) node _T_1030 = asSInt(_T_1029) node _T_1031 = eq(_T_1030, asSInt(UInt<1>(0h0))) node _T_1032 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1033 = cvt(_T_1032) node _T_1034 = and(_T_1033, asSInt(UInt<13>(0h1000))) node _T_1035 = asSInt(_T_1034) node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0))) node _T_1037 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1038 = cvt(_T_1037) node _T_1039 = and(_T_1038, asSInt(UInt<27>(0h4000000))) node _T_1040 = asSInt(_T_1039) node _T_1041 = eq(_T_1040, asSInt(UInt<1>(0h0))) node _T_1042 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1043 = cvt(_T_1042) node _T_1044 = and(_T_1043, asSInt(UInt<13>(0h1000))) node _T_1045 = asSInt(_T_1044) node _T_1046 = eq(_T_1045, asSInt(UInt<1>(0h0))) node _T_1047 = or(_T_1016, _T_1021) node _T_1048 = or(_T_1047, _T_1026) node _T_1049 = or(_T_1048, _T_1031) node _T_1050 = or(_T_1049, _T_1036) node _T_1051 = or(_T_1050, _T_1041) node _T_1052 = or(_T_1051, _T_1046) node _T_1053 = and(_T_1011, _T_1052) node _T_1054 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1055 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1056 = cvt(_T_1055) node _T_1057 = and(_T_1056, asSInt(UInt<17>(0h10000))) node _T_1058 = asSInt(_T_1057) node _T_1059 = eq(_T_1058, asSInt(UInt<1>(0h0))) node _T_1060 = and(_T_1054, _T_1059) node _T_1061 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1062 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = or(UInt<1>(0h0), _T_1063) node _T_1065 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1066 = cvt(_T_1065) node _T_1067 = and(_T_1066, asSInt(UInt<17>(0h10000))) node _T_1068 = asSInt(_T_1067) node _T_1069 = eq(_T_1068, asSInt(UInt<1>(0h0))) node _T_1070 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1071 = cvt(_T_1070) node _T_1072 = and(_T_1071, asSInt(UInt<29>(0h10000000))) node _T_1073 = asSInt(_T_1072) node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0))) node _T_1075 = or(_T_1069, _T_1074) node _T_1076 = and(_T_1064, _T_1075) node _T_1077 = or(UInt<1>(0h0), _T_1053) node _T_1078 = or(_T_1077, _T_1060) node _T_1079 = or(_T_1078, _T_1076) node _T_1080 = and(_T_1007, _T_1079) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_41 node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(source_ok, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(is_aligned, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1090 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_44 node _T_1094 = eq(io.in.a.bits.mask, mask) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_45 node _T_1098 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1098 : node _T_1099 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1101 = and(_T_1099, _T_1100) node _T_1102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1103 = shr(io.in.a.bits.source, 2) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) node _T_1105 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1108 = and(_T_1106, _T_1107) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1109 = shr(io.in.a.bits.source, 2) node _T_1110 = eq(_T_1109, UInt<1>(0h1)) node _T_1111 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1112 = and(_T_1110, _T_1111) node _T_1113 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1114 = and(_T_1112, _T_1113) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1115 = shr(io.in.a.bits.source, 2) node _T_1116 = eq(_T_1115, UInt<2>(0h2)) node _T_1117 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1120 = and(_T_1118, _T_1119) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1121 = shr(io.in.a.bits.source, 2) node _T_1122 = eq(_T_1121, UInt<2>(0h3)) node _T_1123 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1124 = and(_T_1122, _T_1123) node _T_1125 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1126 = and(_T_1124, _T_1125) node _T_1127 = or(_T_1102, _T_1108) node _T_1128 = or(_T_1127, _T_1114) node _T_1129 = or(_T_1128, _T_1120) node _T_1130 = or(_T_1129, _T_1126) node _T_1131 = and(_T_1101, _T_1130) node _T_1132 = or(UInt<1>(0h0), _T_1131) node _T_1133 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1134 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1135 = and(_T_1133, _T_1134) node _T_1136 = or(UInt<1>(0h0), _T_1135) node _T_1137 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<13>(0h1000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = and(_T_1136, _T_1141) node _T_1143 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1144 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<14>(0h2000))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1150 = cvt(_T_1149) node _T_1151 = and(_T_1150, asSInt(UInt<17>(0h10000))) node _T_1152 = asSInt(_T_1151) node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0))) node _T_1154 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1155 = cvt(_T_1154) node _T_1156 = and(_T_1155, asSInt(UInt<18>(0h2f000))) node _T_1157 = asSInt(_T_1156) node _T_1158 = eq(_T_1157, asSInt(UInt<1>(0h0))) node _T_1159 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1160 = cvt(_T_1159) node _T_1161 = and(_T_1160, asSInt(UInt<17>(0h10000))) node _T_1162 = asSInt(_T_1161) node _T_1163 = eq(_T_1162, asSInt(UInt<1>(0h0))) node _T_1164 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1165 = cvt(_T_1164) node _T_1166 = and(_T_1165, asSInt(UInt<13>(0h1000))) node _T_1167 = asSInt(_T_1166) node _T_1168 = eq(_T_1167, asSInt(UInt<1>(0h0))) node _T_1169 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1170 = cvt(_T_1169) node _T_1171 = and(_T_1170, asSInt(UInt<27>(0h4000000))) node _T_1172 = asSInt(_T_1171) node _T_1173 = eq(_T_1172, asSInt(UInt<1>(0h0))) node _T_1174 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1175 = cvt(_T_1174) node _T_1176 = and(_T_1175, asSInt(UInt<13>(0h1000))) node _T_1177 = asSInt(_T_1176) node _T_1178 = eq(_T_1177, asSInt(UInt<1>(0h0))) node _T_1179 = or(_T_1148, _T_1153) node _T_1180 = or(_T_1179, _T_1158) node _T_1181 = or(_T_1180, _T_1163) node _T_1182 = or(_T_1181, _T_1168) node _T_1183 = or(_T_1182, _T_1173) node _T_1184 = or(_T_1183, _T_1178) node _T_1185 = and(_T_1143, _T_1184) node _T_1186 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1187 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = or(UInt<1>(0h0), _T_1188) node _T_1190 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<17>(0h10000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<29>(0h10000000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = or(_T_1194, _T_1199) node _T_1201 = and(_T_1189, _T_1200) node _T_1202 = or(UInt<1>(0h0), _T_1142) node _T_1203 = or(_T_1202, _T_1185) node _T_1204 = or(_T_1203, _T_1201) node _T_1205 = and(_T_1132, _T_1204) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_46 node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(source_ok, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(is_aligned, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1215 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_49 node _T_1219 = eq(io.in.a.bits.mask, mask) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_50 node _T_1223 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1227 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_52 node _source_ok_T_28 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_29 = shr(io.in.d.bits.source, 2) node _source_ok_T_30 = eq(_source_ok_T_29, UInt<1>(0h0)) node _source_ok_T_31 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_T_33 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h1)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<2>(0h2)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h3)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) wire _source_ok_WIRE_1 : UInt<1>[5] connect _source_ok_WIRE_1[0], _source_ok_T_28 connect _source_ok_WIRE_1[1], _source_ok_T_34 connect _source_ok_WIRE_1[2], _source_ok_T_40 connect _source_ok_WIRE_1[3], _source_ok_T_46 connect _source_ok_WIRE_1[4], _source_ok_T_52 node _source_ok_T_53 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE_1[2]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE_1[3]) node source_ok_1 = or(_source_ok_T_55, _source_ok_WIRE_1[4]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1231 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1231 : node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(source_ok_1, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1235 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_54 node _T_1239 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_55 node _T_1243 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_56 node _T_1247 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_57 node _T_1251 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1251 : node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(source_ok_1, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(sink_ok, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1258 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_60 node _T_1262 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_61 node _T_1266 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_62 node _T_1270 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_63 node _T_1274 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1275 = or(UInt<1>(0h1), _T_1274) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_64 node _T_1279 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1279 : node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(source_ok_1, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(sink_ok, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1286 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_67 node _T_1290 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_68 node _T_1294 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_69 node _T_1298 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1299 = or(_T_1298, io.in.d.bits.corrupt) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_70 node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1304 = or(UInt<1>(0h1), _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_71 node _T_1308 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1308 : node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(source_ok_1, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1312 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_73 node _T_1316 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_74 node _T_1320 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1321 = or(UInt<1>(0h1), _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_75 node _T_1325 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1325 : node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(source_ok_1, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1329 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1330 = asUInt(reset) node _T_1331 = eq(_T_1330, UInt<1>(0h0)) when _T_1331 : node _T_1332 = eq(_T_1329, UInt<1>(0h0)) when _T_1332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1329, UInt<1>(0h1), "") : assert_77 node _T_1333 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1334 = or(_T_1333, io.in.d.bits.corrupt) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_78 node _T_1338 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1339 = or(UInt<1>(0h1), _T_1338) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_79 node _T_1343 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1343 : node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(source_ok_1, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1347 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_81 node _T_1351 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_82 node _T_1355 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1356 = or(UInt<1>(0h1), _T_1355) node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(_T_1356, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1356, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1360 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1364 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1368 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1372 = eq(a_first, UInt<1>(0h0)) node _T_1373 = and(io.in.a.valid, _T_1372) when _T_1373 : node _T_1374 = eq(io.in.a.bits.opcode, opcode) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_87 node _T_1378 = eq(io.in.a.bits.param, param) node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(_T_1378, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1378, UInt<1>(0h1), "") : assert_88 node _T_1382 = eq(io.in.a.bits.size, size) node _T_1383 = asUInt(reset) node _T_1384 = eq(_T_1383, UInt<1>(0h0)) when _T_1384 : node _T_1385 = eq(_T_1382, UInt<1>(0h0)) when _T_1385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1382, UInt<1>(0h1), "") : assert_89 node _T_1386 = eq(io.in.a.bits.source, source) node _T_1387 = asUInt(reset) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) when _T_1388 : node _T_1389 = eq(_T_1386, UInt<1>(0h0)) when _T_1389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1386, UInt<1>(0h1), "") : assert_90 node _T_1390 = eq(io.in.a.bits.address, address) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_91 node _T_1394 = and(io.in.a.ready, io.in.a.valid) node _T_1395 = and(_T_1394, a_first) when _T_1395 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1396 = eq(d_first, UInt<1>(0h0)) node _T_1397 = and(io.in.d.valid, _T_1396) when _T_1397 : node _T_1398 = eq(io.in.d.bits.opcode, opcode_1) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_92 node _T_1402 = eq(io.in.d.bits.param, param_1) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_93 node _T_1406 = eq(io.in.d.bits.size, size_1) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_94 node _T_1410 = eq(io.in.d.bits.source, source_1) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_95 node _T_1414 = eq(io.in.d.bits.sink, sink) node _T_1415 = asUInt(reset) node _T_1416 = eq(_T_1415, UInt<1>(0h0)) when _T_1416 : node _T_1417 = eq(_T_1414, UInt<1>(0h0)) when _T_1417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1414, UInt<1>(0h1), "") : assert_96 node _T_1418 = eq(io.in.d.bits.denied, denied) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_97 node _T_1422 = and(io.in.d.ready, io.in.d.valid) node _T_1423 = and(_T_1422, d_first) when _T_1423 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes : UInt<136>, clock, reset, UInt<136>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<17> connect a_set, UInt<17>(0h0) wire a_set_wo_ready : UInt<17> connect a_set_wo_ready, UInt<17>(0h0) wire a_opcodes_set : UInt<68> connect a_opcodes_set, UInt<68>(0h0) wire a_sizes_set : UInt<136> connect a_sizes_set, UInt<136>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1424 = and(io.in.a.valid, a_first_1) node _T_1425 = and(_T_1424, UInt<1>(0h1)) when _T_1425 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1426 = and(io.in.a.ready, io.in.a.valid) node _T_1427 = and(_T_1426, a_first_1) node _T_1428 = and(_T_1427, UInt<1>(0h1)) when _T_1428 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1429 = dshr(inflight, io.in.a.bits.source) node _T_1430 = bits(_T_1429, 0, 0) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<17> connect d_clr, UInt<17>(0h0) wire d_clr_wo_ready : UInt<17> connect d_clr_wo_ready, UInt<17>(0h0) wire d_opcodes_clr : UInt<68> connect d_opcodes_clr, UInt<68>(0h0) wire d_sizes_clr : UInt<136> connect d_sizes_clr, UInt<136>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1435 = and(io.in.d.valid, d_first_1) node _T_1436 = and(_T_1435, UInt<1>(0h1)) node _T_1437 = eq(d_release_ack, UInt<1>(0h0)) node _T_1438 = and(_T_1436, _T_1437) when _T_1438 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1439 = and(io.in.d.ready, io.in.d.valid) node _T_1440 = and(_T_1439, d_first_1) node _T_1441 = and(_T_1440, UInt<1>(0h1)) node _T_1442 = eq(d_release_ack, UInt<1>(0h0)) node _T_1443 = and(_T_1441, _T_1442) when _T_1443 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1444 = and(io.in.d.valid, d_first_1) node _T_1445 = and(_T_1444, UInt<1>(0h1)) node _T_1446 = eq(d_release_ack, UInt<1>(0h0)) node _T_1447 = and(_T_1445, _T_1446) when _T_1447 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1448 = dshr(inflight, io.in.d.bits.source) node _T_1449 = bits(_T_1448, 0, 0) node _T_1450 = or(_T_1449, same_cycle_resp) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1454 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1455 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1456 = or(_T_1454, _T_1455) node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(_T_1456, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1456, UInt<1>(0h1), "") : assert_100 node _T_1460 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_101 else : node _T_1464 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1465 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1466 = or(_T_1464, _T_1465) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_102 node _T_1470 = eq(io.in.d.bits.size, a_size_lookup) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_103 node _T_1474 = and(io.in.d.valid, d_first_1) node _T_1475 = and(_T_1474, a_first_1) node _T_1476 = and(_T_1475, io.in.a.valid) node _T_1477 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1478 = and(_T_1476, _T_1477) node _T_1479 = eq(d_release_ack, UInt<1>(0h0)) node _T_1480 = and(_T_1478, _T_1479) when _T_1480 : node _T_1481 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1482 = or(_T_1481, io.in.a.ready) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_104 node _T_1486 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1487 = orr(a_set_wo_ready) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) node _T_1489 = or(_T_1486, _T_1488) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader node _T_1493 = orr(inflight) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) node _T_1495 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1496 = or(_T_1494, _T_1495) node _T_1497 = lt(watchdog, plusarg_reader.out) node _T_1498 = or(_T_1496, _T_1497) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1502 = and(io.in.a.ready, io.in.a.valid) node _T_1503 = and(io.in.d.ready, io.in.d.valid) node _T_1504 = or(_T_1502, _T_1503) when _T_1504 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes_1 : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes_1 : UInt<136>, clock, reset, UInt<136>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<17> connect c_set, UInt<17>(0h0) wire c_set_wo_ready : UInt<17> connect c_set_wo_ready, UInt<17>(0h0) wire c_opcodes_set : UInt<68> connect c_opcodes_set, UInt<68>(0h0) wire c_sizes_set : UInt<136> connect c_sizes_set, UInt<136>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1505 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1506 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1507 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1508 = and(_T_1506, _T_1507) node _T_1509 = and(_T_1505, _T_1508) when _T_1509 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1510 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1511 = and(_T_1510, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1512 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1513 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1514 = and(_T_1512, _T_1513) node _T_1515 = and(_T_1511, _T_1514) when _T_1515 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1516 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1517 = bits(_T_1516, 0, 0) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(_T_1518, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1518, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<17> connect d_clr_1, UInt<17>(0h0) wire d_clr_wo_ready_1 : UInt<17> connect d_clr_wo_ready_1, UInt<17>(0h0) wire d_opcodes_clr_1 : UInt<68> connect d_opcodes_clr_1, UInt<68>(0h0) wire d_sizes_clr_1 : UInt<136> connect d_sizes_clr_1, UInt<136>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1522 = and(io.in.d.valid, d_first_2) node _T_1523 = and(_T_1522, UInt<1>(0h1)) node _T_1524 = and(_T_1523, d_release_ack_1) when _T_1524 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1525 = and(io.in.d.ready, io.in.d.valid) node _T_1526 = and(_T_1525, d_first_2) node _T_1527 = and(_T_1526, UInt<1>(0h1)) node _T_1528 = and(_T_1527, d_release_ack_1) when _T_1528 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1529 = and(io.in.d.valid, d_first_2) node _T_1530 = and(_T_1529, UInt<1>(0h1)) node _T_1531 = and(_T_1530, d_release_ack_1) when _T_1531 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1532 = dshr(inflight_1, io.in.d.bits.source) node _T_1533 = bits(_T_1532, 0, 0) node _T_1534 = or(_T_1533, same_cycle_resp_1) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1538 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_109 else : node _T_1542 = eq(io.in.d.bits.size, c_size_lookup) node _T_1543 = asUInt(reset) node _T_1544 = eq(_T_1543, UInt<1>(0h0)) when _T_1544 : node _T_1545 = eq(_T_1542, UInt<1>(0h0)) when _T_1545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1542, UInt<1>(0h1), "") : assert_110 node _T_1546 = and(io.in.d.valid, d_first_2) node _T_1547 = and(_T_1546, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1548 = and(_T_1547, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1549 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1550 = and(_T_1548, _T_1549) node _T_1551 = and(_T_1550, d_release_ack_1) node _T_1552 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1553 = and(_T_1551, _T_1552) when _T_1553 : node _T_1554 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1555 = or(_T_1554, _WIRE_23.ready) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_111 node _T_1559 = orr(c_set_wo_ready) when _T_1559 : node _T_1560 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1561 = asUInt(reset) node _T_1562 = eq(_T_1561, UInt<1>(0h0)) when _T_1562 : node _T_1563 = eq(_T_1560, UInt<1>(0h0)) when _T_1563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1560, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_1 node _T_1564 = orr(inflight_1) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) node _T_1566 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1567 = or(_T_1565, _T_1566) node _T_1568 = lt(watchdog_1, plusarg_reader_1.out) node _T_1569 = or(_T_1567, _T_1568) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1573 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1574 = and(io.in.d.ready, io.in.d.valid) node _T_1575 = or(_T_1573, _T_1574) when _T_1575 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_2 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_3 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module HellaCacheArbiter_3 : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} reg s1_id : UInt, clock reg s2_id : UInt, clock connect s2_id, s1_id node _io_mem_keep_clock_enabled_T = or(io.requestor[0].keep_clock_enabled, io.requestor[1].keep_clock_enabled) connect io.mem.keep_clock_enabled, _io_mem_keep_clock_enabled_T node _io_mem_req_valid_T = or(io.requestor[0].req.valid, io.requestor[1].req.valid) connect io.mem.req.valid, _io_mem_req_valid_T connect io.requestor[0].req.ready, io.mem.req.ready node _io_requestor_1_req_ready_T = eq(io.requestor[0].req.valid, UInt<1>(0h0)) node _io_requestor_1_req_ready_T_1 = and(io.requestor[0].req.ready, _io_requestor_1_req_ready_T) connect io.requestor[1].req.ready, _io_requestor_1_req_ready_T_1 connect io.mem.req.bits, io.requestor[1].req.bits node _io_mem_req_bits_tag_T = cat(io.requestor[1].req.bits.tag, UInt<1>(0h1)) connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T connect s1_id, UInt<1>(0h1) connect io.mem.s1_kill, io.requestor[1].s1_kill connect io.mem.s1_data, io.requestor[1].s1_data connect io.mem.s2_kill, io.requestor[1].s2_kill when io.requestor[0].req.valid : connect io.mem.req.bits, io.requestor[0].req.bits node _io_mem_req_bits_tag_T_1 = cat(io.requestor[0].req.bits.tag, UInt<1>(0h0)) connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T_1 connect s1_id, UInt<1>(0h0) node _T = eq(s1_id, UInt<1>(0h0)) when _T : connect io.mem.s1_kill, io.requestor[0].s1_kill connect io.mem.s1_data, io.requestor[0].s1_data node _T_1 = eq(s2_id, UInt<1>(0h0)) when _T_1 : connect io.mem.s2_kill, io.requestor[0].s2_kill node _tag_hit_T = bits(io.mem.resp.bits.tag, 0, 0) node tag_hit = eq(_tag_hit_T, UInt<1>(0h0)) node _io_requestor_0_resp_valid_T = and(io.mem.resp.valid, tag_hit) connect io.requestor[0].resp.valid, _io_requestor_0_resp_valid_T connect io.requestor[0].s2_xcpt, io.mem.s2_xcpt connect io.requestor[0].s2_gpa, io.mem.s2_gpa connect io.requestor[0].s2_gpa_is_pte, io.mem.s2_gpa_is_pte connect io.requestor[0].ordered, io.mem.ordered connect io.requestor[0].store_pending, io.mem.store_pending connect io.requestor[0].perf, io.mem.perf node _io_requestor_0_s2_nack_T = eq(s2_id, UInt<1>(0h0)) node _io_requestor_0_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_0_s2_nack_T) connect io.requestor[0].s2_nack, _io_requestor_0_s2_nack_T_1 connect io.requestor[0].s2_nack_cause_raw, io.mem.s2_nack_cause_raw connect io.requestor[0].s2_uncached, io.mem.s2_uncached connect io.requestor[0].s2_paddr, io.mem.s2_paddr connect io.requestor[0].clock_enabled, io.mem.clock_enabled connect io.requestor[0].resp.bits, io.mem.resp.bits node _io_requestor_0_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) connect io.requestor[0].resp.bits.tag, _io_requestor_0_resp_bits_tag_T connect io.requestor[0].replay_next, io.mem.replay_next node _tag_hit_T_1 = bits(io.mem.resp.bits.tag, 0, 0) node tag_hit_1 = eq(_tag_hit_T_1, UInt<1>(0h1)) node _io_requestor_1_resp_valid_T = and(io.mem.resp.valid, tag_hit_1) connect io.requestor[1].resp.valid, _io_requestor_1_resp_valid_T connect io.requestor[1].s2_xcpt, io.mem.s2_xcpt connect io.requestor[1].s2_gpa, io.mem.s2_gpa connect io.requestor[1].s2_gpa_is_pte, io.mem.s2_gpa_is_pte connect io.requestor[1].ordered, io.mem.ordered connect io.requestor[1].store_pending, io.mem.store_pending connect io.requestor[1].perf, io.mem.perf node _io_requestor_1_s2_nack_T = eq(s2_id, UInt<1>(0h1)) node _io_requestor_1_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_1_s2_nack_T) connect io.requestor[1].s2_nack, _io_requestor_1_s2_nack_T_1 connect io.requestor[1].s2_nack_cause_raw, io.mem.s2_nack_cause_raw connect io.requestor[1].s2_uncached, io.mem.s2_uncached connect io.requestor[1].s2_paddr, io.mem.s2_paddr connect io.requestor[1].clock_enabled, io.mem.clock_enabled connect io.requestor[1].resp.bits, io.mem.resp.bits node _io_requestor_1_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) connect io.requestor[1].resp.bits.tag, _io_requestor_1_resp_bits_tag_T connect io.requestor[1].replay_next, io.mem.replay_next	module HellaCacheArbiter_3( // @[HellaCacheArbiter.scala:10:7] input clock, // @[HellaCacheArbiter.scala:10:7] input reset, // @[HellaCacheArbiter.scala:10:7] output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_0_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_0_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_1_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_1_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_1_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_1_s1_data_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_1_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_1_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_1_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_phys, // @[HellaCacheArbiter.scala:12:14] output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_mem_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_uncached, // @[HellaCacheArbiter.scala:12:14] input [31:0] io_mem_s2_paddr, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_mem_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] input io_mem_replay_next, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_s2_gpa, // @[HellaCacheArbiter.scala:12:14] input io_mem_ordered, // @[HellaCacheArbiter.scala:12:14] input io_mem_store_pending, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_acquire, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_release, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_grant, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_blocked, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterStore // @[HellaCacheArbiter.scala:12:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_req_bits_tag_0 = io_requestor_1_req_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_dprv_0 = io_requestor_1_req_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_dv_0 = io_requestor_1_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_s1_data_mask_0 = io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[HellaCacheArbiter.scala:10:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[HellaCacheArbiter.scala:10:7] wire io_mem_ordered_0 = io_mem_ordered; // @[HellaCacheArbiter.scala:10:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[HellaCacheArbiter.scala:10:7] wire [8:0] _io_mem_req_bits_tag_T_1 = 9'h0; // @[HellaCacheArbiter.scala:34:35] wire [1:0] io_requestor_0_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_requestor_0_req_bits_tag = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s1_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_keep_clock_enabled_T = 1'h0; // @[HellaCacheArbiter.scala:23:81] wire io_mem_req_bits_phys_0 = io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:25:63] wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] reg s1_id; // @[HellaCacheArbiter.scala:20:20] reg s2_id; // @[HellaCacheArbiter.scala:21:24] wire _io_requestor_1_s2_nack_T = s2_id; // @[HellaCacheArbiter.scala:21:24, :68:58] assign _io_mem_req_valid_T = io_requestor_0_req_valid_0 \| io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign io_mem_req_valid_0 = _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:10:7, :25:63] wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] wire [8:0] _io_mem_req_bits_tag_T = {io_requestor_1_req_bits_tag_0, 1'h1}; // @[HellaCacheArbiter.scala:10:7, :34:35] assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_dprv_0 = io_requestor_0_req_valid_0 ? 2'h1 : io_requestor_1_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_dv_0 : io_requestor_1_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 8'h0 : _io_mem_req_bits_tag_T[7:0]; // @[HellaCacheArbiter.scala:10:7, :34:{29,35}, :50:26] assign io_mem_s1_kill_0 = ~s1_id & io_requestor_0_s1_kill_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :38:24, :51:{21,30}] assign io_mem_s1_data_data_0 = s1_id ? io_requestor_1_s1_data_data_0 : 64'h0; // @[HellaCacheArbiter.scala:10:7, :20:20, :39:24, :51:30] assign io_mem_s1_data_mask_0 = s1_id ? io_requestor_1_s1_data_mask_0 : 8'h0; // @[HellaCacheArbiter.scala:10:7, :20:20, :39:24, :51:30] wire _io_requestor_0_s2_nack_T = ~s2_id; // @[HellaCacheArbiter.scala:21:24, :52:21, :68:58] wire _tag_hit_T = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire _tag_hit_T_1 = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire tag_hit = ~_tag_hit_T; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] wire [6:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:1]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [6:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:1]; // @[HellaCacheArbiter.scala:10:7, :74:45] assign io_requestor_0_resp_bits_tag_0 = {1'h0, _io_requestor_0_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_1 = _tag_hit_T_1; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_1_resp_bits_tag_0 = {1'h0, _io_requestor_1_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] always @(posedge clock) begin // @[HellaCacheArbiter.scala:10:7] s1_id <= ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :28:67] s2_id <= s1_id; // @[HellaCacheArbiter.scala:20:20, :21:24] always @(posedge) assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_replay_next = io_requestor_0_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_release = io_requestor_0_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_tlbMiss = io_requestor_0_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_replay_next = io_requestor_1_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_release = io_requestor_1_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_tlbMiss = io_requestor_1_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_phys = io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_mask = io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_127 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_211 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_127( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_211 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_72 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_89 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_72( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_89 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_36 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} inst input_buffer of InputBuffer_36 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) inst route_arbiter of Arbiter3_RouteComputerReq_36 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_10 : connect states[0].g, UInt<3>(0h2) connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id node _T_11 = and(io.router_req.ready, io.router_req.valid) when _T_11 : node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_12, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_16 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_17 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_18 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_18 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3] wire vcalloc_vals : UInt<1>[3] node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0]) node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11) node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12) node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15) node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_19 = and(io.router_req.ready, io.router_req.valid) when _T_19 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_20 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_21 = or(_T_20, vcalloc_vals[2]) when _T_21 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = bits(vcalloc_sel, 0, 0) node _mask_T_7 = bits(vcalloc_sel, 1, 1) node _mask_T_8 = bits(vcalloc_sel, 2, 2) node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_9, _mask_T_10) node _mask_T_13 = or(_mask_T_12, _mask_T_11) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_13 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3] node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3] node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32 connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6 wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3] node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42 connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1] node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_16 : UInt<2> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16 wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_62 connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65) wire _io_vcalloc_req_bits_WIRE_19 : UInt<4> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70) wire _io_vcalloc_req_bits_WIRE_20 : UInt<3> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_72 connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_21 : UInt<4> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_77 connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80) wire _io_vcalloc_req_bits_WIRE_22 : UInt<2> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].flow, states[0].flow node _T_22 = bits(vcalloc_sel, 0, 0) node _T_23 = and(vcalloc_vals[0], _T_22) node _T_24 = and(_T_23, io.vcalloc_req.ready) when _T_24 : connect states[0].g, UInt<3>(0h3) node _T_25 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_25 : connect vcalloc_vals[0], UInt<1>(0h1) connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[1] invalidate vcalloc_reqs[1].vc_sel.`2`[2] invalidate vcalloc_reqs[1].vc_sel.`3`[0] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[1] invalidate vcalloc_reqs[2].vc_sel.`2`[2] invalidate vcalloc_reqs[2].vc_sel.`3`[0] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready) node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1) connect io.debug.va_stall, _io_debug_va_stall_T_5 node _T_26 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_26 : node _T_27 = bits(vcalloc_sel, 0, 0) when _T_27 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_28 = bits(vcalloc_sel, 1, 1) when _T_28 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_29 = bits(vcalloc_sel, 2, 2) when _T_29 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_89 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1]) node _credit_available_T = cat(credit_available_hi, states[0].vc_sel.`0`[0]) node credit_available_hi_1 = cat(states[0].vc_sel.`1`[2], states[0].vc_sel.`1`[1]) node _credit_available_T_1 = cat(credit_available_hi_1, states[0].vc_sel.`1`[0]) node credit_available_hi_2 = cat(states[0].vc_sel.`2`[2], states[0].vc_sel.`2`[1]) node _credit_available_T_2 = cat(credit_available_hi_2, states[0].vc_sel.`2`[0]) node credit_available_lo = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_3 = cat(states[0].vc_sel.`3`[0], _credit_available_T_2) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo) node credit_available_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`0`[0]) node credit_available_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`1`[0]) node credit_available_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`2`[0]) node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4) node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], _credit_available_T_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_1) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_30 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_31 = and(_T_30, input_buffer.io.deq[0].bits.tail) when _T_31 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0] connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`3`[0] node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0) node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_9 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5) node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8 node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_10 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1) node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _vc_sel_WIRE : UInt<1>[3] node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4) node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_7 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_12 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_17 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_4 : UInt<1>[3] node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_22 connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_27 connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_32 connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7 connect vc_sel.`1`, _vc_sel_WIRE_4 wire _vc_sel_WIRE_8 : UInt<1>[3] node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_37 connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_42 connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10 node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_47 connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11 connect vc_sel.`2`, _vc_sel_WIRE_8 wire _vc_sel_WIRE_12 : UInt<1>[1] node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_52 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 connect vc_sel.`3`, _vc_sel_WIRE_12 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2]) node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2]) node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0]) node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2) node virt_channel_lo = bits(_virt_channel_T, 1, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3) node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1]) node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0]) node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2) node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0) node _virt_channel_T_6 = orr(virt_channel_hi_3) node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1) node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1) node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8) node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1]) node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0]) node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2) node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0)) node _virt_channel_T_16 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0)) node _virt_channel_T_17 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0)) node _virt_channel_T_18 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_19 = or(_virt_channel_T_15, _virt_channel_T_16) node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_17) node _virt_channel_T_21 = or(_virt_channel_T_20, _virt_channel_T_18) wire virt_channel : UInt<2> connect virt_channel, _virt_channel_T_21 node _T_32 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_32 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4) node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5) wire _salloc_outs_0_flit_payload_WIRE : UInt<145> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4) node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4) node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`1`[0], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[2], UInt<1>(0h0) connect states[0].vc_sel.`2`[1], UInt<1>(0h0) connect states[0].vc_sel.`2`[2], UInt<1>(0h0) invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`2`[1] invalidate states[1].vc_sel.`2`[2] invalidate states[1].vc_sel.`3`[0] invalidate states[1].g invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`2`[1] invalidate states[2].vc_sel.`2`[2] invalidate states[2].vc_sel.`3`[0] invalidate states[2].g node _T_33 = asUInt(reset) when _T_33 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0)	module InputUnit_36( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_2_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_57 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_57( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IBuf : input clock : Clock input reset : Reset output io : { flip imem : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip kill : UInt<1>, pc : UInt<34>, btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, inst : { flip ready : UInt<1>, valid : UInt<1>, bits : { xcpt0 : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, xcpt1 : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>, rvc : UInt<1>, inst : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, raw : UInt<32>}}[1]} regreset nBufValid : UInt<1>, clock, reset, UInt<1>(0h0) reg buf : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}, clock reg ibufBTBResp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock node pcWordBits = bits(io.imem.bits.pc, 1, 1) wire nReady : UInt<2> connect nReady, UInt<2>(0h0) node _nIC_T = add(io.imem.bits.btb.bridx, UInt<1>(0h1)) node _nIC_T_1 = mux(io.imem.bits.btb.taken, _nIC_T, UInt<2>(0h2)) node _nIC_T_2 = sub(_nIC_T_1, pcWordBits) node nIC = tail(_nIC_T_2, 1) node _nICReady_T = sub(nReady, nBufValid) node nICReady = tail(_nICReady_T, 1) node _nValid_T = mux(io.imem.valid, nIC, UInt<1>(0h0)) node _nValid_T_1 = add(_nValid_T, nBufValid) node nValid = tail(_nValid_T_1, 1) node _io_imem_ready_T = geq(nReady, nBufValid) node _io_imem_ready_T_1 = and(io.inst[0].ready, _io_imem_ready_T) node _io_imem_ready_T_2 = geq(nICReady, nIC) node _io_imem_ready_T_3 = sub(nIC, nICReady) node _io_imem_ready_T_4 = tail(_io_imem_ready_T_3, 1) node _io_imem_ready_T_5 = geq(UInt<1>(0h1), _io_imem_ready_T_4) node _io_imem_ready_T_6 = or(_io_imem_ready_T_2, _io_imem_ready_T_5) node _io_imem_ready_T_7 = and(_io_imem_ready_T_1, _io_imem_ready_T_6) connect io.imem.ready, _io_imem_ready_T_7 when io.inst[0].ready : node _nBufValid_T = geq(nReady, nBufValid) node _nBufValid_T_1 = eq(nBufValid, UInt<1>(0h0)) node _nBufValid_T_2 = or(_nBufValid_T, _nBufValid_T_1) node _nBufValid_T_3 = sub(nBufValid, nReady) node _nBufValid_T_4 = tail(_nBufValid_T_3, 1) node _nBufValid_T_5 = mux(_nBufValid_T_2, UInt<1>(0h0), _nBufValid_T_4) connect nBufValid, _nBufValid_T_5 node _T = geq(nReady, nBufValid) node _T_1 = and(io.imem.valid, _T) node _T_2 = lt(nICReady, nIC) node _T_3 = and(_T_1, _T_2) node _T_4 = sub(nIC, nICReady) node _T_5 = tail(_T_4, 1) node _T_6 = geq(UInt<1>(0h1), _T_5) node _T_7 = and(_T_3, _T_6) when _T_7 : node _shamt_T = add(pcWordBits, nICReady) node shamt = tail(_shamt_T, 1) node _nBufValid_T_6 = sub(nIC, nICReady) node _nBufValid_T_7 = tail(_nBufValid_T_6, 1) connect nBufValid, _nBufValid_T_7 connect buf, io.imem.bits node _buf_data_data_T = shr(io.imem.bits.data, 16) node _buf_data_data_T_1 = cat(_buf_data_data_T, _buf_data_data_T) node buf_data_data = cat(_buf_data_data_T_1, io.imem.bits.data) node _buf_data_T = shl(shamt, 4) node _buf_data_T_1 = dshr(buf_data_data, _buf_data_T) node _buf_data_T_2 = bits(_buf_data_T_1, 15, 0) connect buf.data, _buf_data_T_2 node _buf_pc_T = not(UInt<34>(0h3)) node _buf_pc_T_1 = and(io.imem.bits.pc, _buf_pc_T) node _buf_pc_T_2 = shl(nICReady, 1) node _buf_pc_T_3 = add(io.imem.bits.pc, _buf_pc_T_2) node _buf_pc_T_4 = tail(_buf_pc_T_3, 1) node _buf_pc_T_5 = and(_buf_pc_T_4, UInt<34>(0h3)) node _buf_pc_T_6 = or(_buf_pc_T_1, _buf_pc_T_5) connect buf.pc, _buf_pc_T_6 connect ibufBTBResp, io.imem.bits.btb when io.kill : connect nBufValid, UInt<1>(0h0) node _icShiftAmt_T = add(UInt<2>(0h2), nBufValid) node _icShiftAmt_T_1 = tail(_icShiftAmt_T, 1) node _icShiftAmt_T_2 = sub(_icShiftAmt_T_1, pcWordBits) node _icShiftAmt_T_3 = tail(_icShiftAmt_T_2, 1) node icShiftAmt = bits(_icShiftAmt_T_3, 1, 0) node _icData_T = bits(io.imem.bits.data, 15, 0) node _icData_T_1 = cat(_icData_T, _icData_T) node _icData_T_2 = cat(io.imem.bits.data, _icData_T_1) node _icData_data_T = shr(_icData_T_2, 48) node _icData_data_T_1 = cat(_icData_data_T, _icData_data_T) node _icData_data_T_2 = cat(_icData_data_T_1, _icData_data_T_1) node icData_data = cat(_icData_data_T_2, _icData_T_2) node _icData_T_3 = shl(icShiftAmt, 4) node _icData_T_4 = dshl(icData_data, _icData_T_3) node icData = bits(_icData_T_4, 95, 64) node _icMask_T = not(UInt<32>(0h0)) node _icMask_T_1 = shl(nBufValid, 4) node _icMask_T_2 = dshl(_icMask_T, _icMask_T_1) node icMask = bits(_icMask_T_2, 31, 0) node _inst_T = and(icData, icMask) node _inst_T_1 = not(icMask) node _inst_T_2 = and(buf.data, _inst_T_1) node inst = or(_inst_T, _inst_T_2) node _valid_T = dshl(UInt<1>(0h1), nValid) node _valid_T_1 = sub(_valid_T, UInt<1>(0h1)) node _valid_T_2 = tail(_valid_T_1, 1) node valid = bits(_valid_T_2, 1, 0) node _bufMask_T = dshl(UInt<1>(0h1), nBufValid) node _bufMask_T_1 = sub(_bufMask_T, UInt<1>(0h1)) node bufMask = tail(_bufMask_T_1, 1) node _xcpt_T = bits(bufMask, 0, 0) node xcpt_0 = mux(_xcpt_T, buf.xcpt, io.imem.bits.xcpt) node _xcpt_T_1 = bits(bufMask, 1, 1) node xcpt_1 = mux(_xcpt_T_1, buf.xcpt, io.imem.bits.xcpt) node buf_replay = mux(buf.replay, bufMask, UInt<1>(0h0)) node _ic_replay_T = not(bufMask) node _ic_replay_T_1 = and(valid, _ic_replay_T) node _ic_replay_T_2 = mux(io.imem.bits.replay, _ic_replay_T_1, UInt<1>(0h0)) node ic_replay = or(buf_replay, _ic_replay_T_2) node _T_8 = eq(io.imem.valid, UInt<1>(0h0)) node _T_9 = eq(io.imem.bits.btb.taken, UInt<1>(0h0)) node _T_10 = or(_T_8, _T_9) node _T_11 = geq(io.imem.bits.btb.bridx, pcWordBits) node _T_12 = or(_T_10, _T_11) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IBuf.scala:79 assert(!io.imem.valid \|\| !io.imem.bits.btb.taken \|\| io.imem.bits.btb.bridx >= pcWordBits)\n") : printf assert(clock, _T_12, UInt<1>(0h1), "") : assert connect io.btb_resp, io.imem.bits.btb node _io_pc_T = gt(nBufValid, UInt<1>(0h0)) node _io_pc_T_1 = mux(_io_pc_T, buf.pc, io.imem.bits.pc) connect io.pc, _io_pc_T_1 inst exp of RVCExpander connect exp.clock, clock connect exp.reset, reset connect exp.io.in, inst connect io.inst[0].bits.inst, exp.io.out connect io.inst[0].bits.raw, inst node _replay_T = dshr(ic_replay, UInt<1>(0h0)) node _replay_T_1 = bits(_replay_T, 0, 0) node _replay_T_2 = eq(exp.io.rvc, UInt<1>(0h0)) node _replay_T_3 = add(UInt<1>(0h0), UInt<1>(0h1)) node _replay_T_4 = tail(_replay_T_3, 1) node _replay_T_5 = dshr(ic_replay, _replay_T_4) node _replay_T_6 = bits(_replay_T_5, 0, 0) node _replay_T_7 = and(_replay_T_2, _replay_T_6) node replay = or(_replay_T_1, _replay_T_7) node _full_insn_T = add(UInt<1>(0h0), UInt<1>(0h1)) node _full_insn_T_1 = tail(_full_insn_T, 1) node _full_insn_T_2 = dshr(valid, _full_insn_T_1) node _full_insn_T_3 = bits(_full_insn_T_2, 0, 0) node _full_insn_T_4 = or(exp.io.rvc, _full_insn_T_3) node _full_insn_T_5 = dshr(buf_replay, UInt<1>(0h0)) node _full_insn_T_6 = bits(_full_insn_T_5, 0, 0) node full_insn = or(_full_insn_T_4, _full_insn_T_6) node _io_inst_0_valid_T = dshr(valid, UInt<1>(0h0)) node _io_inst_0_valid_T_1 = bits(_io_inst_0_valid_T, 0, 0) node _io_inst_0_valid_T_2 = and(_io_inst_0_valid_T_1, full_insn) connect io.inst[0].valid, _io_inst_0_valid_T_2 node _io_inst_0_bits_xcpt0_T = eq(UInt<1>(0h0), UInt<1>(0h1)) node _io_inst_0_bits_xcpt0_T_1 = mux(_io_inst_0_bits_xcpt0_T, xcpt_1, xcpt_0) connect io.inst[0].bits.xcpt0, _io_inst_0_bits_xcpt0_T_1 node _io_inst_0_bits_xcpt1_T = add(UInt<1>(0h0), UInt<1>(0h1)) node _io_inst_0_bits_xcpt1_T_1 = tail(_io_inst_0_bits_xcpt1_T, 1) node _io_inst_0_bits_xcpt1_T_2 = eq(_io_inst_0_bits_xcpt1_T_1, UInt<1>(0h1)) node _io_inst_0_bits_xcpt1_T_3 = mux(_io_inst_0_bits_xcpt1_T_2, xcpt_1, xcpt_0) node io_inst_0_bits_xcpt1_hi = cat(_io_inst_0_bits_xcpt1_T_3.pf.inst, _io_inst_0_bits_xcpt1_T_3.gf.inst) node _io_inst_0_bits_xcpt1_T_4 = cat(io_inst_0_bits_xcpt1_hi, _io_inst_0_bits_xcpt1_T_3.ae.inst) node _io_inst_0_bits_xcpt1_T_5 = mux(exp.io.rvc, UInt<1>(0h0), _io_inst_0_bits_xcpt1_T_4) wire _io_inst_0_bits_xcpt1_WIRE : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}} wire _io_inst_0_bits_xcpt1_WIRE_1 : UInt<3> connect _io_inst_0_bits_xcpt1_WIRE_1, _io_inst_0_bits_xcpt1_T_5 node _io_inst_0_bits_xcpt1_T_6 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 0, 0) connect _io_inst_0_bits_xcpt1_WIRE.ae.inst, _io_inst_0_bits_xcpt1_T_6 node _io_inst_0_bits_xcpt1_T_7 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 1, 1) connect _io_inst_0_bits_xcpt1_WIRE.gf.inst, _io_inst_0_bits_xcpt1_T_7 node _io_inst_0_bits_xcpt1_T_8 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 2, 2) connect _io_inst_0_bits_xcpt1_WIRE.pf.inst, _io_inst_0_bits_xcpt1_T_8 connect io.inst[0].bits.xcpt1, _io_inst_0_bits_xcpt1_WIRE connect io.inst[0].bits.replay, replay connect io.inst[0].bits.rvc, exp.io.rvc node _T_16 = dshr(bufMask, UInt<1>(0h0)) node _T_17 = bits(_T_16, 0, 0) node _T_18 = and(_T_17, exp.io.rvc) node _T_19 = add(UInt<1>(0h0), UInt<1>(0h1)) node _T_20 = tail(_T_19, 1) node _T_21 = dshr(bufMask, _T_20) node _T_22 = bits(_T_21, 0, 0) node _T_23 = or(_T_18, _T_22) when _T_23 : connect io.btb_resp, ibufBTBResp node _T_24 = or(UInt<1>(0h1), io.inst[0].ready) node _T_25 = and(full_insn, _T_24) when _T_25 : node _nReady_T = add(UInt<1>(0h0), UInt<1>(0h1)) node _nReady_T_1 = tail(_nReady_T, 1) node _nReady_T_2 = add(UInt<1>(0h0), UInt<2>(0h2)) node _nReady_T_3 = tail(_nReady_T_2, 1) node _nReady_T_4 = mux(exp.io.rvc, _nReady_T_1, _nReady_T_3) connect nReady, _nReady_T_4 node _T_26 = add(UInt<1>(0h0), UInt<1>(0h1)) node _T_27 = tail(_T_26, 1) node _T_28 = add(UInt<1>(0h0), UInt<2>(0h2)) node _T_29 = tail(_T_28, 1) node _T_30 = mux(exp.io.rvc, _T_27, _T_29) node _T_31 = shr(inst, 16) node _T_32 = shr(inst, 32) node _T_33 = mux(exp.io.rvc, _T_31, _T_32)	module IBuf( // @[IBuf.scala:21:7] input clock, // @[IBuf.scala:21:7] input reset, // @[IBuf.scala:21:7] output io_imem_ready, // @[IBuf.scala:22:14] input io_imem_valid, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_btb_cfiType, // @[IBuf.scala:22:14] input io_imem_bits_btb_taken, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_btb_mask, // @[IBuf.scala:22:14] input io_imem_bits_btb_bridx, // @[IBuf.scala:22:14] input [32:0] io_imem_bits_btb_target, // @[IBuf.scala:22:14] input [4:0] io_imem_bits_btb_entry, // @[IBuf.scala:22:14] input [7:0] io_imem_bits_btb_bht_history, // @[IBuf.scala:22:14] input io_imem_bits_btb_bht_value, // @[IBuf.scala:22:14] input [33:0] io_imem_bits_pc, // @[IBuf.scala:22:14] input [31:0] io_imem_bits_data, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_mask, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_pf_inst, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_gf_inst, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_ae_inst, // @[IBuf.scala:22:14] input io_imem_bits_replay, // @[IBuf.scala:22:14] input io_kill, // @[IBuf.scala:22:14] output [33:0] io_pc, // @[IBuf.scala:22:14] output [1:0] io_btb_resp_cfiType, // @[IBuf.scala:22:14] output io_btb_resp_taken, // @[IBuf.scala:22:14] output [1:0] io_btb_resp_mask, // @[IBuf.scala:22:14] output io_btb_resp_bridx, // @[IBuf.scala:22:14] output [32:0] io_btb_resp_target, // @[IBuf.scala:22:14] output [4:0] io_btb_resp_entry, // @[IBuf.scala:22:14] output [7:0] io_btb_resp_bht_history, // @[IBuf.scala:22:14] output io_btb_resp_bht_value, // @[IBuf.scala:22:14] input io_inst_0_ready, // @[IBuf.scala:22:14] output io_inst_0_valid, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_pf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_gf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_ae_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_pf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_gf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_ae_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_replay, // @[IBuf.scala:22:14] output io_inst_0_bits_rvc, // @[IBuf.scala:22:14] output [31:0] io_inst_0_bits_inst_bits, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rd, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs1, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs2, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs3, // @[IBuf.scala:22:14] output [31:0] io_inst_0_bits_raw // @[IBuf.scala:22:14] ); wire _exp_io_rvc; // @[IBuf.scala:86:21] wire io_imem_valid_0 = io_imem_valid; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_btb_cfiType_0 = io_imem_bits_btb_cfiType; // @[IBuf.scala:21:7] wire io_imem_bits_btb_taken_0 = io_imem_bits_btb_taken; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_btb_mask_0 = io_imem_bits_btb_mask; // @[IBuf.scala:21:7] wire io_imem_bits_btb_bridx_0 = io_imem_bits_btb_bridx; // @[IBuf.scala:21:7] wire [32:0] io_imem_bits_btb_target_0 = io_imem_bits_btb_target; // @[IBuf.scala:21:7] wire [4:0] io_imem_bits_btb_entry_0 = io_imem_bits_btb_entry; // @[IBuf.scala:21:7] wire [7:0] io_imem_bits_btb_bht_history_0 = io_imem_bits_btb_bht_history; // @[IBuf.scala:21:7] wire io_imem_bits_btb_bht_value_0 = io_imem_bits_btb_bht_value; // @[IBuf.scala:21:7] wire [33:0] io_imem_bits_pc_0 = io_imem_bits_pc; // @[IBuf.scala:21:7] wire [31:0] io_imem_bits_data_0 = io_imem_bits_data; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_mask_0 = io_imem_bits_mask; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_pf_inst_0 = io_imem_bits_xcpt_pf_inst; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_gf_inst_0 = io_imem_bits_xcpt_gf_inst; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_ae_inst_0 = io_imem_bits_xcpt_ae_inst; // @[IBuf.scala:21:7] wire io_imem_bits_replay_0 = io_imem_bits_replay; // @[IBuf.scala:21:7] wire io_kill_0 = io_kill; // @[IBuf.scala:21:7] wire io_inst_0_ready_0 = io_inst_0_ready; // @[IBuf.scala:21:7] wire [1:0] _replay_T_3 = 2'h1; // @[IBuf.scala:92:63] wire [1:0] _full_insn_T = 2'h1; // @[IBuf.scala:93:44] wire [1:0] _io_inst_0_bits_xcpt1_T = 2'h1; // @[IBuf.scala:96:59] wire [1:0] _nReady_T = 2'h1; // @[IBuf.scala:102:89] wire [1:0] _nReady_T_3 = 2'h2; // @[IBuf.scala:102:96] wire _replay_T_4 = 1'h1; // @[IBuf.scala:92:63] wire _full_insn_T_1 = 1'h1; // @[IBuf.scala:93:44] wire _io_inst_0_bits_xcpt1_T_1 = 1'h1; // @[IBuf.scala:96:59] wire _io_inst_0_bits_xcpt1_T_2 = 1'h1; // @[package.scala:39:86] wire _nReady_T_1 = 1'h1; // @[IBuf.scala:102:89] wire _io_inst_0_bits_xcpt0_T = 1'h0; // @[package.scala:39:86] wire [31:0] _icMask_T = 32'hFFFFFFFF; // @[IBuf.scala:71:17] wire [33:0] _buf_pc_T = 34'h3FFFFFFFC; // @[IBuf.scala:59:37] wire [2:0] _nReady_T_2 = 3'h2; // @[IBuf.scala:102:96] wire _io_imem_ready_T_7; // @[IBuf.scala:44:60] wire [33:0] _io_pc_T_1; // @[IBuf.scala:82:15] wire _io_inst_0_valid_T_2; // @[IBuf.scala:94:36] wire _io_inst_0_bits_xcpt0_T_1_pf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt0_T_1_gf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt0_T_1_ae_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_WIRE_pf_inst; // @[IBuf.scala:96:81] wire _io_inst_0_bits_xcpt1_WIRE_gf_inst; // @[IBuf.scala:96:81] wire _io_inst_0_bits_xcpt1_WIRE_ae_inst; // @[IBuf.scala:96:81] wire replay; // @[IBuf.scala:92:33] wire [31:0] inst; // @[IBuf.scala:72:30] wire io_imem_ready_0; // @[IBuf.scala:21:7] wire [7:0] io_btb_resp_bht_history_0; // @[IBuf.scala:21:7] wire io_btb_resp_bht_value_0; // @[IBuf.scala:21:7] wire [1:0] io_btb_resp_cfiType_0; // @[IBuf.scala:21:7] wire io_btb_resp_taken_0; // @[IBuf.scala:21:7] wire [1:0] io_btb_resp_mask_0; // @[IBuf.scala:21:7] wire io_btb_resp_bridx_0; // @[IBuf.scala:21:7] wire [32:0] io_btb_resp_target_0; // @[IBuf.scala:21:7] wire [4:0] io_btb_resp_entry_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_pf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_gf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_ae_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_pf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_gf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_ae_inst_0; // @[IBuf.scala:21:7] wire [31:0] io_inst_0_bits_inst_bits_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rd_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs1_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs2_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs3_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_replay_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_rvc_0; // @[IBuf.scala:21:7] wire [31:0] io_inst_0_bits_raw_0; // @[IBuf.scala:21:7] wire io_inst_0_valid_0; // @[IBuf.scala:21:7] wire [33:0] io_pc_0; // @[IBuf.scala:21:7] reg nBufValid; // @[IBuf.scala:34:47] wire _io_pc_T = nBufValid; // @[IBuf.scala:34:47, :82:26] reg [1:0] buf_btb_cfiType; // @[IBuf.scala:35:16] reg buf_btb_taken; // @[IBuf.scala:35:16] reg [1:0] buf_btb_mask; // @[IBuf.scala:35:16] reg buf_btb_bridx; // @[IBuf.scala:35:16] reg [32:0] buf_btb_target; // @[IBuf.scala:35:16] reg [4:0] buf_btb_entry; // @[IBuf.scala:35:16] reg [7:0] buf_btb_bht_history; // @[IBuf.scala:35:16] reg buf_btb_bht_value; // @[IBuf.scala:35:16] reg [33:0] buf_pc; // @[IBuf.scala:35:16] reg [31:0] buf_data; // @[IBuf.scala:35:16] reg [1:0] buf_mask; // @[IBuf.scala:35:16] reg buf_xcpt_pf_inst; // @[IBuf.scala:35:16] reg buf_xcpt_gf_inst; // @[IBuf.scala:35:16] reg buf_xcpt_ae_inst; // @[IBuf.scala:35:16] reg buf_replay; // @[IBuf.scala:35:16] reg [1:0] ibufBTBResp_cfiType; // @[IBuf.scala:36:24] reg ibufBTBResp_taken; // @[IBuf.scala:36:24] reg [1:0] ibufBTBResp_mask; // @[IBuf.scala:36:24] reg ibufBTBResp_bridx; // @[IBuf.scala:36:24] reg [32:0] ibufBTBResp_target; // @[IBuf.scala:36:24] reg [4:0] ibufBTBResp_entry; // @[IBuf.scala:36:24] reg [7:0] ibufBTBResp_bht_history; // @[IBuf.scala:36:24] reg ibufBTBResp_bht_value; // @[IBuf.scala:36:24] wire pcWordBits = io_imem_bits_pc_0[1]; // @[package.scala:163:13] wire [1:0] nReady; // @[IBuf.scala:40:27] wire [1:0] _nIC_T = {1'h0, io_imem_bits_btb_bridx_0} + 2'h1; // @[IBuf.scala:21:7, :41:64] wire [1:0] _nIC_T_1 = io_imem_bits_btb_taken_0 ? _nIC_T : 2'h2; // @[IBuf.scala:21:7, :41:{16,64}] wire [2:0] _GEN = {2'h0, pcWordBits}; // @[package.scala:163:13] wire [2:0] _nIC_T_2 = {1'h0, _nIC_T_1} - _GEN; // @[IBuf.scala:41:{16,86}] wire [1:0] nIC = _nIC_T_2[1:0]; // @[IBuf.scala:41:86] wire [2:0] _GEN_0 = {1'h0, nReady}; // @[IBuf.scala:40:27, :42:25] wire [2:0] _GEN_1 = {2'h0, nBufValid}; // @[IBuf.scala:34:47, :42:25] wire [2:0] _nICReady_T = _GEN_0 - _GEN_1; // @[IBuf.scala:42:25] wire [1:0] nICReady = _nICReady_T[1:0]; // @[IBuf.scala:42:25] wire [1:0] _nValid_T = io_imem_valid_0 ? nIC : 2'h0; // @[IBuf.scala:21:7, :41:86, :43:19] wire [2:0] _nValid_T_1 = {1'h0, _nValid_T} + _GEN_1; // @[IBuf.scala:42:25, :43:{19,45}] wire [1:0] nValid = _nValid_T_1[1:0]; // @[IBuf.scala:43:45] wire [1:0] _GEN_2 = {1'h0, nBufValid}; // @[IBuf.scala:34:47, :44:47] wire _T = nReady >= _GEN_2; // @[IBuf.scala:40:27, :44:47] wire _io_imem_ready_T; // @[IBuf.scala:44:47] assign _io_imem_ready_T = _T; // @[IBuf.scala:44:47] wire _nBufValid_T; // @[package.scala:218:33] assign _nBufValid_T = _T; // @[package.scala:218:33] wire _io_imem_ready_T_1 = io_inst_0_ready_0 & _io_imem_ready_T; // @[IBuf.scala:21:7, :44:{37,47}] wire _io_imem_ready_T_2 = nICReady >= nIC; // @[IBuf.scala:41:86, :42:25, :44:73] wire [2:0] _GEN_3 = {1'h0, nICReady}; // @[IBuf.scala:42:25, :44:94] wire [2:0] _T_4 = {1'h0, nIC} - _GEN_3; // @[IBuf.scala:41:86, :44:94] wire [2:0] _io_imem_ready_T_3; // @[IBuf.scala:44:94] assign _io_imem_ready_T_3 = _T_4; // @[IBuf.scala:44:94] wire [2:0] _nBufValid_T_6; // @[IBuf.scala:56:26] assign _nBufValid_T_6 = _T_4; // @[IBuf.scala:44:94, :56:26] wire [1:0] _io_imem_ready_T_4 = _io_imem_ready_T_3[1:0]; // @[IBuf.scala:44:94] wire _io_imem_ready_T_5 = ~(_io_imem_ready_T_4[1]); // @[IBuf.scala:44:{87,94}] wire _io_imem_ready_T_6 = _io_imem_ready_T_2 \| _io_imem_ready_T_5; // @[IBuf.scala:44:{73,80,87}] assign _io_imem_ready_T_7 = _io_imem_ready_T_1 & _io_imem_ready_T_6; // @[IBuf.scala:44:{37,60,80}] assign io_imem_ready_0 = _io_imem_ready_T_7; // @[IBuf.scala:21:7, :44:60] wire _nBufValid_T_1 = ~nBufValid; // @[package.scala:218:43] wire _nBufValid_T_2 = _nBufValid_T \| _nBufValid_T_1; // @[package.scala:218:{33,38,43}] wire [2:0] _nBufValid_T_3 = _GEN_1 - _GEN_0; // @[IBuf.scala:42:25, :48:61] wire [1:0] _nBufValid_T_4 = _nBufValid_T_3[1:0]; // @[IBuf.scala:48:61] wire [1:0] _nBufValid_T_5 = _nBufValid_T_2 ? 2'h0 : _nBufValid_T_4; // @[package.scala:218:38] wire [2:0] _shamt_T = _GEN + _GEN_3; // @[IBuf.scala:41:86, :44:94, :55:32] wire [1:0] shamt = _shamt_T[1:0]; // @[IBuf.scala:55:32] wire [1:0] _nBufValid_T_7 = _nBufValid_T_6[1:0]; // @[IBuf.scala:56:26] wire [15:0] _buf_data_data_T = io_imem_bits_data_0[31:16]; // @[IBuf.scala:21:7, :127:58] wire [31:0] _buf_data_data_T_1 = {2{_buf_data_data_T}}; // @[IBuf.scala:127:{24,58}] wire [63:0] buf_data_data = {_buf_data_data_T_1, io_imem_bits_data_0}; // @[IBuf.scala:21:7, :127:{19,24}] wire [5:0] _buf_data_T = {shamt, 4'h0}; // @[IBuf.scala:55:32, :128:19] wire [63:0] _buf_data_T_1 = buf_data_data >> _buf_data_T; // @[IBuf.scala:127:19, :128:{10,19}] wire [15:0] _buf_data_T_2 = _buf_data_T_1[15:0]; // @[IBuf.scala:58:61, :128:10] wire [33:0] _buf_pc_T_1 = io_imem_bits_pc_0 & 34'h3FFFFFFFC; // @[IBuf.scala:21:7, :59:35] wire [2:0] _buf_pc_T_2 = {nICReady, 1'h0}; // @[IBuf.scala:42:25, :59:80] wire [34:0] _buf_pc_T_3 = {1'h0, io_imem_bits_pc_0} + {32'h0, _buf_pc_T_2}; // @[IBuf.scala:21:7, :59:{68,80}] wire [33:0] _buf_pc_T_4 = _buf_pc_T_3[33:0]; // @[IBuf.scala:59:68] wire [33:0] _buf_pc_T_5 = _buf_pc_T_4 & 34'h3; // @[IBuf.scala:59:{68,109}] wire [33:0] _buf_pc_T_6 = _buf_pc_T_1 \| _buf_pc_T_5; // @[IBuf.scala:59:{35,49,109}] wire [2:0] _icShiftAmt_T = _GEN_1 + 3'h2; // @[IBuf.scala:42:25, :68:34] wire [1:0] _icShiftAmt_T_1 = _icShiftAmt_T[1:0]; // @[IBuf.scala:68:34] wire [2:0] _icShiftAmt_T_2 = {1'h0, _icShiftAmt_T_1} - _GEN; // @[IBuf.scala:41:86, :68:{34,46}] wire [1:0] _icShiftAmt_T_3 = _icShiftAmt_T_2[1:0]; // @[IBuf.scala:68:46] wire [1:0] icShiftAmt = _icShiftAmt_T_3; // @[IBuf.scala:68:{46,59}] wire [15:0] _icData_T = io_imem_bits_data_0[15:0]; // @[IBuf.scala:21:7, :69:87] wire [31:0] _icData_T_1 = {2{_icData_T}}; // @[IBuf.scala:69:{57,87}] wire [63:0] _icData_T_2 = {io_imem_bits_data_0, _icData_T_1}; // @[IBuf.scala:21:7, :69:{33,57}] wire [15:0] _icData_data_T = _icData_T_2[63:48]; // @[IBuf.scala:69:33, :120:58] wire [31:0] _icData_data_T_1 = {2{_icData_data_T}}; // @[IBuf.scala:120:{24,58}] wire [63:0] _icData_data_T_2 = {2{_icData_data_T_1}}; // @[IBuf.scala:120:24] wire [127:0] icData_data = {_icData_data_T_2, _icData_T_2}; // @[IBuf.scala:69:33, :120:{19,24}] wire [5:0] _icData_T_3 = {icShiftAmt, 4'h0}; // @[IBuf.scala:68:59, :121:19] wire [190:0] _icData_T_4 = {63'h0, icData_data} << _icData_T_3; // @[IBuf.scala:120:19, :121:{10,19}] wire [31:0] icData = _icData_T_4[95:64]; // @[package.scala:163:13] wire [4:0] _icMask_T_1 = {nBufValid, 4'h0}; // @[IBuf.scala:34:47, :71:65] wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << _icMask_T_1; // @[IBuf.scala:71:{51,65}] wire [31:0] icMask = _icMask_T_2[31:0]; // @[IBuf.scala:71:{51,92}] wire [31:0] _inst_T = icData & icMask; // @[package.scala:163:13] wire [31:0] _inst_T_1 = ~icMask; // @[IBuf.scala:71:92, :72:43] wire [31:0] _inst_T_2 = buf_data & _inst_T_1; // @[IBuf.scala:35:16, :72:{41,43}] assign inst = _inst_T \| _inst_T_2; // @[IBuf.scala:72:{21,30,41}] assign io_inst_0_bits_raw_0 = inst; // @[IBuf.scala:21:7, :72:30] wire [3:0] _valid_T = 4'h1 << nValid; // @[OneHot.scala:58:35] wire [4:0] _valid_T_1 = {1'h0, _valid_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _valid_T_2 = _valid_T_1[3:0]; // @[IBuf.scala:74:33] wire [1:0] valid = _valid_T_2[1:0]; // @[IBuf.scala:74:{33,39}] wire [1:0] _io_inst_0_valid_T = valid; // @[IBuf.scala:74:39, :94:32] wire [1:0] _bufMask_T = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [2:0] _bufMask_T_1 = {1'h0, _bufMask_T} - 3'h1; // @[OneHot.scala:58:35] wire [1:0] bufMask = _bufMask_T_1[1:0]; // @[IBuf.scala:75:37] wire _xcpt_T = bufMask[0]; // @[IBuf.scala:75:37, :76:61] wire xcpt_0_pf_inst = _xcpt_T ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_0_gf_inst = _xcpt_T ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_0_ae_inst = _xcpt_T ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] assign _io_inst_0_bits_xcpt0_T_1_pf_inst = xcpt_0_pf_inst; // @[package.scala:39:76] assign _io_inst_0_bits_xcpt0_T_1_gf_inst = xcpt_0_gf_inst; // @[package.scala:39:76] assign _io_inst_0_bits_xcpt0_T_1_ae_inst = xcpt_0_ae_inst; // @[package.scala:39:76] wire _xcpt_T_1 = bufMask[1]; // @[IBuf.scala:75:37, :76:61] wire xcpt_1_pf_inst = _xcpt_T_1 ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_1_gf_inst = _xcpt_T_1 ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_1_ae_inst = _xcpt_T_1 ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire _io_inst_0_bits_xcpt1_T_3_pf_inst = xcpt_1_pf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_T_3_gf_inst = xcpt_1_gf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_T_3_ae_inst = xcpt_1_ae_inst; // @[package.scala:39:76] wire [1:0] buf_replay_0 = buf_replay ? bufMask : 2'h0; // @[IBuf.scala:35:16, :75:37, :77:23] wire [1:0] _full_insn_T_5 = buf_replay_0; // @[IBuf.scala:77:23, :93:63] wire [1:0] _ic_replay_T = ~bufMask; // @[IBuf.scala:75:37, :78:65] wire [1:0] _ic_replay_T_1 = valid & _ic_replay_T; // @[IBuf.scala:74:39, :78:{63,65}] wire [1:0] _ic_replay_T_2 = io_imem_bits_replay_0 ? _ic_replay_T_1 : 2'h0; // @[IBuf.scala:21:7, :78:{35,63}] wire [1:0] ic_replay = buf_replay_0 \| _ic_replay_T_2; // @[IBuf.scala:77:23, :78:{30,35}] wire [1:0] _replay_T = ic_replay; // @[IBuf.scala:78:30, :92:29]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_76 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}} wire _in_flight_WIRE : UInt<1>[5] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = or(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_16 = or(_T_15, UInt<1>(0h0)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_21 = or(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_21, UInt<1>(0h1), "") : assert_4 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_28 = and(_T_26, _T_27) node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_32 = and(_T_30, _T_31) node _T_33 = or(_T_25, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_33, UInt<1>(0h1), "") : assert_5	module NoCMonitor_76( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_prcibus_i1_o2_a21d64s10k1z3u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_109 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<10>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<10>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<10>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 9, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<21>(0h0) connect _WIRE_30.bits.source, UInt<10>(0h0) connect _WIRE_30.bits.size, UInt<3>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<21>(0h0) connect _WIRE_32.bits.source, UInt<10>(0h0) connect _WIRE_32.bits.size, UInt<3>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<21>(0h0) connect _WIRE_34.bits.source, UInt<10>(0h0) connect _WIRE_34.bits.size, UInt<3>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<21>(0h0) connect _WIRE_36.bits.source, UInt<10>(0h0) connect _WIRE_36.bits.size, UInt<3>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<21>(0h0) connect _WIRE_38.bits.source, UInt<10>(0h0) connect _WIRE_38.bits.size, UInt<3>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<21>(0h0) connect _WIRE_48.bits.source, UInt<10>(0h0) connect _WIRE_48.bits.size, UInt<3>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<21>(0h0) connect _WIRE_50.bits.source, UInt<10>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<21>(0h0) connect _WIRE_52.bits.source, UInt<10>(0h0) connect _WIRE_52.bits.size, UInt<3>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<21>(0h0) connect _WIRE_54.bits.source, UInt<10>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<21>(0h0) connect _WIRE_56.bits.source, UInt<10>(0h0) connect _WIRE_56.bits.size, UInt<3>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<21>(0h0) connect _WIRE_58.bits.source, UInt<10>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<21>(0h0) connect _WIRE_60.bits.source, UInt<10>(0h0) connect _WIRE_60.bits.size, UInt<3>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<21>(0h0) connect _WIRE_62.bits.source, UInt<10>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<21>(0h0) connect _addressC_WIRE.bits.source, UInt<10>(0h0) connect _addressC_WIRE.bits.size, UInt<3>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<18>(0h10000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<18>(0h10000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<21>(0h0) connect _requestBOI_WIRE.bits.source, UInt<10>(0h0) connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<10>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 9, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 10) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<10>(0h3ff)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<21>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<10>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<10>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 9, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 10) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<10>(0h3ff)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<10>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 9, 0) node _requestDOI_T = shr(out[0].d.bits.source, 10) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<10>(0h3ff)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<10>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 9, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 10) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<10>(0h3ff)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<21>(0h0) connect _beatsBO_WIRE.bits.source, UInt<10>(0h0) connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<21>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<10>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<21>(0h0) connect _beatsCI_WIRE.bits.source, UInt<10>(0h0) connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<21>(0h0) connect _portsBIO_WIRE.bits.source, UInt<10>(0h0) connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<21>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<10>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<21>(0h0) connect _portsCOI_WIRE.bits.source, UInt<10>(0h0) connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<21>(0h0) connect _WIRE_72.bits.source, UInt<10>(0h0) connect _WIRE_72.bits.size, UInt<3>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.address, UInt<21>(0h0) connect _WIRE_76.bits.source, UInt<10>(0h0) connect _WIRE_76.bits.size, UInt<3>(0h0) connect _WIRE_76.bits.param, UInt<3>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_78.bits.sink, UInt<1>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.mask, UInt<8>(0h0) connect _WIRE_80.bits.address, UInt<21>(0h0) connect _WIRE_80.bits.source, UInt<10>(0h0) connect _WIRE_80.bits.size, UInt<3>(0h0) connect _WIRE_80.bits.param, UInt<2>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.mask invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<10> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<3> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)	module TLXbar_prcibus_i1_o2_a21d64s10k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire [9:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [9:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [63:0] auto_anon_out_1_d_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] out_1_d_bits_data = 64'h0; // @[Xbar.scala:216:19] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _in_0_d_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_WIRE_param = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_denied = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _out_1_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_WIRE_sink = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_denied = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_10 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_11 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_6 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [20:0] _addressC_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _addressC_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _requestCIO_T = 21'h0; // @[Parameters.scala:137:31] wire [20:0] _requestCIO_T_5 = 21'h0; // @[Parameters.scala:137:31] wire [20:0] _requestBOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _requestBOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _requestBOI_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _requestBOI_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsBO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _beatsBO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsBO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _beatsBO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsCI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _beatsCI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _portsBIO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _portsBIO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] portsBIO_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] _portsBIO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _portsBIO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] portsBIO_filtered_1_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] _portsCOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _portsCOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] portsCOI_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] portsCOI_filtered_1_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [9:0] _addressC_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _addressC_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _requestBOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _requestBOI_uncommonBits_T = 10'h0; // @[Parameters.scala:52:29] wire [9:0] requestBOI_uncommonBits = 10'h0; // @[Parameters.scala:52:56] wire [9:0] _requestBOI_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _requestBOI_uncommonBits_T_1 = 10'h0; // @[Parameters.scala:52:29] wire [9:0] requestBOI_uncommonBits_1 = 10'h0; // @[Parameters.scala:52:56] wire [9:0] _beatsBO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _beatsBO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsBO_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _beatsBO_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsCI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _beatsCI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _portsBIO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _portsBIO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] portsBIO_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsBIO_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _portsBIO_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] portsBIO_filtered_1_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsCOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _portsCOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] portsCOI_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] portsCOI_filtered_1_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [21:0] _requestCIO_T_1 = 22'h0; // @[Parameters.scala:137:41] wire [21:0] _requestCIO_T_2 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_3 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_6 = 22'h0; // @[Parameters.scala:137:41] wire [21:0] _requestCIO_T_7 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_8 = 22'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [9:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [9:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [20:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [9:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [9:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [20:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [20:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [20:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [9:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [9:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [9:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [21:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] _requestAIO_T_2 = _requestAIO_T_1 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 22'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [20:0] _requestAIO_T_5 = {in_0_a_bits_address[20:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [21:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [21:0] _requestAIO_T_7 = _requestAIO_T_6 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 22'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [9:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [9:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T \| _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid \| portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to this FIRRTL code module PE_402 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_146 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_402( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_146 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FlitToPhit_f32_p32 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}} reg data : UInt<32>[0], clock regreset beat : UInt<0>, clock, reset, UInt<0>(0h0) node _io_in_ready_T = eq(beat, UInt<1>(0h0)) node _io_in_ready_T_1 = and(io.out.ready, _io_in_ready_T) connect io.in.ready, _io_in_ready_T_1 node _io_out_valid_T = neq(beat, UInt<1>(0h0)) node _io_out_valid_T_1 = or(io.in.valid, _io_out_valid_T) connect io.out.valid, _io_out_valid_T_1 connect io.out.bits.phit, io.in.bits.flit node _T = and(io.out.ready, io.out.valid) when _T : node _beat_T = eq(beat, UInt<1>(0h0)) node _beat_T_1 = add(beat, UInt<1>(0h1)) node _beat_T_2 = tail(_beat_T_1, 1) node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2) connect beat, _beat_T_3 node _T_1 = eq(beat, UInt<1>(0h0)) when _T_1 : wire _WIRE : UInt<32>[1] wire _WIRE_1 : UInt<32> connect _WIRE_1, io.in.bits.flit node _T_2 = bits(_WIRE_1, 31, 0) connect _WIRE[0], _T_2	module FlitToPhit_f32_p32( // @[Serdes.scala:71:7] input clock, // @[Serdes.scala:71:7] input reset, // @[Serdes.scala:71:7] output io_in_ready, // @[Serdes.scala:73:14] input io_in_valid, // @[Serdes.scala:73:14] input [31:0] io_in_bits_flit, // @[Serdes.scala:73:14] input io_out_ready, // @[Serdes.scala:73:14] output io_out_valid, // @[Serdes.scala:73:14] output [31:0] io_out_bits_phit // @[Serdes.scala:73:14] ); wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:71:7] wire [31:0] io_in_bits_flit_0 = io_in_bits_flit; // @[Serdes.scala:71:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:71:7] wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T = 1'h1; // @[Serdes.scala:83:39] wire _beat_T = 1'h1; // @[Serdes.scala:88:22] wire _beat_T_2 = 1'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T_1; // @[Serdes.scala:83:31] wire _io_out_valid_T = 1'h0; // @[Serdes.scala:84:39] wire _beat_T_3 = 1'h0; // @[Serdes.scala:88:16] wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:71:7, :84:31] wire [31:0] io_out_bits_phit_0 = io_in_bits_flit_0; // @[Serdes.scala:71:7] assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:71:7, :83:31] wire io_in_ready_0; // @[Serdes.scala:71:7] wire io_out_valid_0; // @[Serdes.scala:71:7] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:71:7, :83:31] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:71:7, :84:31] assign io_in_ready = io_in_ready_0; // @[Serdes.scala:71:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:71:7] assign io_out_bits_phit = io_out_bits_phit_0; // @[Serdes.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_8 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<15>(0h4000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<13>(0h1000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<18>(0h2f000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<27>(0h4000000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_38, _T_43) node _T_85 = or(_T_84, _T_48) node _T_86 = or(_T_85, _T_53) node _T_87 = or(_T_86, _T_58) node _T_88 = or(_T_87, _T_63) node _T_89 = or(_T_88, _T_68) node _T_90 = or(_T_89, _T_73) node _T_91 = or(_T_90, _T_78) node _T_92 = or(_T_91, _T_83) node _T_93 = and(_T_33, _T_92) node _T_94 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_95 = or(UInt<1>(0h0), _T_94) node _T_96 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<17>(0h10000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<29>(0h10000000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = or(_T_100, _T_105) node _T_107 = and(_T_95, _T_106) node _T_108 = or(UInt<1>(0h0), _T_93) node _T_109 = or(_T_108, _T_107) node _T_110 = and(_T_32, _T_109) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_110, UInt<1>(0h1), "") : assert_2 node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_115 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_114 connect _WIRE[1], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = or(_T_117, _T_118) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_119 node _T_120 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_121 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_122 = and(_T_120, _T_121) node _T_123 = or(UInt<1>(0h0), _T_122) node _T_124 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_125 = cvt(_T_124) node _T_126 = and(_T_125, asSInt(UInt<14>(0h2000))) node _T_127 = asSInt(_T_126) node _T_128 = eq(_T_127, asSInt(UInt<1>(0h0))) node _T_129 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_130 = cvt(_T_129) node _T_131 = and(_T_130, asSInt(UInt<13>(0h1000))) node _T_132 = asSInt(_T_131) node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0))) node _T_134 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<17>(0h10000))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<15>(0h4000))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<13>(0h1000))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<18>(0h2f000))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<17>(0h10000))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<13>(0h1000))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<17>(0h10000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<27>(0h4000000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<13>(0h1000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<29>(0h10000000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = or(_T_128, _T_133) node _T_185 = or(_T_184, _T_138) node _T_186 = or(_T_185, _T_143) node _T_187 = or(_T_186, _T_148) node _T_188 = or(_T_187, _T_153) node _T_189 = or(_T_188, _T_158) node _T_190 = or(_T_189, _T_163) node _T_191 = or(_T_190, _T_168) node _T_192 = or(_T_191, _T_173) node _T_193 = or(_T_192, _T_178) node _T_194 = or(_T_193, _T_183) node _T_195 = and(_T_123, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = and(_WIRE_1, _T_196) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_197, UInt<1>(0h1), "") : assert_3 node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(source_ok, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_204 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_204, UInt<1>(0h1), "") : assert_5 node _T_208 = asUInt(reset) node _T_209 = eq(_T_208, UInt<1>(0h0)) when _T_209 : node _T_210 = eq(is_aligned, UInt<1>(0h0)) when _T_210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_211 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_211, UInt<1>(0h1), "") : assert_7 node _T_215 = not(io.in.a.bits.mask) node _T_216 = eq(_T_215, UInt<1>(0h0)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_216, UInt<1>(0h1), "") : assert_8 node _T_220 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_220, UInt<1>(0h1), "") : assert_9 node _T_224 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_224 : node _T_225 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_226 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_229 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_230 = or(_T_228, _T_229) node _T_231 = and(_T_227, _T_230) node _T_232 = or(UInt<1>(0h0), _T_231) node _T_233 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_240 = cvt(_T_239) node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000))) node _T_242 = asSInt(_T_241) node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0))) node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_245 = cvt(_T_244) node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000))) node _T_247 = asSInt(_T_246) node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0))) node _T_249 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<15>(0h4000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<13>(0h1000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<18>(0h2f000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<17>(0h10000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<27>(0h4000000))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<13>(0h1000))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = or(_T_238, _T_243) node _T_285 = or(_T_284, _T_248) node _T_286 = or(_T_285, _T_253) node _T_287 = or(_T_286, _T_258) node _T_288 = or(_T_287, _T_263) node _T_289 = or(_T_288, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = and(_T_233, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_232, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _T_314 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_314 connect _WIRE_2[1], _T_315 node _T_316 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_317 = mux(_WIRE_2[0], _T_316, UInt<1>(0h0)) node _T_318 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = or(_T_317, _T_318) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_319 node _T_320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_322 = and(_T_320, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<14>(0h2000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<13>(0h1000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<15>(0h4000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<18>(0h2f000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<17>(0h10000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<13>(0h1000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_365 = cvt(_T_364) node _T_366 = and(_T_365, asSInt(UInt<17>(0h10000))) node _T_367 = asSInt(_T_366) node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0))) node _T_369 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<27>(0h4000000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<13>(0h1000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<29>(0h10000000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = or(_T_328, _T_333) node _T_385 = or(_T_384, _T_338) node _T_386 = or(_T_385, _T_343) node _T_387 = or(_T_386, _T_348) node _T_388 = or(_T_387, _T_353) node _T_389 = or(_T_388, _T_358) node _T_390 = or(_T_389, _T_363) node _T_391 = or(_T_390, _T_368) node _T_392 = or(_T_391, _T_373) node _T_393 = or(_T_392, _T_378) node _T_394 = or(_T_393, _T_383) node _T_395 = and(_T_323, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = and(_WIRE_3, _T_396) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_397, UInt<1>(0h1), "") : assert_11 node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(source_ok, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_404 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_404, UInt<1>(0h1), "") : assert_13 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(is_aligned, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_411 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_411, UInt<1>(0h1), "") : assert_15 node _T_415 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_415, UInt<1>(0h1), "") : assert_16 node _T_419 = not(io.in.a.bits.mask) node _T_420 = eq(_T_419, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_420, UInt<1>(0h1), "") : assert_17 node _T_424 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_424, UInt<1>(0h1), "") : assert_18 node _T_428 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_428 : node _T_429 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_430 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_433 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_434 = or(_T_432, _T_433) node _T_435 = and(_T_431, _T_434) node _T_436 = or(UInt<1>(0h0), _T_435) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_436, UInt<1>(0h1), "") : assert_19 node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_442 = and(_T_440, _T_441) node _T_443 = or(UInt<1>(0h0), _T_442) node _T_444 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<13>(0h1000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = and(_T_443, _T_448) node _T_450 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_451 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_452 = and(_T_450, _T_451) node _T_453 = or(UInt<1>(0h0), _T_452) node _T_454 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<14>(0h2000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_460 = cvt(_T_459) node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000))) node _T_462 = asSInt(_T_461) node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0))) node _T_464 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_465 = cvt(_T_464) node _T_466 = and(_T_465, asSInt(UInt<18>(0h2f000))) node _T_467 = asSInt(_T_466) node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0))) node _T_469 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_470 = cvt(_T_469) node _T_471 = and(_T_470, asSInt(UInt<17>(0h10000))) node _T_472 = asSInt(_T_471) node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0))) node _T_474 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_475 = cvt(_T_474) node _T_476 = and(_T_475, asSInt(UInt<13>(0h1000))) node _T_477 = asSInt(_T_476) node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0))) node _T_479 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_480 = cvt(_T_479) node _T_481 = and(_T_480, asSInt(UInt<17>(0h10000))) node _T_482 = asSInt(_T_481) node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0))) node _T_484 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_485 = cvt(_T_484) node _T_486 = and(_T_485, asSInt(UInt<27>(0h4000000))) node _T_487 = asSInt(_T_486) node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0))) node _T_489 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_490 = cvt(_T_489) node _T_491 = and(_T_490, asSInt(UInt<13>(0h1000))) node _T_492 = asSInt(_T_491) node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0))) node _T_494 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<29>(0h10000000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = or(_T_458, _T_463) node _T_500 = or(_T_499, _T_468) node _T_501 = or(_T_500, _T_473) node _T_502 = or(_T_501, _T_478) node _T_503 = or(_T_502, _T_483) node _T_504 = or(_T_503, _T_488) node _T_505 = or(_T_504, _T_493) node _T_506 = or(_T_505, _T_498) node _T_507 = and(_T_453, _T_506) node _T_508 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_509 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_510 = and(_T_508, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<15>(0h4000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = or(_T_516, _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = or(UInt<1>(0h0), _T_449) node _T_525 = or(_T_524, _T_507) node _T_526 = or(_T_525, _T_523) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_526, UInt<1>(0h1), "") : assert_20 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(source_ok, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(is_aligned, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_536 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(_T_536, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_536, UInt<1>(0h1), "") : assert_23 node _T_540 = eq(io.in.a.bits.mask, mask) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_540, UInt<1>(0h1), "") : assert_24 node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_544, UInt<1>(0h1), "") : assert_25 node _T_548 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_553 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_554 = or(_T_552, _T_553) node _T_555 = and(_T_551, _T_554) node _T_556 = or(UInt<1>(0h0), _T_555) node _T_557 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_558 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_559 = and(_T_557, _T_558) node _T_560 = or(UInt<1>(0h0), _T_559) node _T_561 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<13>(0h1000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = and(_T_560, _T_565) node _T_567 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_568 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_569 = and(_T_567, _T_568) node _T_570 = or(UInt<1>(0h0), _T_569) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<14>(0h2000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<18>(0h2f000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<17>(0h10000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<13>(0h1000))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<17>(0h10000))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<27>(0h4000000))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_602 = cvt(_T_601) node _T_603 = and(_T_602, asSInt(UInt<13>(0h1000))) node _T_604 = asSInt(_T_603) node _T_605 = eq(_T_604, asSInt(UInt<1>(0h0))) node _T_606 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_607 = cvt(_T_606) node _T_608 = and(_T_607, asSInt(UInt<29>(0h10000000))) node _T_609 = asSInt(_T_608) node _T_610 = eq(_T_609, asSInt(UInt<1>(0h0))) node _T_611 = or(_T_575, _T_580) node _T_612 = or(_T_611, _T_585) node _T_613 = or(_T_612, _T_590) node _T_614 = or(_T_613, _T_595) node _T_615 = or(_T_614, _T_600) node _T_616 = or(_T_615, _T_605) node _T_617 = or(_T_616, _T_610) node _T_618 = and(_T_570, _T_617) node _T_619 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_620 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<15>(0h4000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = or(_T_634, _T_639) node _T_641 = and(_T_629, _T_640) node _T_642 = or(UInt<1>(0h0), _T_566) node _T_643 = or(_T_642, _T_618) node _T_644 = or(_T_643, _T_625) node _T_645 = or(_T_644, _T_641) node _T_646 = and(_T_556, _T_645) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_646, UInt<1>(0h1), "") : assert_26 node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(source_ok, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(is_aligned, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_656 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_657 = asUInt(reset) node _T_658 = eq(_T_657, UInt<1>(0h0)) when _T_658 : node _T_659 = eq(_T_656, UInt<1>(0h0)) when _T_659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_656, UInt<1>(0h1), "") : assert_29 node _T_660 = eq(io.in.a.bits.mask, mask) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_660, UInt<1>(0h1), "") : assert_30 node _T_664 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_664 : node _T_665 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_666 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_667 = and(_T_665, _T_666) node _T_668 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_669 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_670 = or(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) node _T_672 = or(UInt<1>(0h0), _T_671) node _T_673 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_674 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_675 = and(_T_673, _T_674) node _T_676 = or(UInt<1>(0h0), _T_675) node _T_677 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<13>(0h1000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = and(_T_676, _T_681) node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_685 = and(_T_683, _T_684) node _T_686 = or(UInt<1>(0h0), _T_685) node _T_687 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_688 = cvt(_T_687) node _T_689 = and(_T_688, asSInt(UInt<14>(0h2000))) node _T_690 = asSInt(_T_689) node _T_691 = eq(_T_690, asSInt(UInt<1>(0h0))) node _T_692 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_693 = cvt(_T_692) node _T_694 = and(_T_693, asSInt(UInt<18>(0h2f000))) node _T_695 = asSInt(_T_694) node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0))) node _T_697 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_698 = cvt(_T_697) node _T_699 = and(_T_698, asSInt(UInt<17>(0h10000))) node _T_700 = asSInt(_T_699) node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0))) node _T_702 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_703 = cvt(_T_702) node _T_704 = and(_T_703, asSInt(UInt<13>(0h1000))) node _T_705 = asSInt(_T_704) node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0))) node _T_707 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_708 = cvt(_T_707) node _T_709 = and(_T_708, asSInt(UInt<17>(0h10000))) node _T_710 = asSInt(_T_709) node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0))) node _T_712 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_713 = cvt(_T_712) node _T_714 = and(_T_713, asSInt(UInt<27>(0h4000000))) node _T_715 = asSInt(_T_714) node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0))) node _T_717 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_718 = cvt(_T_717) node _T_719 = and(_T_718, asSInt(UInt<13>(0h1000))) node _T_720 = asSInt(_T_719) node _T_721 = eq(_T_720, asSInt(UInt<1>(0h0))) node _T_722 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_723 = cvt(_T_722) node _T_724 = and(_T_723, asSInt(UInt<29>(0h10000000))) node _T_725 = asSInt(_T_724) node _T_726 = eq(_T_725, asSInt(UInt<1>(0h0))) node _T_727 = or(_T_691, _T_696) node _T_728 = or(_T_727, _T_701) node _T_729 = or(_T_728, _T_706) node _T_730 = or(_T_729, _T_711) node _T_731 = or(_T_730, _T_716) node _T_732 = or(_T_731, _T_721) node _T_733 = or(_T_732, _T_726) node _T_734 = and(_T_686, _T_733) node _T_735 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_736 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = and(_T_735, _T_740) node _T_742 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_743 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_744 = and(_T_742, _T_743) node _T_745 = or(UInt<1>(0h0), _T_744) node _T_746 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<15>(0h4000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = or(_T_750, _T_755) node _T_757 = and(_T_745, _T_756) node _T_758 = or(UInt<1>(0h0), _T_682) node _T_759 = or(_T_758, _T_734) node _T_760 = or(_T_759, _T_741) node _T_761 = or(_T_760, _T_757) node _T_762 = and(_T_672, _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_762, UInt<1>(0h1), "") : assert_31 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(source_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(is_aligned, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_772 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_772, UInt<1>(0h1), "") : assert_34 node _T_776 = not(mask) node _T_777 = and(io.in.a.bits.mask, _T_776) node _T_778 = eq(_T_777, UInt<1>(0h0)) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_778, UInt<1>(0h1), "") : assert_35 node _T_782 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_782 : node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_785 = and(_T_783, _T_784) node _T_786 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_787 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_788 = or(_T_786, _T_787) node _T_789 = and(_T_785, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<15>(0h4000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<18>(0h2f000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<17>(0h10000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<27>(0h4000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<29>(0h10000000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = or(_T_799, _T_804) node _T_851 = or(_T_850, _T_809) node _T_852 = or(_T_851, _T_814) node _T_853 = or(_T_852, _T_819) node _T_854 = or(_T_853, _T_824) node _T_855 = or(_T_854, _T_829) node _T_856 = or(_T_855, _T_834) node _T_857 = or(_T_856, _T_839) node _T_858 = or(_T_857, _T_844) node _T_859 = or(_T_858, _T_849) node _T_860 = and(_T_794, _T_859) node _T_861 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_862 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_863 = cvt(_T_862) node _T_864 = and(_T_863, asSInt(UInt<17>(0h10000))) node _T_865 = asSInt(_T_864) node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0))) node _T_867 = and(_T_861, _T_866) node _T_868 = or(UInt<1>(0h0), _T_860) node _T_869 = or(_T_868, _T_867) node _T_870 = and(_T_790, _T_869) node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(_T_870, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_870, UInt<1>(0h1), "") : assert_36 node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(source_ok, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(is_aligned, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_880 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_880, UInt<1>(0h1), "") : assert_39 node _T_884 = eq(io.in.a.bits.mask, mask) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_884, UInt<1>(0h1), "") : assert_40 node _T_888 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_888 : node _T_889 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_890 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_891 = and(_T_889, _T_890) node _T_892 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_893 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_894 = or(_T_892, _T_893) node _T_895 = and(_T_891, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_898 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_899 = and(_T_897, _T_898) node _T_900 = or(UInt<1>(0h0), _T_899) node _T_901 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<14>(0h2000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<13>(0h1000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<15>(0h4000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<13>(0h1000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<18>(0h2f000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_927 = cvt(_T_926) node _T_928 = and(_T_927, asSInt(UInt<17>(0h10000))) node _T_929 = asSInt(_T_928) node _T_930 = eq(_T_929, asSInt(UInt<1>(0h0))) node _T_931 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_932 = cvt(_T_931) node _T_933 = and(_T_932, asSInt(UInt<13>(0h1000))) node _T_934 = asSInt(_T_933) node _T_935 = eq(_T_934, asSInt(UInt<1>(0h0))) node _T_936 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_937 = cvt(_T_936) node _T_938 = and(_T_937, asSInt(UInt<17>(0h10000))) node _T_939 = asSInt(_T_938) node _T_940 = eq(_T_939, asSInt(UInt<1>(0h0))) node _T_941 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_942 = cvt(_T_941) node _T_943 = and(_T_942, asSInt(UInt<27>(0h4000000))) node _T_944 = asSInt(_T_943) node _T_945 = eq(_T_944, asSInt(UInt<1>(0h0))) node _T_946 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_947 = cvt(_T_946) node _T_948 = and(_T_947, asSInt(UInt<13>(0h1000))) node _T_949 = asSInt(_T_948) node _T_950 = eq(_T_949, asSInt(UInt<1>(0h0))) node _T_951 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<29>(0h10000000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = or(_T_905, _T_910) node _T_957 = or(_T_956, _T_915) node _T_958 = or(_T_957, _T_920) node _T_959 = or(_T_958, _T_925) node _T_960 = or(_T_959, _T_930) node _T_961 = or(_T_960, _T_935) node _T_962 = or(_T_961, _T_940) node _T_963 = or(_T_962, _T_945) node _T_964 = or(_T_963, _T_950) node _T_965 = or(_T_964, _T_955) node _T_966 = and(_T_900, _T_965) node _T_967 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_968 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = and(_T_967, _T_972) node _T_974 = or(UInt<1>(0h0), _T_966) node _T_975 = or(_T_974, _T_973) node _T_976 = and(_T_896, _T_975) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_976, UInt<1>(0h1), "") : assert_41 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(is_aligned, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_986 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_986, UInt<1>(0h1), "") : assert_44 node _T_990 = eq(io.in.a.bits.mask, mask) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_990, UInt<1>(0h1), "") : assert_45 node _T_994 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_994 : node _T_995 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_996 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_997 = and(_T_995, _T_996) node _T_998 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_999 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_1000 = or(_T_998, _T_999) node _T_1001 = and(_T_997, _T_1000) node _T_1002 = or(UInt<1>(0h0), _T_1001) node _T_1003 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1004 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = or(UInt<1>(0h0), _T_1005) node _T_1007 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = and(_T_1006, _T_1011) node _T_1013 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1014 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<14>(0h2000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1020 = cvt(_T_1019) node _T_1021 = and(_T_1020, asSInt(UInt<17>(0h10000))) node _T_1022 = asSInt(_T_1021) node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0))) node _T_1024 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<15>(0h4000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_1030 = cvt(_T_1029) node _T_1031 = and(_T_1030, asSInt(UInt<13>(0h1000))) node _T_1032 = asSInt(_T_1031) node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0))) node _T_1034 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1035 = cvt(_T_1034) node _T_1036 = and(_T_1035, asSInt(UInt<18>(0h2f000))) node _T_1037 = asSInt(_T_1036) node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0))) node _T_1039 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1040 = cvt(_T_1039) node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000))) node _T_1042 = asSInt(_T_1041) node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) node _T_1044 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1045 = cvt(_T_1044) node _T_1046 = and(_T_1045, asSInt(UInt<13>(0h1000))) node _T_1047 = asSInt(_T_1046) node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) node _T_1049 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1050 = cvt(_T_1049) node _T_1051 = and(_T_1050, asSInt(UInt<27>(0h4000000))) node _T_1052 = asSInt(_T_1051) node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1055 = cvt(_T_1054) node _T_1056 = and(_T_1055, asSInt(UInt<13>(0h1000))) node _T_1057 = asSInt(_T_1056) node _T_1058 = eq(_T_1057, asSInt(UInt<1>(0h0))) node _T_1059 = or(_T_1018, _T_1023) node _T_1060 = or(_T_1059, _T_1028) node _T_1061 = or(_T_1060, _T_1033) node _T_1062 = or(_T_1061, _T_1038) node _T_1063 = or(_T_1062, _T_1043) node _T_1064 = or(_T_1063, _T_1048) node _T_1065 = or(_T_1064, _T_1053) node _T_1066 = or(_T_1065, _T_1058) node _T_1067 = and(_T_1013, _T_1066) node _T_1068 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1069 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = or(UInt<1>(0h0), _T_1070) node _T_1072 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1073 = cvt(_T_1072) node _T_1074 = and(_T_1073, asSInt(UInt<17>(0h10000))) node _T_1075 = asSInt(_T_1074) node _T_1076 = eq(_T_1075, asSInt(UInt<1>(0h0))) node _T_1077 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1078 = cvt(_T_1077) node _T_1079 = and(_T_1078, asSInt(UInt<29>(0h10000000))) node _T_1080 = asSInt(_T_1079) node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0))) node _T_1082 = or(_T_1076, _T_1081) node _T_1083 = and(_T_1071, _T_1082) node _T_1084 = or(UInt<1>(0h0), _T_1012) node _T_1085 = or(_T_1084, _T_1067) node _T_1086 = or(_T_1085, _T_1083) node _T_1087 = and(_T_1002, _T_1086) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_46 node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(is_aligned, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1097 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_49 node _T_1101 = eq(io.in.a.bits.mask, mask) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_50 node _T_1105 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1109 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1113 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1113 : node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(source_ok_1, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1117 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_54 node _T_1121 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_55 node _T_1125 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_56 node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_57 node _T_1133 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1133 : node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(source_ok_1, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(sink_ok, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1140 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_60 node _T_1144 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_61 node _T_1148 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_62 node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_63 node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1157 = or(UInt<1>(0h1), _T_1156) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_64 node _T_1161 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1161 : node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(source_ok_1, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(sink_ok, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1168 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_67 node _T_1172 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_68 node _T_1176 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_69 node _T_1180 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1181 = or(_T_1180, io.in.d.bits.corrupt) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_70 node _T_1185 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1186 = or(UInt<1>(0h1), _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_71 node _T_1190 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1190 : node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(source_ok_1, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1194 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_73 node _T_1198 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_74 node _T_1202 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1203 = or(UInt<1>(0h1), _T_1202) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_75 node _T_1207 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1207 : node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(source_ok_1, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1211 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_77 node _T_1215 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1216 = or(_T_1215, io.in.d.bits.corrupt) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_78 node _T_1220 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1221 = or(UInt<1>(0h1), _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_79 node _T_1225 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1225 : node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(source_ok_1, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1229 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_81 node _T_1233 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_82 node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1238 = or(UInt<1>(0h1), _T_1237) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1242 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_84 node _T_1246 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) node _T_1248 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<1>(0h0))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = or(_T_1247, _T_1252) node _T_1254 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) node _T_1256 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1257 = cvt(_T_1256) node _T_1258 = and(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = asSInt(_T_1258) node _T_1260 = eq(_T_1259, asSInt(UInt<1>(0h0))) node _T_1261 = or(_T_1255, _T_1260) node _T_1262 = and(_T_1253, _T_1261) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<18>(0h21000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<18>(0h22000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<13>(0h1000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<18>(0h23000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<13>(0h1000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<13>(0h1000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<17>(0h10000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_61 = cvt(_address_ok_T_60) node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<13>(0h1000))) node _address_ok_T_63 = asSInt(_address_ok_T_62) node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0))) node _address_ok_T_65 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_66 = cvt(_address_ok_T_65) node _address_ok_T_67 = and(_address_ok_T_66, asSInt(UInt<17>(0h10000))) node _address_ok_T_68 = asSInt(_address_ok_T_67) node _address_ok_T_69 = eq(_address_ok_T_68, asSInt(UInt<1>(0h0))) node _address_ok_T_70 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<27>(0h4000000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<29>(0h10000000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[17] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 connect _address_ok_WIRE[12], _address_ok_T_64 connect _address_ok_WIRE[13], _address_ok_T_69 connect _address_ok_WIRE[14], _address_ok_T_74 connect _address_ok_WIRE[15], _address_ok_T_79 connect _address_ok_WIRE[16], _address_ok_T_84 node _address_ok_T_85 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_86 = or(_address_ok_T_85, _address_ok_WIRE[2]) node _address_ok_T_87 = or(_address_ok_T_86, _address_ok_WIRE[3]) node _address_ok_T_88 = or(_address_ok_T_87, _address_ok_WIRE[4]) node _address_ok_T_89 = or(_address_ok_T_88, _address_ok_WIRE[5]) node _address_ok_T_90 = or(_address_ok_T_89, _address_ok_WIRE[6]) node _address_ok_T_91 = or(_address_ok_T_90, _address_ok_WIRE[7]) node _address_ok_T_92 = or(_address_ok_T_91, _address_ok_WIRE[8]) node _address_ok_T_93 = or(_address_ok_T_92, _address_ok_WIRE[9]) node _address_ok_T_94 = or(_address_ok_T_93, _address_ok_WIRE[10]) node _address_ok_T_95 = or(_address_ok_T_94, _address_ok_WIRE[11]) node _address_ok_T_96 = or(_address_ok_T_95, _address_ok_WIRE[12]) node _address_ok_T_97 = or(_address_ok_T_96, _address_ok_WIRE[13]) node _address_ok_T_98 = or(_address_ok_T_97, _address_ok_WIRE[14]) node _address_ok_T_99 = or(_address_ok_T_98, _address_ok_WIRE[15]) node address_ok = or(_address_ok_T_99, _address_ok_WIRE[16]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3) wire _legal_source_WIRE_1 : UInt<1> connect _legal_source_WIRE_1, _legal_source_T_4 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1266 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1266 : node _T_1267 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1268 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1267 connect _WIRE_4[1], _T_1268 node _T_1269 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1270 = mux(_WIRE_4[0], _T_1269, UInt<1>(0h0)) node _T_1271 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1272 = or(_T_1270, _T_1271) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1272 node _T_1273 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1274 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = or(UInt<1>(0h0), _T_1275) node _T_1277 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1278 = cvt(_T_1277) node _T_1279 = and(_T_1278, asSInt(UInt<14>(0h2000))) node _T_1280 = asSInt(_T_1279) node _T_1281 = eq(_T_1280, asSInt(UInt<1>(0h0))) node _T_1282 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<13>(0h1000))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1288 = cvt(_T_1287) node _T_1289 = and(_T_1288, asSInt(UInt<17>(0h10000))) node _T_1290 = asSInt(_T_1289) node _T_1291 = eq(_T_1290, asSInt(UInt<1>(0h0))) node _T_1292 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1293 = cvt(_T_1292) node _T_1294 = and(_T_1293, asSInt(UInt<15>(0h4000))) node _T_1295 = asSInt(_T_1294) node _T_1296 = eq(_T_1295, asSInt(UInt<1>(0h0))) node _T_1297 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<18>(0h2f000))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1308 = cvt(_T_1307) node _T_1309 = and(_T_1308, asSInt(UInt<17>(0h10000))) node _T_1310 = asSInt(_T_1309) node _T_1311 = eq(_T_1310, asSInt(UInt<1>(0h0))) node _T_1312 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1313 = cvt(_T_1312) node _T_1314 = and(_T_1313, asSInt(UInt<13>(0h1000))) node _T_1315 = asSInt(_T_1314) node _T_1316 = eq(_T_1315, asSInt(UInt<1>(0h0))) node _T_1317 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1318 = cvt(_T_1317) node _T_1319 = and(_T_1318, asSInt(UInt<17>(0h10000))) node _T_1320 = asSInt(_T_1319) node _T_1321 = eq(_T_1320, asSInt(UInt<1>(0h0))) node _T_1322 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1323 = cvt(_T_1322) node _T_1324 = and(_T_1323, asSInt(UInt<27>(0h4000000))) node _T_1325 = asSInt(_T_1324) node _T_1326 = eq(_T_1325, asSInt(UInt<1>(0h0))) node _T_1327 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1328 = cvt(_T_1327) node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000))) node _T_1330 = asSInt(_T_1329) node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) node _T_1332 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<29>(0h10000000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = or(_T_1281, _T_1286) node _T_1338 = or(_T_1337, _T_1291) node _T_1339 = or(_T_1338, _T_1296) node _T_1340 = or(_T_1339, _T_1301) node _T_1341 = or(_T_1340, _T_1306) node _T_1342 = or(_T_1341, _T_1311) node _T_1343 = or(_T_1342, _T_1316) node _T_1344 = or(_T_1343, _T_1321) node _T_1345 = or(_T_1344, _T_1326) node _T_1346 = or(_T_1345, _T_1331) node _T_1347 = or(_T_1346, _T_1336) node _T_1348 = and(_T_1276, _T_1347) node _T_1349 = or(UInt<1>(0h0), _T_1348) node _T_1350 = and(_WIRE_5, _T_1349) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_86 node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(address_ok, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(legal_source, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1363 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_90 node _T_1367 = eq(io.in.b.bits.mask, mask_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_91 node _T_1371 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_92 node _T_1375 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1375 : node _T_1376 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1377 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = or(UInt<1>(0h0), _T_1378) node _T_1380 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1381 = cvt(_T_1380) node _T_1382 = and(_T_1381, asSInt(UInt<14>(0h2000))) node _T_1383 = asSInt(_T_1382) node _T_1384 = eq(_T_1383, asSInt(UInt<1>(0h0))) node _T_1385 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1386 = cvt(_T_1385) node _T_1387 = and(_T_1386, asSInt(UInt<13>(0h1000))) node _T_1388 = asSInt(_T_1387) node _T_1389 = eq(_T_1388, asSInt(UInt<1>(0h0))) node _T_1390 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1391 = cvt(_T_1390) node _T_1392 = and(_T_1391, asSInt(UInt<17>(0h10000))) node _T_1393 = asSInt(_T_1392) node _T_1394 = eq(_T_1393, asSInt(UInt<1>(0h0))) node _T_1395 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1396 = cvt(_T_1395) node _T_1397 = and(_T_1396, asSInt(UInt<15>(0h4000))) node _T_1398 = asSInt(_T_1397) node _T_1399 = eq(_T_1398, asSInt(UInt<1>(0h0))) node _T_1400 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1401 = cvt(_T_1400) node _T_1402 = and(_T_1401, asSInt(UInt<13>(0h1000))) node _T_1403 = asSInt(_T_1402) node _T_1404 = eq(_T_1403, asSInt(UInt<1>(0h0))) node _T_1405 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1406 = cvt(_T_1405) node _T_1407 = and(_T_1406, asSInt(UInt<18>(0h2f000))) node _T_1408 = asSInt(_T_1407) node _T_1409 = eq(_T_1408, asSInt(UInt<1>(0h0))) node _T_1410 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1411 = cvt(_T_1410) node _T_1412 = and(_T_1411, asSInt(UInt<17>(0h10000))) node _T_1413 = asSInt(_T_1412) node _T_1414 = eq(_T_1413, asSInt(UInt<1>(0h0))) node _T_1415 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1416 = cvt(_T_1415) node _T_1417 = and(_T_1416, asSInt(UInt<13>(0h1000))) node _T_1418 = asSInt(_T_1417) node _T_1419 = eq(_T_1418, asSInt(UInt<1>(0h0))) node _T_1420 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1421 = cvt(_T_1420) node _T_1422 = and(_T_1421, asSInt(UInt<17>(0h10000))) node _T_1423 = asSInt(_T_1422) node _T_1424 = eq(_T_1423, asSInt(UInt<1>(0h0))) node _T_1425 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1426 = cvt(_T_1425) node _T_1427 = and(_T_1426, asSInt(UInt<27>(0h4000000))) node _T_1428 = asSInt(_T_1427) node _T_1429 = eq(_T_1428, asSInt(UInt<1>(0h0))) node _T_1430 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1431 = cvt(_T_1430) node _T_1432 = and(_T_1431, asSInt(UInt<13>(0h1000))) node _T_1433 = asSInt(_T_1432) node _T_1434 = eq(_T_1433, asSInt(UInt<1>(0h0))) node _T_1435 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<29>(0h10000000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = or(_T_1384, _T_1389) node _T_1441 = or(_T_1440, _T_1394) node _T_1442 = or(_T_1441, _T_1399) node _T_1443 = or(_T_1442, _T_1404) node _T_1444 = or(_T_1443, _T_1409) node _T_1445 = or(_T_1444, _T_1414) node _T_1446 = or(_T_1445, _T_1419) node _T_1447 = or(_T_1446, _T_1424) node _T_1448 = or(_T_1447, _T_1429) node _T_1449 = or(_T_1448, _T_1434) node _T_1450 = or(_T_1449, _T_1439) node _T_1451 = and(_T_1379, _T_1450) node _T_1452 = or(UInt<1>(0h0), _T_1451) node _T_1453 = and(UInt<1>(0h0), _T_1452) node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(_T_1453, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1453, UInt<1>(0h1), "") : assert_93 node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(address_ok, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(legal_source, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1466 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_97 node _T_1470 = eq(io.in.b.bits.mask, mask_1) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_98 node _T_1474 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(_T_1474, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1474, UInt<1>(0h1), "") : assert_99 node _T_1478 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1478 : node _T_1479 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1480 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1481 = and(_T_1479, _T_1480) node _T_1482 = or(UInt<1>(0h0), _T_1481) node _T_1483 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1484 = cvt(_T_1483) node _T_1485 = and(_T_1484, asSInt(UInt<14>(0h2000))) node _T_1486 = asSInt(_T_1485) node _T_1487 = eq(_T_1486, asSInt(UInt<1>(0h0))) node _T_1488 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1489 = cvt(_T_1488) node _T_1490 = and(_T_1489, asSInt(UInt<13>(0h1000))) node _T_1491 = asSInt(_T_1490) node _T_1492 = eq(_T_1491, asSInt(UInt<1>(0h0))) node _T_1493 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1494 = cvt(_T_1493) node _T_1495 = and(_T_1494, asSInt(UInt<17>(0h10000))) node _T_1496 = asSInt(_T_1495) node _T_1497 = eq(_T_1496, asSInt(UInt<1>(0h0))) node _T_1498 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1499 = cvt(_T_1498) node _T_1500 = and(_T_1499, asSInt(UInt<15>(0h4000))) node _T_1501 = asSInt(_T_1500) node _T_1502 = eq(_T_1501, asSInt(UInt<1>(0h0))) node _T_1503 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1504 = cvt(_T_1503) node _T_1505 = and(_T_1504, asSInt(UInt<13>(0h1000))) node _T_1506 = asSInt(_T_1505) node _T_1507 = eq(_T_1506, asSInt(UInt<1>(0h0))) node _T_1508 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1509 = cvt(_T_1508) node _T_1510 = and(_T_1509, asSInt(UInt<18>(0h2f000))) node _T_1511 = asSInt(_T_1510) node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0))) node _T_1513 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1514 = cvt(_T_1513) node _T_1515 = and(_T_1514, asSInt(UInt<17>(0h10000))) node _T_1516 = asSInt(_T_1515) node _T_1517 = eq(_T_1516, asSInt(UInt<1>(0h0))) node _T_1518 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1519 = cvt(_T_1518) node _T_1520 = and(_T_1519, asSInt(UInt<13>(0h1000))) node _T_1521 = asSInt(_T_1520) node _T_1522 = eq(_T_1521, asSInt(UInt<1>(0h0))) node _T_1523 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1524 = cvt(_T_1523) node _T_1525 = and(_T_1524, asSInt(UInt<17>(0h10000))) node _T_1526 = asSInt(_T_1525) node _T_1527 = eq(_T_1526, asSInt(UInt<1>(0h0))) node _T_1528 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1529 = cvt(_T_1528) node _T_1530 = and(_T_1529, asSInt(UInt<27>(0h4000000))) node _T_1531 = asSInt(_T_1530) node _T_1532 = eq(_T_1531, asSInt(UInt<1>(0h0))) node _T_1533 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1534 = cvt(_T_1533) node _T_1535 = and(_T_1534, asSInt(UInt<13>(0h1000))) node _T_1536 = asSInt(_T_1535) node _T_1537 = eq(_T_1536, asSInt(UInt<1>(0h0))) node _T_1538 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1539 = cvt(_T_1538) node _T_1540 = and(_T_1539, asSInt(UInt<29>(0h10000000))) node _T_1541 = asSInt(_T_1540) node _T_1542 = eq(_T_1541, asSInt(UInt<1>(0h0))) node _T_1543 = or(_T_1487, _T_1492) node _T_1544 = or(_T_1543, _T_1497) node _T_1545 = or(_T_1544, _T_1502) node _T_1546 = or(_T_1545, _T_1507) node _T_1547 = or(_T_1546, _T_1512) node _T_1548 = or(_T_1547, _T_1517) node _T_1549 = or(_T_1548, _T_1522) node _T_1550 = or(_T_1549, _T_1527) node _T_1551 = or(_T_1550, _T_1532) node _T_1552 = or(_T_1551, _T_1537) node _T_1553 = or(_T_1552, _T_1542) node _T_1554 = and(_T_1482, _T_1553) node _T_1555 = or(UInt<1>(0h0), _T_1554) node _T_1556 = and(UInt<1>(0h0), _T_1555) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_100 node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(address_ok, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(legal_source, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1566 = asUInt(reset) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) when _T_1567 : node _T_1568 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1569 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_104 node _T_1573 = eq(io.in.b.bits.mask, mask_1) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_105 node _T_1577 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1577 : node _T_1578 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1579 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1580 = and(_T_1578, _T_1579) node _T_1581 = or(UInt<1>(0h0), _T_1580) node _T_1582 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1583 = cvt(_T_1582) node _T_1584 = and(_T_1583, asSInt(UInt<14>(0h2000))) node _T_1585 = asSInt(_T_1584) node _T_1586 = eq(_T_1585, asSInt(UInt<1>(0h0))) node _T_1587 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1588 = cvt(_T_1587) node _T_1589 = and(_T_1588, asSInt(UInt<13>(0h1000))) node _T_1590 = asSInt(_T_1589) node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0))) node _T_1592 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1593 = cvt(_T_1592) node _T_1594 = and(_T_1593, asSInt(UInt<17>(0h10000))) node _T_1595 = asSInt(_T_1594) node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1598 = cvt(_T_1597) node _T_1599 = and(_T_1598, asSInt(UInt<15>(0h4000))) node _T_1600 = asSInt(_T_1599) node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0))) node _T_1602 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<18>(0h2f000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<17>(0h10000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<13>(0h1000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<17>(0h10000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<27>(0h4000000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1638 = cvt(_T_1637) node _T_1639 = and(_T_1638, asSInt(UInt<29>(0h10000000))) node _T_1640 = asSInt(_T_1639) node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0))) node _T_1642 = or(_T_1586, _T_1591) node _T_1643 = or(_T_1642, _T_1596) node _T_1644 = or(_T_1643, _T_1601) node _T_1645 = or(_T_1644, _T_1606) node _T_1646 = or(_T_1645, _T_1611) node _T_1647 = or(_T_1646, _T_1616) node _T_1648 = or(_T_1647, _T_1621) node _T_1649 = or(_T_1648, _T_1626) node _T_1650 = or(_T_1649, _T_1631) node _T_1651 = or(_T_1650, _T_1636) node _T_1652 = or(_T_1651, _T_1641) node _T_1653 = and(_T_1581, _T_1652) node _T_1654 = or(UInt<1>(0h0), _T_1653) node _T_1655 = and(UInt<1>(0h0), _T_1654) node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(_T_1655, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1655, UInt<1>(0h1), "") : assert_106 node _T_1659 = asUInt(reset) node _T_1660 = eq(_T_1659, UInt<1>(0h0)) when _T_1660 : node _T_1661 = eq(address_ok, UInt<1>(0h0)) when _T_1661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(legal_source, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1668 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1669 = asUInt(reset) node _T_1670 = eq(_T_1669, UInt<1>(0h0)) when _T_1670 : node _T_1671 = eq(_T_1668, UInt<1>(0h0)) when _T_1671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1668, UInt<1>(0h1), "") : assert_110 node _T_1672 = not(mask_1) node _T_1673 = and(io.in.b.bits.mask, _T_1672) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_111 node _T_1678 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1678 : node _T_1679 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1680 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1681 = and(_T_1679, _T_1680) node _T_1682 = or(UInt<1>(0h0), _T_1681) node _T_1683 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1684 = cvt(_T_1683) node _T_1685 = and(_T_1684, asSInt(UInt<14>(0h2000))) node _T_1686 = asSInt(_T_1685) node _T_1687 = eq(_T_1686, asSInt(UInt<1>(0h0))) node _T_1688 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1689 = cvt(_T_1688) node _T_1690 = and(_T_1689, asSInt(UInt<13>(0h1000))) node _T_1691 = asSInt(_T_1690) node _T_1692 = eq(_T_1691, asSInt(UInt<1>(0h0))) node _T_1693 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1694 = cvt(_T_1693) node _T_1695 = and(_T_1694, asSInt(UInt<17>(0h10000))) node _T_1696 = asSInt(_T_1695) node _T_1697 = eq(_T_1696, asSInt(UInt<1>(0h0))) node _T_1698 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1699 = cvt(_T_1698) node _T_1700 = and(_T_1699, asSInt(UInt<15>(0h4000))) node _T_1701 = asSInt(_T_1700) node _T_1702 = eq(_T_1701, asSInt(UInt<1>(0h0))) node _T_1703 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1704 = cvt(_T_1703) node _T_1705 = and(_T_1704, asSInt(UInt<13>(0h1000))) node _T_1706 = asSInt(_T_1705) node _T_1707 = eq(_T_1706, asSInt(UInt<1>(0h0))) node _T_1708 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1709 = cvt(_T_1708) node _T_1710 = and(_T_1709, asSInt(UInt<18>(0h2f000))) node _T_1711 = asSInt(_T_1710) node _T_1712 = eq(_T_1711, asSInt(UInt<1>(0h0))) node _T_1713 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1714 = cvt(_T_1713) node _T_1715 = and(_T_1714, asSInt(UInt<17>(0h10000))) node _T_1716 = asSInt(_T_1715) node _T_1717 = eq(_T_1716, asSInt(UInt<1>(0h0))) node _T_1718 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1719 = cvt(_T_1718) node _T_1720 = and(_T_1719, asSInt(UInt<13>(0h1000))) node _T_1721 = asSInt(_T_1720) node _T_1722 = eq(_T_1721, asSInt(UInt<1>(0h0))) node _T_1723 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1724 = cvt(_T_1723) node _T_1725 = and(_T_1724, asSInt(UInt<17>(0h10000))) node _T_1726 = asSInt(_T_1725) node _T_1727 = eq(_T_1726, asSInt(UInt<1>(0h0))) node _T_1728 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1729 = cvt(_T_1728) node _T_1730 = and(_T_1729, asSInt(UInt<27>(0h4000000))) node _T_1731 = asSInt(_T_1730) node _T_1732 = eq(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1734 = cvt(_T_1733) node _T_1735 = and(_T_1734, asSInt(UInt<13>(0h1000))) node _T_1736 = asSInt(_T_1735) node _T_1737 = eq(_T_1736, asSInt(UInt<1>(0h0))) node _T_1738 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1739 = cvt(_T_1738) node _T_1740 = and(_T_1739, asSInt(UInt<29>(0h10000000))) node _T_1741 = asSInt(_T_1740) node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0))) node _T_1743 = or(_T_1687, _T_1692) node _T_1744 = or(_T_1743, _T_1697) node _T_1745 = or(_T_1744, _T_1702) node _T_1746 = or(_T_1745, _T_1707) node _T_1747 = or(_T_1746, _T_1712) node _T_1748 = or(_T_1747, _T_1717) node _T_1749 = or(_T_1748, _T_1722) node _T_1750 = or(_T_1749, _T_1727) node _T_1751 = or(_T_1750, _T_1732) node _T_1752 = or(_T_1751, _T_1737) node _T_1753 = or(_T_1752, _T_1742) node _T_1754 = and(_T_1682, _T_1753) node _T_1755 = or(UInt<1>(0h0), _T_1754) node _T_1756 = and(UInt<1>(0h0), _T_1755) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_112 node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(address_ok, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(legal_source, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_116 node _T_1773 = eq(io.in.b.bits.mask, mask_1) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_117 node _T_1777 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1777 : node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1783 = cvt(_T_1782) node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000))) node _T_1785 = asSInt(_T_1784) node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0))) node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1788 = cvt(_T_1787) node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000))) node _T_1790 = asSInt(_T_1789) node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0))) node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<15>(0h4000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<13>(0h1000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1838 = cvt(_T_1837) node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000))) node _T_1840 = asSInt(_T_1839) node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0))) node _T_1842 = or(_T_1786, _T_1791) node _T_1843 = or(_T_1842, _T_1796) node _T_1844 = or(_T_1843, _T_1801) node _T_1845 = or(_T_1844, _T_1806) node _T_1846 = or(_T_1845, _T_1811) node _T_1847 = or(_T_1846, _T_1816) node _T_1848 = or(_T_1847, _T_1821) node _T_1849 = or(_T_1848, _T_1826) node _T_1850 = or(_T_1849, _T_1831) node _T_1851 = or(_T_1850, _T_1836) node _T_1852 = or(_T_1851, _T_1841) node _T_1853 = and(_T_1781, _T_1852) node _T_1854 = or(UInt<1>(0h0), _T_1853) node _T_1855 = and(UInt<1>(0h0), _T_1854) node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(_T_1855, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1855, UInt<1>(0h1), "") : assert_118 node _T_1859 = asUInt(reset) node _T_1860 = eq(_T_1859, UInt<1>(0h0)) when _T_1860 : node _T_1861 = eq(address_ok, UInt<1>(0h0)) when _T_1861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(legal_source, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1868 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_122 node _T_1872 = eq(io.in.b.bits.mask, mask_1) node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(_T_1872, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1872, UInt<1>(0h1), "") : assert_123 node _T_1876 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1876 : node _T_1877 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1878 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1879 = and(_T_1877, _T_1878) node _T_1880 = or(UInt<1>(0h0), _T_1879) node _T_1881 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1882 = cvt(_T_1881) node _T_1883 = and(_T_1882, asSInt(UInt<14>(0h2000))) node _T_1884 = asSInt(_T_1883) node _T_1885 = eq(_T_1884, asSInt(UInt<1>(0h0))) node _T_1886 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1887 = cvt(_T_1886) node _T_1888 = and(_T_1887, asSInt(UInt<13>(0h1000))) node _T_1889 = asSInt(_T_1888) node _T_1890 = eq(_T_1889, asSInt(UInt<1>(0h0))) node _T_1891 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1892 = cvt(_T_1891) node _T_1893 = and(_T_1892, asSInt(UInt<17>(0h10000))) node _T_1894 = asSInt(_T_1893) node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1897 = cvt(_T_1896) node _T_1898 = and(_T_1897, asSInt(UInt<15>(0h4000))) node _T_1899 = asSInt(_T_1898) node _T_1900 = eq(_T_1899, asSInt(UInt<1>(0h0))) node _T_1901 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<13>(0h1000))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1907 = cvt(_T_1906) node _T_1908 = and(_T_1907, asSInt(UInt<18>(0h2f000))) node _T_1909 = asSInt(_T_1908) node _T_1910 = eq(_T_1909, asSInt(UInt<1>(0h0))) node _T_1911 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1912 = cvt(_T_1911) node _T_1913 = and(_T_1912, asSInt(UInt<17>(0h10000))) node _T_1914 = asSInt(_T_1913) node _T_1915 = eq(_T_1914, asSInt(UInt<1>(0h0))) node _T_1916 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1917 = cvt(_T_1916) node _T_1918 = and(_T_1917, asSInt(UInt<13>(0h1000))) node _T_1919 = asSInt(_T_1918) node _T_1920 = eq(_T_1919, asSInt(UInt<1>(0h0))) node _T_1921 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1922 = cvt(_T_1921) node _T_1923 = and(_T_1922, asSInt(UInt<17>(0h10000))) node _T_1924 = asSInt(_T_1923) node _T_1925 = eq(_T_1924, asSInt(UInt<1>(0h0))) node _T_1926 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1927 = cvt(_T_1926) node _T_1928 = and(_T_1927, asSInt(UInt<27>(0h4000000))) node _T_1929 = asSInt(_T_1928) node _T_1930 = eq(_T_1929, asSInt(UInt<1>(0h0))) node _T_1931 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1932 = cvt(_T_1931) node _T_1933 = and(_T_1932, asSInt(UInt<13>(0h1000))) node _T_1934 = asSInt(_T_1933) node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0))) node _T_1936 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1937 = cvt(_T_1936) node _T_1938 = and(_T_1937, asSInt(UInt<29>(0h10000000))) node _T_1939 = asSInt(_T_1938) node _T_1940 = eq(_T_1939, asSInt(UInt<1>(0h0))) node _T_1941 = or(_T_1885, _T_1890) node _T_1942 = or(_T_1941, _T_1895) node _T_1943 = or(_T_1942, _T_1900) node _T_1944 = or(_T_1943, _T_1905) node _T_1945 = or(_T_1944, _T_1910) node _T_1946 = or(_T_1945, _T_1915) node _T_1947 = or(_T_1946, _T_1920) node _T_1948 = or(_T_1947, _T_1925) node _T_1949 = or(_T_1948, _T_1930) node _T_1950 = or(_T_1949, _T_1935) node _T_1951 = or(_T_1950, _T_1940) node _T_1952 = and(_T_1880, _T_1951) node _T_1953 = or(UInt<1>(0h0), _T_1952) node _T_1954 = and(UInt<1>(0h0), _T_1953) node _T_1955 = asUInt(reset) node _T_1956 = eq(_T_1955, UInt<1>(0h0)) when _T_1956 : node _T_1957 = eq(_T_1954, UInt<1>(0h0)) when _T_1957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1954, UInt<1>(0h1), "") : assert_124 node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(address_ok, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(legal_source, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1964 = asUInt(reset) node _T_1965 = eq(_T_1964, UInt<1>(0h0)) when _T_1965 : node _T_1966 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1967 = eq(io.in.b.bits.mask, mask_1) node _T_1968 = asUInt(reset) node _T_1969 = eq(_T_1968, UInt<1>(0h0)) when _T_1969 : node _T_1970 = eq(_T_1967, UInt<1>(0h0)) when _T_1970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1967, UInt<1>(0h1), "") : assert_128 node _T_1971 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1972 = asUInt(reset) node _T_1973 = eq(_T_1972, UInt<1>(0h0)) when _T_1973 : node _T_1974 = eq(_T_1971, UInt<1>(0h0)) when _T_1974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1971, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1975 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1976 = asUInt(reset) node _T_1977 = eq(_T_1976, UInt<1>(0h0)) when _T_1977 : node _T_1978 = eq(_T_1975, UInt<1>(0h0)) when _T_1978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1975, UInt<1>(0h1), "") : assert_130 node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_4 connect _source_ok_WIRE_2[1], _source_ok_T_5 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<13>(0h1000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<13>(0h1000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<17>(0h10000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<18>(0h21000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<13>(0h1000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) node _address_ok_T_130 = xor(io.in.c.bits.address, UInt<18>(0h22000)) node _address_ok_T_131 = cvt(_address_ok_T_130) node _address_ok_T_132 = and(_address_ok_T_131, asSInt(UInt<13>(0h1000))) node _address_ok_T_133 = asSInt(_address_ok_T_132) node _address_ok_T_134 = eq(_address_ok_T_133, asSInt(UInt<1>(0h0))) node _address_ok_T_135 = xor(io.in.c.bits.address, UInt<18>(0h23000)) node _address_ok_T_136 = cvt(_address_ok_T_135) node _address_ok_T_137 = and(_address_ok_T_136, asSInt(UInt<13>(0h1000))) node _address_ok_T_138 = asSInt(_address_ok_T_137) node _address_ok_T_139 = eq(_address_ok_T_138, asSInt(UInt<1>(0h0))) node _address_ok_T_140 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _address_ok_T_141 = cvt(_address_ok_T_140) node _address_ok_T_142 = and(_address_ok_T_141, asSInt(UInt<13>(0h1000))) node _address_ok_T_143 = asSInt(_address_ok_T_142) node _address_ok_T_144 = eq(_address_ok_T_143, asSInt(UInt<1>(0h0))) node _address_ok_T_145 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_146 = cvt(_address_ok_T_145) node _address_ok_T_147 = and(_address_ok_T_146, asSInt(UInt<13>(0h1000))) node _address_ok_T_148 = asSInt(_address_ok_T_147) node _address_ok_T_149 = eq(_address_ok_T_148, asSInt(UInt<1>(0h0))) node _address_ok_T_150 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_151 = cvt(_address_ok_T_150) node _address_ok_T_152 = and(_address_ok_T_151, asSInt(UInt<13>(0h1000))) node _address_ok_T_153 = asSInt(_address_ok_T_152) node _address_ok_T_154 = eq(_address_ok_T_153, asSInt(UInt<1>(0h0))) node _address_ok_T_155 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_156 = cvt(_address_ok_T_155) node _address_ok_T_157 = and(_address_ok_T_156, asSInt(UInt<17>(0h10000))) node _address_ok_T_158 = asSInt(_address_ok_T_157) node _address_ok_T_159 = eq(_address_ok_T_158, asSInt(UInt<1>(0h0))) node _address_ok_T_160 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_161 = cvt(_address_ok_T_160) node _address_ok_T_162 = and(_address_ok_T_161, asSInt(UInt<13>(0h1000))) node _address_ok_T_163 = asSInt(_address_ok_T_162) node _address_ok_T_164 = eq(_address_ok_T_163, asSInt(UInt<1>(0h0))) node _address_ok_T_165 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_166 = cvt(_address_ok_T_165) node _address_ok_T_167 = and(_address_ok_T_166, asSInt(UInt<17>(0h10000))) node _address_ok_T_168 = asSInt(_address_ok_T_167) node _address_ok_T_169 = eq(_address_ok_T_168, asSInt(UInt<1>(0h0))) node _address_ok_T_170 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_171 = cvt(_address_ok_T_170) node _address_ok_T_172 = and(_address_ok_T_171, asSInt(UInt<27>(0h4000000))) node _address_ok_T_173 = asSInt(_address_ok_T_172) node _address_ok_T_174 = eq(_address_ok_T_173, asSInt(UInt<1>(0h0))) node _address_ok_T_175 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_176 = cvt(_address_ok_T_175) node _address_ok_T_177 = and(_address_ok_T_176, asSInt(UInt<13>(0h1000))) node _address_ok_T_178 = asSInt(_address_ok_T_177) node _address_ok_T_179 = eq(_address_ok_T_178, asSInt(UInt<1>(0h0))) node _address_ok_T_180 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_181 = cvt(_address_ok_T_180) node _address_ok_T_182 = and(_address_ok_T_181, asSInt(UInt<29>(0h10000000))) node _address_ok_T_183 = asSInt(_address_ok_T_182) node _address_ok_T_184 = eq(_address_ok_T_183, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[17] connect _address_ok_WIRE_1[0], _address_ok_T_104 connect _address_ok_WIRE_1[1], _address_ok_T_109 connect _address_ok_WIRE_1[2], _address_ok_T_114 connect _address_ok_WIRE_1[3], _address_ok_T_119 connect _address_ok_WIRE_1[4], _address_ok_T_124 connect _address_ok_WIRE_1[5], _address_ok_T_129 connect _address_ok_WIRE_1[6], _address_ok_T_134 connect _address_ok_WIRE_1[7], _address_ok_T_139 connect _address_ok_WIRE_1[8], _address_ok_T_144 connect _address_ok_WIRE_1[9], _address_ok_T_149 connect _address_ok_WIRE_1[10], _address_ok_T_154 connect _address_ok_WIRE_1[11], _address_ok_T_159 connect _address_ok_WIRE_1[12], _address_ok_T_164 connect _address_ok_WIRE_1[13], _address_ok_T_169 connect _address_ok_WIRE_1[14], _address_ok_T_174 connect _address_ok_WIRE_1[15], _address_ok_T_179 connect _address_ok_WIRE_1[16], _address_ok_T_184 node _address_ok_T_185 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_186 = or(_address_ok_T_185, _address_ok_WIRE_1[2]) node _address_ok_T_187 = or(_address_ok_T_186, _address_ok_WIRE_1[3]) node _address_ok_T_188 = or(_address_ok_T_187, _address_ok_WIRE_1[4]) node _address_ok_T_189 = or(_address_ok_T_188, _address_ok_WIRE_1[5]) node _address_ok_T_190 = or(_address_ok_T_189, _address_ok_WIRE_1[6]) node _address_ok_T_191 = or(_address_ok_T_190, _address_ok_WIRE_1[7]) node _address_ok_T_192 = or(_address_ok_T_191, _address_ok_WIRE_1[8]) node _address_ok_T_193 = or(_address_ok_T_192, _address_ok_WIRE_1[9]) node _address_ok_T_194 = or(_address_ok_T_193, _address_ok_WIRE_1[10]) node _address_ok_T_195 = or(_address_ok_T_194, _address_ok_WIRE_1[11]) node _address_ok_T_196 = or(_address_ok_T_195, _address_ok_WIRE_1[12]) node _address_ok_T_197 = or(_address_ok_T_196, _address_ok_WIRE_1[13]) node _address_ok_T_198 = or(_address_ok_T_197, _address_ok_WIRE_1[14]) node _address_ok_T_199 = or(_address_ok_T_198, _address_ok_WIRE_1[15]) node address_ok_1 = or(_address_ok_T_199, _address_ok_WIRE_1[16]) node _T_1979 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) node _T_1981 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1982 = cvt(_T_1981) node _T_1983 = and(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = asSInt(_T_1983) node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0))) node _T_1986 = or(_T_1980, _T_1985) node _T_1987 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) node _T_1989 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<1>(0h0))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = or(_T_1988, _T_1993) node _T_1995 = and(_T_1986, _T_1994) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_131 node _T_1999 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1999 : node _T_2000 = asUInt(reset) node _T_2001 = eq(_T_2000, UInt<1>(0h0)) when _T_2001 : node _T_2002 = eq(address_ok_1, UInt<1>(0h0)) when _T_2002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(source_ok_2, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2006 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_134 node _T_2010 = asUInt(reset) node _T_2011 = eq(_T_2010, UInt<1>(0h0)) when _T_2011 : node _T_2012 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2013 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_136 node _T_2017 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_137 node _T_2021 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2021 : node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(address_ok_1, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(source_ok_2, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2028 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_140 node _T_2032 = asUInt(reset) node _T_2033 = eq(_T_2032, UInt<1>(0h0)) when _T_2033 : node _T_2034 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2035 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2036 = asUInt(reset) node _T_2037 = eq(_T_2036, UInt<1>(0h0)) when _T_2037 : node _T_2038 = eq(_T_2035, UInt<1>(0h0)) when _T_2038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2035, UInt<1>(0h1), "") : assert_142 node _T_2039 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2039 : node _T_2040 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2041 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2044 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2045 = or(_T_2043, _T_2044) node _T_2046 = and(_T_2042, _T_2045) node _T_2047 = or(UInt<1>(0h0), _T_2046) node _T_2048 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2049 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2050 = cvt(_T_2049) node _T_2051 = and(_T_2050, asSInt(UInt<14>(0h2000))) node _T_2052 = asSInt(_T_2051) node _T_2053 = eq(_T_2052, asSInt(UInt<1>(0h0))) node _T_2054 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2055 = cvt(_T_2054) node _T_2056 = and(_T_2055, asSInt(UInt<13>(0h1000))) node _T_2057 = asSInt(_T_2056) node _T_2058 = eq(_T_2057, asSInt(UInt<1>(0h0))) node _T_2059 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2060 = cvt(_T_2059) node _T_2061 = and(_T_2060, asSInt(UInt<17>(0h10000))) node _T_2062 = asSInt(_T_2061) node _T_2063 = eq(_T_2062, asSInt(UInt<1>(0h0))) node _T_2064 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2065 = cvt(_T_2064) node _T_2066 = and(_T_2065, asSInt(UInt<15>(0h4000))) node _T_2067 = asSInt(_T_2066) node _T_2068 = eq(_T_2067, asSInt(UInt<1>(0h0))) node _T_2069 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2070 = cvt(_T_2069) node _T_2071 = and(_T_2070, asSInt(UInt<13>(0h1000))) node _T_2072 = asSInt(_T_2071) node _T_2073 = eq(_T_2072, asSInt(UInt<1>(0h0))) node _T_2074 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2075 = cvt(_T_2074) node _T_2076 = and(_T_2075, asSInt(UInt<18>(0h2f000))) node _T_2077 = asSInt(_T_2076) node _T_2078 = eq(_T_2077, asSInt(UInt<1>(0h0))) node _T_2079 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2080 = cvt(_T_2079) node _T_2081 = and(_T_2080, asSInt(UInt<17>(0h10000))) node _T_2082 = asSInt(_T_2081) node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0))) node _T_2084 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2090 = cvt(_T_2089) node _T_2091 = and(_T_2090, asSInt(UInt<27>(0h4000000))) node _T_2092 = asSInt(_T_2091) node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0))) node _T_2094 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<13>(0h1000))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = or(_T_2053, _T_2058) node _T_2100 = or(_T_2099, _T_2063) node _T_2101 = or(_T_2100, _T_2068) node _T_2102 = or(_T_2101, _T_2073) node _T_2103 = or(_T_2102, _T_2078) node _T_2104 = or(_T_2103, _T_2083) node _T_2105 = or(_T_2104, _T_2088) node _T_2106 = or(_T_2105, _T_2093) node _T_2107 = or(_T_2106, _T_2098) node _T_2108 = and(_T_2048, _T_2107) node _T_2109 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2110 = or(UInt<1>(0h0), _T_2109) node _T_2111 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<17>(0h10000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2117 = cvt(_T_2116) node _T_2118 = and(_T_2117, asSInt(UInt<29>(0h10000000))) node _T_2119 = asSInt(_T_2118) node _T_2120 = eq(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = or(_T_2115, _T_2120) node _T_2122 = and(_T_2110, _T_2121) node _T_2123 = or(UInt<1>(0h0), _T_2108) node _T_2124 = or(_T_2123, _T_2122) node _T_2125 = and(_T_2047, _T_2124) node _T_2126 = asUInt(reset) node _T_2127 = eq(_T_2126, UInt<1>(0h0)) when _T_2127 : node _T_2128 = eq(_T_2125, UInt<1>(0h0)) when _T_2128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2125, UInt<1>(0h1), "") : assert_143 node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2130 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_2129 connect _WIRE_6[1], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_6[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = or(_T_2132, _T_2133) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2134 node _T_2135 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2136 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2137 = and(_T_2135, _T_2136) node _T_2138 = or(UInt<1>(0h0), _T_2137) node _T_2139 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2140 = cvt(_T_2139) node _T_2141 = and(_T_2140, asSInt(UInt<14>(0h2000))) node _T_2142 = asSInt(_T_2141) node _T_2143 = eq(_T_2142, asSInt(UInt<1>(0h0))) node _T_2144 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2145 = cvt(_T_2144) node _T_2146 = and(_T_2145, asSInt(UInt<13>(0h1000))) node _T_2147 = asSInt(_T_2146) node _T_2148 = eq(_T_2147, asSInt(UInt<1>(0h0))) node _T_2149 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2150 = cvt(_T_2149) node _T_2151 = and(_T_2150, asSInt(UInt<17>(0h10000))) node _T_2152 = asSInt(_T_2151) node _T_2153 = eq(_T_2152, asSInt(UInt<1>(0h0))) node _T_2154 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2155 = cvt(_T_2154) node _T_2156 = and(_T_2155, asSInt(UInt<15>(0h4000))) node _T_2157 = asSInt(_T_2156) node _T_2158 = eq(_T_2157, asSInt(UInt<1>(0h0))) node _T_2159 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2160 = cvt(_T_2159) node _T_2161 = and(_T_2160, asSInt(UInt<13>(0h1000))) node _T_2162 = asSInt(_T_2161) node _T_2163 = eq(_T_2162, asSInt(UInt<1>(0h0))) node _T_2164 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2165 = cvt(_T_2164) node _T_2166 = and(_T_2165, asSInt(UInt<18>(0h2f000))) node _T_2167 = asSInt(_T_2166) node _T_2168 = eq(_T_2167, asSInt(UInt<1>(0h0))) node _T_2169 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2170 = cvt(_T_2169) node _T_2171 = and(_T_2170, asSInt(UInt<17>(0h10000))) node _T_2172 = asSInt(_T_2171) node _T_2173 = eq(_T_2172, asSInt(UInt<1>(0h0))) node _T_2174 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<13>(0h1000))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2180 = cvt(_T_2179) node _T_2181 = and(_T_2180, asSInt(UInt<17>(0h10000))) node _T_2182 = asSInt(_T_2181) node _T_2183 = eq(_T_2182, asSInt(UInt<1>(0h0))) node _T_2184 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2185 = cvt(_T_2184) node _T_2186 = and(_T_2185, asSInt(UInt<27>(0h4000000))) node _T_2187 = asSInt(_T_2186) node _T_2188 = eq(_T_2187, asSInt(UInt<1>(0h0))) node _T_2189 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2190 = cvt(_T_2189) node _T_2191 = and(_T_2190, asSInt(UInt<13>(0h1000))) node _T_2192 = asSInt(_T_2191) node _T_2193 = eq(_T_2192, asSInt(UInt<1>(0h0))) node _T_2194 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2195 = cvt(_T_2194) node _T_2196 = and(_T_2195, asSInt(UInt<29>(0h10000000))) node _T_2197 = asSInt(_T_2196) node _T_2198 = eq(_T_2197, asSInt(UInt<1>(0h0))) node _T_2199 = or(_T_2143, _T_2148) node _T_2200 = or(_T_2199, _T_2153) node _T_2201 = or(_T_2200, _T_2158) node _T_2202 = or(_T_2201, _T_2163) node _T_2203 = or(_T_2202, _T_2168) node _T_2204 = or(_T_2203, _T_2173) node _T_2205 = or(_T_2204, _T_2178) node _T_2206 = or(_T_2205, _T_2183) node _T_2207 = or(_T_2206, _T_2188) node _T_2208 = or(_T_2207, _T_2193) node _T_2209 = or(_T_2208, _T_2198) node _T_2210 = and(_T_2138, _T_2209) node _T_2211 = or(UInt<1>(0h0), _T_2210) node _T_2212 = and(_WIRE_7, _T_2211) node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(_T_2212, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2212, UInt<1>(0h1), "") : assert_144 node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(source_ok_2, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2219 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_146 node _T_2223 = asUInt(reset) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) when _T_2224 : node _T_2225 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2226 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(_T_2226, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2226, UInt<1>(0h1), "") : assert_148 node _T_2230 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_149 node _T_2234 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2234 : node _T_2235 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2236 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2237 = and(_T_2235, _T_2236) node _T_2238 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2239 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2240 = or(_T_2238, _T_2239) node _T_2241 = and(_T_2237, _T_2240) node _T_2242 = or(UInt<1>(0h0), _T_2241) node _T_2243 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2244 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2245 = cvt(_T_2244) node _T_2246 = and(_T_2245, asSInt(UInt<14>(0h2000))) node _T_2247 = asSInt(_T_2246) node _T_2248 = eq(_T_2247, asSInt(UInt<1>(0h0))) node _T_2249 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2250 = cvt(_T_2249) node _T_2251 = and(_T_2250, asSInt(UInt<13>(0h1000))) node _T_2252 = asSInt(_T_2251) node _T_2253 = eq(_T_2252, asSInt(UInt<1>(0h0))) node _T_2254 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2255 = cvt(_T_2254) node _T_2256 = and(_T_2255, asSInt(UInt<17>(0h10000))) node _T_2257 = asSInt(_T_2256) node _T_2258 = eq(_T_2257, asSInt(UInt<1>(0h0))) node _T_2259 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2260 = cvt(_T_2259) node _T_2261 = and(_T_2260, asSInt(UInt<15>(0h4000))) node _T_2262 = asSInt(_T_2261) node _T_2263 = eq(_T_2262, asSInt(UInt<1>(0h0))) node _T_2264 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2265 = cvt(_T_2264) node _T_2266 = and(_T_2265, asSInt(UInt<13>(0h1000))) node _T_2267 = asSInt(_T_2266) node _T_2268 = eq(_T_2267, asSInt(UInt<1>(0h0))) node _T_2269 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2270 = cvt(_T_2269) node _T_2271 = and(_T_2270, asSInt(UInt<18>(0h2f000))) node _T_2272 = asSInt(_T_2271) node _T_2273 = eq(_T_2272, asSInt(UInt<1>(0h0))) node _T_2274 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2275 = cvt(_T_2274) node _T_2276 = and(_T_2275, asSInt(UInt<17>(0h10000))) node _T_2277 = asSInt(_T_2276) node _T_2278 = eq(_T_2277, asSInt(UInt<1>(0h0))) node _T_2279 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2280 = cvt(_T_2279) node _T_2281 = and(_T_2280, asSInt(UInt<13>(0h1000))) node _T_2282 = asSInt(_T_2281) node _T_2283 = eq(_T_2282, asSInt(UInt<1>(0h0))) node _T_2284 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2285 = cvt(_T_2284) node _T_2286 = and(_T_2285, asSInt(UInt<27>(0h4000000))) node _T_2287 = asSInt(_T_2286) node _T_2288 = eq(_T_2287, asSInt(UInt<1>(0h0))) node _T_2289 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2290 = cvt(_T_2289) node _T_2291 = and(_T_2290, asSInt(UInt<13>(0h1000))) node _T_2292 = asSInt(_T_2291) node _T_2293 = eq(_T_2292, asSInt(UInt<1>(0h0))) node _T_2294 = or(_T_2248, _T_2253) node _T_2295 = or(_T_2294, _T_2258) node _T_2296 = or(_T_2295, _T_2263) node _T_2297 = or(_T_2296, _T_2268) node _T_2298 = or(_T_2297, _T_2273) node _T_2299 = or(_T_2298, _T_2278) node _T_2300 = or(_T_2299, _T_2283) node _T_2301 = or(_T_2300, _T_2288) node _T_2302 = or(_T_2301, _T_2293) node _T_2303 = and(_T_2243, _T_2302) node _T_2304 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2305 = or(UInt<1>(0h0), _T_2304) node _T_2306 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2307 = cvt(_T_2306) node _T_2308 = and(_T_2307, asSInt(UInt<17>(0h10000))) node _T_2309 = asSInt(_T_2308) node _T_2310 = eq(_T_2309, asSInt(UInt<1>(0h0))) node _T_2311 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2312 = cvt(_T_2311) node _T_2313 = and(_T_2312, asSInt(UInt<29>(0h10000000))) node _T_2314 = asSInt(_T_2313) node _T_2315 = eq(_T_2314, asSInt(UInt<1>(0h0))) node _T_2316 = or(_T_2310, _T_2315) node _T_2317 = and(_T_2305, _T_2316) node _T_2318 = or(UInt<1>(0h0), _T_2303) node _T_2319 = or(_T_2318, _T_2317) node _T_2320 = and(_T_2242, _T_2319) node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(_T_2320, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2320, UInt<1>(0h1), "") : assert_150 node _T_2324 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2325 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2324 connect _WIRE_8[1], _T_2325 node _T_2326 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2327 = mux(_WIRE_8[0], _T_2326, UInt<1>(0h0)) node _T_2328 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2329 = or(_T_2327, _T_2328) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2329 node _T_2330 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2331 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2332 = and(_T_2330, _T_2331) node _T_2333 = or(UInt<1>(0h0), _T_2332) node _T_2334 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2335 = cvt(_T_2334) node _T_2336 = and(_T_2335, asSInt(UInt<14>(0h2000))) node _T_2337 = asSInt(_T_2336) node _T_2338 = eq(_T_2337, asSInt(UInt<1>(0h0))) node _T_2339 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2340 = cvt(_T_2339) node _T_2341 = and(_T_2340, asSInt(UInt<13>(0h1000))) node _T_2342 = asSInt(_T_2341) node _T_2343 = eq(_T_2342, asSInt(UInt<1>(0h0))) node _T_2344 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2345 = cvt(_T_2344) node _T_2346 = and(_T_2345, asSInt(UInt<17>(0h10000))) node _T_2347 = asSInt(_T_2346) node _T_2348 = eq(_T_2347, asSInt(UInt<1>(0h0))) node _T_2349 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2350 = cvt(_T_2349) node _T_2351 = and(_T_2350, asSInt(UInt<15>(0h4000))) node _T_2352 = asSInt(_T_2351) node _T_2353 = eq(_T_2352, asSInt(UInt<1>(0h0))) node _T_2354 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2355 = cvt(_T_2354) node _T_2356 = and(_T_2355, asSInt(UInt<13>(0h1000))) node _T_2357 = asSInt(_T_2356) node _T_2358 = eq(_T_2357, asSInt(UInt<1>(0h0))) node _T_2359 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2360 = cvt(_T_2359) node _T_2361 = and(_T_2360, asSInt(UInt<18>(0h2f000))) node _T_2362 = asSInt(_T_2361) node _T_2363 = eq(_T_2362, asSInt(UInt<1>(0h0))) node _T_2364 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2365 = cvt(_T_2364) node _T_2366 = and(_T_2365, asSInt(UInt<17>(0h10000))) node _T_2367 = asSInt(_T_2366) node _T_2368 = eq(_T_2367, asSInt(UInt<1>(0h0))) node _T_2369 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2370 = cvt(_T_2369) node _T_2371 = and(_T_2370, asSInt(UInt<13>(0h1000))) node _T_2372 = asSInt(_T_2371) node _T_2373 = eq(_T_2372, asSInt(UInt<1>(0h0))) node _T_2374 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2375 = cvt(_T_2374) node _T_2376 = and(_T_2375, asSInt(UInt<17>(0h10000))) node _T_2377 = asSInt(_T_2376) node _T_2378 = eq(_T_2377, asSInt(UInt<1>(0h0))) node _T_2379 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2380 = cvt(_T_2379) node _T_2381 = and(_T_2380, asSInt(UInt<27>(0h4000000))) node _T_2382 = asSInt(_T_2381) node _T_2383 = eq(_T_2382, asSInt(UInt<1>(0h0))) node _T_2384 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2385 = cvt(_T_2384) node _T_2386 = and(_T_2385, asSInt(UInt<13>(0h1000))) node _T_2387 = asSInt(_T_2386) node _T_2388 = eq(_T_2387, asSInt(UInt<1>(0h0))) node _T_2389 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2390 = cvt(_T_2389) node _T_2391 = and(_T_2390, asSInt(UInt<29>(0h10000000))) node _T_2392 = asSInt(_T_2391) node _T_2393 = eq(_T_2392, asSInt(UInt<1>(0h0))) node _T_2394 = or(_T_2338, _T_2343) node _T_2395 = or(_T_2394, _T_2348) node _T_2396 = or(_T_2395, _T_2353) node _T_2397 = or(_T_2396, _T_2358) node _T_2398 = or(_T_2397, _T_2363) node _T_2399 = or(_T_2398, _T_2368) node _T_2400 = or(_T_2399, _T_2373) node _T_2401 = or(_T_2400, _T_2378) node _T_2402 = or(_T_2401, _T_2383) node _T_2403 = or(_T_2402, _T_2388) node _T_2404 = or(_T_2403, _T_2393) node _T_2405 = and(_T_2333, _T_2404) node _T_2406 = or(UInt<1>(0h0), _T_2405) node _T_2407 = and(_WIRE_9, _T_2406) node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(_T_2407, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2407, UInt<1>(0h1), "") : assert_151 node _T_2411 = asUInt(reset) node _T_2412 = eq(_T_2411, UInt<1>(0h0)) when _T_2412 : node _T_2413 = eq(source_ok_2, UInt<1>(0h0)) when _T_2413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2414 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2415 = asUInt(reset) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) when _T_2416 : node _T_2417 = eq(_T_2414, UInt<1>(0h0)) when _T_2417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2414, UInt<1>(0h1), "") : assert_153 node _T_2418 = asUInt(reset) node _T_2419 = eq(_T_2418, UInt<1>(0h0)) when _T_2419 : node _T_2420 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2421 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_155 node _T_2425 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2425 : node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(address_ok_1, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2429 = asUInt(reset) node _T_2430 = eq(_T_2429, UInt<1>(0h0)) when _T_2430 : node _T_2431 = eq(source_ok_2, UInt<1>(0h0)) when _T_2431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2435 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_159 node _T_2439 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2440 = asUInt(reset) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) when _T_2441 : node _T_2442 = eq(_T_2439, UInt<1>(0h0)) when _T_2442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2439, UInt<1>(0h1), "") : assert_160 node _T_2443 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2443 : node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(address_ok_1, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(source_ok_2, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2453 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_164 node _T_2457 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2457 : node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(address_ok_1, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2461 = asUInt(reset) node _T_2462 = eq(_T_2461, UInt<1>(0h0)) when _T_2462 : node _T_2463 = eq(source_ok_2, UInt<1>(0h0)) when _T_2463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2467 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_168 node _T_2471 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2472 = asUInt(reset) node _T_2473 = eq(_T_2472, UInt<1>(0h0)) when _T_2473 : node _T_2474 = eq(_T_2471, UInt<1>(0h0)) when _T_2474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2471, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2475 = asUInt(reset) node _T_2476 = eq(_T_2475, UInt<1>(0h0)) when _T_2476 : node _T_2477 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2478 = eq(a_first, UInt<1>(0h0)) node _T_2479 = and(io.in.a.valid, _T_2478) when _T_2479 : node _T_2480 = eq(io.in.a.bits.opcode, opcode) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_171 node _T_2484 = eq(io.in.a.bits.param, param) node _T_2485 = asUInt(reset) node _T_2486 = eq(_T_2485, UInt<1>(0h0)) when _T_2486 : node _T_2487 = eq(_T_2484, UInt<1>(0h0)) when _T_2487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2484, UInt<1>(0h1), "") : assert_172 node _T_2488 = eq(io.in.a.bits.size, size) node _T_2489 = asUInt(reset) node _T_2490 = eq(_T_2489, UInt<1>(0h0)) when _T_2490 : node _T_2491 = eq(_T_2488, UInt<1>(0h0)) when _T_2491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2488, UInt<1>(0h1), "") : assert_173 node _T_2492 = eq(io.in.a.bits.source, source) node _T_2493 = asUInt(reset) node _T_2494 = eq(_T_2493, UInt<1>(0h0)) when _T_2494 : node _T_2495 = eq(_T_2492, UInt<1>(0h0)) when _T_2495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2492, UInt<1>(0h1), "") : assert_174 node _T_2496 = eq(io.in.a.bits.address, address) node _T_2497 = asUInt(reset) node _T_2498 = eq(_T_2497, UInt<1>(0h0)) when _T_2498 : node _T_2499 = eq(_T_2496, UInt<1>(0h0)) when _T_2499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2496, UInt<1>(0h1), "") : assert_175 node _T_2500 = and(io.in.a.ready, io.in.a.valid) node _T_2501 = and(_T_2500, a_first) when _T_2501 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2502 = eq(d_first, UInt<1>(0h0)) node _T_2503 = and(io.in.d.valid, _T_2502) when _T_2503 : node _T_2504 = eq(io.in.d.bits.opcode, opcode_1) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_176 node _T_2508 = eq(io.in.d.bits.param, param_1) node _T_2509 = asUInt(reset) node _T_2510 = eq(_T_2509, UInt<1>(0h0)) when _T_2510 : node _T_2511 = eq(_T_2508, UInt<1>(0h0)) when _T_2511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2508, UInt<1>(0h1), "") : assert_177 node _T_2512 = eq(io.in.d.bits.size, size_1) node _T_2513 = asUInt(reset) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) when _T_2514 : node _T_2515 = eq(_T_2512, UInt<1>(0h0)) when _T_2515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2512, UInt<1>(0h1), "") : assert_178 node _T_2516 = eq(io.in.d.bits.source, source_1) node _T_2517 = asUInt(reset) node _T_2518 = eq(_T_2517, UInt<1>(0h0)) when _T_2518 : node _T_2519 = eq(_T_2516, UInt<1>(0h0)) when _T_2519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2516, UInt<1>(0h1), "") : assert_179 node _T_2520 = eq(io.in.d.bits.sink, sink) node _T_2521 = asUInt(reset) node _T_2522 = eq(_T_2521, UInt<1>(0h0)) when _T_2522 : node _T_2523 = eq(_T_2520, UInt<1>(0h0)) when _T_2523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2520, UInt<1>(0h1), "") : assert_180 node _T_2524 = eq(io.in.d.bits.denied, denied) node _T_2525 = asUInt(reset) node _T_2526 = eq(_T_2525, UInt<1>(0h0)) when _T_2526 : node _T_2527 = eq(_T_2524, UInt<1>(0h0)) when _T_2527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2524, UInt<1>(0h1), "") : assert_181 node _T_2528 = and(io.in.d.ready, io.in.d.valid) node _T_2529 = and(_T_2528, d_first) when _T_2529 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2530 = eq(b_first, UInt<1>(0h0)) node _T_2531 = and(io.in.b.valid, _T_2530) when _T_2531 : node _T_2532 = eq(io.in.b.bits.opcode, opcode_2) node _T_2533 = asUInt(reset) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) when _T_2534 : node _T_2535 = eq(_T_2532, UInt<1>(0h0)) when _T_2535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2532, UInt<1>(0h1), "") : assert_182 node _T_2536 = eq(io.in.b.bits.param, param_2) node _T_2537 = asUInt(reset) node _T_2538 = eq(_T_2537, UInt<1>(0h0)) when _T_2538 : node _T_2539 = eq(_T_2536, UInt<1>(0h0)) when _T_2539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2536, UInt<1>(0h1), "") : assert_183 node _T_2540 = eq(io.in.b.bits.size, size_2) node _T_2541 = asUInt(reset) node _T_2542 = eq(_T_2541, UInt<1>(0h0)) when _T_2542 : node _T_2543 = eq(_T_2540, UInt<1>(0h0)) when _T_2543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2540, UInt<1>(0h1), "") : assert_184 node _T_2544 = eq(io.in.b.bits.source, source_2) node _T_2545 = asUInt(reset) node _T_2546 = eq(_T_2545, UInt<1>(0h0)) when _T_2546 : node _T_2547 = eq(_T_2544, UInt<1>(0h0)) when _T_2547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2544, UInt<1>(0h1), "") : assert_185 node _T_2548 = eq(io.in.b.bits.address, address_1) node _T_2549 = asUInt(reset) node _T_2550 = eq(_T_2549, UInt<1>(0h0)) when _T_2550 : node _T_2551 = eq(_T_2548, UInt<1>(0h0)) when _T_2551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2548, UInt<1>(0h1), "") : assert_186 node _T_2552 = and(io.in.b.ready, io.in.b.valid) node _T_2553 = and(_T_2552, b_first) when _T_2553 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2554 = eq(c_first, UInt<1>(0h0)) node _T_2555 = and(io.in.c.valid, _T_2554) when _T_2555 : node _T_2556 = eq(io.in.c.bits.opcode, opcode_3) node _T_2557 = asUInt(reset) node _T_2558 = eq(_T_2557, UInt<1>(0h0)) when _T_2558 : node _T_2559 = eq(_T_2556, UInt<1>(0h0)) when _T_2559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2556, UInt<1>(0h1), "") : assert_187 node _T_2560 = eq(io.in.c.bits.param, param_3) node _T_2561 = asUInt(reset) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) when _T_2562 : node _T_2563 = eq(_T_2560, UInt<1>(0h0)) when _T_2563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2560, UInt<1>(0h1), "") : assert_188 node _T_2564 = eq(io.in.c.bits.size, size_3) node _T_2565 = asUInt(reset) node _T_2566 = eq(_T_2565, UInt<1>(0h0)) when _T_2566 : node _T_2567 = eq(_T_2564, UInt<1>(0h0)) when _T_2567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2564, UInt<1>(0h1), "") : assert_189 node _T_2568 = eq(io.in.c.bits.source, source_3) node _T_2569 = asUInt(reset) node _T_2570 = eq(_T_2569, UInt<1>(0h0)) when _T_2570 : node _T_2571 = eq(_T_2568, UInt<1>(0h0)) when _T_2571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2568, UInt<1>(0h1), "") : assert_190 node _T_2572 = eq(io.in.c.bits.address, address_2) node _T_2573 = asUInt(reset) node _T_2574 = eq(_T_2573, UInt<1>(0h0)) when _T_2574 : node _T_2575 = eq(_T_2572, UInt<1>(0h0)) when _T_2575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2572, UInt<1>(0h1), "") : assert_191 node _T_2576 = and(io.in.c.ready, io.in.c.valid) node _T_2577 = and(_T_2576, c_first) when _T_2577 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2578 = and(io.in.a.valid, a_first_1) node _T_2579 = and(_T_2578, UInt<1>(0h1)) when _T_2579 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2580 = and(io.in.a.ready, io.in.a.valid) node _T_2581 = and(_T_2580, a_first_1) node _T_2582 = and(_T_2581, UInt<1>(0h1)) when _T_2582 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2583 = dshr(inflight, io.in.a.bits.source) node _T_2584 = bits(_T_2583, 0, 0) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) node _T_2586 = asUInt(reset) node _T_2587 = eq(_T_2586, UInt<1>(0h0)) when _T_2587 : node _T_2588 = eq(_T_2585, UInt<1>(0h0)) when _T_2588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2585, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2589 = and(io.in.d.valid, d_first_1) node _T_2590 = and(_T_2589, UInt<1>(0h1)) node _T_2591 = eq(d_release_ack, UInt<1>(0h0)) node _T_2592 = and(_T_2590, _T_2591) when _T_2592 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2593 = and(io.in.d.ready, io.in.d.valid) node _T_2594 = and(_T_2593, d_first_1) node _T_2595 = and(_T_2594, UInt<1>(0h1)) node _T_2596 = eq(d_release_ack, UInt<1>(0h0)) node _T_2597 = and(_T_2595, _T_2596) when _T_2597 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2598 = and(io.in.d.valid, d_first_1) node _T_2599 = and(_T_2598, UInt<1>(0h1)) node _T_2600 = eq(d_release_ack, UInt<1>(0h0)) node _T_2601 = and(_T_2599, _T_2600) when _T_2601 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2602 = dshr(inflight, io.in.d.bits.source) node _T_2603 = bits(_T_2602, 0, 0) node _T_2604 = or(_T_2603, same_cycle_resp) node _T_2605 = asUInt(reset) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) when _T_2606 : node _T_2607 = eq(_T_2604, UInt<1>(0h0)) when _T_2607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2604, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2608 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2609 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2610 = or(_T_2608, _T_2609) node _T_2611 = asUInt(reset) node _T_2612 = eq(_T_2611, UInt<1>(0h0)) when _T_2612 : node _T_2613 = eq(_T_2610, UInt<1>(0h0)) when _T_2613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2610, UInt<1>(0h1), "") : assert_194 node _T_2614 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2615 = asUInt(reset) node _T_2616 = eq(_T_2615, UInt<1>(0h0)) when _T_2616 : node _T_2617 = eq(_T_2614, UInt<1>(0h0)) when _T_2617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2614, UInt<1>(0h1), "") : assert_195 else : node _T_2618 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2619 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2620 = or(_T_2618, _T_2619) node _T_2621 = asUInt(reset) node _T_2622 = eq(_T_2621, UInt<1>(0h0)) when _T_2622 : node _T_2623 = eq(_T_2620, UInt<1>(0h0)) when _T_2623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2620, UInt<1>(0h1), "") : assert_196 node _T_2624 = eq(io.in.d.bits.size, a_size_lookup) node _T_2625 = asUInt(reset) node _T_2626 = eq(_T_2625, UInt<1>(0h0)) when _T_2626 : node _T_2627 = eq(_T_2624, UInt<1>(0h0)) when _T_2627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2624, UInt<1>(0h1), "") : assert_197 node _T_2628 = and(io.in.d.valid, d_first_1) node _T_2629 = and(_T_2628, a_first_1) node _T_2630 = and(_T_2629, io.in.a.valid) node _T_2631 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2632 = and(_T_2630, _T_2631) node _T_2633 = eq(d_release_ack, UInt<1>(0h0)) node _T_2634 = and(_T_2632, _T_2633) when _T_2634 : node _T_2635 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2636 = or(_T_2635, io.in.a.ready) node _T_2637 = asUInt(reset) node _T_2638 = eq(_T_2637, UInt<1>(0h0)) when _T_2638 : node _T_2639 = eq(_T_2636, UInt<1>(0h0)) when _T_2639 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2636, UInt<1>(0h1), "") : assert_198 node _T_2640 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2641 = orr(a_set_wo_ready) node _T_2642 = eq(_T_2641, UInt<1>(0h0)) node _T_2643 = or(_T_2640, _T_2642) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_16 node _T_2647 = orr(inflight) node _T_2648 = eq(_T_2647, UInt<1>(0h0)) node _T_2649 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2650 = or(_T_2648, _T_2649) node _T_2651 = lt(watchdog, plusarg_reader.out) node _T_2652 = or(_T_2650, _T_2651) node _T_2653 = asUInt(reset) node _T_2654 = eq(_T_2653, UInt<1>(0h0)) when _T_2654 : node _T_2655 = eq(_T_2652, UInt<1>(0h0)) when _T_2655 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2652, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2656 = and(io.in.a.ready, io.in.a.valid) node _T_2657 = and(io.in.d.ready, io.in.d.valid) node _T_2658 = or(_T_2656, _T_2657) when _T_2658 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2659 = and(io.in.c.valid, c_first_1) node _T_2660 = bits(io.in.c.bits.opcode, 2, 2) node _T_2661 = bits(io.in.c.bits.opcode, 1, 1) node _T_2662 = and(_T_2660, _T_2661) node _T_2663 = and(_T_2659, _T_2662) when _T_2663 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2664 = and(io.in.c.ready, io.in.c.valid) node _T_2665 = and(_T_2664, c_first_1) node _T_2666 = bits(io.in.c.bits.opcode, 2, 2) node _T_2667 = bits(io.in.c.bits.opcode, 1, 1) node _T_2668 = and(_T_2666, _T_2667) node _T_2669 = and(_T_2665, _T_2668) when _T_2669 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2670 = dshr(inflight_1, io.in.c.bits.source) node _T_2671 = bits(_T_2670, 0, 0) node _T_2672 = eq(_T_2671, UInt<1>(0h0)) node _T_2673 = asUInt(reset) node _T_2674 = eq(_T_2673, UInt<1>(0h0)) when _T_2674 : node _T_2675 = eq(_T_2672, UInt<1>(0h0)) when _T_2675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2672, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2676 = and(io.in.d.valid, d_first_2) node _T_2677 = and(_T_2676, UInt<1>(0h1)) node _T_2678 = and(_T_2677, d_release_ack_1) when _T_2678 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2679 = and(io.in.d.ready, io.in.d.valid) node _T_2680 = and(_T_2679, d_first_2) node _T_2681 = and(_T_2680, UInt<1>(0h1)) node _T_2682 = and(_T_2681, d_release_ack_1) when _T_2682 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2683 = and(io.in.d.valid, d_first_2) node _T_2684 = and(_T_2683, UInt<1>(0h1)) node _T_2685 = and(_T_2684, d_release_ack_1) when _T_2685 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2686 = dshr(inflight_1, io.in.d.bits.source) node _T_2687 = bits(_T_2686, 0, 0) node _T_2688 = or(_T_2687, same_cycle_resp_1) node _T_2689 = asUInt(reset) node _T_2690 = eq(_T_2689, UInt<1>(0h0)) when _T_2690 : node _T_2691 = eq(_T_2688, UInt<1>(0h0)) when _T_2691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2688, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2692 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2693 = asUInt(reset) node _T_2694 = eq(_T_2693, UInt<1>(0h0)) when _T_2694 : node _T_2695 = eq(_T_2692, UInt<1>(0h0)) when _T_2695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2692, UInt<1>(0h1), "") : assert_203 else : node _T_2696 = eq(io.in.d.bits.size, c_size_lookup) node _T_2697 = asUInt(reset) node _T_2698 = eq(_T_2697, UInt<1>(0h0)) when _T_2698 : node _T_2699 = eq(_T_2696, UInt<1>(0h0)) when _T_2699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2696, UInt<1>(0h1), "") : assert_204 node _T_2700 = and(io.in.d.valid, d_first_2) node _T_2701 = and(_T_2700, c_first_1) node _T_2702 = and(_T_2701, io.in.c.valid) node _T_2703 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2704 = and(_T_2702, _T_2703) node _T_2705 = and(_T_2704, d_release_ack_1) node _T_2706 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2707 = and(_T_2705, _T_2706) when _T_2707 : node _T_2708 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2709 = or(_T_2708, io.in.c.ready) node _T_2710 = asUInt(reset) node _T_2711 = eq(_T_2710, UInt<1>(0h0)) when _T_2711 : node _T_2712 = eq(_T_2709, UInt<1>(0h0)) when _T_2712 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2709, UInt<1>(0h1), "") : assert_205 node _T_2713 = orr(c_set_wo_ready) when _T_2713 : node _T_2714 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2715 = asUInt(reset) node _T_2716 = eq(_T_2715, UInt<1>(0h0)) when _T_2716 : node _T_2717 = eq(_T_2714, UInt<1>(0h0)) when _T_2717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2714, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_17 node _T_2718 = orr(inflight_1) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) node _T_2720 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2721 = or(_T_2719, _T_2720) node _T_2722 = lt(watchdog_1, plusarg_reader_1.out) node _T_2723 = or(_T_2721, _T_2722) node _T_2724 = asUInt(reset) node _T_2725 = eq(_T_2724, UInt<1>(0h0)) when _T_2725 : node _T_2726 = eq(_T_2723, UInt<1>(0h0)) when _T_2726 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2723, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2727 = and(io.in.c.ready, io.in.c.valid) node _T_2728 = and(io.in.d.ready, io.in.d.valid) node _T_2729 = or(_T_2727, _T_2728) when _T_2729 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2730 = and(io.in.d.ready, io.in.d.valid) node _T_2731 = and(_T_2730, d_first_3) node _T_2732 = bits(io.in.d.bits.opcode, 2, 2) node _T_2733 = bits(io.in.d.bits.opcode, 1, 1) node _T_2734 = eq(_T_2733, UInt<1>(0h0)) node _T_2735 = and(_T_2732, _T_2734) node _T_2736 = and(_T_2731, _T_2735) when _T_2736 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2737 = dshr(inflight_2, io.in.d.bits.sink) node _T_2738 = bits(_T_2737, 0, 0) node _T_2739 = eq(_T_2738, UInt<1>(0h0)) node _T_2740 = asUInt(reset) node _T_2741 = eq(_T_2740, UInt<1>(0h0)) when _T_2741 : node _T_2742 = eq(_T_2739, UInt<1>(0h0)) when _T_2742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2739, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2743 = and(io.in.e.ready, io.in.e.valid) node _T_2744 = and(_T_2743, UInt<1>(0h1)) node _T_2745 = and(_T_2744, UInt<1>(0h1)) when _T_2745 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2746 = or(d_set, inflight_2) node _T_2747 = dshr(_T_2746, io.in.e.bits.sink) node _T_2748 = bits(_T_2747, 0, 0) node _T_2749 = asUInt(reset) node _T_2750 = eq(_T_2749, UInt<1>(0h0)) when _T_2750 : node _T_2751 = eq(_T_2748, UInt<1>(0h0)) when _T_2751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2748, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_8( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [17:0] _GEN_2 = io_in_b_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:18], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [17:0] _GEN_3 = io_in_b_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:18], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [20:0] _GEN_4 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:21], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [25:0] _GEN_5 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:26], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire [25:0] _GEN_6 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_60 = {io_in_b_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46] wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40] wire [27:0] _GEN_7 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_65 = {io_in_b_bits_address_0[31:28], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_66 = {1'h0, _address_ok_T_65}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_67 = _address_ok_T_66 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_68 = _address_ok_T_67; // @[Parameters.scala:137:46] wire _address_ok_T_69 = _address_ok_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_13 = _address_ok_T_69; // @[Parameters.scala:612:40] wire [27:0] _GEN_8 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = {io_in_b_bits_address_0[31:28], _GEN_8}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_14 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [28:0] _GEN_9 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_75 = {io_in_b_bits_address_0[31:29], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_15 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_80 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_16 = _address_ok_T_84; // @[Parameters.scala:612:40] wire _address_ok_T_85 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_86 = _address_ok_T_85 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_87 = _address_ok_T_86 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_88 = _address_ok_T_87 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_89 = _address_ok_T_88 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_90 = _address_ok_T_89 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_91 = _address_ok_T_90 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_92 = _address_ok_T_91 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_93 = _address_ok_T_92 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_94 = _address_ok_T_93 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_95 = _address_ok_T_94 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_96 = _address_ok_T_95 \| _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_97 = _address_ok_T_96 \| _address_ok_WIRE_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_98 = _address_ok_T_97 \| _address_ok_WIRE_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_99 = _address_ok_T_98 \| _address_ok_WIRE_15; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_99 \| _address_ok_WIRE_16; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_10 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_10; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_10; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_11 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_11; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_11; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_11; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [13:0] _GEN_12 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:14], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [16:0] _GEN_13 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:17], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [17:0] _GEN_14 = io_in_c_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:18], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_129; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_130 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_131 = {1'h0, _address_ok_T_130}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_132 = _address_ok_T_131 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_133 = _address_ok_T_132; // @[Parameters.scala:137:46] wire _address_ok_T_134 = _address_ok_T_133 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_134; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_135 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_136 = {1'h0, _address_ok_T_135}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_137 = _address_ok_T_136 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_138 = _address_ok_T_137; // @[Parameters.scala:137:46] wire _address_ok_T_139 = _address_ok_T_138 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_139; // @[Parameters.scala:612:40] wire [17:0] _GEN_15 = io_in_c_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_140 = {io_in_c_bits_address_0[31:18], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_141 = {1'h0, _address_ok_T_140}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_142 = _address_ok_T_141 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_143 = _address_ok_T_142; // @[Parameters.scala:137:46] wire _address_ok_T_144 = _address_ok_T_143 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_144; // @[Parameters.scala:612:40] wire [20:0] _GEN_16 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_145 = {io_in_c_bits_address_0[31:21], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_146 = {1'h0, _address_ok_T_145}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_147 = _address_ok_T_146 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_148 = _address_ok_T_147; // @[Parameters.scala:137:46] wire _address_ok_T_149 = _address_ok_T_148 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_149; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_150 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_151 = {1'h0, _address_ok_T_150}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_152 = _address_ok_T_151 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_153 = _address_ok_T_152; // @[Parameters.scala:137:46] wire _address_ok_T_154 = _address_ok_T_153 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_154; // @[Parameters.scala:612:40] wire [25:0] _GEN_17 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_155 = {io_in_c_bits_address_0[31:26], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_156 = {1'h0, _address_ok_T_155}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_157 = _address_ok_T_156 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_158 = _address_ok_T_157; // @[Parameters.scala:137:46] wire _address_ok_T_159 = _address_ok_T_158 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_159; // @[Parameters.scala:612:40] wire [25:0] _GEN_18 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_160 = {io_in_c_bits_address_0[31:26], _GEN_18}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_161 = {1'h0, _address_ok_T_160}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_162 = _address_ok_T_161 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_163 = _address_ok_T_162; // @[Parameters.scala:137:46] wire _address_ok_T_164 = _address_ok_T_163 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_12 = _address_ok_T_164; // @[Parameters.scala:612:40] wire [27:0] _GEN_19 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_165 = {io_in_c_bits_address_0[31:28], _GEN_19}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_166 = {1'h0, _address_ok_T_165}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_167 = _address_ok_T_166 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_168 = _address_ok_T_167; // @[Parameters.scala:137:46] wire _address_ok_T_169 = _address_ok_T_168 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_13 = _address_ok_T_169; // @[Parameters.scala:612:40] wire [27:0] _GEN_20 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_170 = {io_in_c_bits_address_0[31:28], _GEN_20}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_171 = {1'h0, _address_ok_T_170}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_172 = _address_ok_T_171 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_173 = _address_ok_T_172; // @[Parameters.scala:137:46] wire _address_ok_T_174 = _address_ok_T_173 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_14 = _address_ok_T_174; // @[Parameters.scala:612:40] wire [28:0] _GEN_21 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_175 = {io_in_c_bits_address_0[31:29], _GEN_21}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_176 = {1'h0, _address_ok_T_175}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_177 = _address_ok_T_176 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_178 = _address_ok_T_177; // @[Parameters.scala:137:46] wire _address_ok_T_179 = _address_ok_T_178 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_15 = _address_ok_T_179; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_180 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_181 = {1'h0, _address_ok_T_180}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_182 = _address_ok_T_181 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_183 = _address_ok_T_182; // @[Parameters.scala:137:46] wire _address_ok_T_184 = _address_ok_T_183 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_16 = _address_ok_T_184; // @[Parameters.scala:612:40] wire _address_ok_T_185 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_186 = _address_ok_T_185 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_187 = _address_ok_T_186 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_188 = _address_ok_T_187 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_189 = _address_ok_T_188 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_190 = _address_ok_T_189 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_191 = _address_ok_T_190 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_192 = _address_ok_T_191 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_193 = _address_ok_T_192 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_194 = _address_ok_T_193 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_195 = _address_ok_T_194 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_196 = _address_ok_T_195 \| _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_197 = _address_ok_T_196 \| _address_ok_WIRE_1_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_198 = _address_ok_T_197 \| _address_ok_WIRE_1_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_199 = _address_ok_T_198 \| _address_ok_WIRE_1_15; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_199 \| _address_ok_WIRE_1_16; // @[Parameters.scala:612:40, :636:64] wire _T_2656 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2656; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2656; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2730 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2730; // @[Decoupled.scala:51:35] wire [26:0] _GEN_22 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_22; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2727 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2727; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2727; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_23 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_23; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_23; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_23; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_23; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_24 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_24; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_24; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_24; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_24; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_25 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_26 = 2'h1 << _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_26; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2582 = _T_2656 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2582 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2582 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2582 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2582 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2582 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_27 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_27; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_27; // @[Monitor.scala:673:46, :783:46] wire _T_2628 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_28 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_29 = 2'h1 << _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_29; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2628 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2597 = _T_2730 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2597 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2597 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2597 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_30 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_31 = 2'h1 << _GEN_30; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_31; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_31; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2669 = _T_2727 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2669 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2669 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2669 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2669 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2669 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2700 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2700 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2682 = _T_2730 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2682 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2682 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2682 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2736 = _T_2730 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_32 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_32; // @[OneHot.scala:58:35] assign d_set = _T_2736 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2745 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_33 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_33; // @[OneHot.scala:58:35] assign e_clr = _T_2745 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_246 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_246( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_131 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_131( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_81 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_81( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_167 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_299 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_167( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_299 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_73 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_86 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_73( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_86 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_296 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_40 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_296( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_40 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_33 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_66 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_67 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_202 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_202( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_100 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_100( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_debug : input clock : Clock input reset : Reset output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fragmenter of TLFragmenter_Debug connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect fragmenter.auto.anon_in, tlOut connect tlIn, auto.tl_in connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready	module TLInterconnectCoupler_cbus_to_debug( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_Debug fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip bypass : UInt<1>, pending : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_99 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) connect in_reset, UInt<1>(0h0) reg bypass_reg : UInt<1>, clock node bypass = mux(in_reset, io.bypass, bypass_reg) regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) node _T = and(nodeIn.a.ready, nodeIn.a.valid) node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node a_first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node a_last = or(_r_last_T, _r_last_T_1) node r_3 = and(a_last, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(a_first, r_beats1, r_counter1) connect r_counter, _r_counter_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) node r_counter1_1 = tail(_r_counter1_T_1, 1) node b_first = eq(r_counter_1, UInt<1>(0h0)) node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) node b_last = or(_r_last_T_2, _r_last_T_3) node r_3_1 = and(b_last, _T_1) node _r_count_T_1 = not(r_counter1_1) node r_4_1 = and(r_beats1_1, _r_count_T_1) when _T_1 : node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) connect r_counter_1, _r_counter_T_1 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) node r_counter1_2 = tail(_r_counter1_T_2, 1) node c_first = eq(r_counter_2, UInt<1>(0h0)) node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) node c_last = or(_r_last_T_4, _r_last_T_5) node r_3_2 = and(c_last, _T_2) node _r_count_T_2 = not(r_counter1_2) node r_4_2 = and(r_beats1_2, _r_count_T_2) when _T_2 : node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) connect r_counter_2, _r_counter_T_2 node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) node r_counter1_3 = tail(_r_counter1_T_3, 1) node d_first = eq(r_counter_3, UInt<1>(0h0)) node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) node d_last = or(_r_last_T_6, _r_last_T_7) node r_3_3 = and(d_last, _T_3) node _r_count_T_3 = not(r_counter1_3) node r_4_3 = and(r_beats1_3, _r_count_T_3) when _T_3 : node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) connect r_counter_3, _r_counter_T_3 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) node r_counter1_4 = tail(_r_counter1_T_4, 1) node e_first = eq(r_counter_4, UInt<1>(0h0)) node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node e_last = or(_r_last_T_8, _r_last_T_9) node r_3_4 = and(e_last, _T_4) node _r_count_T_4 = not(r_counter1_4) node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) when _T_4 : node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) connect r_counter_4, _r_counter_T_4 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.mask, UInt<4>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<2>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) node c_request = and(_T_5, _T_6) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_8 = eq(_T_7, UInt<1>(0h0)) node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_10 = eq(_T_9, UInt<1>(0h0)) node c_response = or(_T_8, _T_10) node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) node _T_13 = eq(_T_12, UInt<1>(0h0)) node d_request = and(_T_11, _T_13) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_14.bits.sink, UInt<1>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_inc_T_1 = and(_a_inc_T, a_first) node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_inc_WIRE.bits.data, UInt<32>(0h0) connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) connect _b_inc_WIRE.bits.address, UInt<9>(0h0) connect _b_inc_WIRE.bits.source, UInt<1>(0h0) connect _b_inc_WIRE.bits.size, UInt<2>(0h0) connect _b_inc_WIRE.bits.param, UInt<2>(0h0) connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _b_inc_WIRE.valid, UInt<1>(0h0) connect _b_inc_WIRE.ready, UInt<1>(0h0) wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) node _b_inc_T_1 = and(_b_inc_T, b_first) node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_inc_WIRE.bits.data, UInt<32>(0h0) connect _c_inc_WIRE.bits.address, UInt<9>(0h0) connect _c_inc_WIRE.bits.source, UInt<1>(0h0) connect _c_inc_WIRE.bits.size, UInt<2>(0h0) connect _c_inc_WIRE.bits.param, UInt<3>(0h0) connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _c_inc_WIRE.valid, UInt<1>(0h0) connect _c_inc_WIRE.ready, UInt<1>(0h0) wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) node _c_inc_T_1 = and(_c_inc_T, c_first) node c_inc = and(_c_inc_T_1, c_request) node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_inc_T_1 = and(_d_inc_T, d_first) node d_inc = and(_d_inc_T_1, d_request) wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) connect _e_inc_WIRE.valid, UInt<1>(0h0) connect _e_inc_WIRE.ready, UInt<1>(0h0) wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) node _e_inc_T_1 = and(_e_inc_T, e_first) node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) node inc = cat(a_inc, d_inc) node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_dec_T_1 = and(_a_dec_T, a_last) node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_dec_WIRE.bits.data, UInt<32>(0h0) connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) connect _b_dec_WIRE.bits.address, UInt<9>(0h0) connect _b_dec_WIRE.bits.source, UInt<1>(0h0) connect _b_dec_WIRE.bits.size, UInt<2>(0h0) connect _b_dec_WIRE.bits.param, UInt<2>(0h0) connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _b_dec_WIRE.valid, UInt<1>(0h0) connect _b_dec_WIRE.ready, UInt<1>(0h0) wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) node _b_dec_T_1 = and(_b_dec_T, b_last) node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_dec_WIRE.bits.data, UInt<32>(0h0) connect _c_dec_WIRE.bits.address, UInt<9>(0h0) connect _c_dec_WIRE.bits.source, UInt<1>(0h0) connect _c_dec_WIRE.bits.size, UInt<2>(0h0) connect _c_dec_WIRE.bits.param, UInt<3>(0h0) connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _c_dec_WIRE.valid, UInt<1>(0h0) connect _c_dec_WIRE.ready, UInt<1>(0h0) wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) node _c_dec_T_1 = and(_c_dec_T, c_last) node c_dec = and(_c_dec_T_1, c_response) node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_dec_T_1 = and(_d_dec_T, d_last) node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) connect _e_dec_WIRE.valid, UInt<1>(0h0) connect _e_dec_WIRE.ready, UInt<1>(0h0) wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) node _e_dec_T_1 = and(_e_dec_T, e_last) node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) node dec = cat(a_dec, d_dec) node _next_flight_T = bits(inc, 0, 0) node _next_flight_T_1 = bits(inc, 1, 1) node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) node _next_flight_T_4 = add(flight, _next_flight_T_3) node _next_flight_T_5 = tail(_next_flight_T_4, 1) node _next_flight_T_6 = bits(dec, 0, 0) node _next_flight_T_7 = bits(dec, 1, 1) node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) node next_flight = tail(_next_flight_T_10, 1) connect flight, next_flight node _io_pending_T = gt(flight, UInt<1>(0h0)) connect io.pending, _io_pending_T node _T_14 = eq(next_flight, UInt<1>(0h0)) node _T_15 = or(in_reset, _T_14) when _T_15 : connect bypass_reg, io.bypass node _stall_T = neq(bypass, io.bypass) node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) node stall_counter1 = tail(_stall_counter1_T, 1) node stall_first = eq(stall_counter, UInt<1>(0h0)) node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) node stall_last = or(_stall_last_T, _stall_last_T_1) node stall_done = and(stall_last, _stall_T_1) node _stall_count_T = not(stall_counter1) node stall_count = and(stall_beats1, _stall_count_T) when _stall_T_1 : node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) connect stall_counter, _stall_counter_T node stall = and(_stall_T, stall_first) node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) connect nodeIn.a.ready, _nodeIn_a_ready_T_2 connect nodeOut.a.bits, nodeIn.a.bits connect x1_nodeOut.a.bits, nodeIn.a.bits node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) connect nodeOut.d.ready, _nodeOut_d_ready_T node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) connect nodeIn.d.valid, _nodeIn_d_valid_T wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out, nodeIn.d.bits connect nodeIn_d_bits_out, nodeOut.d.bits wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out_1, nodeIn.d.bits connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.mask, UInt<4>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.ready, UInt<1>(0h1) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.address, UInt<128>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<2>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.valid, UInt<1>(0h0) wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_28.bits.sink, UInt<1>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<9>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<2>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<9>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<2>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready connect _WIRE_33.valid, UInt<1>(0h0) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_34.bits.sink, UInt<1>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) extmodule plusarg_reader_201 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_202 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = \|flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset \| next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_99 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AXI4IdIndexer : input clock : Clock input reset : Reset output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}, last : UInt<1>}}}} wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}, last : UInt<1>}}} invalidate nodeOut.r.bits.last invalidate nodeOut.r.bits.echo.tl_state.source invalidate nodeOut.r.bits.echo.tl_state.size invalidate nodeOut.r.bits.resp invalidate nodeOut.r.bits.data invalidate nodeOut.r.bits.id invalidate nodeOut.r.valid invalidate nodeOut.r.ready invalidate nodeOut.ar.bits.echo.tl_state.source invalidate nodeOut.ar.bits.echo.tl_state.size invalidate nodeOut.ar.bits.qos invalidate nodeOut.ar.bits.prot invalidate nodeOut.ar.bits.cache invalidate nodeOut.ar.bits.lock invalidate nodeOut.ar.bits.burst invalidate nodeOut.ar.bits.size invalidate nodeOut.ar.bits.len invalidate nodeOut.ar.bits.addr invalidate nodeOut.ar.bits.id invalidate nodeOut.ar.valid invalidate nodeOut.ar.ready invalidate nodeOut.b.bits.echo.tl_state.source invalidate nodeOut.b.bits.echo.tl_state.size invalidate nodeOut.b.bits.resp invalidate nodeOut.b.bits.id invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.w.bits.last invalidate nodeOut.w.bits.strb invalidate nodeOut.w.bits.data invalidate nodeOut.w.valid invalidate nodeOut.w.ready invalidate nodeOut.aw.bits.echo.tl_state.source invalidate nodeOut.aw.bits.echo.tl_state.size invalidate nodeOut.aw.bits.qos invalidate nodeOut.aw.bits.prot invalidate nodeOut.aw.bits.cache invalidate nodeOut.aw.bits.lock invalidate nodeOut.aw.bits.burst invalidate nodeOut.aw.bits.size invalidate nodeOut.aw.bits.len invalidate nodeOut.aw.bits.addr invalidate nodeOut.aw.bits.id invalidate nodeOut.aw.valid invalidate nodeOut.aw.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut.ar.bits.echo.tl_state.source, nodeIn.ar.bits.echo.tl_state.source connect nodeOut.ar.bits.echo.tl_state.size, nodeIn.ar.bits.echo.tl_state.size connect nodeOut.ar.bits.qos, nodeIn.ar.bits.qos connect nodeOut.ar.bits.prot, nodeIn.ar.bits.prot connect nodeOut.ar.bits.cache, nodeIn.ar.bits.cache connect nodeOut.ar.bits.lock, nodeIn.ar.bits.lock connect nodeOut.ar.bits.burst, nodeIn.ar.bits.burst connect nodeOut.ar.bits.size, nodeIn.ar.bits.size connect nodeOut.ar.bits.len, nodeIn.ar.bits.len connect nodeOut.ar.bits.addr, nodeIn.ar.bits.addr connect nodeOut.ar.bits.id, nodeIn.ar.bits.id connect nodeOut.ar.valid, nodeIn.ar.valid connect nodeIn.ar.ready, nodeOut.ar.ready connect nodeOut.aw.bits.echo.tl_state.source, nodeIn.aw.bits.echo.tl_state.source connect nodeOut.aw.bits.echo.tl_state.size, nodeIn.aw.bits.echo.tl_state.size connect nodeOut.aw.bits.qos, nodeIn.aw.bits.qos connect nodeOut.aw.bits.prot, nodeIn.aw.bits.prot connect nodeOut.aw.bits.cache, nodeIn.aw.bits.cache connect nodeOut.aw.bits.lock, nodeIn.aw.bits.lock connect nodeOut.aw.bits.burst, nodeIn.aw.bits.burst connect nodeOut.aw.bits.size, nodeIn.aw.bits.size connect nodeOut.aw.bits.len, nodeIn.aw.bits.len connect nodeOut.aw.bits.addr, nodeIn.aw.bits.addr connect nodeOut.aw.bits.id, nodeIn.aw.bits.id connect nodeOut.aw.valid, nodeIn.aw.valid connect nodeIn.aw.ready, nodeOut.aw.ready connect nodeOut.w.bits.last, nodeIn.w.bits.last connect nodeOut.w.bits.strb, nodeIn.w.bits.strb connect nodeOut.w.bits.data, nodeIn.w.bits.data connect nodeOut.w.valid, nodeIn.w.valid connect nodeIn.w.ready, nodeOut.w.ready connect nodeIn.b.bits.echo.tl_state.source, nodeOut.b.bits.echo.tl_state.source connect nodeIn.b.bits.echo.tl_state.size, nodeOut.b.bits.echo.tl_state.size connect nodeIn.b.bits.resp, nodeOut.b.bits.resp connect nodeIn.b.bits.id, nodeOut.b.bits.id connect nodeIn.b.valid, nodeOut.b.valid connect nodeOut.b.ready, nodeIn.b.ready connect nodeIn.r.bits.last, nodeOut.r.bits.last connect nodeIn.r.bits.echo.tl_state.source, nodeOut.r.bits.echo.tl_state.source connect nodeIn.r.bits.echo.tl_state.size, nodeOut.r.bits.echo.tl_state.size connect nodeIn.r.bits.resp, nodeOut.r.bits.resp connect nodeIn.r.bits.data, nodeOut.r.bits.data connect nodeIn.r.bits.id, nodeOut.r.bits.id connect nodeIn.r.valid, nodeOut.r.valid connect nodeOut.r.ready, nodeIn.r.ready extmodule plusarg_reader_66 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_67 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module AXI4IdIndexer( // @[IdIndexer.scala:63:9] input clock, // @[IdIndexer.scala:63:9] input reset, // @[IdIndexer.scala:63:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[IdIndexer.scala:63:9] wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[IdIndexer.scala:63:9] wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_echo_tl_state_size_0 = auto_in_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_echo_tl_state_source_0 = auto_in_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_in_w_valid_0 = auto_in_w_valid; // @[IdIndexer.scala:63:9] wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[IdIndexer.scala:63:9] wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[IdIndexer.scala:63:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[IdIndexer.scala:63:9] wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[IdIndexer.scala:63:9] wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[IdIndexer.scala:63:9] wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_echo_tl_state_size_0 = auto_in_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_echo_tl_state_source_0 = auto_in_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_in_r_ready_0 = auto_in_r_ready; // @[IdIndexer.scala:63:9] wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[IdIndexer.scala:63:9] wire auto_out_w_ready_0 = auto_out_w_ready; // @[IdIndexer.scala:63:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_b_bits_echo_tl_state_size_0 = auto_out_b_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_b_bits_echo_tl_state_source_0 = auto_out_b_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[IdIndexer.scala:63:9] wire auto_out_r_valid_0 = auto_out_r_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[IdIndexer.scala:63:9] wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_r_bits_echo_tl_state_size_0 = auto_out_r_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_r_bits_echo_tl_state_source_0 = auto_out_r_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[IdIndexer.scala:63:9] wire nodeIn_aw_ready; // @[MixedNode.scala:551:17] wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[IdIndexer.scala:63:9] wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeIn_w_ready; // @[MixedNode.scala:551:17] wire nodeIn_w_valid = auto_in_w_valid_0; // @[IdIndexer.scala:63:9] wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[IdIndexer.scala:63:9] wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[IdIndexer.scala:63:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[IdIndexer.scala:63:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_ar_ready; // @[MixedNode.scala:551:17] wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[IdIndexer.scala:63:9] wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeIn_r_ready = auto_in_r_ready_0; // @[IdIndexer.scala:63:9] wire nodeIn_r_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_r_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17] wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_aw_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_w_ready = auto_out_w_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_w_valid; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17] wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeOut_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_ar_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_r_ready; // @[MixedNode.scala:542:17] wire nodeOut_r_valid = auto_out_r_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[IdIndexer.scala:63:9] wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeOut_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_in_aw_ready_0; // @[IdIndexer.scala:63:9] wire auto_in_w_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_b_bits_id_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_b_bits_resp_0; // @[IdIndexer.scala:63:9] wire auto_in_b_valid_0; // @[IdIndexer.scala:63:9] wire auto_in_ar_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_r_bits_id_0; // @[IdIndexer.scala:63:9] wire [63:0] auto_in_r_bits_data_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_r_bits_resp_0; // @[IdIndexer.scala:63:9] wire auto_in_r_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_in_r_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] auto_out_aw_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_aw_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_aw_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_aw_bits_burst_0; // @[IdIndexer.scala:63:9] wire auto_out_aw_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_aw_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_qos_0; // @[IdIndexer.scala:63:9] wire auto_out_aw_valid_0; // @[IdIndexer.scala:63:9] wire [63:0] auto_out_w_bits_data_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_w_bits_strb_0; // @[IdIndexer.scala:63:9] wire auto_out_w_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_out_w_valid_0; // @[IdIndexer.scala:63:9] wire auto_out_b_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] auto_out_ar_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_ar_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_ar_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_ar_bits_burst_0; // @[IdIndexer.scala:63:9] wire auto_out_ar_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_ar_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_qos_0; // @[IdIndexer.scala:63:9] wire auto_out_ar_valid_0; // @[IdIndexer.scala:63:9] wire auto_out_r_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[IdIndexer.scala:63:9] assign nodeOut_aw_valid = nodeIn_aw_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_addr = nodeIn_aw_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_len = nodeIn_aw_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_size = nodeIn_aw_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_burst = nodeIn_aw_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_lock = nodeIn_aw_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_cache = nodeIn_aw_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_prot = nodeIn_aw_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_qos = nodeIn_aw_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_echo_tl_state_size = nodeIn_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_echo_tl_state_source = nodeIn_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign auto_in_w_ready_0 = nodeIn_w_ready; // @[IdIndexer.scala:63:9] assign nodeOut_w_valid = nodeIn_w_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_data = nodeIn_w_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_strb = nodeIn_w_bits_strb; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_last = nodeIn_w_bits_last; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_size_0 = nodeIn_b_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_source_0 = nodeIn_b_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[IdIndexer.scala:63:9] assign nodeOut_ar_valid = nodeIn_ar_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_addr = nodeIn_ar_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_len = nodeIn_ar_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_size = nodeIn_ar_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_burst = nodeIn_ar_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_lock = nodeIn_ar_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_cache = nodeIn_ar_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_prot = nodeIn_ar_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_qos = nodeIn_ar_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_echo_tl_state_size = nodeIn_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_echo_tl_state_source = nodeIn_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_r_valid_0 = nodeIn_r_valid; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_size_0 = nodeIn_r_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_source_0 = nodeIn_r_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[IdIndexer.scala:63:9] assign nodeIn_aw_ready = nodeOut_aw_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_size_0 = nodeOut_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_source_0 = nodeOut_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign nodeIn_w_ready = nodeOut_w_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_w_valid_0 = nodeOut_w_valid; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[IdIndexer.scala:63:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[IdIndexer.scala:63:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_resp = nodeOut_b_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_echo_tl_state_size = nodeOut_b_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_echo_tl_state_source = nodeOut_b_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_ar_ready = nodeOut_ar_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_size_0 = nodeOut_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_source_0 = nodeOut_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_out_r_ready_0 = nodeOut_r_ready; // @[IdIndexer.scala:63:9] assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_echo_tl_state_size = nodeOut_r_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_echo_tl_state_source = nodeOut_r_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_last = nodeOut_r_bits_last; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_id = {1'h0, nodeIn_ar_bits_id}; // @[IdIndexer.scala:69:43] assign nodeOut_aw_bits_id = {1'h0, nodeIn_aw_bits_id}; // @[IdIndexer.scala:69:43, :72:43] assign nodeIn_b_bits_id = nodeOut_b_bits_id[2:0]; // @[IdIndexer.scala:78:43] assign nodeIn_r_bits_id = nodeOut_r_bits_id[2:0]; // @[IdIndexer.scala:81:43] assign auto_in_aw_ready = auto_in_aw_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_w_ready = auto_in_w_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_id = auto_in_b_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_resp = auto_in_b_bits_resp_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_size = auto_in_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_source = auto_in_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_in_ar_ready = auto_in_ar_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_r_valid = auto_in_r_valid_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_id = auto_in_r_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_data = auto_in_r_bits_data_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_resp = auto_in_r_bits_resp_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_size = auto_in_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_source = auto_in_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_last = auto_in_r_bits_last_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_valid = auto_out_aw_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_id = auto_out_aw_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_addr = auto_out_aw_bits_addr_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_len = auto_out_aw_bits_len_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_size = auto_out_aw_bits_size_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_burst = auto_out_aw_bits_burst_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_lock = auto_out_aw_bits_lock_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_cache = auto_out_aw_bits_cache_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_prot = auto_out_aw_bits_prot_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_qos = auto_out_aw_bits_qos_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_size = auto_out_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_source = auto_out_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_out_w_valid = auto_out_w_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_data = auto_out_w_bits_data_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_strb = auto_out_w_bits_strb_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_last = auto_out_w_bits_last_0; // @[IdIndexer.scala:63:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_valid = auto_out_ar_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_id = auto_out_ar_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_addr = auto_out_ar_bits_addr_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_len = auto_out_ar_bits_len_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_size = auto_out_ar_bits_size_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_burst = auto_out_ar_bits_burst_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_lock = auto_out_ar_bits_lock_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_cache = auto_out_ar_bits_cache_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_prot = auto_out_ar_bits_prot_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_qos = auto_out_ar_bits_qos_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_size = auto_out_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_source = auto_out_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_out_r_ready = auto_out_r_ready_0; // @[IdIndexer.scala:63:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_73 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_73 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_73( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_73 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_29 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_29( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_acd_router_7ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, routers_egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_7 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0 connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1 connect auto.routers_egress_nodes_out.flit.bits, routers.auto.egress_nodes_out.flit.bits connect auto.routers_egress_nodes_out.flit.valid, routers.auto.egress_nodes_out.flit.valid connect routers.auto.egress_nodes_out.flit.ready, auto.routers_egress_nodes_out.flit.ready connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module TLSplitACDxBENoC_acd_router_7ClockSinkDomain( // @[ClockDomain.scala:14:9] output [1:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_7 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4), .auto_egress_nodes_out_flit_ready (auto_routers_egress_nodes_out_flit_ready), .auto_egress_nodes_out_flit_valid (auto_routers_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (auto_routers_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (auto_routers_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (auto_routers_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid), .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head), .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail), .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload), .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return), .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_288 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_288( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_50 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node adjustedSig = shl(io.in.sig, 25) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _common_expOut_T = bits(sAdjustedExp, 8, 0) node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0)) node _common_expOut_T_2 = tail(_common_expOut_T_1, 1) connect common_expOut, _common_expOut_T_2 node _common_fractOut_T = bits(adjustedSig, 25, 3) node _common_fractOut_T_1 = bits(adjustedSig, 24, 2) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) connect common_underflow, UInt<1>(0h0) connect common_inexact, UInt<1>(0h0) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_50(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_7 node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h4)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_28 = cvt(_T_27) node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = asSInt(_T_29) node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) node _T_32 = or(_T_26, _T_31) node _T_33 = and(_T_16, _T_24) node _T_34 = and(_T_33, _T_32) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_34, UInt<1>(0h1), "") : assert_1 node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_38 : node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_41 = and(_T_39, _T_40) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_42 = shr(io.in.a.bits.source, 3) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = leq(UInt<1>(0h0), uncommonBits_1) node _T_45 = and(_T_43, _T_44) node _T_46 = leq(uncommonBits_1, UInt<3>(0h4)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_49 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_50 = or(_T_47, _T_48) node _T_51 = or(_T_50, _T_49) node _T_52 = and(_T_41, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_59, _T_64) node _T_101 = or(_T_100, _T_69) node _T_102 = or(_T_101, _T_74) node _T_103 = or(_T_102, _T_79) node _T_104 = or(_T_103, _T_84) node _T_105 = or(_T_104, _T_89) node _T_106 = or(_T_105, _T_94) node _T_107 = or(_T_106, _T_99) node _T_108 = and(_T_54, _T_107) node _T_109 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_110 = or(UInt<1>(0h0), _T_109) node _T_111 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<29>(0h10000000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = or(_T_115, _T_120) node _T_122 = and(_T_110, _T_121) node _T_123 = or(UInt<1>(0h0), _T_108) node _T_124 = or(_T_123, _T_122) node _T_125 = and(_T_53, _T_124) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_125, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_129 = shr(io.in.a.bits.source, 3) node _T_130 = eq(_T_129, UInt<1>(0h0)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_2) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_2, UInt<3>(0h4)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_136 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_134 connect _WIRE[1], _T_135 connect _WIRE[2], _T_136 node _T_137 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_138 = mux(_WIRE[0], _T_137, UInt<1>(0h0)) node _T_139 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_141 = or(_T_138, _T_139) node _T_142 = or(_T_141, _T_140) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_142 node _T_143 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_144 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_145 = and(_T_143, _T_144) node _T_146 = or(UInt<1>(0h0), _T_145) node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<14>(0h2000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<18>(0h2f000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<13>(0h1000))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_178 = cvt(_T_177) node _T_179 = and(_T_178, asSInt(UInt<17>(0h10000))) node _T_180 = asSInt(_T_179) node _T_181 = eq(_T_180, asSInt(UInt<1>(0h0))) node _T_182 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<27>(0h4000000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_188 = cvt(_T_187) node _T_189 = and(_T_188, asSInt(UInt<13>(0h1000))) node _T_190 = asSInt(_T_189) node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0))) node _T_192 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_193 = cvt(_T_192) node _T_194 = and(_T_193, asSInt(UInt<13>(0h1000))) node _T_195 = asSInt(_T_194) node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<29>(0h10000000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = or(_T_151, _T_156) node _T_203 = or(_T_202, _T_161) node _T_204 = or(_T_203, _T_166) node _T_205 = or(_T_204, _T_171) node _T_206 = or(_T_205, _T_176) node _T_207 = or(_T_206, _T_181) node _T_208 = or(_T_207, _T_186) node _T_209 = or(_T_208, _T_191) node _T_210 = or(_T_209, _T_196) node _T_211 = or(_T_210, _T_201) node _T_212 = and(_T_146, _T_211) node _T_213 = or(UInt<1>(0h0), _T_212) node _T_214 = and(_WIRE_1, _T_213) node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_T_214, UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_214, UInt<1>(0h1), "") : assert_3 node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(source_ok, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_221 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_221, UInt<1>(0h1), "") : assert_5 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_228 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_228, UInt<1>(0h1), "") : assert_7 node _T_232 = not(io.in.a.bits.mask) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_233, UInt<1>(0h1), "") : assert_8 node _T_237 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(_T_237, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_237, UInt<1>(0h1), "") : assert_9 node _T_241 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_241 : node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_244 = and(_T_242, _T_243) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_245 = shr(io.in.a.bits.source, 3) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_3) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_3, UInt<3>(0h4)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_252 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_253 = or(_T_250, _T_251) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_244, _T_254) node _T_256 = or(UInt<1>(0h0), _T_255) node _T_257 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<14>(0h2000))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<13>(0h1000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<17>(0h10000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<18>(0h2f000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<17>(0h10000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<27>(0h4000000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<13>(0h1000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<13>(0h1000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_262, _T_267) node _T_304 = or(_T_303, _T_272) node _T_305 = or(_T_304, _T_277) node _T_306 = or(_T_305, _T_282) node _T_307 = or(_T_306, _T_287) node _T_308 = or(_T_307, _T_292) node _T_309 = or(_T_308, _T_297) node _T_310 = or(_T_309, _T_302) node _T_311 = and(_T_257, _T_310) node _T_312 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<17>(0h10000))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<29>(0h10000000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = or(_T_318, _T_323) node _T_325 = and(_T_313, _T_324) node _T_326 = or(UInt<1>(0h0), _T_311) node _T_327 = or(_T_326, _T_325) node _T_328 = and(_T_256, _T_327) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_328, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_332 = shr(io.in.a.bits.source, 3) node _T_333 = eq(_T_332, UInt<1>(0h0)) node _T_334 = leq(UInt<1>(0h0), uncommonBits_4) node _T_335 = and(_T_333, _T_334) node _T_336 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_339 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_337 connect _WIRE_2[1], _T_338 connect _WIRE_2[2], _T_339 node _T_340 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_341 = mux(_WIRE_2[0], _T_340, UInt<1>(0h0)) node _T_342 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_343 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_344 = or(_T_341, _T_342) node _T_345 = or(_T_344, _T_343) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_345 node _T_346 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_347 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_348 = and(_T_346, _T_347) node _T_349 = or(UInt<1>(0h0), _T_348) node _T_350 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<14>(0h2000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<17>(0h10000))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_366 = cvt(_T_365) node _T_367 = and(_T_366, asSInt(UInt<18>(0h2f000))) node _T_368 = asSInt(_T_367) node _T_369 = eq(_T_368, asSInt(UInt<1>(0h0))) node _T_370 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_371 = cvt(_T_370) node _T_372 = and(_T_371, asSInt(UInt<17>(0h10000))) node _T_373 = asSInt(_T_372) node _T_374 = eq(_T_373, asSInt(UInt<1>(0h0))) node _T_375 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<13>(0h1000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<17>(0h10000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_386 = cvt(_T_385) node _T_387 = and(_T_386, asSInt(UInt<27>(0h4000000))) node _T_388 = asSInt(_T_387) node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0))) node _T_390 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_391 = cvt(_T_390) node _T_392 = and(_T_391, asSInt(UInt<13>(0h1000))) node _T_393 = asSInt(_T_392) node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0))) node _T_395 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<13>(0h1000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<29>(0h10000000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = or(_T_354, _T_359) node _T_406 = or(_T_405, _T_364) node _T_407 = or(_T_406, _T_369) node _T_408 = or(_T_407, _T_374) node _T_409 = or(_T_408, _T_379) node _T_410 = or(_T_409, _T_384) node _T_411 = or(_T_410, _T_389) node _T_412 = or(_T_411, _T_394) node _T_413 = or(_T_412, _T_399) node _T_414 = or(_T_413, _T_404) node _T_415 = and(_T_349, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = and(_WIRE_3, _T_416) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_417, UInt<1>(0h1), "") : assert_11 node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(source_ok, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_424 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_424, UInt<1>(0h1), "") : assert_13 node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(is_aligned, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_431 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_431, UInt<1>(0h1), "") : assert_15 node _T_435 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_435, UInt<1>(0h1), "") : assert_16 node _T_439 = not(io.in.a.bits.mask) node _T_440 = eq(_T_439, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_440, UInt<1>(0h1), "") : assert_17 node _T_444 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_444, UInt<1>(0h1), "") : assert_18 node _T_448 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_448 : node _T_449 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_450 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_452 = shr(io.in.a.bits.source, 3) node _T_453 = eq(_T_452, UInt<1>(0h0)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_5) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_459 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_460 = or(_T_457, _T_458) node _T_461 = or(_T_460, _T_459) node _T_462 = and(_T_451, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_479 = and(_T_477, _T_478) node _T_480 = or(UInt<1>(0h0), _T_479) node _T_481 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_482 = cvt(_T_481) node _T_483 = and(_T_482, asSInt(UInt<14>(0h2000))) node _T_484 = asSInt(_T_483) node _T_485 = eq(_T_484, asSInt(UInt<1>(0h0))) node _T_486 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_487 = cvt(_T_486) node _T_488 = and(_T_487, asSInt(UInt<17>(0h10000))) node _T_489 = asSInt(_T_488) node _T_490 = eq(_T_489, asSInt(UInt<1>(0h0))) node _T_491 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_492 = cvt(_T_491) node _T_493 = and(_T_492, asSInt(UInt<18>(0h2f000))) node _T_494 = asSInt(_T_493) node _T_495 = eq(_T_494, asSInt(UInt<1>(0h0))) node _T_496 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<17>(0h10000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_502 = cvt(_T_501) node _T_503 = and(_T_502, asSInt(UInt<13>(0h1000))) node _T_504 = asSInt(_T_503) node _T_505 = eq(_T_504, asSInt(UInt<1>(0h0))) node _T_506 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<17>(0h10000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<27>(0h4000000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<29>(0h10000000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = or(_T_485, _T_490) node _T_532 = or(_T_531, _T_495) node _T_533 = or(_T_532, _T_500) node _T_534 = or(_T_533, _T_505) node _T_535 = or(_T_534, _T_510) node _T_536 = or(_T_535, _T_515) node _T_537 = or(_T_536, _T_520) node _T_538 = or(_T_537, _T_525) node _T_539 = or(_T_538, _T_530) node _T_540 = and(_T_480, _T_539) node _T_541 = or(UInt<1>(0h0), _T_476) node _T_542 = or(_T_541, _T_540) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_542, UInt<1>(0h1), "") : assert_20 node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(source_ok, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(is_aligned, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_552 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_552, UInt<1>(0h1), "") : assert_23 node _T_556 = eq(io.in.a.bits.mask, mask) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_556, UInt<1>(0h1), "") : assert_24 node _T_560 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_560, UInt<1>(0h1), "") : assert_25 node _T_564 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_564 : node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_567 = and(_T_565, _T_566) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_568 = shr(io.in.a.bits.source, 3) node _T_569 = eq(_T_568, UInt<1>(0h0)) node _T_570 = leq(UInt<1>(0h0), uncommonBits_6) node _T_571 = and(_T_569, _T_570) node _T_572 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_573 = and(_T_571, _T_572) node _T_574 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_575 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_576 = or(_T_573, _T_574) node _T_577 = or(_T_576, _T_575) node _T_578 = and(_T_567, _T_577) node _T_579 = or(UInt<1>(0h0), _T_578) node _T_580 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_581 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_582 = and(_T_580, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<13>(0h1000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = and(_T_583, _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<14>(0h2000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<18>(0h2f000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<17>(0h10000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<13>(0h1000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<27>(0h4000000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<13>(0h1000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<13>(0h1000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<29>(0h10000000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = or(_T_598, _T_603) node _T_640 = or(_T_639, _T_608) node _T_641 = or(_T_640, _T_613) node _T_642 = or(_T_641, _T_618) node _T_643 = or(_T_642, _T_623) node _T_644 = or(_T_643, _T_628) node _T_645 = or(_T_644, _T_633) node _T_646 = or(_T_645, _T_638) node _T_647 = and(_T_593, _T_646) node _T_648 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_649 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_650 = cvt(_T_649) node _T_651 = and(_T_650, asSInt(UInt<17>(0h10000))) node _T_652 = asSInt(_T_651) node _T_653 = eq(_T_652, asSInt(UInt<1>(0h0))) node _T_654 = and(_T_648, _T_653) node _T_655 = or(UInt<1>(0h0), _T_589) node _T_656 = or(_T_655, _T_647) node _T_657 = or(_T_656, _T_654) node _T_658 = and(_T_579, _T_657) node _T_659 = asUInt(reset) node _T_660 = eq(_T_659, UInt<1>(0h0)) when _T_660 : node _T_661 = eq(_T_658, UInt<1>(0h0)) when _T_661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_658, UInt<1>(0h1), "") : assert_26 node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(source_ok, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_665 = asUInt(reset) node _T_666 = eq(_T_665, UInt<1>(0h0)) when _T_666 : node _T_667 = eq(is_aligned, UInt<1>(0h0)) when _T_667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_668 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_668, UInt<1>(0h1), "") : assert_29 node _T_672 = eq(io.in.a.bits.mask, mask) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_672, UInt<1>(0h1), "") : assert_30 node _T_676 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_676 : node _T_677 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_678 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_679 = and(_T_677, _T_678) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_680 = shr(io.in.a.bits.source, 3) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = leq(UInt<1>(0h0), uncommonBits_7) node _T_683 = and(_T_681, _T_682) node _T_684 = leq(uncommonBits_7, UInt<3>(0h4)) node _T_685 = and(_T_683, _T_684) node _T_686 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_687 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_688 = or(_T_685, _T_686) node _T_689 = or(_T_688, _T_687) node _T_690 = and(_T_679, _T_689) node _T_691 = or(UInt<1>(0h0), _T_690) node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_693 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_694 = and(_T_692, _T_693) node _T_695 = or(UInt<1>(0h0), _T_694) node _T_696 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<13>(0h1000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = and(_T_695, _T_700) node _T_702 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_703 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_704 = and(_T_702, _T_703) node _T_705 = or(UInt<1>(0h0), _T_704) node _T_706 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<14>(0h2000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<18>(0h2f000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<13>(0h1000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<27>(0h4000000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<13>(0h1000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<29>(0h10000000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = or(_T_710, _T_715) node _T_752 = or(_T_751, _T_720) node _T_753 = or(_T_752, _T_725) node _T_754 = or(_T_753, _T_730) node _T_755 = or(_T_754, _T_735) node _T_756 = or(_T_755, _T_740) node _T_757 = or(_T_756, _T_745) node _T_758 = or(_T_757, _T_750) node _T_759 = and(_T_705, _T_758) node _T_760 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_761 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<17>(0h10000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = and(_T_760, _T_765) node _T_767 = or(UInt<1>(0h0), _T_701) node _T_768 = or(_T_767, _T_759) node _T_769 = or(_T_768, _T_766) node _T_770 = and(_T_691, _T_769) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_770, UInt<1>(0h1), "") : assert_31 node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(source_ok, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(is_aligned, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_780 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_780, UInt<1>(0h1), "") : assert_34 node _T_784 = not(mask) node _T_785 = and(io.in.a.bits.mask, _T_784) node _T_786 = eq(_T_785, UInt<1>(0h0)) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_786, UInt<1>(0h1), "") : assert_35 node _T_790 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_790 : node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_793 = and(_T_791, _T_792) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_794 = shr(io.in.a.bits.source, 3) node _T_795 = eq(_T_794, UInt<1>(0h0)) node _T_796 = leq(UInt<1>(0h0), uncommonBits_8) node _T_797 = and(_T_795, _T_796) node _T_798 = leq(uncommonBits_8, UInt<3>(0h4)) node _T_799 = and(_T_797, _T_798) node _T_800 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_801 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_802 = or(_T_799, _T_800) node _T_803 = or(_T_802, _T_801) node _T_804 = and(_T_793, _T_803) node _T_805 = or(UInt<1>(0h0), _T_804) node _T_806 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_807 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_808 = and(_T_806, _T_807) node _T_809 = or(UInt<1>(0h0), _T_808) node _T_810 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<14>(0h2000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<18>(0h2f000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<17>(0h10000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<27>(0h4000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<13>(0h1000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = or(_T_814, _T_819) node _T_851 = or(_T_850, _T_824) node _T_852 = or(_T_851, _T_829) node _T_853 = or(_T_852, _T_834) node _T_854 = or(_T_853, _T_839) node _T_855 = or(_T_854, _T_844) node _T_856 = or(_T_855, _T_849) node _T_857 = and(_T_809, _T_856) node _T_858 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = and(_T_858, _T_863) node _T_865 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_866 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_867 = and(_T_865, _T_866) node _T_868 = or(UInt<1>(0h0), _T_867) node _T_869 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<29>(0h10000000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = or(_T_873, _T_878) node _T_880 = and(_T_868, _T_879) node _T_881 = or(UInt<1>(0h0), _T_857) node _T_882 = or(_T_881, _T_864) node _T_883 = or(_T_882, _T_880) node _T_884 = and(_T_805, _T_883) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_884, UInt<1>(0h1), "") : assert_36 node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(source_ok, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(is_aligned, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_894 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_894, UInt<1>(0h1), "") : assert_39 node _T_898 = eq(io.in.a.bits.mask, mask) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_898, UInt<1>(0h1), "") : assert_40 node _T_902 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_902 : node _T_903 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_904 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_905 = and(_T_903, _T_904) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_906 = shr(io.in.a.bits.source, 3) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = leq(UInt<1>(0h0), uncommonBits_9) node _T_909 = and(_T_907, _T_908) node _T_910 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_913 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_914 = or(_T_911, _T_912) node _T_915 = or(_T_914, _T_913) node _T_916 = and(_T_905, _T_915) node _T_917 = or(UInt<1>(0h0), _T_916) node _T_918 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_919 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_920 = and(_T_918, _T_919) node _T_921 = or(UInt<1>(0h0), _T_920) node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<13>(0h1000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_953 = cvt(_T_952) node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000))) node _T_955 = asSInt(_T_954) node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0))) node _T_957 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_958 = cvt(_T_957) node _T_959 = and(_T_958, asSInt(UInt<13>(0h1000))) node _T_960 = asSInt(_T_959) node _T_961 = eq(_T_960, asSInt(UInt<1>(0h0))) node _T_962 = or(_T_926, _T_931) node _T_963 = or(_T_962, _T_936) node _T_964 = or(_T_963, _T_941) node _T_965 = or(_T_964, _T_946) node _T_966 = or(_T_965, _T_951) node _T_967 = or(_T_966, _T_956) node _T_968 = or(_T_967, _T_961) node _T_969 = and(_T_921, _T_968) node _T_970 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_971 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_972 = cvt(_T_971) node _T_973 = and(_T_972, asSInt(UInt<17>(0h10000))) node _T_974 = asSInt(_T_973) node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0))) node _T_976 = and(_T_970, _T_975) node _T_977 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_978 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_979 = and(_T_977, _T_978) node _T_980 = or(UInt<1>(0h0), _T_979) node _T_981 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_982 = cvt(_T_981) node _T_983 = and(_T_982, asSInt(UInt<17>(0h10000))) node _T_984 = asSInt(_T_983) node _T_985 = eq(_T_984, asSInt(UInt<1>(0h0))) node _T_986 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_987 = cvt(_T_986) node _T_988 = and(_T_987, asSInt(UInt<29>(0h10000000))) node _T_989 = asSInt(_T_988) node _T_990 = eq(_T_989, asSInt(UInt<1>(0h0))) node _T_991 = or(_T_985, _T_990) node _T_992 = and(_T_980, _T_991) node _T_993 = or(UInt<1>(0h0), _T_969) node _T_994 = or(_T_993, _T_976) node _T_995 = or(_T_994, _T_992) node _T_996 = and(_T_917, _T_995) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_996, UInt<1>(0h1), "") : assert_41 node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(source_ok, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(is_aligned, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1006 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_44 node _T_1010 = eq(io.in.a.bits.mask, mask) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_45 node _T_1014 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1014 : node _T_1015 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1016 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1017 = and(_T_1015, _T_1016) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_1018 = shr(io.in.a.bits.source, 3) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) node _T_1020 = leq(UInt<1>(0h0), uncommonBits_10) node _T_1021 = and(_T_1019, _T_1020) node _T_1022 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_1025 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_1026 = or(_T_1023, _T_1024) node _T_1027 = or(_T_1026, _T_1025) node _T_1028 = and(_T_1017, _T_1027) node _T_1029 = or(UInt<1>(0h0), _T_1028) node _T_1030 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1031 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1032 = and(_T_1030, _T_1031) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1035 = cvt(_T_1034) node _T_1036 = and(_T_1035, asSInt(UInt<13>(0h1000))) node _T_1037 = asSInt(_T_1036) node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0))) node _T_1039 = and(_T_1033, _T_1038) node _T_1040 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1041 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1042 = cvt(_T_1041) node _T_1043 = and(_T_1042, asSInt(UInt<14>(0h2000))) node _T_1044 = asSInt(_T_1043) node _T_1045 = eq(_T_1044, asSInt(UInt<1>(0h0))) node _T_1046 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1047 = cvt(_T_1046) node _T_1048 = and(_T_1047, asSInt(UInt<17>(0h10000))) node _T_1049 = asSInt(_T_1048) node _T_1050 = eq(_T_1049, asSInt(UInt<1>(0h0))) node _T_1051 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<18>(0h2f000))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<17>(0h10000))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1062 = cvt(_T_1061) node _T_1063 = and(_T_1062, asSInt(UInt<13>(0h1000))) node _T_1064 = asSInt(_T_1063) node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0))) node _T_1066 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1067 = cvt(_T_1066) node _T_1068 = and(_T_1067, asSInt(UInt<27>(0h4000000))) node _T_1069 = asSInt(_T_1068) node _T_1070 = eq(_T_1069, asSInt(UInt<1>(0h0))) node _T_1071 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1072 = cvt(_T_1071) node _T_1073 = and(_T_1072, asSInt(UInt<13>(0h1000))) node _T_1074 = asSInt(_T_1073) node _T_1075 = eq(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1077 = cvt(_T_1076) node _T_1078 = and(_T_1077, asSInt(UInt<13>(0h1000))) node _T_1079 = asSInt(_T_1078) node _T_1080 = eq(_T_1079, asSInt(UInt<1>(0h0))) node _T_1081 = or(_T_1045, _T_1050) node _T_1082 = or(_T_1081, _T_1055) node _T_1083 = or(_T_1082, _T_1060) node _T_1084 = or(_T_1083, _T_1065) node _T_1085 = or(_T_1084, _T_1070) node _T_1086 = or(_T_1085, _T_1075) node _T_1087 = or(_T_1086, _T_1080) node _T_1088 = and(_T_1040, _T_1087) node _T_1089 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1090 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1091 = and(_T_1089, _T_1090) node _T_1092 = or(UInt<1>(0h0), _T_1091) node _T_1093 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1094 = cvt(_T_1093) node _T_1095 = and(_T_1094, asSInt(UInt<17>(0h10000))) node _T_1096 = asSInt(_T_1095) node _T_1097 = eq(_T_1096, asSInt(UInt<1>(0h0))) node _T_1098 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1099 = cvt(_T_1098) node _T_1100 = and(_T_1099, asSInt(UInt<29>(0h10000000))) node _T_1101 = asSInt(_T_1100) node _T_1102 = eq(_T_1101, asSInt(UInt<1>(0h0))) node _T_1103 = or(_T_1097, _T_1102) node _T_1104 = and(_T_1092, _T_1103) node _T_1105 = or(UInt<1>(0h0), _T_1039) node _T_1106 = or(_T_1105, _T_1088) node _T_1107 = or(_T_1106, _T_1104) node _T_1108 = and(_T_1029, _T_1107) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_46 node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(source_ok, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(is_aligned, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1118 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_49 node _T_1122 = eq(io.in.a.bits.mask, mask) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_50 node _T_1126 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1130 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_9 = shr(io.in.d.bits.source, 3) node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0)) node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<3>(0h4)) node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13) node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<3>(0h5)) node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_14 connect _source_ok_WIRE_1[1], _source_ok_T_15 connect _source_ok_WIRE_1[2], _source_ok_T_16 node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1134 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1134 : node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(source_ok_1, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1138 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_54 node _T_1142 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_55 node _T_1146 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_56 node _T_1150 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_57 node _T_1154 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1154 : node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(source_ok_1, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(sink_ok, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1161 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_60 node _T_1165 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_61 node _T_1169 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_62 node _T_1173 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_63 node _T_1177 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1178 = or(UInt<1>(0h1), _T_1177) node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(_T_1178, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1178, UInt<1>(0h1), "") : assert_64 node _T_1182 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1182 : node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(source_ok_1, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(sink_ok, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1189 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_67 node _T_1193 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_68 node _T_1197 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_69 node _T_1201 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.d.bits.corrupt) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_70 node _T_1206 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1207 = or(UInt<1>(0h1), _T_1206) node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(_T_1207, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1207, UInt<1>(0h1), "") : assert_71 node _T_1211 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1211 : node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(source_ok_1, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1215 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_73 node _T_1219 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_74 node _T_1223 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1224 = or(UInt<1>(0h1), _T_1223) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_75 node _T_1228 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1228 : node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(source_ok_1, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1232 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_77 node _T_1236 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.d.bits.corrupt) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_78 node _T_1241 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1242 = or(UInt<1>(0h1), _T_1241) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_79 node _T_1246 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1246 : node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(source_ok_1, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1250 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_81 node _T_1254 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_82 node _T_1258 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1259 = or(UInt<1>(0h1), _T_1258) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1263 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_1267 = shr(io.in.b.bits.source, 3) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) node _T_1269 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_1272 = and(_T_1270, _T_1271) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1275 = cvt(_T_1274) node _T_1276 = and(_T_1275, asSInt(UInt<1>(0h0))) node _T_1277 = asSInt(_T_1276) node _T_1278 = eq(_T_1277, asSInt(UInt<1>(0h0))) node _T_1279 = or(_T_1273, _T_1278) node _T_1280 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) node _T_1282 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = or(_T_1281, _T_1286) node _T_1288 = eq(io.in.b.bits.source, UInt<4>(0h8)) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) node _T_1290 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<1>(0h0))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = or(_T_1289, _T_1294) node _T_1296 = and(_T_1279, _T_1287) node _T_1297 = and(_T_1296, _T_1295) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<13>(0h1000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_61 = cvt(_address_ok_T_60) node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<29>(0h10000000))) node _address_ok_T_63 = asSInt(_address_ok_T_62) node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[13] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 connect _address_ok_WIRE[12], _address_ok_T_64 node _address_ok_T_65 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[2]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[3]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[4]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[5]) node _address_ok_T_70 = or(_address_ok_T_69, _address_ok_WIRE[6]) node _address_ok_T_71 = or(_address_ok_T_70, _address_ok_WIRE[7]) node _address_ok_T_72 = or(_address_ok_T_71, _address_ok_WIRE[8]) node _address_ok_T_73 = or(_address_ok_T_72, _address_ok_WIRE[9]) node _address_ok_T_74 = or(_address_ok_T_73, _address_ok_WIRE[10]) node _address_ok_T_75 = or(_address_ok_T_74, _address_ok_WIRE[11]) node address_ok = or(_address_ok_T_75, _address_ok_WIRE[12]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_7 node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<3>(0h5), UInt<1>(0h0)) node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) wire _legal_source_WIRE_1 : UInt<4> connect _legal_source_WIRE_1, _legal_source_T_12 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1301 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1301 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_1302 = shr(io.in.b.bits.source, 3) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) node _T_1304 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = leq(uncommonBits_12, UInt<3>(0h4)) node _T_1307 = and(_T_1305, _T_1306) node _T_1308 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1309 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1307 connect _WIRE_4[1], _T_1308 connect _WIRE_4[2], _T_1309 node _T_1310 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1311 = mux(_WIRE_4[0], _T_1310, UInt<1>(0h0)) node _T_1312 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1313 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1314 = or(_T_1311, _T_1312) node _T_1315 = or(_T_1314, _T_1313) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1315 node _T_1316 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1317 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1318 = and(_T_1316, _T_1317) node _T_1319 = or(UInt<1>(0h0), _T_1318) node _T_1320 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1321 = cvt(_T_1320) node _T_1322 = and(_T_1321, asSInt(UInt<14>(0h2000))) node _T_1323 = asSInt(_T_1322) node _T_1324 = eq(_T_1323, asSInt(UInt<1>(0h0))) node _T_1325 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1326 = cvt(_T_1325) node _T_1327 = and(_T_1326, asSInt(UInt<13>(0h1000))) node _T_1328 = asSInt(_T_1327) node _T_1329 = eq(_T_1328, asSInt(UInt<1>(0h0))) node _T_1330 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1331 = cvt(_T_1330) node _T_1332 = and(_T_1331, asSInt(UInt<17>(0h10000))) node _T_1333 = asSInt(_T_1332) node _T_1334 = eq(_T_1333, asSInt(UInt<1>(0h0))) node _T_1335 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1336 = cvt(_T_1335) node _T_1337 = and(_T_1336, asSInt(UInt<18>(0h2f000))) node _T_1338 = asSInt(_T_1337) node _T_1339 = eq(_T_1338, asSInt(UInt<1>(0h0))) node _T_1340 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1341 = cvt(_T_1340) node _T_1342 = and(_T_1341, asSInt(UInt<17>(0h10000))) node _T_1343 = asSInt(_T_1342) node _T_1344 = eq(_T_1343, asSInt(UInt<1>(0h0))) node _T_1345 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1346 = cvt(_T_1345) node _T_1347 = and(_T_1346, asSInt(UInt<13>(0h1000))) node _T_1348 = asSInt(_T_1347) node _T_1349 = eq(_T_1348, asSInt(UInt<1>(0h0))) node _T_1350 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1351 = cvt(_T_1350) node _T_1352 = and(_T_1351, asSInt(UInt<17>(0h10000))) node _T_1353 = asSInt(_T_1352) node _T_1354 = eq(_T_1353, asSInt(UInt<1>(0h0))) node _T_1355 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1356 = cvt(_T_1355) node _T_1357 = and(_T_1356, asSInt(UInt<27>(0h4000000))) node _T_1358 = asSInt(_T_1357) node _T_1359 = eq(_T_1358, asSInt(UInt<1>(0h0))) node _T_1360 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1361 = cvt(_T_1360) node _T_1362 = and(_T_1361, asSInt(UInt<13>(0h1000))) node _T_1363 = asSInt(_T_1362) node _T_1364 = eq(_T_1363, asSInt(UInt<1>(0h0))) node _T_1365 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1366 = cvt(_T_1365) node _T_1367 = and(_T_1366, asSInt(UInt<13>(0h1000))) node _T_1368 = asSInt(_T_1367) node _T_1369 = eq(_T_1368, asSInt(UInt<1>(0h0))) node _T_1370 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1371 = cvt(_T_1370) node _T_1372 = and(_T_1371, asSInt(UInt<29>(0h10000000))) node _T_1373 = asSInt(_T_1372) node _T_1374 = eq(_T_1373, asSInt(UInt<1>(0h0))) node _T_1375 = or(_T_1324, _T_1329) node _T_1376 = or(_T_1375, _T_1334) node _T_1377 = or(_T_1376, _T_1339) node _T_1378 = or(_T_1377, _T_1344) node _T_1379 = or(_T_1378, _T_1349) node _T_1380 = or(_T_1379, _T_1354) node _T_1381 = or(_T_1380, _T_1359) node _T_1382 = or(_T_1381, _T_1364) node _T_1383 = or(_T_1382, _T_1369) node _T_1384 = or(_T_1383, _T_1374) node _T_1385 = and(_T_1319, _T_1384) node _T_1386 = or(UInt<1>(0h0), _T_1385) node _T_1387 = and(_WIRE_5, _T_1386) node _T_1388 = asUInt(reset) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) when _T_1389 : node _T_1390 = eq(_T_1387, UInt<1>(0h0)) when _T_1390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1387, UInt<1>(0h1), "") : assert_86 node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(address_ok, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(legal_source, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1400 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_90 node _T_1404 = eq(io.in.b.bits.mask, mask_1) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_91 node _T_1408 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1409 = asUInt(reset) node _T_1410 = eq(_T_1409, UInt<1>(0h0)) when _T_1410 : node _T_1411 = eq(_T_1408, UInt<1>(0h0)) when _T_1411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1408, UInt<1>(0h1), "") : assert_92 node _T_1412 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1412 : node _T_1413 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1414 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1415 = and(_T_1413, _T_1414) node _T_1416 = or(UInt<1>(0h0), _T_1415) node _T_1417 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1418 = cvt(_T_1417) node _T_1419 = and(_T_1418, asSInt(UInt<14>(0h2000))) node _T_1420 = asSInt(_T_1419) node _T_1421 = eq(_T_1420, asSInt(UInt<1>(0h0))) node _T_1422 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1423 = cvt(_T_1422) node _T_1424 = and(_T_1423, asSInt(UInt<13>(0h1000))) node _T_1425 = asSInt(_T_1424) node _T_1426 = eq(_T_1425, asSInt(UInt<1>(0h0))) node _T_1427 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1428 = cvt(_T_1427) node _T_1429 = and(_T_1428, asSInt(UInt<17>(0h10000))) node _T_1430 = asSInt(_T_1429) node _T_1431 = eq(_T_1430, asSInt(UInt<1>(0h0))) node _T_1432 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1433 = cvt(_T_1432) node _T_1434 = and(_T_1433, asSInt(UInt<18>(0h2f000))) node _T_1435 = asSInt(_T_1434) node _T_1436 = eq(_T_1435, asSInt(UInt<1>(0h0))) node _T_1437 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1438 = cvt(_T_1437) node _T_1439 = and(_T_1438, asSInt(UInt<17>(0h10000))) node _T_1440 = asSInt(_T_1439) node _T_1441 = eq(_T_1440, asSInt(UInt<1>(0h0))) node _T_1442 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1443 = cvt(_T_1442) node _T_1444 = and(_T_1443, asSInt(UInt<13>(0h1000))) node _T_1445 = asSInt(_T_1444) node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) node _T_1447 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1448 = cvt(_T_1447) node _T_1449 = and(_T_1448, asSInt(UInt<17>(0h10000))) node _T_1450 = asSInt(_T_1449) node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) node _T_1452 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1453 = cvt(_T_1452) node _T_1454 = and(_T_1453, asSInt(UInt<27>(0h4000000))) node _T_1455 = asSInt(_T_1454) node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) node _T_1457 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<13>(0h1000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<29>(0h10000000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = or(_T_1421, _T_1426) node _T_1473 = or(_T_1472, _T_1431) node _T_1474 = or(_T_1473, _T_1436) node _T_1475 = or(_T_1474, _T_1441) node _T_1476 = or(_T_1475, _T_1446) node _T_1477 = or(_T_1476, _T_1451) node _T_1478 = or(_T_1477, _T_1456) node _T_1479 = or(_T_1478, _T_1461) node _T_1480 = or(_T_1479, _T_1466) node _T_1481 = or(_T_1480, _T_1471) node _T_1482 = and(_T_1416, _T_1481) node _T_1483 = or(UInt<1>(0h0), _T_1482) node _T_1484 = and(UInt<1>(0h0), _T_1483) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_93 node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(address_ok, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(legal_source, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1497 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1498 = asUInt(reset) node _T_1499 = eq(_T_1498, UInt<1>(0h0)) when _T_1499 : node _T_1500 = eq(_T_1497, UInt<1>(0h0)) when _T_1500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1497, UInt<1>(0h1), "") : assert_97 node _T_1501 = eq(io.in.b.bits.mask, mask_1) node _T_1502 = asUInt(reset) node _T_1503 = eq(_T_1502, UInt<1>(0h0)) when _T_1503 : node _T_1504 = eq(_T_1501, UInt<1>(0h0)) when _T_1504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1501, UInt<1>(0h1), "") : assert_98 node _T_1505 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1506 = asUInt(reset) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) when _T_1507 : node _T_1508 = eq(_T_1505, UInt<1>(0h0)) when _T_1508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1505, UInt<1>(0h1), "") : assert_99 node _T_1509 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1509 : node _T_1510 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1511 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1512 = and(_T_1510, _T_1511) node _T_1513 = or(UInt<1>(0h0), _T_1512) node _T_1514 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1515 = cvt(_T_1514) node _T_1516 = and(_T_1515, asSInt(UInt<14>(0h2000))) node _T_1517 = asSInt(_T_1516) node _T_1518 = eq(_T_1517, asSInt(UInt<1>(0h0))) node _T_1519 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1520 = cvt(_T_1519) node _T_1521 = and(_T_1520, asSInt(UInt<13>(0h1000))) node _T_1522 = asSInt(_T_1521) node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1525 = cvt(_T_1524) node _T_1526 = and(_T_1525, asSInt(UInt<17>(0h10000))) node _T_1527 = asSInt(_T_1526) node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0))) node _T_1529 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1530 = cvt(_T_1529) node _T_1531 = and(_T_1530, asSInt(UInt<18>(0h2f000))) node _T_1532 = asSInt(_T_1531) node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) node _T_1534 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<17>(0h10000))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1540 = cvt(_T_1539) node _T_1541 = and(_T_1540, asSInt(UInt<13>(0h1000))) node _T_1542 = asSInt(_T_1541) node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) node _T_1544 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<17>(0h10000))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1550 = cvt(_T_1549) node _T_1551 = and(_T_1550, asSInt(UInt<27>(0h4000000))) node _T_1552 = asSInt(_T_1551) node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) node _T_1554 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<13>(0h1000))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<13>(0h1000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1565 = cvt(_T_1564) node _T_1566 = and(_T_1565, asSInt(UInt<29>(0h10000000))) node _T_1567 = asSInt(_T_1566) node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) node _T_1569 = or(_T_1518, _T_1523) node _T_1570 = or(_T_1569, _T_1528) node _T_1571 = or(_T_1570, _T_1533) node _T_1572 = or(_T_1571, _T_1538) node _T_1573 = or(_T_1572, _T_1543) node _T_1574 = or(_T_1573, _T_1548) node _T_1575 = or(_T_1574, _T_1553) node _T_1576 = or(_T_1575, _T_1558) node _T_1577 = or(_T_1576, _T_1563) node _T_1578 = or(_T_1577, _T_1568) node _T_1579 = and(_T_1513, _T_1578) node _T_1580 = or(UInt<1>(0h0), _T_1579) node _T_1581 = and(UInt<1>(0h0), _T_1580) node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(_T_1581, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1581, UInt<1>(0h1), "") : assert_100 node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(address_ok, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(legal_source, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1594 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(_T_1594, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1594, UInt<1>(0h1), "") : assert_104 node _T_1598 = eq(io.in.b.bits.mask, mask_1) node _T_1599 = asUInt(reset) node _T_1600 = eq(_T_1599, UInt<1>(0h0)) when _T_1600 : node _T_1601 = eq(_T_1598, UInt<1>(0h0)) when _T_1601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1598, UInt<1>(0h1), "") : assert_105 node _T_1602 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1602 : node _T_1603 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1604 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = or(UInt<1>(0h0), _T_1605) node _T_1607 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<14>(0h2000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<18>(0h2f000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<17>(0h10000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1638 = cvt(_T_1637) node _T_1639 = and(_T_1638, asSInt(UInt<17>(0h10000))) node _T_1640 = asSInt(_T_1639) node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0))) node _T_1642 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1643 = cvt(_T_1642) node _T_1644 = and(_T_1643, asSInt(UInt<27>(0h4000000))) node _T_1645 = asSInt(_T_1644) node _T_1646 = eq(_T_1645, asSInt(UInt<1>(0h0))) node _T_1647 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1648 = cvt(_T_1647) node _T_1649 = and(_T_1648, asSInt(UInt<13>(0h1000))) node _T_1650 = asSInt(_T_1649) node _T_1651 = eq(_T_1650, asSInt(UInt<1>(0h0))) node _T_1652 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1653 = cvt(_T_1652) node _T_1654 = and(_T_1653, asSInt(UInt<13>(0h1000))) node _T_1655 = asSInt(_T_1654) node _T_1656 = eq(_T_1655, asSInt(UInt<1>(0h0))) node _T_1657 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1658 = cvt(_T_1657) node _T_1659 = and(_T_1658, asSInt(UInt<29>(0h10000000))) node _T_1660 = asSInt(_T_1659) node _T_1661 = eq(_T_1660, asSInt(UInt<1>(0h0))) node _T_1662 = or(_T_1611, _T_1616) node _T_1663 = or(_T_1662, _T_1621) node _T_1664 = or(_T_1663, _T_1626) node _T_1665 = or(_T_1664, _T_1631) node _T_1666 = or(_T_1665, _T_1636) node _T_1667 = or(_T_1666, _T_1641) node _T_1668 = or(_T_1667, _T_1646) node _T_1669 = or(_T_1668, _T_1651) node _T_1670 = or(_T_1669, _T_1656) node _T_1671 = or(_T_1670, _T_1661) node _T_1672 = and(_T_1606, _T_1671) node _T_1673 = or(UInt<1>(0h0), _T_1672) node _T_1674 = and(UInt<1>(0h0), _T_1673) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_106 node _T_1678 = asUInt(reset) node _T_1679 = eq(_T_1678, UInt<1>(0h0)) when _T_1679 : node _T_1680 = eq(address_ok, UInt<1>(0h0)) when _T_1680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1681 = asUInt(reset) node _T_1682 = eq(_T_1681, UInt<1>(0h0)) when _T_1682 : node _T_1683 = eq(legal_source, UInt<1>(0h0)) when _T_1683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1687 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_110 node _T_1691 = not(mask_1) node _T_1692 = and(io.in.b.bits.mask, _T_1691) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) node _T_1694 = asUInt(reset) node _T_1695 = eq(_T_1694, UInt<1>(0h0)) when _T_1695 : node _T_1696 = eq(_T_1693, UInt<1>(0h0)) when _T_1696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1693, UInt<1>(0h1), "") : assert_111 node _T_1697 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1697 : node _T_1698 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1699 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1700 = and(_T_1698, _T_1699) node _T_1701 = or(UInt<1>(0h0), _T_1700) node _T_1702 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1703 = cvt(_T_1702) node _T_1704 = and(_T_1703, asSInt(UInt<14>(0h2000))) node _T_1705 = asSInt(_T_1704) node _T_1706 = eq(_T_1705, asSInt(UInt<1>(0h0))) node _T_1707 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1708 = cvt(_T_1707) node _T_1709 = and(_T_1708, asSInt(UInt<13>(0h1000))) node _T_1710 = asSInt(_T_1709) node _T_1711 = eq(_T_1710, asSInt(UInt<1>(0h0))) node _T_1712 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1713 = cvt(_T_1712) node _T_1714 = and(_T_1713, asSInt(UInt<17>(0h10000))) node _T_1715 = asSInt(_T_1714) node _T_1716 = eq(_T_1715, asSInt(UInt<1>(0h0))) node _T_1717 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1718 = cvt(_T_1717) node _T_1719 = and(_T_1718, asSInt(UInt<18>(0h2f000))) node _T_1720 = asSInt(_T_1719) node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0))) node _T_1722 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<17>(0h10000))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<13>(0h1000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<17>(0h10000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<27>(0h4000000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<13>(0h1000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<29>(0h10000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = or(_T_1706, _T_1711) node _T_1758 = or(_T_1757, _T_1716) node _T_1759 = or(_T_1758, _T_1721) node _T_1760 = or(_T_1759, _T_1726) node _T_1761 = or(_T_1760, _T_1731) node _T_1762 = or(_T_1761, _T_1736) node _T_1763 = or(_T_1762, _T_1741) node _T_1764 = or(_T_1763, _T_1746) node _T_1765 = or(_T_1764, _T_1751) node _T_1766 = or(_T_1765, _T_1756) node _T_1767 = and(_T_1701, _T_1766) node _T_1768 = or(UInt<1>(0h0), _T_1767) node _T_1769 = and(UInt<1>(0h0), _T_1768) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_112 node _T_1773 = asUInt(reset) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) when _T_1774 : node _T_1775 = eq(address_ok, UInt<1>(0h0)) when _T_1775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(legal_source, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1782 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_116 node _T_1786 = eq(io.in.b.bits.mask, mask_1) node _T_1787 = asUInt(reset) node _T_1788 = eq(_T_1787, UInt<1>(0h0)) when _T_1788 : node _T_1789 = eq(_T_1786, UInt<1>(0h0)) when _T_1789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1786, UInt<1>(0h1), "") : assert_117 node _T_1790 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1790 : node _T_1791 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1792 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = or(UInt<1>(0h0), _T_1793) node _T_1795 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1796 = cvt(_T_1795) node _T_1797 = and(_T_1796, asSInt(UInt<14>(0h2000))) node _T_1798 = asSInt(_T_1797) node _T_1799 = eq(_T_1798, asSInt(UInt<1>(0h0))) node _T_1800 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1801 = cvt(_T_1800) node _T_1802 = and(_T_1801, asSInt(UInt<13>(0h1000))) node _T_1803 = asSInt(_T_1802) node _T_1804 = eq(_T_1803, asSInt(UInt<1>(0h0))) node _T_1805 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<17>(0h10000))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1811 = cvt(_T_1810) node _T_1812 = and(_T_1811, asSInt(UInt<18>(0h2f000))) node _T_1813 = asSInt(_T_1812) node _T_1814 = eq(_T_1813, asSInt(UInt<1>(0h0))) node _T_1815 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1816 = cvt(_T_1815) node _T_1817 = and(_T_1816, asSInt(UInt<17>(0h10000))) node _T_1818 = asSInt(_T_1817) node _T_1819 = eq(_T_1818, asSInt(UInt<1>(0h0))) node _T_1820 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1821 = cvt(_T_1820) node _T_1822 = and(_T_1821, asSInt(UInt<13>(0h1000))) node _T_1823 = asSInt(_T_1822) node _T_1824 = eq(_T_1823, asSInt(UInt<1>(0h0))) node _T_1825 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1826 = cvt(_T_1825) node _T_1827 = and(_T_1826, asSInt(UInt<17>(0h10000))) node _T_1828 = asSInt(_T_1827) node _T_1829 = eq(_T_1828, asSInt(UInt<1>(0h0))) node _T_1830 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1831 = cvt(_T_1830) node _T_1832 = and(_T_1831, asSInt(UInt<27>(0h4000000))) node _T_1833 = asSInt(_T_1832) node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1836 = cvt(_T_1835) node _T_1837 = and(_T_1836, asSInt(UInt<13>(0h1000))) node _T_1838 = asSInt(_T_1837) node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0))) node _T_1840 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<13>(0h1000))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1846 = cvt(_T_1845) node _T_1847 = and(_T_1846, asSInt(UInt<29>(0h10000000))) node _T_1848 = asSInt(_T_1847) node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0))) node _T_1850 = or(_T_1799, _T_1804) node _T_1851 = or(_T_1850, _T_1809) node _T_1852 = or(_T_1851, _T_1814) node _T_1853 = or(_T_1852, _T_1819) node _T_1854 = or(_T_1853, _T_1824) node _T_1855 = or(_T_1854, _T_1829) node _T_1856 = or(_T_1855, _T_1834) node _T_1857 = or(_T_1856, _T_1839) node _T_1858 = or(_T_1857, _T_1844) node _T_1859 = or(_T_1858, _T_1849) node _T_1860 = and(_T_1794, _T_1859) node _T_1861 = or(UInt<1>(0h0), _T_1860) node _T_1862 = and(UInt<1>(0h0), _T_1861) node _T_1863 = asUInt(reset) node _T_1864 = eq(_T_1863, UInt<1>(0h0)) when _T_1864 : node _T_1865 = eq(_T_1862, UInt<1>(0h0)) when _T_1865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1862, UInt<1>(0h1), "") : assert_118 node _T_1866 = asUInt(reset) node _T_1867 = eq(_T_1866, UInt<1>(0h0)) when _T_1867 : node _T_1868 = eq(address_ok, UInt<1>(0h0)) when _T_1868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(legal_source, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1872 = asUInt(reset) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) when _T_1873 : node _T_1874 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1875 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(_T_1875, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1875, UInt<1>(0h1), "") : assert_122 node _T_1879 = eq(io.in.b.bits.mask, mask_1) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_123 node _T_1883 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1883 : node _T_1884 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1885 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1886 = and(_T_1884, _T_1885) node _T_1887 = or(UInt<1>(0h0), _T_1886) node _T_1888 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1889 = cvt(_T_1888) node _T_1890 = and(_T_1889, asSInt(UInt<14>(0h2000))) node _T_1891 = asSInt(_T_1890) node _T_1892 = eq(_T_1891, asSInt(UInt<1>(0h0))) node _T_1893 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1894 = cvt(_T_1893) node _T_1895 = and(_T_1894, asSInt(UInt<13>(0h1000))) node _T_1896 = asSInt(_T_1895) node _T_1897 = eq(_T_1896, asSInt(UInt<1>(0h0))) node _T_1898 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1899 = cvt(_T_1898) node _T_1900 = and(_T_1899, asSInt(UInt<17>(0h10000))) node _T_1901 = asSInt(_T_1900) node _T_1902 = eq(_T_1901, asSInt(UInt<1>(0h0))) node _T_1903 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1904 = cvt(_T_1903) node _T_1905 = and(_T_1904, asSInt(UInt<18>(0h2f000))) node _T_1906 = asSInt(_T_1905) node _T_1907 = eq(_T_1906, asSInt(UInt<1>(0h0))) node _T_1908 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<17>(0h10000))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1914 = cvt(_T_1913) node _T_1915 = and(_T_1914, asSInt(UInt<13>(0h1000))) node _T_1916 = asSInt(_T_1915) node _T_1917 = eq(_T_1916, asSInt(UInt<1>(0h0))) node _T_1918 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1919 = cvt(_T_1918) node _T_1920 = and(_T_1919, asSInt(UInt<17>(0h10000))) node _T_1921 = asSInt(_T_1920) node _T_1922 = eq(_T_1921, asSInt(UInt<1>(0h0))) node _T_1923 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1924 = cvt(_T_1923) node _T_1925 = and(_T_1924, asSInt(UInt<27>(0h4000000))) node _T_1926 = asSInt(_T_1925) node _T_1927 = eq(_T_1926, asSInt(UInt<1>(0h0))) node _T_1928 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1929 = cvt(_T_1928) node _T_1930 = and(_T_1929, asSInt(UInt<13>(0h1000))) node _T_1931 = asSInt(_T_1930) node _T_1932 = eq(_T_1931, asSInt(UInt<1>(0h0))) node _T_1933 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1934 = cvt(_T_1933) node _T_1935 = and(_T_1934, asSInt(UInt<13>(0h1000))) node _T_1936 = asSInt(_T_1935) node _T_1937 = eq(_T_1936, asSInt(UInt<1>(0h0))) node _T_1938 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1939 = cvt(_T_1938) node _T_1940 = and(_T_1939, asSInt(UInt<29>(0h10000000))) node _T_1941 = asSInt(_T_1940) node _T_1942 = eq(_T_1941, asSInt(UInt<1>(0h0))) node _T_1943 = or(_T_1892, _T_1897) node _T_1944 = or(_T_1943, _T_1902) node _T_1945 = or(_T_1944, _T_1907) node _T_1946 = or(_T_1945, _T_1912) node _T_1947 = or(_T_1946, _T_1917) node _T_1948 = or(_T_1947, _T_1922) node _T_1949 = or(_T_1948, _T_1927) node _T_1950 = or(_T_1949, _T_1932) node _T_1951 = or(_T_1950, _T_1937) node _T_1952 = or(_T_1951, _T_1942) node _T_1953 = and(_T_1887, _T_1952) node _T_1954 = or(UInt<1>(0h0), _T_1953) node _T_1955 = and(UInt<1>(0h0), _T_1954) node _T_1956 = asUInt(reset) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) when _T_1957 : node _T_1958 = eq(_T_1955, UInt<1>(0h0)) when _T_1958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1955, UInt<1>(0h1), "") : assert_124 node _T_1959 = asUInt(reset) node _T_1960 = eq(_T_1959, UInt<1>(0h0)) when _T_1960 : node _T_1961 = eq(address_ok, UInt<1>(0h0)) when _T_1961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1962 = asUInt(reset) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) when _T_1963 : node _T_1964 = eq(legal_source, UInt<1>(0h0)) when _T_1964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1965 = asUInt(reset) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) when _T_1966 : node _T_1967 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1968 = eq(io.in.b.bits.mask, mask_1) node _T_1969 = asUInt(reset) node _T_1970 = eq(_T_1969, UInt<1>(0h0)) when _T_1970 : node _T_1971 = eq(_T_1968, UInt<1>(0h0)) when _T_1971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1968, UInt<1>(0h1), "") : assert_128 node _T_1972 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(_T_1972, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1972, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1976 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_18 = shr(io.in.c.bits.source, 3) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<3>(0h4)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_23 connect _source_ok_WIRE_2[1], _source_ok_T_24 connect _source_ok_WIRE_2[2], _source_ok_T_25 node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_76 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_77 = cvt(_address_ok_T_76) node _address_ok_T_78 = and(_address_ok_T_77, asSInt(UInt<13>(0h1000))) node _address_ok_T_79 = asSInt(_address_ok_T_78) node _address_ok_T_80 = eq(_address_ok_T_79, asSInt(UInt<1>(0h0))) node _address_ok_T_81 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_82 = cvt(_address_ok_T_81) node _address_ok_T_83 = and(_address_ok_T_82, asSInt(UInt<13>(0h1000))) node _address_ok_T_84 = asSInt(_address_ok_T_83) node _address_ok_T_85 = eq(_address_ok_T_84, asSInt(UInt<1>(0h0))) node _address_ok_T_86 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_87 = cvt(_address_ok_T_86) node _address_ok_T_88 = and(_address_ok_T_87, asSInt(UInt<13>(0h1000))) node _address_ok_T_89 = asSInt(_address_ok_T_88) node _address_ok_T_90 = eq(_address_ok_T_89, asSInt(UInt<1>(0h0))) node _address_ok_T_91 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_92 = cvt(_address_ok_T_91) node _address_ok_T_93 = and(_address_ok_T_92, asSInt(UInt<17>(0h10000))) node _address_ok_T_94 = asSInt(_address_ok_T_93) node _address_ok_T_95 = eq(_address_ok_T_94, asSInt(UInt<1>(0h0))) node _address_ok_T_96 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_97 = cvt(_address_ok_T_96) node _address_ok_T_98 = and(_address_ok_T_97, asSInt(UInt<13>(0h1000))) node _address_ok_T_99 = asSInt(_address_ok_T_98) node _address_ok_T_100 = eq(_address_ok_T_99, asSInt(UInt<1>(0h0))) node _address_ok_T_101 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_102 = cvt(_address_ok_T_101) node _address_ok_T_103 = and(_address_ok_T_102, asSInt(UInt<13>(0h1000))) node _address_ok_T_104 = asSInt(_address_ok_T_103) node _address_ok_T_105 = eq(_address_ok_T_104, asSInt(UInt<1>(0h0))) node _address_ok_T_106 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_107 = cvt(_address_ok_T_106) node _address_ok_T_108 = and(_address_ok_T_107, asSInt(UInt<17>(0h10000))) node _address_ok_T_109 = asSInt(_address_ok_T_108) node _address_ok_T_110 = eq(_address_ok_T_109, asSInt(UInt<1>(0h0))) node _address_ok_T_111 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_112 = cvt(_address_ok_T_111) node _address_ok_T_113 = and(_address_ok_T_112, asSInt(UInt<13>(0h1000))) node _address_ok_T_114 = asSInt(_address_ok_T_113) node _address_ok_T_115 = eq(_address_ok_T_114, asSInt(UInt<1>(0h0))) node _address_ok_T_116 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_117 = cvt(_address_ok_T_116) node _address_ok_T_118 = and(_address_ok_T_117, asSInt(UInt<17>(0h10000))) node _address_ok_T_119 = asSInt(_address_ok_T_118) node _address_ok_T_120 = eq(_address_ok_T_119, asSInt(UInt<1>(0h0))) node _address_ok_T_121 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_122 = cvt(_address_ok_T_121) node _address_ok_T_123 = and(_address_ok_T_122, asSInt(UInt<27>(0h4000000))) node _address_ok_T_124 = asSInt(_address_ok_T_123) node _address_ok_T_125 = eq(_address_ok_T_124, asSInt(UInt<1>(0h0))) node _address_ok_T_126 = xor(io.in.c.bits.address, UInt<29>(0h10016000)) node _address_ok_T_127 = cvt(_address_ok_T_126) node _address_ok_T_128 = and(_address_ok_T_127, asSInt(UInt<13>(0h1000))) node _address_ok_T_129 = asSInt(_address_ok_T_128) node _address_ok_T_130 = eq(_address_ok_T_129, asSInt(UInt<1>(0h0))) node _address_ok_T_131 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_132 = cvt(_address_ok_T_131) node _address_ok_T_133 = and(_address_ok_T_132, asSInt(UInt<13>(0h1000))) node _address_ok_T_134 = asSInt(_address_ok_T_133) node _address_ok_T_135 = eq(_address_ok_T_134, asSInt(UInt<1>(0h0))) node _address_ok_T_136 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_137 = cvt(_address_ok_T_136) node _address_ok_T_138 = and(_address_ok_T_137, asSInt(UInt<29>(0h10000000))) node _address_ok_T_139 = asSInt(_address_ok_T_138) node _address_ok_T_140 = eq(_address_ok_T_139, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[13] connect _address_ok_WIRE_1[0], _address_ok_T_80 connect _address_ok_WIRE_1[1], _address_ok_T_85 connect _address_ok_WIRE_1[2], _address_ok_T_90 connect _address_ok_WIRE_1[3], _address_ok_T_95 connect _address_ok_WIRE_1[4], _address_ok_T_100 connect _address_ok_WIRE_1[5], _address_ok_T_105 connect _address_ok_WIRE_1[6], _address_ok_T_110 connect _address_ok_WIRE_1[7], _address_ok_T_115 connect _address_ok_WIRE_1[8], _address_ok_T_120 connect _address_ok_WIRE_1[9], _address_ok_T_125 connect _address_ok_WIRE_1[10], _address_ok_T_130 connect _address_ok_WIRE_1[11], _address_ok_T_135 connect _address_ok_WIRE_1[12], _address_ok_T_140 node _address_ok_T_141 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_142 = or(_address_ok_T_141, _address_ok_WIRE_1[2]) node _address_ok_T_143 = or(_address_ok_T_142, _address_ok_WIRE_1[3]) node _address_ok_T_144 = or(_address_ok_T_143, _address_ok_WIRE_1[4]) node _address_ok_T_145 = or(_address_ok_T_144, _address_ok_WIRE_1[5]) node _address_ok_T_146 = or(_address_ok_T_145, _address_ok_WIRE_1[6]) node _address_ok_T_147 = or(_address_ok_T_146, _address_ok_WIRE_1[7]) node _address_ok_T_148 = or(_address_ok_T_147, _address_ok_WIRE_1[8]) node _address_ok_T_149 = or(_address_ok_T_148, _address_ok_WIRE_1[9]) node _address_ok_T_150 = or(_address_ok_T_149, _address_ok_WIRE_1[10]) node _address_ok_T_151 = or(_address_ok_T_150, _address_ok_WIRE_1[11]) node address_ok_1 = or(_address_ok_T_151, _address_ok_WIRE_1[12]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_1980 = shr(io.in.c.bits.source, 3) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) node _T_1982 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1983 = and(_T_1981, _T_1982) node _T_1984 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_1985 = and(_T_1983, _T_1984) node _T_1986 = eq(_T_1985, UInt<1>(0h0)) node _T_1987 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1988 = cvt(_T_1987) node _T_1989 = and(_T_1988, asSInt(UInt<1>(0h0))) node _T_1990 = asSInt(_T_1989) node _T_1991 = eq(_T_1990, asSInt(UInt<1>(0h0))) node _T_1992 = or(_T_1986, _T_1991) node _T_1993 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1994 = eq(_T_1993, UInt<1>(0h0)) node _T_1995 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1996 = cvt(_T_1995) node _T_1997 = and(_T_1996, asSInt(UInt<1>(0h0))) node _T_1998 = asSInt(_T_1997) node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0))) node _T_2000 = or(_T_1994, _T_1999) node _T_2001 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) node _T_2003 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2004 = cvt(_T_2003) node _T_2005 = and(_T_2004, asSInt(UInt<1>(0h0))) node _T_2006 = asSInt(_T_2005) node _T_2007 = eq(_T_2006, asSInt(UInt<1>(0h0))) node _T_2008 = or(_T_2002, _T_2007) node _T_2009 = and(_T_1992, _T_2000) node _T_2010 = and(_T_2009, _T_2008) node _T_2011 = asUInt(reset) node _T_2012 = eq(_T_2011, UInt<1>(0h0)) when _T_2012 : node _T_2013 = eq(_T_2010, UInt<1>(0h0)) when _T_2013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_2010, UInt<1>(0h1), "") : assert_131 node _T_2014 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_2014 : node _T_2015 = asUInt(reset) node _T_2016 = eq(_T_2015, UInt<1>(0h0)) when _T_2016 : node _T_2017 = eq(address_ok_1, UInt<1>(0h0)) when _T_2017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(source_ok_2, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2021 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(_T_2021, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2021, UInt<1>(0h1), "") : assert_134 node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2028 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_136 node _T_2032 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2033 = asUInt(reset) node _T_2034 = eq(_T_2033, UInt<1>(0h0)) when _T_2034 : node _T_2035 = eq(_T_2032, UInt<1>(0h0)) when _T_2035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2032, UInt<1>(0h1), "") : assert_137 node _T_2036 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2036 : node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(address_ok_1, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2040 = asUInt(reset) node _T_2041 = eq(_T_2040, UInt<1>(0h0)) when _T_2041 : node _T_2042 = eq(source_ok_2, UInt<1>(0h0)) when _T_2042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2043 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2044 = asUInt(reset) node _T_2045 = eq(_T_2044, UInt<1>(0h0)) when _T_2045 : node _T_2046 = eq(_T_2043, UInt<1>(0h0)) when _T_2046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2043, UInt<1>(0h1), "") : assert_140 node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2050 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_142 node _T_2054 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2054 : node _T_2055 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2056 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2057 = and(_T_2055, _T_2056) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_2058 = shr(io.in.c.bits.source, 3) node _T_2059 = eq(_T_2058, UInt<1>(0h0)) node _T_2060 = leq(UInt<1>(0h0), uncommonBits_14) node _T_2061 = and(_T_2059, _T_2060) node _T_2062 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_2063 = and(_T_2061, _T_2062) node _T_2064 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2065 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2066 = or(_T_2063, _T_2064) node _T_2067 = or(_T_2066, _T_2065) node _T_2068 = and(_T_2057, _T_2067) node _T_2069 = or(UInt<1>(0h0), _T_2068) node _T_2070 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2071 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2072 = cvt(_T_2071) node _T_2073 = and(_T_2072, asSInt(UInt<14>(0h2000))) node _T_2074 = asSInt(_T_2073) node _T_2075 = eq(_T_2074, asSInt(UInt<1>(0h0))) node _T_2076 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2077 = cvt(_T_2076) node _T_2078 = and(_T_2077, asSInt(UInt<13>(0h1000))) node _T_2079 = asSInt(_T_2078) node _T_2080 = eq(_T_2079, asSInt(UInt<1>(0h0))) node _T_2081 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2082 = cvt(_T_2081) node _T_2083 = and(_T_2082, asSInt(UInt<17>(0h10000))) node _T_2084 = asSInt(_T_2083) node _T_2085 = eq(_T_2084, asSInt(UInt<1>(0h0))) node _T_2086 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2087 = cvt(_T_2086) node _T_2088 = and(_T_2087, asSInt(UInt<18>(0h2f000))) node _T_2089 = asSInt(_T_2088) node _T_2090 = eq(_T_2089, asSInt(UInt<1>(0h0))) node _T_2091 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2092 = cvt(_T_2091) node _T_2093 = and(_T_2092, asSInt(UInt<17>(0h10000))) node _T_2094 = asSInt(_T_2093) node _T_2095 = eq(_T_2094, asSInt(UInt<1>(0h0))) node _T_2096 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2097 = cvt(_T_2096) node _T_2098 = and(_T_2097, asSInt(UInt<13>(0h1000))) node _T_2099 = asSInt(_T_2098) node _T_2100 = eq(_T_2099, asSInt(UInt<1>(0h0))) node _T_2101 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2102 = cvt(_T_2101) node _T_2103 = and(_T_2102, asSInt(UInt<27>(0h4000000))) node _T_2104 = asSInt(_T_2103) node _T_2105 = eq(_T_2104, asSInt(UInt<1>(0h0))) node _T_2106 = xor(io.in.c.bits.address, UInt<29>(0h10016000)) node _T_2107 = cvt(_T_2106) node _T_2108 = and(_T_2107, asSInt(UInt<13>(0h1000))) node _T_2109 = asSInt(_T_2108) node _T_2110 = eq(_T_2109, asSInt(UInt<1>(0h0))) node _T_2111 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<13>(0h1000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = or(_T_2075, _T_2080) node _T_2117 = or(_T_2116, _T_2085) node _T_2118 = or(_T_2117, _T_2090) node _T_2119 = or(_T_2118, _T_2095) node _T_2120 = or(_T_2119, _T_2100) node _T_2121 = or(_T_2120, _T_2105) node _T_2122 = or(_T_2121, _T_2110) node _T_2123 = or(_T_2122, _T_2115) node _T_2124 = and(_T_2070, _T_2123) node _T_2125 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2126 = or(UInt<1>(0h0), _T_2125) node _T_2127 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2128 = cvt(_T_2127) node _T_2129 = and(_T_2128, asSInt(UInt<17>(0h10000))) node _T_2130 = asSInt(_T_2129) node _T_2131 = eq(_T_2130, asSInt(UInt<1>(0h0))) node _T_2132 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2133 = cvt(_T_2132) node _T_2134 = and(_T_2133, asSInt(UInt<29>(0h10000000))) node _T_2135 = asSInt(_T_2134) node _T_2136 = eq(_T_2135, asSInt(UInt<1>(0h0))) node _T_2137 = or(_T_2131, _T_2136) node _T_2138 = and(_T_2126, _T_2137) node _T_2139 = or(UInt<1>(0h0), _T_2124) node _T_2140 = or(_T_2139, _T_2138) node _T_2141 = and(_T_2069, _T_2140) node _T_2142 = asUInt(reset) node _T_2143 = eq(_T_2142, UInt<1>(0h0)) when _T_2143 : node _T_2144 = eq(_T_2141, UInt<1>(0h0)) when _T_2144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2141, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 2, 0) node _T_2145 = shr(io.in.c.bits.source, 3) node _T_2146 = eq(_T_2145, UInt<1>(0h0)) node _T_2147 = leq(UInt<1>(0h0), uncommonBits_15) node _T_2148 = and(_T_2146, _T_2147) node _T_2149 = leq(uncommonBits_15, UInt<3>(0h4)) node _T_2150 = and(_T_2148, _T_2149) node _T_2151 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2152 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2150 connect _WIRE_6[1], _T_2151 connect _WIRE_6[2], _T_2152 node _T_2153 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2154 = mux(_WIRE_6[0], _T_2153, UInt<1>(0h0)) node _T_2155 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2156 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2157 = or(_T_2154, _T_2155) node _T_2158 = or(_T_2157, _T_2156) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2158 node _T_2159 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2160 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2161 = and(_T_2159, _T_2160) node _T_2162 = or(UInt<1>(0h0), _T_2161) node _T_2163 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2164 = cvt(_T_2163) node _T_2165 = and(_T_2164, asSInt(UInt<14>(0h2000))) node _T_2166 = asSInt(_T_2165) node _T_2167 = eq(_T_2166, asSInt(UInt<1>(0h0))) node _T_2168 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2169 = cvt(_T_2168) node _T_2170 = and(_T_2169, asSInt(UInt<13>(0h1000))) node _T_2171 = asSInt(_T_2170) node _T_2172 = eq(_T_2171, asSInt(UInt<1>(0h0))) node _T_2173 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2174 = cvt(_T_2173) node _T_2175 = and(_T_2174, asSInt(UInt<17>(0h10000))) node _T_2176 = asSInt(_T_2175) node _T_2177 = eq(_T_2176, asSInt(UInt<1>(0h0))) node _T_2178 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2179 = cvt(_T_2178) node _T_2180 = and(_T_2179, asSInt(UInt<18>(0h2f000))) node _T_2181 = asSInt(_T_2180) node _T_2182 = eq(_T_2181, asSInt(UInt<1>(0h0))) node _T_2183 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2184 = cvt(_T_2183) node _T_2185 = and(_T_2184, asSInt(UInt<17>(0h10000))) node _T_2186 = asSInt(_T_2185) node _T_2187 = eq(_T_2186, asSInt(UInt<1>(0h0))) node _T_2188 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2189 = cvt(_T_2188) node _T_2190 = and(_T_2189, asSInt(UInt<13>(0h1000))) node _T_2191 = asSInt(_T_2190) node _T_2192 = eq(_T_2191, asSInt(UInt<1>(0h0))) node _T_2193 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2194 = cvt(_T_2193) node _T_2195 = and(_T_2194, asSInt(UInt<17>(0h10000))) node _T_2196 = asSInt(_T_2195) node _T_2197 = eq(_T_2196, asSInt(UInt<1>(0h0))) node _T_2198 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2199 = cvt(_T_2198) node _T_2200 = and(_T_2199, asSInt(UInt<27>(0h4000000))) node _T_2201 = asSInt(_T_2200) node _T_2202 = eq(_T_2201, asSInt(UInt<1>(0h0))) node _T_2203 = xor(io.in.c.bits.address, UInt<29>(0h10016000)) node _T_2204 = cvt(_T_2203) node _T_2205 = and(_T_2204, asSInt(UInt<13>(0h1000))) node _T_2206 = asSInt(_T_2205) node _T_2207 = eq(_T_2206, asSInt(UInt<1>(0h0))) node _T_2208 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2209 = cvt(_T_2208) node _T_2210 = and(_T_2209, asSInt(UInt<13>(0h1000))) node _T_2211 = asSInt(_T_2210) node _T_2212 = eq(_T_2211, asSInt(UInt<1>(0h0))) node _T_2213 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2214 = cvt(_T_2213) node _T_2215 = and(_T_2214, asSInt(UInt<29>(0h10000000))) node _T_2216 = asSInt(_T_2215) node _T_2217 = eq(_T_2216, asSInt(UInt<1>(0h0))) node _T_2218 = or(_T_2167, _T_2172) node _T_2219 = or(_T_2218, _T_2177) node _T_2220 = or(_T_2219, _T_2182) node _T_2221 = or(_T_2220, _T_2187) node _T_2222 = or(_T_2221, _T_2192) node _T_2223 = or(_T_2222, _T_2197) node _T_2224 = or(_T_2223, _T_2202) node _T_2225 = or(_T_2224, _T_2207) node _T_2226 = or(_T_2225, _T_2212) node _T_2227 = or(_T_2226, _T_2217) node _T_2228 = and(_T_2162, _T_2227) node _T_2229 = or(UInt<1>(0h0), _T_2228) node _T_2230 = and(_WIRE_7, _T_2229) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_144 node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(source_ok_2, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2237 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_146 node _T_2241 = asUInt(reset) node _T_2242 = eq(_T_2241, UInt<1>(0h0)) when _T_2242 : node _T_2243 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2244 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(_T_2244, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2244, UInt<1>(0h1), "") : assert_148 node _T_2248 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_149 node _T_2252 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2252 : node _T_2253 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2254 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2255 = and(_T_2253, _T_2254) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_2256 = shr(io.in.c.bits.source, 3) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) node _T_2258 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2259 = and(_T_2257, _T_2258) node _T_2260 = leq(uncommonBits_16, UInt<3>(0h4)) node _T_2261 = and(_T_2259, _T_2260) node _T_2262 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2263 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2264 = or(_T_2261, _T_2262) node _T_2265 = or(_T_2264, _T_2263) node _T_2266 = and(_T_2255, _T_2265) node _T_2267 = or(UInt<1>(0h0), _T_2266) node _T_2268 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2269 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2270 = cvt(_T_2269) node _T_2271 = and(_T_2270, asSInt(UInt<14>(0h2000))) node _T_2272 = asSInt(_T_2271) node _T_2273 = eq(_T_2272, asSInt(UInt<1>(0h0))) node _T_2274 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2275 = cvt(_T_2274) node _T_2276 = and(_T_2275, asSInt(UInt<13>(0h1000))) node _T_2277 = asSInt(_T_2276) node _T_2278 = eq(_T_2277, asSInt(UInt<1>(0h0))) node _T_2279 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2280 = cvt(_T_2279) node _T_2281 = and(_T_2280, asSInt(UInt<17>(0h10000))) node _T_2282 = asSInt(_T_2281) node _T_2283 = eq(_T_2282, asSInt(UInt<1>(0h0))) node _T_2284 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2285 = cvt(_T_2284) node _T_2286 = and(_T_2285, asSInt(UInt<18>(0h2f000))) node _T_2287 = asSInt(_T_2286) node _T_2288 = eq(_T_2287, asSInt(UInt<1>(0h0))) node _T_2289 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2290 = cvt(_T_2289) node _T_2291 = and(_T_2290, asSInt(UInt<17>(0h10000))) node _T_2292 = asSInt(_T_2291) node _T_2293 = eq(_T_2292, asSInt(UInt<1>(0h0))) node _T_2294 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2295 = cvt(_T_2294) node _T_2296 = and(_T_2295, asSInt(UInt<13>(0h1000))) node _T_2297 = asSInt(_T_2296) node _T_2298 = eq(_T_2297, asSInt(UInt<1>(0h0))) node _T_2299 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2300 = cvt(_T_2299) node _T_2301 = and(_T_2300, asSInt(UInt<27>(0h4000000))) node _T_2302 = asSInt(_T_2301) node _T_2303 = eq(_T_2302, asSInt(UInt<1>(0h0))) node _T_2304 = xor(io.in.c.bits.address, UInt<29>(0h10016000)) node _T_2305 = cvt(_T_2304) node _T_2306 = and(_T_2305, asSInt(UInt<13>(0h1000))) node _T_2307 = asSInt(_T_2306) node _T_2308 = eq(_T_2307, asSInt(UInt<1>(0h0))) node _T_2309 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2310 = cvt(_T_2309) node _T_2311 = and(_T_2310, asSInt(UInt<13>(0h1000))) node _T_2312 = asSInt(_T_2311) node _T_2313 = eq(_T_2312, asSInt(UInt<1>(0h0))) node _T_2314 = or(_T_2273, _T_2278) node _T_2315 = or(_T_2314, _T_2283) node _T_2316 = or(_T_2315, _T_2288) node _T_2317 = or(_T_2316, _T_2293) node _T_2318 = or(_T_2317, _T_2298) node _T_2319 = or(_T_2318, _T_2303) node _T_2320 = or(_T_2319, _T_2308) node _T_2321 = or(_T_2320, _T_2313) node _T_2322 = and(_T_2268, _T_2321) node _T_2323 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2324 = or(UInt<1>(0h0), _T_2323) node _T_2325 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2326 = cvt(_T_2325) node _T_2327 = and(_T_2326, asSInt(UInt<17>(0h10000))) node _T_2328 = asSInt(_T_2327) node _T_2329 = eq(_T_2328, asSInt(UInt<1>(0h0))) node _T_2330 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2331 = cvt(_T_2330) node _T_2332 = and(_T_2331, asSInt(UInt<29>(0h10000000))) node _T_2333 = asSInt(_T_2332) node _T_2334 = eq(_T_2333, asSInt(UInt<1>(0h0))) node _T_2335 = or(_T_2329, _T_2334) node _T_2336 = and(_T_2324, _T_2335) node _T_2337 = or(UInt<1>(0h0), _T_2322) node _T_2338 = or(_T_2337, _T_2336) node _T_2339 = and(_T_2267, _T_2338) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_2343 = shr(io.in.c.bits.source, 3) node _T_2344 = eq(_T_2343, UInt<1>(0h0)) node _T_2345 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2346 = and(_T_2344, _T_2345) node _T_2347 = leq(uncommonBits_17, UInt<3>(0h4)) node _T_2348 = and(_T_2346, _T_2347) node _T_2349 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2350 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2348 connect _WIRE_8[1], _T_2349 connect _WIRE_8[2], _T_2350 node _T_2351 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2352 = mux(_WIRE_8[0], _T_2351, UInt<1>(0h0)) node _T_2353 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2354 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2355 = or(_T_2352, _T_2353) node _T_2356 = or(_T_2355, _T_2354) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2356 node _T_2357 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2358 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2359 = and(_T_2357, _T_2358) node _T_2360 = or(UInt<1>(0h0), _T_2359) node _T_2361 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2362 = cvt(_T_2361) node _T_2363 = and(_T_2362, asSInt(UInt<14>(0h2000))) node _T_2364 = asSInt(_T_2363) node _T_2365 = eq(_T_2364, asSInt(UInt<1>(0h0))) node _T_2366 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2367 = cvt(_T_2366) node _T_2368 = and(_T_2367, asSInt(UInt<13>(0h1000))) node _T_2369 = asSInt(_T_2368) node _T_2370 = eq(_T_2369, asSInt(UInt<1>(0h0))) node _T_2371 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2372 = cvt(_T_2371) node _T_2373 = and(_T_2372, asSInt(UInt<17>(0h10000))) node _T_2374 = asSInt(_T_2373) node _T_2375 = eq(_T_2374, asSInt(UInt<1>(0h0))) node _T_2376 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2377 = cvt(_T_2376) node _T_2378 = and(_T_2377, asSInt(UInt<18>(0h2f000))) node _T_2379 = asSInt(_T_2378) node _T_2380 = eq(_T_2379, asSInt(UInt<1>(0h0))) node _T_2381 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2382 = cvt(_T_2381) node _T_2383 = and(_T_2382, asSInt(UInt<17>(0h10000))) node _T_2384 = asSInt(_T_2383) node _T_2385 = eq(_T_2384, asSInt(UInt<1>(0h0))) node _T_2386 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2387 = cvt(_T_2386) node _T_2388 = and(_T_2387, asSInt(UInt<13>(0h1000))) node _T_2389 = asSInt(_T_2388) node _T_2390 = eq(_T_2389, asSInt(UInt<1>(0h0))) node _T_2391 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2392 = cvt(_T_2391) node _T_2393 = and(_T_2392, asSInt(UInt<17>(0h10000))) node _T_2394 = asSInt(_T_2393) node _T_2395 = eq(_T_2394, asSInt(UInt<1>(0h0))) node _T_2396 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2397 = cvt(_T_2396) node _T_2398 = and(_T_2397, asSInt(UInt<27>(0h4000000))) node _T_2399 = asSInt(_T_2398) node _T_2400 = eq(_T_2399, asSInt(UInt<1>(0h0))) node _T_2401 = xor(io.in.c.bits.address, UInt<29>(0h10016000)) node _T_2402 = cvt(_T_2401) node _T_2403 = and(_T_2402, asSInt(UInt<13>(0h1000))) node _T_2404 = asSInt(_T_2403) node _T_2405 = eq(_T_2404, asSInt(UInt<1>(0h0))) node _T_2406 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2407 = cvt(_T_2406) node _T_2408 = and(_T_2407, asSInt(UInt<13>(0h1000))) node _T_2409 = asSInt(_T_2408) node _T_2410 = eq(_T_2409, asSInt(UInt<1>(0h0))) node _T_2411 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2412 = cvt(_T_2411) node _T_2413 = and(_T_2412, asSInt(UInt<29>(0h10000000))) node _T_2414 = asSInt(_T_2413) node _T_2415 = eq(_T_2414, asSInt(UInt<1>(0h0))) node _T_2416 = or(_T_2365, _T_2370) node _T_2417 = or(_T_2416, _T_2375) node _T_2418 = or(_T_2417, _T_2380) node _T_2419 = or(_T_2418, _T_2385) node _T_2420 = or(_T_2419, _T_2390) node _T_2421 = or(_T_2420, _T_2395) node _T_2422 = or(_T_2421, _T_2400) node _T_2423 = or(_T_2422, _T_2405) node _T_2424 = or(_T_2423, _T_2410) node _T_2425 = or(_T_2424, _T_2415) node _T_2426 = and(_T_2360, _T_2425) node _T_2427 = or(UInt<1>(0h0), _T_2426) node _T_2428 = and(_WIRE_9, _T_2427) node _T_2429 = asUInt(reset) node _T_2430 = eq(_T_2429, UInt<1>(0h0)) when _T_2430 : node _T_2431 = eq(_T_2428, UInt<1>(0h0)) when _T_2431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2428, UInt<1>(0h1), "") : assert_151 node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(source_ok_2, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2435 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_153 node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2442 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2443 = asUInt(reset) node _T_2444 = eq(_T_2443, UInt<1>(0h0)) when _T_2444 : node _T_2445 = eq(_T_2442, UInt<1>(0h0)) when _T_2445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2442, UInt<1>(0h1), "") : assert_155 node _T_2446 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2446 : node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(address_ok_1, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(source_ok_2, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2453 = asUInt(reset) node _T_2454 = eq(_T_2453, UInt<1>(0h0)) when _T_2454 : node _T_2455 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2456 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2457 = asUInt(reset) node _T_2458 = eq(_T_2457, UInt<1>(0h0)) when _T_2458 : node _T_2459 = eq(_T_2456, UInt<1>(0h0)) when _T_2459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2456, UInt<1>(0h1), "") : assert_159 node _T_2460 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2461 = asUInt(reset) node _T_2462 = eq(_T_2461, UInt<1>(0h0)) when _T_2462 : node _T_2463 = eq(_T_2460, UInt<1>(0h0)) when _T_2463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2460, UInt<1>(0h1), "") : assert_160 node _T_2464 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2464 : node _T_2465 = asUInt(reset) node _T_2466 = eq(_T_2465, UInt<1>(0h0)) when _T_2466 : node _T_2467 = eq(address_ok_1, UInt<1>(0h0)) when _T_2467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(source_ok_2, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2471 = asUInt(reset) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) when _T_2472 : node _T_2473 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2474 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2475 = asUInt(reset) node _T_2476 = eq(_T_2475, UInt<1>(0h0)) when _T_2476 : node _T_2477 = eq(_T_2474, UInt<1>(0h0)) when _T_2477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2474, UInt<1>(0h1), "") : assert_164 node _T_2478 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2478 : node _T_2479 = asUInt(reset) node _T_2480 = eq(_T_2479, UInt<1>(0h0)) when _T_2480 : node _T_2481 = eq(address_ok_1, UInt<1>(0h0)) when _T_2481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(source_ok_2, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2485 = asUInt(reset) node _T_2486 = eq(_T_2485, UInt<1>(0h0)) when _T_2486 : node _T_2487 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2488 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2489 = asUInt(reset) node _T_2490 = eq(_T_2489, UInt<1>(0h0)) when _T_2490 : node _T_2491 = eq(_T_2488, UInt<1>(0h0)) when _T_2491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2488, UInt<1>(0h1), "") : assert_168 node _T_2492 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2493 = asUInt(reset) node _T_2494 = eq(_T_2493, UInt<1>(0h0)) when _T_2494 : node _T_2495 = eq(_T_2492, UInt<1>(0h0)) when _T_2495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2492, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<5>(0h10)) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2499 = eq(a_first, UInt<1>(0h0)) node _T_2500 = and(io.in.a.valid, _T_2499) when _T_2500 : node _T_2501 = eq(io.in.a.bits.opcode, opcode) node _T_2502 = asUInt(reset) node _T_2503 = eq(_T_2502, UInt<1>(0h0)) when _T_2503 : node _T_2504 = eq(_T_2501, UInt<1>(0h0)) when _T_2504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2501, UInt<1>(0h1), "") : assert_171 node _T_2505 = eq(io.in.a.bits.param, param) node _T_2506 = asUInt(reset) node _T_2507 = eq(_T_2506, UInt<1>(0h0)) when _T_2507 : node _T_2508 = eq(_T_2505, UInt<1>(0h0)) when _T_2508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2505, UInt<1>(0h1), "") : assert_172 node _T_2509 = eq(io.in.a.bits.size, size) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_173 node _T_2513 = eq(io.in.a.bits.source, source) node _T_2514 = asUInt(reset) node _T_2515 = eq(_T_2514, UInt<1>(0h0)) when _T_2515 : node _T_2516 = eq(_T_2513, UInt<1>(0h0)) when _T_2516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2513, UInt<1>(0h1), "") : assert_174 node _T_2517 = eq(io.in.a.bits.address, address) node _T_2518 = asUInt(reset) node _T_2519 = eq(_T_2518, UInt<1>(0h0)) when _T_2519 : node _T_2520 = eq(_T_2517, UInt<1>(0h0)) when _T_2520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2517, UInt<1>(0h1), "") : assert_175 node _T_2521 = and(io.in.a.ready, io.in.a.valid) node _T_2522 = and(_T_2521, a_first) when _T_2522 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2523 = eq(d_first, UInt<1>(0h0)) node _T_2524 = and(io.in.d.valid, _T_2523) when _T_2524 : node _T_2525 = eq(io.in.d.bits.opcode, opcode_1) node _T_2526 = asUInt(reset) node _T_2527 = eq(_T_2526, UInt<1>(0h0)) when _T_2527 : node _T_2528 = eq(_T_2525, UInt<1>(0h0)) when _T_2528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2525, UInt<1>(0h1), "") : assert_176 node _T_2529 = eq(io.in.d.bits.param, param_1) node _T_2530 = asUInt(reset) node _T_2531 = eq(_T_2530, UInt<1>(0h0)) when _T_2531 : node _T_2532 = eq(_T_2529, UInt<1>(0h0)) when _T_2532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2529, UInt<1>(0h1), "") : assert_177 node _T_2533 = eq(io.in.d.bits.size, size_1) node _T_2534 = asUInt(reset) node _T_2535 = eq(_T_2534, UInt<1>(0h0)) when _T_2535 : node _T_2536 = eq(_T_2533, UInt<1>(0h0)) when _T_2536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2533, UInt<1>(0h1), "") : assert_178 node _T_2537 = eq(io.in.d.bits.source, source_1) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_179 node _T_2541 = eq(io.in.d.bits.sink, sink) node _T_2542 = asUInt(reset) node _T_2543 = eq(_T_2542, UInt<1>(0h0)) when _T_2543 : node _T_2544 = eq(_T_2541, UInt<1>(0h0)) when _T_2544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2541, UInt<1>(0h1), "") : assert_180 node _T_2545 = eq(io.in.d.bits.denied, denied) node _T_2546 = asUInt(reset) node _T_2547 = eq(_T_2546, UInt<1>(0h0)) when _T_2547 : node _T_2548 = eq(_T_2545, UInt<1>(0h0)) when _T_2548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2545, UInt<1>(0h1), "") : assert_181 node _T_2549 = and(io.in.d.ready, io.in.d.valid) node _T_2550 = and(_T_2549, d_first) when _T_2550 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2551 = eq(b_first, UInt<1>(0h0)) node _T_2552 = and(io.in.b.valid, _T_2551) when _T_2552 : node _T_2553 = eq(io.in.b.bits.opcode, opcode_2) node _T_2554 = asUInt(reset) node _T_2555 = eq(_T_2554, UInt<1>(0h0)) when _T_2555 : node _T_2556 = eq(_T_2553, UInt<1>(0h0)) when _T_2556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2553, UInt<1>(0h1), "") : assert_182 node _T_2557 = eq(io.in.b.bits.param, param_2) node _T_2558 = asUInt(reset) node _T_2559 = eq(_T_2558, UInt<1>(0h0)) when _T_2559 : node _T_2560 = eq(_T_2557, UInt<1>(0h0)) when _T_2560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2557, UInt<1>(0h1), "") : assert_183 node _T_2561 = eq(io.in.b.bits.size, size_2) node _T_2562 = asUInt(reset) node _T_2563 = eq(_T_2562, UInt<1>(0h0)) when _T_2563 : node _T_2564 = eq(_T_2561, UInt<1>(0h0)) when _T_2564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2561, UInt<1>(0h1), "") : assert_184 node _T_2565 = eq(io.in.b.bits.source, source_2) node _T_2566 = asUInt(reset) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) when _T_2567 : node _T_2568 = eq(_T_2565, UInt<1>(0h0)) when _T_2568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2565, UInt<1>(0h1), "") : assert_185 node _T_2569 = eq(io.in.b.bits.address, address_1) node _T_2570 = asUInt(reset) node _T_2571 = eq(_T_2570, UInt<1>(0h0)) when _T_2571 : node _T_2572 = eq(_T_2569, UInt<1>(0h0)) when _T_2572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2569, UInt<1>(0h1), "") : assert_186 node _T_2573 = and(io.in.b.ready, io.in.b.valid) node _T_2574 = and(_T_2573, b_first) when _T_2574 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2575 = eq(c_first, UInt<1>(0h0)) node _T_2576 = and(io.in.c.valid, _T_2575) when _T_2576 : node _T_2577 = eq(io.in.c.bits.opcode, opcode_3) node _T_2578 = asUInt(reset) node _T_2579 = eq(_T_2578, UInt<1>(0h0)) when _T_2579 : node _T_2580 = eq(_T_2577, UInt<1>(0h0)) when _T_2580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2577, UInt<1>(0h1), "") : assert_187 node _T_2581 = eq(io.in.c.bits.param, param_3) node _T_2582 = asUInt(reset) node _T_2583 = eq(_T_2582, UInt<1>(0h0)) when _T_2583 : node _T_2584 = eq(_T_2581, UInt<1>(0h0)) when _T_2584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2581, UInt<1>(0h1), "") : assert_188 node _T_2585 = eq(io.in.c.bits.size, size_3) node _T_2586 = asUInt(reset) node _T_2587 = eq(_T_2586, UInt<1>(0h0)) when _T_2587 : node _T_2588 = eq(_T_2585, UInt<1>(0h0)) when _T_2588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2585, UInt<1>(0h1), "") : assert_189 node _T_2589 = eq(io.in.c.bits.source, source_3) node _T_2590 = asUInt(reset) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) when _T_2591 : node _T_2592 = eq(_T_2589, UInt<1>(0h0)) when _T_2592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2589, UInt<1>(0h1), "") : assert_190 node _T_2593 = eq(io.in.c.bits.address, address_2) node _T_2594 = asUInt(reset) node _T_2595 = eq(_T_2594, UInt<1>(0h0)) when _T_2595 : node _T_2596 = eq(_T_2593, UInt<1>(0h0)) when _T_2596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2593, UInt<1>(0h1), "") : assert_191 node _T_2597 = and(io.in.c.ready, io.in.c.valid) node _T_2598 = and(_T_2597, c_first) when _T_2598 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes : UInt<72>, clock, reset, UInt<72>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<9> connect a_set, UInt<9>(0h0) wire a_set_wo_ready : UInt<9> connect a_set_wo_ready, UInt<9>(0h0) wire a_opcodes_set : UInt<36> connect a_opcodes_set, UInt<36>(0h0) wire a_sizes_set : UInt<72> connect a_sizes_set, UInt<72>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2599 = and(io.in.a.valid, a_first_1) node _T_2600 = and(_T_2599, UInt<1>(0h1)) when _T_2600 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2601 = and(io.in.a.ready, io.in.a.valid) node _T_2602 = and(_T_2601, a_first_1) node _T_2603 = and(_T_2602, UInt<1>(0h1)) when _T_2603 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2604 = dshr(inflight, io.in.a.bits.source) node _T_2605 = bits(_T_2604, 0, 0) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) node _T_2607 = asUInt(reset) node _T_2608 = eq(_T_2607, UInt<1>(0h0)) when _T_2608 : node _T_2609 = eq(_T_2606, UInt<1>(0h0)) when _T_2609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2606, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<9> connect d_clr, UInt<9>(0h0) wire d_clr_wo_ready : UInt<9> connect d_clr_wo_ready, UInt<9>(0h0) wire d_opcodes_clr : UInt<36> connect d_opcodes_clr, UInt<36>(0h0) wire d_sizes_clr : UInt<72> connect d_sizes_clr, UInt<72>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2610 = and(io.in.d.valid, d_first_1) node _T_2611 = and(_T_2610, UInt<1>(0h1)) node _T_2612 = eq(d_release_ack, UInt<1>(0h0)) node _T_2613 = and(_T_2611, _T_2612) when _T_2613 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2614 = and(io.in.d.ready, io.in.d.valid) node _T_2615 = and(_T_2614, d_first_1) node _T_2616 = and(_T_2615, UInt<1>(0h1)) node _T_2617 = eq(d_release_ack, UInt<1>(0h0)) node _T_2618 = and(_T_2616, _T_2617) when _T_2618 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2619 = and(io.in.d.valid, d_first_1) node _T_2620 = and(_T_2619, UInt<1>(0h1)) node _T_2621 = eq(d_release_ack, UInt<1>(0h0)) node _T_2622 = and(_T_2620, _T_2621) when _T_2622 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2623 = dshr(inflight, io.in.d.bits.source) node _T_2624 = bits(_T_2623, 0, 0) node _T_2625 = or(_T_2624, same_cycle_resp) node _T_2626 = asUInt(reset) node _T_2627 = eq(_T_2626, UInt<1>(0h0)) when _T_2627 : node _T_2628 = eq(_T_2625, UInt<1>(0h0)) when _T_2628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2625, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2629 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2630 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2631 = or(_T_2629, _T_2630) node _T_2632 = asUInt(reset) node _T_2633 = eq(_T_2632, UInt<1>(0h0)) when _T_2633 : node _T_2634 = eq(_T_2631, UInt<1>(0h0)) when _T_2634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2631, UInt<1>(0h1), "") : assert_194 node _T_2635 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2636 = asUInt(reset) node _T_2637 = eq(_T_2636, UInt<1>(0h0)) when _T_2637 : node _T_2638 = eq(_T_2635, UInt<1>(0h0)) when _T_2638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2635, UInt<1>(0h1), "") : assert_195 else : node _T_2639 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2640 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2641 = or(_T_2639, _T_2640) node _T_2642 = asUInt(reset) node _T_2643 = eq(_T_2642, UInt<1>(0h0)) when _T_2643 : node _T_2644 = eq(_T_2641, UInt<1>(0h0)) when _T_2644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2641, UInt<1>(0h1), "") : assert_196 node _T_2645 = eq(io.in.d.bits.size, a_size_lookup) node _T_2646 = asUInt(reset) node _T_2647 = eq(_T_2646, UInt<1>(0h0)) when _T_2647 : node _T_2648 = eq(_T_2645, UInt<1>(0h0)) when _T_2648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2645, UInt<1>(0h1), "") : assert_197 node _T_2649 = and(io.in.d.valid, d_first_1) node _T_2650 = and(_T_2649, a_first_1) node _T_2651 = and(_T_2650, io.in.a.valid) node _T_2652 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2653 = and(_T_2651, _T_2652) node _T_2654 = eq(d_release_ack, UInt<1>(0h0)) node _T_2655 = and(_T_2653, _T_2654) when _T_2655 : node _T_2656 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2657 = or(_T_2656, io.in.a.ready) node _T_2658 = asUInt(reset) node _T_2659 = eq(_T_2658, UInt<1>(0h0)) when _T_2659 : node _T_2660 = eq(_T_2657, UInt<1>(0h0)) when _T_2660 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2657, UInt<1>(0h1), "") : assert_198 node _T_2661 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2662 = orr(a_set_wo_ready) node _T_2663 = eq(_T_2662, UInt<1>(0h0)) node _T_2664 = or(_T_2661, _T_2663) node _T_2665 = asUInt(reset) node _T_2666 = eq(_T_2665, UInt<1>(0h0)) when _T_2666 : node _T_2667 = eq(_T_2664, UInt<1>(0h0)) when _T_2667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2664, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_2 node _T_2668 = orr(inflight) node _T_2669 = eq(_T_2668, UInt<1>(0h0)) node _T_2670 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2671 = or(_T_2669, _T_2670) node _T_2672 = lt(watchdog, plusarg_reader.out) node _T_2673 = or(_T_2671, _T_2672) node _T_2674 = asUInt(reset) node _T_2675 = eq(_T_2674, UInt<1>(0h0)) when _T_2675 : node _T_2676 = eq(_T_2673, UInt<1>(0h0)) when _T_2676 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2673, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2677 = and(io.in.a.ready, io.in.a.valid) node _T_2678 = and(io.in.d.ready, io.in.d.valid) node _T_2679 = or(_T_2677, _T_2678) when _T_2679 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes_1 : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes_1 : UInt<72>, clock, reset, UInt<72>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<9> connect c_set, UInt<9>(0h0) wire c_set_wo_ready : UInt<9> connect c_set_wo_ready, UInt<9>(0h0) wire c_opcodes_set : UInt<36> connect c_opcodes_set, UInt<36>(0h0) wire c_sizes_set : UInt<72> connect c_sizes_set, UInt<72>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2680 = and(io.in.c.valid, c_first_1) node _T_2681 = bits(io.in.c.bits.opcode, 2, 2) node _T_2682 = bits(io.in.c.bits.opcode, 1, 1) node _T_2683 = and(_T_2681, _T_2682) node _T_2684 = and(_T_2680, _T_2683) when _T_2684 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2685 = and(io.in.c.ready, io.in.c.valid) node _T_2686 = and(_T_2685, c_first_1) node _T_2687 = bits(io.in.c.bits.opcode, 2, 2) node _T_2688 = bits(io.in.c.bits.opcode, 1, 1) node _T_2689 = and(_T_2687, _T_2688) node _T_2690 = and(_T_2686, _T_2689) when _T_2690 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2691 = dshr(inflight_1, io.in.c.bits.source) node _T_2692 = bits(_T_2691, 0, 0) node _T_2693 = eq(_T_2692, UInt<1>(0h0)) node _T_2694 = asUInt(reset) node _T_2695 = eq(_T_2694, UInt<1>(0h0)) when _T_2695 : node _T_2696 = eq(_T_2693, UInt<1>(0h0)) when _T_2696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2693, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<9> connect d_clr_1, UInt<9>(0h0) wire d_clr_wo_ready_1 : UInt<9> connect d_clr_wo_ready_1, UInt<9>(0h0) wire d_opcodes_clr_1 : UInt<36> connect d_opcodes_clr_1, UInt<36>(0h0) wire d_sizes_clr_1 : UInt<72> connect d_sizes_clr_1, UInt<72>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2697 = and(io.in.d.valid, d_first_2) node _T_2698 = and(_T_2697, UInt<1>(0h1)) node _T_2699 = and(_T_2698, d_release_ack_1) when _T_2699 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2700 = and(io.in.d.ready, io.in.d.valid) node _T_2701 = and(_T_2700, d_first_2) node _T_2702 = and(_T_2701, UInt<1>(0h1)) node _T_2703 = and(_T_2702, d_release_ack_1) when _T_2703 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2704 = and(io.in.d.valid, d_first_2) node _T_2705 = and(_T_2704, UInt<1>(0h1)) node _T_2706 = and(_T_2705, d_release_ack_1) when _T_2706 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2707 = dshr(inflight_1, io.in.d.bits.source) node _T_2708 = bits(_T_2707, 0, 0) node _T_2709 = or(_T_2708, same_cycle_resp_1) node _T_2710 = asUInt(reset) node _T_2711 = eq(_T_2710, UInt<1>(0h0)) when _T_2711 : node _T_2712 = eq(_T_2709, UInt<1>(0h0)) when _T_2712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2709, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2713 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2714 = asUInt(reset) node _T_2715 = eq(_T_2714, UInt<1>(0h0)) when _T_2715 : node _T_2716 = eq(_T_2713, UInt<1>(0h0)) when _T_2716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2713, UInt<1>(0h1), "") : assert_203 else : node _T_2717 = eq(io.in.d.bits.size, c_size_lookup) node _T_2718 = asUInt(reset) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) when _T_2719 : node _T_2720 = eq(_T_2717, UInt<1>(0h0)) when _T_2720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2717, UInt<1>(0h1), "") : assert_204 node _T_2721 = and(io.in.d.valid, d_first_2) node _T_2722 = and(_T_2721, c_first_1) node _T_2723 = and(_T_2722, io.in.c.valid) node _T_2724 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2725 = and(_T_2723, _T_2724) node _T_2726 = and(_T_2725, d_release_ack_1) node _T_2727 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2728 = and(_T_2726, _T_2727) when _T_2728 : node _T_2729 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2730 = or(_T_2729, io.in.c.ready) node _T_2731 = asUInt(reset) node _T_2732 = eq(_T_2731, UInt<1>(0h0)) when _T_2732 : node _T_2733 = eq(_T_2730, UInt<1>(0h0)) when _T_2733 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2730, UInt<1>(0h1), "") : assert_205 node _T_2734 = orr(c_set_wo_ready) when _T_2734 : node _T_2735 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2736 = asUInt(reset) node _T_2737 = eq(_T_2736, UInt<1>(0h0)) when _T_2737 : node _T_2738 = eq(_T_2735, UInt<1>(0h0)) when _T_2738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2735, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_3 node _T_2739 = orr(inflight_1) node _T_2740 = eq(_T_2739, UInt<1>(0h0)) node _T_2741 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2742 = or(_T_2740, _T_2741) node _T_2743 = lt(watchdog_1, plusarg_reader_1.out) node _T_2744 = or(_T_2742, _T_2743) node _T_2745 = asUInt(reset) node _T_2746 = eq(_T_2745, UInt<1>(0h0)) when _T_2746 : node _T_2747 = eq(_T_2744, UInt<1>(0h0)) when _T_2747 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2744, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2748 = and(io.in.c.ready, io.in.c.valid) node _T_2749 = and(io.in.d.ready, io.in.d.valid) node _T_2750 = or(_T_2748, _T_2749) when _T_2750 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<16>, clock, reset, UInt<16>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<16> connect d_set, UInt<16>(0h0) node _T_2751 = and(io.in.d.ready, io.in.d.valid) node _T_2752 = and(_T_2751, d_first_3) node _T_2753 = bits(io.in.d.bits.opcode, 2, 2) node _T_2754 = bits(io.in.d.bits.opcode, 1, 1) node _T_2755 = eq(_T_2754, UInt<1>(0h0)) node _T_2756 = and(_T_2753, _T_2755) node _T_2757 = and(_T_2752, _T_2756) when _T_2757 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2758 = dshr(inflight_2, io.in.d.bits.sink) node _T_2759 = bits(_T_2758, 0, 0) node _T_2760 = eq(_T_2759, UInt<1>(0h0)) node _T_2761 = asUInt(reset) node _T_2762 = eq(_T_2761, UInt<1>(0h0)) when _T_2762 : node _T_2763 = eq(_T_2760, UInt<1>(0h0)) when _T_2763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2760, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<16> connect e_clr, UInt<16>(0h0) node _T_2764 = and(io.in.e.ready, io.in.e.valid) node _T_2765 = and(_T_2764, UInt<1>(0h1)) node _T_2766 = and(_T_2765, UInt<1>(0h1)) when _T_2766 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2767 = or(d_set, inflight_2) node _T_2768 = dshr(_T_2767, io.in.e.bits.sink) node _T_2769 = bits(_T_2768, 0, 0) node _T_2770 = asUInt(reset) node _T_2771 = eq(_T_2770, UInt<1>(0h0)) when _T_2771 : node _T_2772 = eq(_T_2769, UInt<1>(0h0)) when _T_2772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2769, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_source = 4'h0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = 4'h0; // @[Parameters.scala:52:29] wire [3:0] _legal_source_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29] wire [3:0] _legal_source_T_10 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_12 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_WIRE_1 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _uncommonBits_T_12 = 4'h0; // @[Parameters.scala:52:29] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_7 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] uncommonBits_11 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _legal_source_T_9 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_11 = 3'h0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_12 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] b_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_76 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = io_in_a_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31] wire _source_ok_T_8 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_8 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_2 = _uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_3 = _uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_8 = _uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_9 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_10 = ~_source_ok_T_9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_13 = source_ok_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_14 = _source_ok_T_12 & _source_ok_T_13; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31] wire _source_ok_T_15 = io_in_d_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31] wire _source_ok_T_16 = io_in_d_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31] wire _source_ok_T_17 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_17 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10016000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [28:0] _GEN_8 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:29], _GEN_8}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_60 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46] wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40] wire _address_ok_T_65 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_70 = _address_ok_T_69 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_71 = _address_ok_T_70 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_72 = _address_ok_T_71 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_73 = _address_ok_T_72 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_74 = _address_ok_T_73 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_75 = _address_ok_T_74 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_75 \| _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = io_in_c_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_2 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = io_in_c_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_c_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_26 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_77 = {1'h0, _address_ok_T_76}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_78 = _address_ok_T_77 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_79 = _address_ok_T_78; // @[Parameters.scala:137:46] wire _address_ok_T_80 = _address_ok_T_79 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_80; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_81 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_82 = {1'h0, _address_ok_T_81}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_83 = _address_ok_T_82 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_84 = _address_ok_T_83; // @[Parameters.scala:137:46] wire _address_ok_T_85 = _address_ok_T_84 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_85; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_86 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_87 = {1'h0, _address_ok_T_86}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_88 = _address_ok_T_87 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_89 = _address_ok_T_88; // @[Parameters.scala:137:46] wire _address_ok_T_90 = _address_ok_T_89 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_90; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_91 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_92 = {1'h0, _address_ok_T_91}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_93 = _address_ok_T_92 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_94 = _address_ok_T_93; // @[Parameters.scala:137:46] wire _address_ok_T_95 = _address_ok_T_94 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_95; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_96 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_97 = {1'h0, _address_ok_T_96}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_98 = _address_ok_T_97 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_99 = _address_ok_T_98; // @[Parameters.scala:137:46] wire _address_ok_T_100 = _address_ok_T_99 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_100; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_101 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_102 = {1'h0, _address_ok_T_101}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_103 = _address_ok_T_102 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_104 = _address_ok_T_103; // @[Parameters.scala:137:46] wire _address_ok_T_105 = _address_ok_T_104 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_105; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_106 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_107 = {1'h0, _address_ok_T_106}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_108 = _address_ok_T_107 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_109 = _address_ok_T_108; // @[Parameters.scala:137:46] wire _address_ok_T_110 = _address_ok_T_109 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_110; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_111 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_112 = {1'h0, _address_ok_T_111}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_113 = _address_ok_T_112 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_114 = _address_ok_T_113; // @[Parameters.scala:137:46] wire _address_ok_T_115 = _address_ok_T_114 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_115; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_116 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_117 = {1'h0, _address_ok_T_116}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_118 = _address_ok_T_117 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_119 = _address_ok_T_118; // @[Parameters.scala:137:46] wire _address_ok_T_120 = _address_ok_T_119 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_120; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_121 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_122 = {1'h0, _address_ok_T_121}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_123 = _address_ok_T_122 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_124 = _address_ok_T_123; // @[Parameters.scala:137:46] wire _address_ok_T_125 = _address_ok_T_124 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_125; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10016000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_126 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_127 = {1'h0, _address_ok_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_128 = _address_ok_T_127 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_129 = _address_ok_T_128; // @[Parameters.scala:137:46] wire _address_ok_T_130 = _address_ok_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_130; // @[Parameters.scala:612:40] wire [28:0] _GEN_18 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_131 = {io_in_c_bits_address_0[31:29], _GEN_18}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_132 = {1'h0, _address_ok_T_131}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_133 = _address_ok_T_132 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_134 = _address_ok_T_133; // @[Parameters.scala:137:46] wire _address_ok_T_135 = _address_ok_T_134 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_135; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_136 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_137 = {1'h0, _address_ok_T_136}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_138 = _address_ok_T_137 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_139 = _address_ok_T_138; // @[Parameters.scala:137:46] wire _address_ok_T_140 = _address_ok_T_139 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_12 = _address_ok_T_140; // @[Parameters.scala:612:40] wire _address_ok_T_141 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_142 = _address_ok_T_141 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_143 = _address_ok_T_142 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_144 = _address_ok_T_143 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_145 = _address_ok_T_144 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_146 = _address_ok_T_145 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_147 = _address_ok_T_146 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_148 = _address_ok_T_147 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_149 = _address_ok_T_148 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_150 = _address_ok_T_149 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_151 = _address_ok_T_150 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_151 \| _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_15 = _uncommonBits_T_15[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire _T_2677 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2677; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2677; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2751 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2751; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2751; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2751; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2751; // @[Decoupled.scala:51:35] wire [26:0] _GEN_19 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_19; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_19; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_19; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_19; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2748 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2748; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2748; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [8:0] inflight; // @[Monitor.scala:614:27] reg [35:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [71:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] a_set; // @[Monitor.scala:626:34] wire [8:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [35:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [71:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_20 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_20; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_20; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_20; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_20; // @[Monitor.scala:637:69, :790:101] wire [35:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [35:0] _a_opcode_lookup_T_6 = {32'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [35:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_21 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_21; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_21; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_21; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_21; // @[Monitor.scala:641:65, :791:99] wire [71:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [71:0] _a_size_lookup_T_6 = {64'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [71:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[71:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_22 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2603 = _T_2677 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2603 ? _a_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2603 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2603 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2603 ? _a_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2603 ? _a_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8:0] d_clr; // @[Monitor.scala:664:34] wire [8:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [35:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [71:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2649 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_24 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_24; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_24; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_24; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2649 & ~d_release_ack ? _d_clr_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2618 = _T_2751 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2618 ? _d_clr_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2618 ? _d_opcodes_clr_T_5[35:0] : 36'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2618 ? _d_sizes_clr_T_5[71:0] : 72'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [35:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [35:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [35:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [71:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [71:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [71:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8:0] inflight_1; // @[Monitor.scala:726:35] reg [35:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [71:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] c_set; // @[Monitor.scala:738:34] wire [8:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [35:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [71:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [35:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [35:0] _c_opcode_lookup_T_6 = {32'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [35:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [71:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [71:0] _c_size_lookup_T_6 = {64'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [71:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[71:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_25 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_25; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2690 = _T_2748 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2690 ? _c_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2690 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2690 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2690 ? _c_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2690 ? _c_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [8:0] d_clr_1; // @[Monitor.scala:774:34] wire [8:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [35:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [71:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2721 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2721 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2703 = _T_2751 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2703 ? _d_clr_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2703 ? _d_opcodes_clr_T_11[35:0] : 36'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2703 ? _d_sizes_clr_T_11[71:0] : 72'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [8:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [8:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [35:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [35:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [35:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [71:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [71:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [71:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2757 = _T_2751 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_26 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_26; // @[OneHot.scala:58:35] assign d_set = _T_2757 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire [15:0] _GEN_27 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_27; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_106 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_213 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_214 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_106( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_192 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_192( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_21 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_21( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip bypass : UInt<1>, pending : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_52 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) connect in_reset, UInt<1>(0h0) reg bypass_reg : UInt<1>, clock node bypass = mux(in_reset, io.bypass, bypass_reg) regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) node _T = and(nodeIn.a.ready, nodeIn.a.valid) node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node a_first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node a_last = or(_r_last_T, _r_last_T_1) node r_3 = and(a_last, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(a_first, r_beats1, r_counter1) connect r_counter, _r_counter_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) node r_counter1_1 = tail(_r_counter1_T_1, 1) node b_first = eq(r_counter_1, UInt<1>(0h0)) node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) node b_last = or(_r_last_T_2, _r_last_T_3) node r_3_1 = and(b_last, _T_1) node _r_count_T_1 = not(r_counter1_1) node r_4_1 = and(r_beats1_1, _r_count_T_1) when _T_1 : node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) connect r_counter_1, _r_counter_T_1 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) node r_counter1_2 = tail(_r_counter1_T_2, 1) node c_first = eq(r_counter_2, UInt<1>(0h0)) node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) node c_last = or(_r_last_T_4, _r_last_T_5) node r_3_2 = and(c_last, _T_2) node _r_count_T_2 = not(r_counter1_2) node r_4_2 = and(r_beats1_2, _r_count_T_2) when _T_2 : node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) connect r_counter_2, _r_counter_T_2 node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) node r_counter1_3 = tail(_r_counter1_T_3, 1) node d_first = eq(r_counter_3, UInt<1>(0h0)) node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) node d_last = or(_r_last_T_6, _r_last_T_7) node r_3_3 = and(d_last, _T_3) node _r_count_T_3 = not(r_counter1_3) node r_4_3 = and(r_beats1_3, _r_count_T_3) when _T_3 : node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) connect r_counter_3, _r_counter_T_3 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) node r_counter1_4 = tail(_r_counter1_T_4, 1) node e_first = eq(r_counter_4, UInt<1>(0h0)) node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node e_last = or(_r_last_T_8, _r_last_T_9) node r_3_4 = and(e_last, _T_4) node _r_count_T_4 = not(r_counter1_4) node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) when _T_4 : node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) connect r_counter_4, _r_counter_T_4 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.mask, UInt<4>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<2>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) node c_request = and(_T_5, _T_6) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_8 = eq(_T_7, UInt<1>(0h0)) node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_10 = eq(_T_9, UInt<1>(0h0)) node c_response = or(_T_8, _T_10) node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) node _T_13 = eq(_T_12, UInt<1>(0h0)) node d_request = and(_T_11, _T_13) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_14.bits.sink, UInt<1>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_inc_T_1 = and(_a_inc_T, a_first) node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_inc_WIRE.bits.data, UInt<32>(0h0) connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) connect _b_inc_WIRE.bits.address, UInt<9>(0h0) connect _b_inc_WIRE.bits.source, UInt<1>(0h0) connect _b_inc_WIRE.bits.size, UInt<2>(0h0) connect _b_inc_WIRE.bits.param, UInt<2>(0h0) connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _b_inc_WIRE.valid, UInt<1>(0h0) connect _b_inc_WIRE.ready, UInt<1>(0h0) wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) node _b_inc_T_1 = and(_b_inc_T, b_first) node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_inc_WIRE.bits.data, UInt<32>(0h0) connect _c_inc_WIRE.bits.address, UInt<9>(0h0) connect _c_inc_WIRE.bits.source, UInt<1>(0h0) connect _c_inc_WIRE.bits.size, UInt<2>(0h0) connect _c_inc_WIRE.bits.param, UInt<3>(0h0) connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _c_inc_WIRE.valid, UInt<1>(0h0) connect _c_inc_WIRE.ready, UInt<1>(0h0) wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) node _c_inc_T_1 = and(_c_inc_T, c_first) node c_inc = and(_c_inc_T_1, c_request) node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_inc_T_1 = and(_d_inc_T, d_first) node d_inc = and(_d_inc_T_1, d_request) wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) connect _e_inc_WIRE.valid, UInt<1>(0h0) connect _e_inc_WIRE.ready, UInt<1>(0h0) wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) node _e_inc_T_1 = and(_e_inc_T, e_first) node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) node inc = cat(a_inc, d_inc) node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_dec_T_1 = and(_a_dec_T, a_last) node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_dec_WIRE.bits.data, UInt<32>(0h0) connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) connect _b_dec_WIRE.bits.address, UInt<9>(0h0) connect _b_dec_WIRE.bits.source, UInt<1>(0h0) connect _b_dec_WIRE.bits.size, UInt<2>(0h0) connect _b_dec_WIRE.bits.param, UInt<2>(0h0) connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _b_dec_WIRE.valid, UInt<1>(0h0) connect _b_dec_WIRE.ready, UInt<1>(0h0) wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) node _b_dec_T_1 = and(_b_dec_T, b_last) node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_dec_WIRE.bits.data, UInt<32>(0h0) connect _c_dec_WIRE.bits.address, UInt<9>(0h0) connect _c_dec_WIRE.bits.source, UInt<1>(0h0) connect _c_dec_WIRE.bits.size, UInt<2>(0h0) connect _c_dec_WIRE.bits.param, UInt<3>(0h0) connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _c_dec_WIRE.valid, UInt<1>(0h0) connect _c_dec_WIRE.ready, UInt<1>(0h0) wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) node _c_dec_T_1 = and(_c_dec_T, c_last) node c_dec = and(_c_dec_T_1, c_response) node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_dec_T_1 = and(_d_dec_T, d_last) node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) connect _e_dec_WIRE.valid, UInt<1>(0h0) connect _e_dec_WIRE.ready, UInt<1>(0h0) wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) node _e_dec_T_1 = and(_e_dec_T, e_last) node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) node dec = cat(a_dec, d_dec) node _next_flight_T = bits(inc, 0, 0) node _next_flight_T_1 = bits(inc, 1, 1) node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) node _next_flight_T_4 = add(flight, _next_flight_T_3) node _next_flight_T_5 = tail(_next_flight_T_4, 1) node _next_flight_T_6 = bits(dec, 0, 0) node _next_flight_T_7 = bits(dec, 1, 1) node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) node next_flight = tail(_next_flight_T_10, 1) connect flight, next_flight node _io_pending_T = gt(flight, UInt<1>(0h0)) connect io.pending, _io_pending_T node _T_14 = eq(next_flight, UInt<1>(0h0)) node _T_15 = or(in_reset, _T_14) when _T_15 : connect bypass_reg, io.bypass node _stall_T = neq(bypass, io.bypass) node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) node stall_counter1 = tail(_stall_counter1_T, 1) node stall_first = eq(stall_counter, UInt<1>(0h0)) node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) node stall_last = or(_stall_last_T, _stall_last_T_1) node stall_done = and(stall_last, _stall_T_1) node _stall_count_T = not(stall_counter1) node stall_count = and(stall_beats1, _stall_count_T) when _stall_T_1 : node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) connect stall_counter, _stall_counter_T node stall = and(_stall_T, stall_first) node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) connect nodeIn.a.ready, _nodeIn_a_ready_T_2 connect nodeOut.a.bits, nodeIn.a.bits connect x1_nodeOut.a.bits, nodeIn.a.bits node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) connect nodeOut.d.ready, _nodeOut_d_ready_T node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) connect nodeIn.d.valid, _nodeIn_d_valid_T wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out, nodeIn.d.bits connect nodeIn_d_bits_out, nodeOut.d.bits wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out_1, nodeIn.d.bits connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.mask, UInt<4>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.ready, UInt<1>(0h1) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.address, UInt<128>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<2>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.valid, UInt<1>(0h0) wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_28.bits.sink, UInt<1>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<9>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<2>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<9>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<2>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready connect _WIRE_33.valid, UInt<1>(0h0) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_34.bits.sink, UInt<1>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) extmodule plusarg_reader_107 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_108 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = \|flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset \| next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_52 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_22 : input clock : Clock input reset : Reset output io : { req : { flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}}, resp : { `1` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, `0` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<13> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_andMatrixInput_6) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_6_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_3, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_4_5, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_orMatrixOutputs_hi = cat(decoded_andMatrixOutputs_5_2, decoded_andMatrixOutputs_3_2) node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_2 = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 1, 0) node _decoded_T_1 = bits(_decoded_T, 0, 0) node _decoded_T_2 = bits(_decoded_T, 1, 1) node _decoded_T_3 = cat(_decoded_T_1, _decoded_T_2) node _decoded_T_4 = bits(decoded_plaOutput, 3, 2) node _decoded_T_5 = bits(_decoded_T_4, 0, 0) node _decoded_T_6 = bits(_decoded_T_4, 1, 1) node _decoded_T_7 = cat(_decoded_T_5, _decoded_T_6) node decoded = cat(_decoded_T_3, _decoded_T_7) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T connect io.resp.`0`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<13> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_8, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_5_6, decoded_andMatrixOutputs_andMatrixInput_6_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T_4 = orr(decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_lo_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs_1, 3, 3) node decoded_invMatrixOutputs_lo_1 = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_1 = cat(_decoded_invMatrixOutputs_T_7, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_8 = bits(decoded_plaOutput_1, 1, 0) node _decoded_T_9 = bits(_decoded_T_8, 0, 0) node _decoded_T_10 = bits(_decoded_T_8, 1, 1) node _decoded_T_11 = cat(_decoded_T_9, _decoded_T_10) node _decoded_T_12 = bits(decoded_plaOutput_1, 3, 2) node _decoded_T_13 = bits(_decoded_T_12, 0, 0) node _decoded_T_14 = bits(_decoded_T_12, 1, 1) node _decoded_T_15 = cat(_decoded_T_13, _decoded_T_14) node decoded_1 = cat(_decoded_T_11, _decoded_T_15) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T connect io.resp.`1`.vc_sel.`1`[0], UInt<1>(0h0) extmodule plusarg_reader_40 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20	module RouteComputer_22( // @[RouteComputer.scala:29:7] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1 // @[RouteComputer.scala:40:14] ); wire [11:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id[0], io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_3 = ~(io_req_1_bits_flow_egress_node[3]); // @[pla.scala:78:21] assign io_resp_0_vc_sel_0_0 = \|{&{decoded_invInputs[0], io_req_0_bits_flow_egress_node[0], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], decoded_invInputs[9], decoded_invInputs[10]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_1 = \|{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_src_virt_id[0]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[0], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_src_virt_id[0]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_src_virt_id[0]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<29>(0h10000000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<29>(0h10000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<29>(0h10000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<29>(0h10000000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<29>(0h10000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<29>(0h10000000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<29>(0h10000000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<29>(0h10000000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<29>(0h10000000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h1), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h1), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h1), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h1), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h1), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_32 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_33 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_87 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_104 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_87( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_104 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RVCExpander_6 : input clock : Clock input reset : Reset output io : { flip in : UInt<32>, out : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>, ill : UInt<1>} node _io_rvc_T = bits(io.in, 1, 0) node _io_rvc_T_1 = neq(_io_rvc_T, UInt<2>(0h3)) connect io.rvc, _io_rvc_T_1 node _io_out_s_opc_T = bits(io.in, 12, 5) node _io_out_s_opc_T_1 = orr(_io_out_s_opc_T) node io_out_s_opc = mux(_io_out_s_opc_T_1, UInt<7>(0h13), UInt<7>(0h1f)) node _io_out_s_T = bits(io.in, 10, 7) node _io_out_s_T_1 = bits(io.in, 12, 11) node _io_out_s_T_2 = bits(io.in, 5, 5) node _io_out_s_T_3 = bits(io.in, 6, 6) node io_out_s_lo = cat(_io_out_s_T_3, UInt<2>(0h0)) node io_out_s_hi_hi = cat(_io_out_s_T, _io_out_s_T_1) node io_out_s_hi = cat(io_out_s_hi_hi, _io_out_s_T_2) node _io_out_s_T_4 = cat(io_out_s_hi, io_out_s_lo) node _io_out_s_T_5 = bits(io.in, 4, 2) node _io_out_s_T_6 = cat(UInt<2>(0h1), _io_out_s_T_5) node io_out_s_lo_1 = cat(_io_out_s_T_6, io_out_s_opc) node io_out_s_hi_hi_1 = cat(_io_out_s_T_4, UInt<5>(0h2)) node io_out_s_hi_1 = cat(io_out_s_hi_hi_1, UInt<3>(0h0)) node _io_out_s_T_7 = cat(io_out_s_hi_1, io_out_s_lo_1) node _io_out_s_T_8 = bits(io.in, 4, 2) node _io_out_s_T_9 = cat(UInt<2>(0h1), _io_out_s_T_8) node _io_out_s_T_10 = bits(io.in, 4, 2) node _io_out_s_T_11 = cat(UInt<2>(0h1), _io_out_s_T_10) node _io_out_s_T_12 = bits(io.in, 31, 27) wire io_out_s_0 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_0.bits, _io_out_s_T_7 connect io_out_s_0.rd, _io_out_s_T_9 connect io_out_s_0.rs1, UInt<5>(0h2) connect io_out_s_0.rs2, _io_out_s_T_11 connect io_out_s_0.rs3, _io_out_s_T_12 node _io_out_s_T_13 = bits(io.in, 6, 5) node _io_out_s_T_14 = bits(io.in, 12, 10) node io_out_s_hi_2 = cat(_io_out_s_T_13, _io_out_s_T_14) node _io_out_s_T_15 = cat(io_out_s_hi_2, UInt<3>(0h0)) node _io_out_s_T_16 = bits(io.in, 9, 7) node _io_out_s_T_17 = cat(UInt<2>(0h1), _io_out_s_T_16) node _io_out_s_T_18 = bits(io.in, 4, 2) node _io_out_s_T_19 = cat(UInt<2>(0h1), _io_out_s_T_18) node io_out_s_lo_2 = cat(_io_out_s_T_19, UInt<7>(0h7)) node io_out_s_hi_hi_2 = cat(_io_out_s_T_15, _io_out_s_T_17) node io_out_s_hi_3 = cat(io_out_s_hi_hi_2, UInt<3>(0h3)) node _io_out_s_T_20 = cat(io_out_s_hi_3, io_out_s_lo_2) node _io_out_s_T_21 = bits(io.in, 4, 2) node _io_out_s_T_22 = cat(UInt<2>(0h1), _io_out_s_T_21) node _io_out_s_T_23 = bits(io.in, 9, 7) node _io_out_s_T_24 = cat(UInt<2>(0h1), _io_out_s_T_23) node _io_out_s_T_25 = bits(io.in, 4, 2) node _io_out_s_T_26 = cat(UInt<2>(0h1), _io_out_s_T_25) node _io_out_s_T_27 = bits(io.in, 31, 27) wire io_out_s_1 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_1.bits, _io_out_s_T_20 connect io_out_s_1.rd, _io_out_s_T_22 connect io_out_s_1.rs1, _io_out_s_T_24 connect io_out_s_1.rs2, _io_out_s_T_26 connect io_out_s_1.rs3, _io_out_s_T_27 node _io_out_s_T_28 = bits(io.in, 5, 5) node _io_out_s_T_29 = bits(io.in, 12, 10) node _io_out_s_T_30 = bits(io.in, 6, 6) node io_out_s_lo_3 = cat(_io_out_s_T_30, UInt<2>(0h0)) node io_out_s_hi_4 = cat(_io_out_s_T_28, _io_out_s_T_29) node _io_out_s_T_31 = cat(io_out_s_hi_4, io_out_s_lo_3) node _io_out_s_T_32 = bits(io.in, 9, 7) node _io_out_s_T_33 = cat(UInt<2>(0h1), _io_out_s_T_32) node _io_out_s_T_34 = bits(io.in, 4, 2) node _io_out_s_T_35 = cat(UInt<2>(0h1), _io_out_s_T_34) node io_out_s_lo_4 = cat(_io_out_s_T_35, UInt<7>(0h3)) node io_out_s_hi_hi_3 = cat(_io_out_s_T_31, _io_out_s_T_33) node io_out_s_hi_5 = cat(io_out_s_hi_hi_3, UInt<3>(0h2)) node _io_out_s_T_36 = cat(io_out_s_hi_5, io_out_s_lo_4) node _io_out_s_T_37 = bits(io.in, 4, 2) node _io_out_s_T_38 = cat(UInt<2>(0h1), _io_out_s_T_37) node _io_out_s_T_39 = bits(io.in, 9, 7) node _io_out_s_T_40 = cat(UInt<2>(0h1), _io_out_s_T_39) node _io_out_s_T_41 = bits(io.in, 4, 2) node _io_out_s_T_42 = cat(UInt<2>(0h1), _io_out_s_T_41) node _io_out_s_T_43 = bits(io.in, 31, 27) wire io_out_s_2 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_2.bits, _io_out_s_T_36 connect io_out_s_2.rd, _io_out_s_T_38 connect io_out_s_2.rs1, _io_out_s_T_40 connect io_out_s_2.rs2, _io_out_s_T_42 connect io_out_s_2.rs3, _io_out_s_T_43 node _io_out_s_T_44 = bits(io.in, 6, 5) node _io_out_s_T_45 = bits(io.in, 12, 10) node io_out_s_hi_6 = cat(_io_out_s_T_44, _io_out_s_T_45) node _io_out_s_T_46 = cat(io_out_s_hi_6, UInt<3>(0h0)) node _io_out_s_T_47 = bits(io.in, 9, 7) node _io_out_s_T_48 = cat(UInt<2>(0h1), _io_out_s_T_47) node _io_out_s_T_49 = bits(io.in, 4, 2) node _io_out_s_T_50 = cat(UInt<2>(0h1), _io_out_s_T_49) node io_out_s_lo_5 = cat(_io_out_s_T_50, UInt<7>(0h3)) node io_out_s_hi_hi_4 = cat(_io_out_s_T_46, _io_out_s_T_48) node io_out_s_hi_7 = cat(io_out_s_hi_hi_4, UInt<3>(0h3)) node _io_out_s_T_51 = cat(io_out_s_hi_7, io_out_s_lo_5) node _io_out_s_T_52 = bits(io.in, 4, 2) node _io_out_s_T_53 = cat(UInt<2>(0h1), _io_out_s_T_52) node _io_out_s_T_54 = bits(io.in, 9, 7) node _io_out_s_T_55 = cat(UInt<2>(0h1), _io_out_s_T_54) node _io_out_s_T_56 = bits(io.in, 4, 2) node _io_out_s_T_57 = cat(UInt<2>(0h1), _io_out_s_T_56) node _io_out_s_T_58 = bits(io.in, 31, 27) wire io_out_s_3 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_3.bits, _io_out_s_T_51 connect io_out_s_3.rd, _io_out_s_T_53 connect io_out_s_3.rs1, _io_out_s_T_55 connect io_out_s_3.rs2, _io_out_s_T_57 connect io_out_s_3.rs3, _io_out_s_T_58 node _io_out_s_T_59 = bits(io.in, 5, 5) node _io_out_s_T_60 = bits(io.in, 12, 10) node _io_out_s_T_61 = bits(io.in, 6, 6) node io_out_s_lo_6 = cat(_io_out_s_T_61, UInt<2>(0h0)) node io_out_s_hi_8 = cat(_io_out_s_T_59, _io_out_s_T_60) node _io_out_s_T_62 = cat(io_out_s_hi_8, io_out_s_lo_6) node _io_out_s_T_63 = shr(_io_out_s_T_62, 5) node _io_out_s_T_64 = bits(io.in, 4, 2) node _io_out_s_T_65 = cat(UInt<2>(0h1), _io_out_s_T_64) node _io_out_s_T_66 = bits(io.in, 9, 7) node _io_out_s_T_67 = cat(UInt<2>(0h1), _io_out_s_T_66) node _io_out_s_T_68 = bits(io.in, 5, 5) node _io_out_s_T_69 = bits(io.in, 12, 10) node _io_out_s_T_70 = bits(io.in, 6, 6) node io_out_s_lo_7 = cat(_io_out_s_T_70, UInt<2>(0h0)) node io_out_s_hi_9 = cat(_io_out_s_T_68, _io_out_s_T_69) node _io_out_s_T_71 = cat(io_out_s_hi_9, io_out_s_lo_7) node _io_out_s_T_72 = bits(_io_out_s_T_71, 4, 0) node io_out_s_lo_hi = cat(UInt<3>(0h2), _io_out_s_T_72) node io_out_s_lo_8 = cat(io_out_s_lo_hi, UInt<7>(0h3f)) node io_out_s_hi_hi_5 = cat(_io_out_s_T_63, _io_out_s_T_65) node io_out_s_hi_10 = cat(io_out_s_hi_hi_5, _io_out_s_T_67) node _io_out_s_T_73 = cat(io_out_s_hi_10, io_out_s_lo_8) node _io_out_s_T_74 = bits(io.in, 4, 2) node _io_out_s_T_75 = cat(UInt<2>(0h1), _io_out_s_T_74) node _io_out_s_T_76 = bits(io.in, 9, 7) node _io_out_s_T_77 = cat(UInt<2>(0h1), _io_out_s_T_76) node _io_out_s_T_78 = bits(io.in, 4, 2) node _io_out_s_T_79 = cat(UInt<2>(0h1), _io_out_s_T_78) node _io_out_s_T_80 = bits(io.in, 31, 27) wire io_out_s_4 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_4.bits, _io_out_s_T_73 connect io_out_s_4.rd, _io_out_s_T_75 connect io_out_s_4.rs1, _io_out_s_T_77 connect io_out_s_4.rs2, _io_out_s_T_79 connect io_out_s_4.rs3, _io_out_s_T_80 node _io_out_s_T_81 = bits(io.in, 6, 5) node _io_out_s_T_82 = bits(io.in, 12, 10) node io_out_s_hi_11 = cat(_io_out_s_T_81, _io_out_s_T_82) node _io_out_s_T_83 = cat(io_out_s_hi_11, UInt<3>(0h0)) node _io_out_s_T_84 = shr(_io_out_s_T_83, 5) node _io_out_s_T_85 = bits(io.in, 4, 2) node _io_out_s_T_86 = cat(UInt<2>(0h1), _io_out_s_T_85) node _io_out_s_T_87 = bits(io.in, 9, 7) node _io_out_s_T_88 = cat(UInt<2>(0h1), _io_out_s_T_87) node _io_out_s_T_89 = bits(io.in, 6, 5) node _io_out_s_T_90 = bits(io.in, 12, 10) node io_out_s_hi_12 = cat(_io_out_s_T_89, _io_out_s_T_90) node _io_out_s_T_91 = cat(io_out_s_hi_12, UInt<3>(0h0)) node _io_out_s_T_92 = bits(_io_out_s_T_91, 4, 0) node io_out_s_lo_hi_1 = cat(UInt<3>(0h3), _io_out_s_T_92) node io_out_s_lo_9 = cat(io_out_s_lo_hi_1, UInt<7>(0h27)) node io_out_s_hi_hi_6 = cat(_io_out_s_T_84, _io_out_s_T_86) node io_out_s_hi_13 = cat(io_out_s_hi_hi_6, _io_out_s_T_88) node _io_out_s_T_93 = cat(io_out_s_hi_13, io_out_s_lo_9) node _io_out_s_T_94 = bits(io.in, 4, 2) node _io_out_s_T_95 = cat(UInt<2>(0h1), _io_out_s_T_94) node _io_out_s_T_96 = bits(io.in, 9, 7) node _io_out_s_T_97 = cat(UInt<2>(0h1), _io_out_s_T_96) node _io_out_s_T_98 = bits(io.in, 4, 2) node _io_out_s_T_99 = cat(UInt<2>(0h1), _io_out_s_T_98) node _io_out_s_T_100 = bits(io.in, 31, 27) wire io_out_s_5 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_5.bits, _io_out_s_T_93 connect io_out_s_5.rd, _io_out_s_T_95 connect io_out_s_5.rs1, _io_out_s_T_97 connect io_out_s_5.rs2, _io_out_s_T_99 connect io_out_s_5.rs3, _io_out_s_T_100 node _io_out_s_T_101 = bits(io.in, 5, 5) node _io_out_s_T_102 = bits(io.in, 12, 10) node _io_out_s_T_103 = bits(io.in, 6, 6) node io_out_s_lo_10 = cat(_io_out_s_T_103, UInt<2>(0h0)) node io_out_s_hi_14 = cat(_io_out_s_T_101, _io_out_s_T_102) node _io_out_s_T_104 = cat(io_out_s_hi_14, io_out_s_lo_10) node _io_out_s_T_105 = shr(_io_out_s_T_104, 5) node _io_out_s_T_106 = bits(io.in, 4, 2) node _io_out_s_T_107 = cat(UInt<2>(0h1), _io_out_s_T_106) node _io_out_s_T_108 = bits(io.in, 9, 7) node _io_out_s_T_109 = cat(UInt<2>(0h1), _io_out_s_T_108) node _io_out_s_T_110 = bits(io.in, 5, 5) node _io_out_s_T_111 = bits(io.in, 12, 10) node _io_out_s_T_112 = bits(io.in, 6, 6) node io_out_s_lo_11 = cat(_io_out_s_T_112, UInt<2>(0h0)) node io_out_s_hi_15 = cat(_io_out_s_T_110, _io_out_s_T_111) node _io_out_s_T_113 = cat(io_out_s_hi_15, io_out_s_lo_11) node _io_out_s_T_114 = bits(_io_out_s_T_113, 4, 0) node io_out_s_lo_hi_2 = cat(UInt<3>(0h2), _io_out_s_T_114) node io_out_s_lo_12 = cat(io_out_s_lo_hi_2, UInt<7>(0h23)) node io_out_s_hi_hi_7 = cat(_io_out_s_T_105, _io_out_s_T_107) node io_out_s_hi_16 = cat(io_out_s_hi_hi_7, _io_out_s_T_109) node _io_out_s_T_115 = cat(io_out_s_hi_16, io_out_s_lo_12) node _io_out_s_T_116 = bits(io.in, 4, 2) node _io_out_s_T_117 = cat(UInt<2>(0h1), _io_out_s_T_116) node _io_out_s_T_118 = bits(io.in, 9, 7) node _io_out_s_T_119 = cat(UInt<2>(0h1), _io_out_s_T_118) node _io_out_s_T_120 = bits(io.in, 4, 2) node _io_out_s_T_121 = cat(UInt<2>(0h1), _io_out_s_T_120) node _io_out_s_T_122 = bits(io.in, 31, 27) wire io_out_s_6 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_6.bits, _io_out_s_T_115 connect io_out_s_6.rd, _io_out_s_T_117 connect io_out_s_6.rs1, _io_out_s_T_119 connect io_out_s_6.rs2, _io_out_s_T_121 connect io_out_s_6.rs3, _io_out_s_T_122 node _io_out_s_T_123 = bits(io.in, 6, 5) node _io_out_s_T_124 = bits(io.in, 12, 10) node io_out_s_hi_17 = cat(_io_out_s_T_123, _io_out_s_T_124) node _io_out_s_T_125 = cat(io_out_s_hi_17, UInt<3>(0h0)) node _io_out_s_T_126 = shr(_io_out_s_T_125, 5) node _io_out_s_T_127 = bits(io.in, 4, 2) node _io_out_s_T_128 = cat(UInt<2>(0h1), _io_out_s_T_127) node _io_out_s_T_129 = bits(io.in, 9, 7) node _io_out_s_T_130 = cat(UInt<2>(0h1), _io_out_s_T_129) node _io_out_s_T_131 = bits(io.in, 6, 5) node _io_out_s_T_132 = bits(io.in, 12, 10) node io_out_s_hi_18 = cat(_io_out_s_T_131, _io_out_s_T_132) node _io_out_s_T_133 = cat(io_out_s_hi_18, UInt<3>(0h0)) node _io_out_s_T_134 = bits(_io_out_s_T_133, 4, 0) node io_out_s_lo_hi_3 = cat(UInt<3>(0h3), _io_out_s_T_134) node io_out_s_lo_13 = cat(io_out_s_lo_hi_3, UInt<7>(0h23)) node io_out_s_hi_hi_8 = cat(_io_out_s_T_126, _io_out_s_T_128) node io_out_s_hi_19 = cat(io_out_s_hi_hi_8, _io_out_s_T_130) node _io_out_s_T_135 = cat(io_out_s_hi_19, io_out_s_lo_13) node _io_out_s_T_136 = bits(io.in, 4, 2) node _io_out_s_T_137 = cat(UInt<2>(0h1), _io_out_s_T_136) node _io_out_s_T_138 = bits(io.in, 9, 7) node _io_out_s_T_139 = cat(UInt<2>(0h1), _io_out_s_T_138) node _io_out_s_T_140 = bits(io.in, 4, 2) node _io_out_s_T_141 = cat(UInt<2>(0h1), _io_out_s_T_140) node _io_out_s_T_142 = bits(io.in, 31, 27) wire io_out_s_7 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_7.bits, _io_out_s_T_135 connect io_out_s_7.rd, _io_out_s_T_137 connect io_out_s_7.rs1, _io_out_s_T_139 connect io_out_s_7.rs2, _io_out_s_T_141 connect io_out_s_7.rs3, _io_out_s_T_142 node _io_out_s_T_143 = bits(io.in, 12, 12) node _io_out_s_T_144 = mux(_io_out_s_T_143, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_145 = bits(io.in, 6, 2) node _io_out_s_T_146 = cat(_io_out_s_T_144, _io_out_s_T_145) node _io_out_s_T_147 = bits(io.in, 11, 7) node _io_out_s_T_148 = bits(io.in, 11, 7) node io_out_s_lo_14 = cat(_io_out_s_T_148, UInt<7>(0h13)) node io_out_s_hi_hi_9 = cat(_io_out_s_T_146, _io_out_s_T_147) node io_out_s_hi_20 = cat(io_out_s_hi_hi_9, UInt<3>(0h0)) node _io_out_s_T_149 = cat(io_out_s_hi_20, io_out_s_lo_14) node _io_out_s_T_150 = bits(io.in, 11, 7) node _io_out_s_T_151 = bits(io.in, 11, 7) node _io_out_s_T_152 = bits(io.in, 4, 2) node _io_out_s_T_153 = cat(UInt<2>(0h1), _io_out_s_T_152) node _io_out_s_T_154 = bits(io.in, 31, 27) wire io_out_s_8 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_8.bits, _io_out_s_T_149 connect io_out_s_8.rd, _io_out_s_T_150 connect io_out_s_8.rs1, _io_out_s_T_151 connect io_out_s_8.rs2, _io_out_s_T_153 connect io_out_s_8.rs3, _io_out_s_T_154 node _io_out_s_opc_T_2 = bits(io.in, 11, 7) node _io_out_s_opc_T_3 = orr(_io_out_s_opc_T_2) node io_out_s_opc_1 = mux(_io_out_s_opc_T_3, UInt<7>(0h1b), UInt<7>(0h1f)) node _io_out_s_T_155 = bits(io.in, 12, 12) node _io_out_s_T_156 = mux(_io_out_s_T_155, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_157 = bits(io.in, 6, 2) node _io_out_s_T_158 = cat(_io_out_s_T_156, _io_out_s_T_157) node _io_out_s_T_159 = bits(io.in, 11, 7) node _io_out_s_T_160 = bits(io.in, 11, 7) node io_out_s_lo_15 = cat(_io_out_s_T_160, io_out_s_opc_1) node io_out_s_hi_hi_10 = cat(_io_out_s_T_158, _io_out_s_T_159) node io_out_s_hi_21 = cat(io_out_s_hi_hi_10, UInt<3>(0h0)) node _io_out_s_T_161 = cat(io_out_s_hi_21, io_out_s_lo_15) node _io_out_s_T_162 = bits(io.in, 11, 7) node _io_out_s_T_163 = bits(io.in, 11, 7) node _io_out_s_T_164 = bits(io.in, 4, 2) node _io_out_s_T_165 = cat(UInt<2>(0h1), _io_out_s_T_164) node _io_out_s_T_166 = bits(io.in, 31, 27) wire io_out_s_9 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_9.bits, _io_out_s_T_161 connect io_out_s_9.rd, _io_out_s_T_162 connect io_out_s_9.rs1, _io_out_s_T_163 connect io_out_s_9.rs2, _io_out_s_T_165 connect io_out_s_9.rs3, _io_out_s_T_166 node _io_out_s_T_167 = bits(io.in, 12, 12) node _io_out_s_T_168 = mux(_io_out_s_T_167, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_169 = bits(io.in, 6, 2) node _io_out_s_T_170 = cat(_io_out_s_T_168, _io_out_s_T_169) node _io_out_s_T_171 = bits(io.in, 11, 7) node io_out_s_lo_16 = cat(_io_out_s_T_171, UInt<7>(0h13)) node io_out_s_hi_hi_11 = cat(_io_out_s_T_170, UInt<5>(0h0)) node io_out_s_hi_22 = cat(io_out_s_hi_hi_11, UInt<3>(0h0)) node _io_out_s_T_172 = cat(io_out_s_hi_22, io_out_s_lo_16) node _io_out_s_T_173 = bits(io.in, 11, 7) node _io_out_s_T_174 = bits(io.in, 4, 2) node _io_out_s_T_175 = cat(UInt<2>(0h1), _io_out_s_T_174) node _io_out_s_T_176 = bits(io.in, 31, 27) wire io_out_s_10 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_10.bits, _io_out_s_T_172 connect io_out_s_10.rd, _io_out_s_T_173 connect io_out_s_10.rs1, UInt<5>(0h0) connect io_out_s_10.rs2, _io_out_s_T_175 connect io_out_s_10.rs3, _io_out_s_T_176 node _io_out_s_opc_T_4 = bits(io.in, 12, 12) node _io_out_s_opc_T_5 = mux(_io_out_s_opc_T_4, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_opc_T_6 = bits(io.in, 6, 2) node _io_out_s_opc_T_7 = cat(_io_out_s_opc_T_5, _io_out_s_opc_T_6) node _io_out_s_opc_T_8 = orr(_io_out_s_opc_T_7) node io_out_s_opc_2 = mux(_io_out_s_opc_T_8, UInt<7>(0h37), UInt<7>(0h3f)) node _io_out_s_me_T = bits(io.in, 12, 12) node _io_out_s_me_T_1 = mux(_io_out_s_me_T, UInt<15>(0h7fff), UInt<15>(0h0)) node _io_out_s_me_T_2 = bits(io.in, 6, 2) node io_out_s_me_hi = cat(_io_out_s_me_T_1, _io_out_s_me_T_2) node _io_out_s_me_T_3 = cat(io_out_s_me_hi, UInt<12>(0h0)) node _io_out_s_me_T_4 = bits(_io_out_s_me_T_3, 31, 12) node _io_out_s_me_T_5 = bits(io.in, 11, 7) node io_out_s_me_hi_1 = cat(_io_out_s_me_T_4, _io_out_s_me_T_5) node _io_out_s_me_T_6 = cat(io_out_s_me_hi_1, io_out_s_opc_2) node _io_out_s_me_T_7 = bits(io.in, 11, 7) node _io_out_s_me_T_8 = bits(io.in, 11, 7) node _io_out_s_me_T_9 = bits(io.in, 4, 2) node _io_out_s_me_T_10 = cat(UInt<2>(0h1), _io_out_s_me_T_9) node _io_out_s_me_T_11 = bits(io.in, 31, 27) wire io_out_s_me : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_me.bits, _io_out_s_me_T_6 connect io_out_s_me.rd, _io_out_s_me_T_7 connect io_out_s_me.rs1, _io_out_s_me_T_8 connect io_out_s_me.rs2, _io_out_s_me_T_10 connect io_out_s_me.rs3, _io_out_s_me_T_11 node _io_out_s_T_177 = bits(io.in, 11, 7) node _io_out_s_T_178 = eq(_io_out_s_T_177, UInt<5>(0h0)) node _io_out_s_T_179 = bits(io.in, 11, 7) node _io_out_s_T_180 = eq(_io_out_s_T_179, UInt<5>(0h2)) node _io_out_s_T_181 = or(_io_out_s_T_178, _io_out_s_T_180) node _io_out_s_opc_T_9 = bits(io.in, 12, 12) node _io_out_s_opc_T_10 = mux(_io_out_s_opc_T_9, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_opc_T_11 = bits(io.in, 6, 2) node _io_out_s_opc_T_12 = cat(_io_out_s_opc_T_10, _io_out_s_opc_T_11) node _io_out_s_opc_T_13 = orr(_io_out_s_opc_T_12) node io_out_s_opc_3 = mux(_io_out_s_opc_T_13, UInt<7>(0h13), UInt<7>(0h1f)) node _io_out_s_T_182 = bits(io.in, 12, 12) node _io_out_s_T_183 = mux(_io_out_s_T_182, UInt<3>(0h7), UInt<3>(0h0)) node _io_out_s_T_184 = bits(io.in, 4, 3) node _io_out_s_T_185 = bits(io.in, 5, 5) node _io_out_s_T_186 = bits(io.in, 2, 2) node _io_out_s_T_187 = bits(io.in, 6, 6) node io_out_s_lo_hi_4 = cat(_io_out_s_T_186, _io_out_s_T_187) node io_out_s_lo_17 = cat(io_out_s_lo_hi_4, UInt<4>(0h0)) node io_out_s_hi_hi_12 = cat(_io_out_s_T_183, _io_out_s_T_184) node io_out_s_hi_23 = cat(io_out_s_hi_hi_12, _io_out_s_T_185) node _io_out_s_T_188 = cat(io_out_s_hi_23, io_out_s_lo_17) node _io_out_s_T_189 = bits(io.in, 11, 7) node _io_out_s_T_190 = bits(io.in, 11, 7) node io_out_s_lo_18 = cat(_io_out_s_T_190, io_out_s_opc_3) node io_out_s_hi_hi_13 = cat(_io_out_s_T_188, _io_out_s_T_189) node io_out_s_hi_24 = cat(io_out_s_hi_hi_13, UInt<3>(0h0)) node _io_out_s_T_191 = cat(io_out_s_hi_24, io_out_s_lo_18) node _io_out_s_T_192 = bits(io.in, 11, 7) node _io_out_s_T_193 = bits(io.in, 11, 7) node _io_out_s_T_194 = bits(io.in, 4, 2) node _io_out_s_T_195 = cat(UInt<2>(0h1), _io_out_s_T_194) node _io_out_s_T_196 = bits(io.in, 31, 27) wire io_out_s_res : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_res.bits, _io_out_s_T_191 connect io_out_s_res.rd, _io_out_s_T_192 connect io_out_s_res.rs1, _io_out_s_T_193 connect io_out_s_res.rs2, _io_out_s_T_195 connect io_out_s_res.rs3, _io_out_s_T_196 node io_out_s_11 = mux(_io_out_s_T_181, io_out_s_res, io_out_s_me) node _io_out_s_T_197 = bits(io.in, 12, 12) node _io_out_s_T_198 = bits(io.in, 6, 2) node _io_out_s_T_199 = cat(_io_out_s_T_197, _io_out_s_T_198) node _io_out_s_T_200 = bits(io.in, 9, 7) node _io_out_s_T_201 = cat(UInt<2>(0h1), _io_out_s_T_200) node _io_out_s_T_202 = bits(io.in, 9, 7) node _io_out_s_T_203 = cat(UInt<2>(0h1), _io_out_s_T_202) node io_out_s_lo_19 = cat(_io_out_s_T_203, UInt<7>(0h13)) node io_out_s_hi_hi_14 = cat(_io_out_s_T_199, _io_out_s_T_201) node io_out_s_hi_25 = cat(io_out_s_hi_hi_14, UInt<3>(0h5)) node _io_out_s_T_204 = cat(io_out_s_hi_25, io_out_s_lo_19) node _io_out_s_T_205 = bits(io.in, 12, 12) node _io_out_s_T_206 = bits(io.in, 6, 2) node _io_out_s_T_207 = cat(_io_out_s_T_205, _io_out_s_T_206) node _io_out_s_T_208 = bits(io.in, 9, 7) node _io_out_s_T_209 = cat(UInt<2>(0h1), _io_out_s_T_208) node _io_out_s_T_210 = bits(io.in, 9, 7) node _io_out_s_T_211 = cat(UInt<2>(0h1), _io_out_s_T_210) node io_out_s_lo_20 = cat(_io_out_s_T_211, UInt<7>(0h13)) node io_out_s_hi_hi_15 = cat(_io_out_s_T_207, _io_out_s_T_209) node io_out_s_hi_26 = cat(io_out_s_hi_hi_15, UInt<3>(0h5)) node _io_out_s_T_212 = cat(io_out_s_hi_26, io_out_s_lo_20) node _io_out_s_T_213 = or(_io_out_s_T_212, UInt<31>(0h40000000)) node _io_out_s_T_214 = bits(io.in, 12, 12) node _io_out_s_T_215 = mux(_io_out_s_T_214, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_216 = bits(io.in, 6, 2) node _io_out_s_T_217 = cat(_io_out_s_T_215, _io_out_s_T_216) node _io_out_s_T_218 = bits(io.in, 9, 7) node _io_out_s_T_219 = cat(UInt<2>(0h1), _io_out_s_T_218) node _io_out_s_T_220 = bits(io.in, 9, 7) node _io_out_s_T_221 = cat(UInt<2>(0h1), _io_out_s_T_220) node io_out_s_lo_21 = cat(_io_out_s_T_221, UInt<7>(0h13)) node io_out_s_hi_hi_16 = cat(_io_out_s_T_217, _io_out_s_T_219) node io_out_s_hi_27 = cat(io_out_s_hi_hi_16, UInt<3>(0h7)) node _io_out_s_T_222 = cat(io_out_s_hi_27, io_out_s_lo_21) node _io_out_s_funct_T = bits(io.in, 12, 12) node _io_out_s_funct_T_1 = bits(io.in, 6, 5) node _io_out_s_funct_T_2 = cat(_io_out_s_funct_T, _io_out_s_funct_T_1) node _io_out_s_funct_T_3 = eq(_io_out_s_funct_T_2, UInt<1>(0h1)) node _io_out_s_funct_T_4 = mux(_io_out_s_funct_T_3, UInt<3>(0h4), UInt<1>(0h0)) node _io_out_s_funct_T_5 = eq(_io_out_s_funct_T_2, UInt<2>(0h2)) node _io_out_s_funct_T_6 = mux(_io_out_s_funct_T_5, UInt<3>(0h6), _io_out_s_funct_T_4) node _io_out_s_funct_T_7 = eq(_io_out_s_funct_T_2, UInt<2>(0h3)) node _io_out_s_funct_T_8 = mux(_io_out_s_funct_T_7, UInt<3>(0h7), _io_out_s_funct_T_6) node _io_out_s_funct_T_9 = eq(_io_out_s_funct_T_2, UInt<3>(0h4)) node _io_out_s_funct_T_10 = mux(_io_out_s_funct_T_9, UInt<1>(0h0), _io_out_s_funct_T_8) node _io_out_s_funct_T_11 = eq(_io_out_s_funct_T_2, UInt<3>(0h5)) node _io_out_s_funct_T_12 = mux(_io_out_s_funct_T_11, UInt<1>(0h0), _io_out_s_funct_T_10) node _io_out_s_funct_T_13 = eq(_io_out_s_funct_T_2, UInt<3>(0h6)) node _io_out_s_funct_T_14 = mux(_io_out_s_funct_T_13, UInt<2>(0h2), _io_out_s_funct_T_12) node _io_out_s_funct_T_15 = eq(_io_out_s_funct_T_2, UInt<3>(0h7)) node io_out_s_funct = mux(_io_out_s_funct_T_15, UInt<2>(0h3), _io_out_s_funct_T_14) node _io_out_s_sub_T = bits(io.in, 6, 5) node _io_out_s_sub_T_1 = eq(_io_out_s_sub_T, UInt<1>(0h0)) node io_out_s_sub = mux(_io_out_s_sub_T_1, UInt<31>(0h40000000), UInt<1>(0h0)) node _io_out_s_opc_T_14 = bits(io.in, 12, 12) node io_out_s_opc_4 = mux(_io_out_s_opc_T_14, UInt<7>(0h3b), UInt<7>(0h33)) node _io_out_s_T_223 = bits(io.in, 4, 2) node _io_out_s_T_224 = cat(UInt<2>(0h1), _io_out_s_T_223) node _io_out_s_T_225 = bits(io.in, 9, 7) node _io_out_s_T_226 = cat(UInt<2>(0h1), _io_out_s_T_225) node _io_out_s_T_227 = bits(io.in, 9, 7) node _io_out_s_T_228 = cat(UInt<2>(0h1), _io_out_s_T_227) node io_out_s_lo_22 = cat(_io_out_s_T_228, io_out_s_opc_4) node io_out_s_hi_hi_17 = cat(_io_out_s_T_224, _io_out_s_T_226) node io_out_s_hi_28 = cat(io_out_s_hi_hi_17, io_out_s_funct) node _io_out_s_T_229 = cat(io_out_s_hi_28, io_out_s_lo_22) node _io_out_s_T_230 = or(_io_out_s_T_229, io_out_s_sub) node _io_out_s_T_231 = bits(io.in, 11, 10) node _io_out_s_T_232 = eq(_io_out_s_T_231, UInt<1>(0h1)) node _io_out_s_T_233 = mux(_io_out_s_T_232, _io_out_s_T_213, _io_out_s_T_204) node _io_out_s_T_234 = eq(_io_out_s_T_231, UInt<2>(0h2)) node _io_out_s_T_235 = mux(_io_out_s_T_234, _io_out_s_T_222, _io_out_s_T_233) node _io_out_s_T_236 = eq(_io_out_s_T_231, UInt<2>(0h3)) node _io_out_s_T_237 = mux(_io_out_s_T_236, _io_out_s_T_230, _io_out_s_T_235) node _io_out_s_T_238 = bits(io.in, 9, 7) node _io_out_s_T_239 = cat(UInt<2>(0h1), _io_out_s_T_238) node _io_out_s_T_240 = bits(io.in, 9, 7) node _io_out_s_T_241 = cat(UInt<2>(0h1), _io_out_s_T_240) node _io_out_s_T_242 = bits(io.in, 4, 2) node _io_out_s_T_243 = cat(UInt<2>(0h1), _io_out_s_T_242) node _io_out_s_T_244 = bits(io.in, 31, 27) wire io_out_s_12 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_12.bits, _io_out_s_T_237 connect io_out_s_12.rd, _io_out_s_T_239 connect io_out_s_12.rs1, _io_out_s_T_241 connect io_out_s_12.rs2, _io_out_s_T_243 connect io_out_s_12.rs3, _io_out_s_T_244 node _io_out_s_T_245 = bits(io.in, 12, 12) node _io_out_s_T_246 = mux(_io_out_s_T_245, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_247 = bits(io.in, 8, 8) node _io_out_s_T_248 = bits(io.in, 10, 9) node _io_out_s_T_249 = bits(io.in, 6, 6) node _io_out_s_T_250 = bits(io.in, 7, 7) node _io_out_s_T_251 = bits(io.in, 2, 2) node _io_out_s_T_252 = bits(io.in, 11, 11) node _io_out_s_T_253 = bits(io.in, 5, 3) node io_out_s_lo_lo = cat(_io_out_s_T_253, UInt<1>(0h0)) node io_out_s_lo_hi_5 = cat(_io_out_s_T_251, _io_out_s_T_252) node io_out_s_lo_23 = cat(io_out_s_lo_hi_5, io_out_s_lo_lo) node io_out_s_hi_lo = cat(_io_out_s_T_249, _io_out_s_T_250) node io_out_s_hi_hi_hi = cat(_io_out_s_T_246, _io_out_s_T_247) node io_out_s_hi_hi_18 = cat(io_out_s_hi_hi_hi, _io_out_s_T_248) node io_out_s_hi_29 = cat(io_out_s_hi_hi_18, io_out_s_hi_lo) node _io_out_s_T_254 = cat(io_out_s_hi_29, io_out_s_lo_23) node _io_out_s_T_255 = bits(_io_out_s_T_254, 20, 20) node _io_out_s_T_256 = bits(io.in, 12, 12) node _io_out_s_T_257 = mux(_io_out_s_T_256, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_258 = bits(io.in, 8, 8) node _io_out_s_T_259 = bits(io.in, 10, 9) node _io_out_s_T_260 = bits(io.in, 6, 6) node _io_out_s_T_261 = bits(io.in, 7, 7) node _io_out_s_T_262 = bits(io.in, 2, 2) node _io_out_s_T_263 = bits(io.in, 11, 11) node _io_out_s_T_264 = bits(io.in, 5, 3) node io_out_s_lo_lo_1 = cat(_io_out_s_T_264, UInt<1>(0h0)) node io_out_s_lo_hi_6 = cat(_io_out_s_T_262, _io_out_s_T_263) node io_out_s_lo_24 = cat(io_out_s_lo_hi_6, io_out_s_lo_lo_1) node io_out_s_hi_lo_1 = cat(_io_out_s_T_260, _io_out_s_T_261) node io_out_s_hi_hi_hi_1 = cat(_io_out_s_T_257, _io_out_s_T_258) node io_out_s_hi_hi_19 = cat(io_out_s_hi_hi_hi_1, _io_out_s_T_259) node io_out_s_hi_30 = cat(io_out_s_hi_hi_19, io_out_s_hi_lo_1) node _io_out_s_T_265 = cat(io_out_s_hi_30, io_out_s_lo_24) node _io_out_s_T_266 = bits(_io_out_s_T_265, 10, 1) node _io_out_s_T_267 = bits(io.in, 12, 12) node _io_out_s_T_268 = mux(_io_out_s_T_267, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_269 = bits(io.in, 8, 8) node _io_out_s_T_270 = bits(io.in, 10, 9) node _io_out_s_T_271 = bits(io.in, 6, 6) node _io_out_s_T_272 = bits(io.in, 7, 7) node _io_out_s_T_273 = bits(io.in, 2, 2) node _io_out_s_T_274 = bits(io.in, 11, 11) node _io_out_s_T_275 = bits(io.in, 5, 3) node io_out_s_lo_lo_2 = cat(_io_out_s_T_275, UInt<1>(0h0)) node io_out_s_lo_hi_7 = cat(_io_out_s_T_273, _io_out_s_T_274) node io_out_s_lo_25 = cat(io_out_s_lo_hi_7, io_out_s_lo_lo_2) node io_out_s_hi_lo_2 = cat(_io_out_s_T_271, _io_out_s_T_272) node io_out_s_hi_hi_hi_2 = cat(_io_out_s_T_268, _io_out_s_T_269) node io_out_s_hi_hi_20 = cat(io_out_s_hi_hi_hi_2, _io_out_s_T_270) node io_out_s_hi_31 = cat(io_out_s_hi_hi_20, io_out_s_hi_lo_2) node _io_out_s_T_276 = cat(io_out_s_hi_31, io_out_s_lo_25) node _io_out_s_T_277 = bits(_io_out_s_T_276, 11, 11) node _io_out_s_T_278 = bits(io.in, 12, 12) node _io_out_s_T_279 = mux(_io_out_s_T_278, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_280 = bits(io.in, 8, 8) node _io_out_s_T_281 = bits(io.in, 10, 9) node _io_out_s_T_282 = bits(io.in, 6, 6) node _io_out_s_T_283 = bits(io.in, 7, 7) node _io_out_s_T_284 = bits(io.in, 2, 2) node _io_out_s_T_285 = bits(io.in, 11, 11) node _io_out_s_T_286 = bits(io.in, 5, 3) node io_out_s_lo_lo_3 = cat(_io_out_s_T_286, UInt<1>(0h0)) node io_out_s_lo_hi_8 = cat(_io_out_s_T_284, _io_out_s_T_285) node io_out_s_lo_26 = cat(io_out_s_lo_hi_8, io_out_s_lo_lo_3) node io_out_s_hi_lo_3 = cat(_io_out_s_T_282, _io_out_s_T_283) node io_out_s_hi_hi_hi_3 = cat(_io_out_s_T_279, _io_out_s_T_280) node io_out_s_hi_hi_21 = cat(io_out_s_hi_hi_hi_3, _io_out_s_T_281) node io_out_s_hi_32 = cat(io_out_s_hi_hi_21, io_out_s_hi_lo_3) node _io_out_s_T_287 = cat(io_out_s_hi_32, io_out_s_lo_26) node _io_out_s_T_288 = bits(_io_out_s_T_287, 19, 12) node io_out_s_lo_hi_9 = cat(_io_out_s_T_288, UInt<5>(0h0)) node io_out_s_lo_27 = cat(io_out_s_lo_hi_9, UInt<7>(0h6f)) node io_out_s_hi_hi_22 = cat(_io_out_s_T_255, _io_out_s_T_266) node io_out_s_hi_33 = cat(io_out_s_hi_hi_22, _io_out_s_T_277) node _io_out_s_T_289 = cat(io_out_s_hi_33, io_out_s_lo_27) node _io_out_s_T_290 = bits(io.in, 9, 7) node _io_out_s_T_291 = cat(UInt<2>(0h1), _io_out_s_T_290) node _io_out_s_T_292 = bits(io.in, 4, 2) node _io_out_s_T_293 = cat(UInt<2>(0h1), _io_out_s_T_292) node _io_out_s_T_294 = bits(io.in, 31, 27) wire io_out_s_13 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_13.bits, _io_out_s_T_289 connect io_out_s_13.rd, UInt<5>(0h0) connect io_out_s_13.rs1, _io_out_s_T_291 connect io_out_s_13.rs2, _io_out_s_T_293 connect io_out_s_13.rs3, _io_out_s_T_294 node _io_out_s_T_295 = bits(io.in, 12, 12) node _io_out_s_T_296 = mux(_io_out_s_T_295, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_297 = bits(io.in, 6, 5) node _io_out_s_T_298 = bits(io.in, 2, 2) node _io_out_s_T_299 = bits(io.in, 11, 10) node _io_out_s_T_300 = bits(io.in, 4, 3) node io_out_s_lo_hi_10 = cat(_io_out_s_T_299, _io_out_s_T_300) node io_out_s_lo_28 = cat(io_out_s_lo_hi_10, UInt<1>(0h0)) node io_out_s_hi_hi_23 = cat(_io_out_s_T_296, _io_out_s_T_297) node io_out_s_hi_34 = cat(io_out_s_hi_hi_23, _io_out_s_T_298) node _io_out_s_T_301 = cat(io_out_s_hi_34, io_out_s_lo_28) node _io_out_s_T_302 = bits(_io_out_s_T_301, 12, 12) node _io_out_s_T_303 = bits(io.in, 12, 12) node _io_out_s_T_304 = mux(_io_out_s_T_303, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_305 = bits(io.in, 6, 5) node _io_out_s_T_306 = bits(io.in, 2, 2) node _io_out_s_T_307 = bits(io.in, 11, 10) node _io_out_s_T_308 = bits(io.in, 4, 3) node io_out_s_lo_hi_11 = cat(_io_out_s_T_307, _io_out_s_T_308) node io_out_s_lo_29 = cat(io_out_s_lo_hi_11, UInt<1>(0h0)) node io_out_s_hi_hi_24 = cat(_io_out_s_T_304, _io_out_s_T_305) node io_out_s_hi_35 = cat(io_out_s_hi_hi_24, _io_out_s_T_306) node _io_out_s_T_309 = cat(io_out_s_hi_35, io_out_s_lo_29) node _io_out_s_T_310 = bits(_io_out_s_T_309, 10, 5) node _io_out_s_T_311 = bits(io.in, 9, 7) node _io_out_s_T_312 = cat(UInt<2>(0h1), _io_out_s_T_311) node _io_out_s_T_313 = bits(io.in, 12, 12) node _io_out_s_T_314 = mux(_io_out_s_T_313, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_315 = bits(io.in, 6, 5) node _io_out_s_T_316 = bits(io.in, 2, 2) node _io_out_s_T_317 = bits(io.in, 11, 10) node _io_out_s_T_318 = bits(io.in, 4, 3) node io_out_s_lo_hi_12 = cat(_io_out_s_T_317, _io_out_s_T_318) node io_out_s_lo_30 = cat(io_out_s_lo_hi_12, UInt<1>(0h0)) node io_out_s_hi_hi_25 = cat(_io_out_s_T_314, _io_out_s_T_315) node io_out_s_hi_36 = cat(io_out_s_hi_hi_25, _io_out_s_T_316) node _io_out_s_T_319 = cat(io_out_s_hi_36, io_out_s_lo_30) node _io_out_s_T_320 = bits(_io_out_s_T_319, 4, 1) node _io_out_s_T_321 = bits(io.in, 12, 12) node _io_out_s_T_322 = mux(_io_out_s_T_321, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_323 = bits(io.in, 6, 5) node _io_out_s_T_324 = bits(io.in, 2, 2) node _io_out_s_T_325 = bits(io.in, 11, 10) node _io_out_s_T_326 = bits(io.in, 4, 3) node io_out_s_lo_hi_13 = cat(_io_out_s_T_325, _io_out_s_T_326) node io_out_s_lo_31 = cat(io_out_s_lo_hi_13, UInt<1>(0h0)) node io_out_s_hi_hi_26 = cat(_io_out_s_T_322, _io_out_s_T_323) node io_out_s_hi_37 = cat(io_out_s_hi_hi_26, _io_out_s_T_324) node _io_out_s_T_327 = cat(io_out_s_hi_37, io_out_s_lo_31) node _io_out_s_T_328 = bits(_io_out_s_T_327, 11, 11) node io_out_s_lo_lo_4 = cat(_io_out_s_T_328, UInt<7>(0h63)) node io_out_s_lo_hi_14 = cat(UInt<3>(0h0), _io_out_s_T_320) node io_out_s_lo_32 = cat(io_out_s_lo_hi_14, io_out_s_lo_lo_4) node io_out_s_hi_lo_4 = cat(UInt<5>(0h0), _io_out_s_T_312) node io_out_s_hi_hi_27 = cat(_io_out_s_T_302, _io_out_s_T_310) node io_out_s_hi_38 = cat(io_out_s_hi_hi_27, io_out_s_hi_lo_4) node _io_out_s_T_329 = cat(io_out_s_hi_38, io_out_s_lo_32) node _io_out_s_T_330 = bits(io.in, 9, 7) node _io_out_s_T_331 = cat(UInt<2>(0h1), _io_out_s_T_330) node _io_out_s_T_332 = bits(io.in, 9, 7) node _io_out_s_T_333 = cat(UInt<2>(0h1), _io_out_s_T_332) node _io_out_s_T_334 = bits(io.in, 31, 27) wire io_out_s_14 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_14.bits, _io_out_s_T_329 connect io_out_s_14.rd, _io_out_s_T_331 connect io_out_s_14.rs1, _io_out_s_T_333 connect io_out_s_14.rs2, UInt<5>(0h0) connect io_out_s_14.rs3, _io_out_s_T_334 node _io_out_s_T_335 = bits(io.in, 12, 12) node _io_out_s_T_336 = mux(_io_out_s_T_335, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_337 = bits(io.in, 6, 5) node _io_out_s_T_338 = bits(io.in, 2, 2) node _io_out_s_T_339 = bits(io.in, 11, 10) node _io_out_s_T_340 = bits(io.in, 4, 3) node io_out_s_lo_hi_15 = cat(_io_out_s_T_339, _io_out_s_T_340) node io_out_s_lo_33 = cat(io_out_s_lo_hi_15, UInt<1>(0h0)) node io_out_s_hi_hi_28 = cat(_io_out_s_T_336, _io_out_s_T_337) node io_out_s_hi_39 = cat(io_out_s_hi_hi_28, _io_out_s_T_338) node _io_out_s_T_341 = cat(io_out_s_hi_39, io_out_s_lo_33) node _io_out_s_T_342 = bits(_io_out_s_T_341, 12, 12) node _io_out_s_T_343 = bits(io.in, 12, 12) node _io_out_s_T_344 = mux(_io_out_s_T_343, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_345 = bits(io.in, 6, 5) node _io_out_s_T_346 = bits(io.in, 2, 2) node _io_out_s_T_347 = bits(io.in, 11, 10) node _io_out_s_T_348 = bits(io.in, 4, 3) node io_out_s_lo_hi_16 = cat(_io_out_s_T_347, _io_out_s_T_348) node io_out_s_lo_34 = cat(io_out_s_lo_hi_16, UInt<1>(0h0)) node io_out_s_hi_hi_29 = cat(_io_out_s_T_344, _io_out_s_T_345) node io_out_s_hi_40 = cat(io_out_s_hi_hi_29, _io_out_s_T_346) node _io_out_s_T_349 = cat(io_out_s_hi_40, io_out_s_lo_34) node _io_out_s_T_350 = bits(_io_out_s_T_349, 10, 5) node _io_out_s_T_351 = bits(io.in, 9, 7) node _io_out_s_T_352 = cat(UInt<2>(0h1), _io_out_s_T_351) node _io_out_s_T_353 = bits(io.in, 12, 12) node _io_out_s_T_354 = mux(_io_out_s_T_353, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_355 = bits(io.in, 6, 5) node _io_out_s_T_356 = bits(io.in, 2, 2) node _io_out_s_T_357 = bits(io.in, 11, 10) node _io_out_s_T_358 = bits(io.in, 4, 3) node io_out_s_lo_hi_17 = cat(_io_out_s_T_357, _io_out_s_T_358) node io_out_s_lo_35 = cat(io_out_s_lo_hi_17, UInt<1>(0h0)) node io_out_s_hi_hi_30 = cat(_io_out_s_T_354, _io_out_s_T_355) node io_out_s_hi_41 = cat(io_out_s_hi_hi_30, _io_out_s_T_356) node _io_out_s_T_359 = cat(io_out_s_hi_41, io_out_s_lo_35) node _io_out_s_T_360 = bits(_io_out_s_T_359, 4, 1) node _io_out_s_T_361 = bits(io.in, 12, 12) node _io_out_s_T_362 = mux(_io_out_s_T_361, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_363 = bits(io.in, 6, 5) node _io_out_s_T_364 = bits(io.in, 2, 2) node _io_out_s_T_365 = bits(io.in, 11, 10) node _io_out_s_T_366 = bits(io.in, 4, 3) node io_out_s_lo_hi_18 = cat(_io_out_s_T_365, _io_out_s_T_366) node io_out_s_lo_36 = cat(io_out_s_lo_hi_18, UInt<1>(0h0)) node io_out_s_hi_hi_31 = cat(_io_out_s_T_362, _io_out_s_T_363) node io_out_s_hi_42 = cat(io_out_s_hi_hi_31, _io_out_s_T_364) node _io_out_s_T_367 = cat(io_out_s_hi_42, io_out_s_lo_36) node _io_out_s_T_368 = bits(_io_out_s_T_367, 11, 11) node io_out_s_lo_lo_5 = cat(_io_out_s_T_368, UInt<7>(0h63)) node io_out_s_lo_hi_19 = cat(UInt<3>(0h1), _io_out_s_T_360) node io_out_s_lo_37 = cat(io_out_s_lo_hi_19, io_out_s_lo_lo_5) node io_out_s_hi_lo_5 = cat(UInt<5>(0h0), _io_out_s_T_352) node io_out_s_hi_hi_32 = cat(_io_out_s_T_342, _io_out_s_T_350) node io_out_s_hi_43 = cat(io_out_s_hi_hi_32, io_out_s_hi_lo_5) node _io_out_s_T_369 = cat(io_out_s_hi_43, io_out_s_lo_37) node _io_out_s_T_370 = bits(io.in, 9, 7) node _io_out_s_T_371 = cat(UInt<2>(0h1), _io_out_s_T_370) node _io_out_s_T_372 = bits(io.in, 31, 27) wire io_out_s_15 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_15.bits, _io_out_s_T_369 connect io_out_s_15.rd, UInt<5>(0h0) connect io_out_s_15.rs1, _io_out_s_T_371 connect io_out_s_15.rs2, UInt<5>(0h0) connect io_out_s_15.rs3, _io_out_s_T_372 node _io_out_s_load_opc_T = bits(io.in, 11, 7) node _io_out_s_load_opc_T_1 = orr(_io_out_s_load_opc_T) node io_out_s_load_opc = mux(_io_out_s_load_opc_T_1, UInt<7>(0h3), UInt<7>(0h1f)) node _io_out_s_T_373 = bits(io.in, 12, 12) node _io_out_s_T_374 = bits(io.in, 6, 2) node _io_out_s_T_375 = cat(_io_out_s_T_373, _io_out_s_T_374) node _io_out_s_T_376 = bits(io.in, 11, 7) node _io_out_s_T_377 = bits(io.in, 11, 7) node io_out_s_lo_38 = cat(_io_out_s_T_377, UInt<7>(0h13)) node io_out_s_hi_hi_33 = cat(_io_out_s_T_375, _io_out_s_T_376) node io_out_s_hi_44 = cat(io_out_s_hi_hi_33, UInt<3>(0h1)) node _io_out_s_T_378 = cat(io_out_s_hi_44, io_out_s_lo_38) node _io_out_s_T_379 = bits(io.in, 11, 7) node _io_out_s_T_380 = bits(io.in, 11, 7) node _io_out_s_T_381 = bits(io.in, 6, 2) node _io_out_s_T_382 = bits(io.in, 31, 27) wire io_out_s_16 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_16.bits, _io_out_s_T_378 connect io_out_s_16.rd, _io_out_s_T_379 connect io_out_s_16.rs1, _io_out_s_T_380 connect io_out_s_16.rs2, _io_out_s_T_381 connect io_out_s_16.rs3, _io_out_s_T_382 node _io_out_s_T_383 = bits(io.in, 4, 2) node _io_out_s_T_384 = bits(io.in, 12, 12) node _io_out_s_T_385 = bits(io.in, 6, 5) node io_out_s_lo_39 = cat(_io_out_s_T_385, UInt<3>(0h0)) node io_out_s_hi_45 = cat(_io_out_s_T_383, _io_out_s_T_384) node _io_out_s_T_386 = cat(io_out_s_hi_45, io_out_s_lo_39) node _io_out_s_T_387 = bits(io.in, 11, 7) node io_out_s_lo_40 = cat(_io_out_s_T_387, UInt<7>(0h7)) node io_out_s_hi_hi_34 = cat(_io_out_s_T_386, UInt<5>(0h2)) node io_out_s_hi_46 = cat(io_out_s_hi_hi_34, UInt<3>(0h3)) node _io_out_s_T_388 = cat(io_out_s_hi_46, io_out_s_lo_40) node _io_out_s_T_389 = bits(io.in, 11, 7) node _io_out_s_T_390 = bits(io.in, 6, 2) node _io_out_s_T_391 = bits(io.in, 31, 27) wire io_out_s_17 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_17.bits, _io_out_s_T_388 connect io_out_s_17.rd, _io_out_s_T_389 connect io_out_s_17.rs1, UInt<5>(0h2) connect io_out_s_17.rs2, _io_out_s_T_390 connect io_out_s_17.rs3, _io_out_s_T_391 node _io_out_s_T_392 = bits(io.in, 3, 2) node _io_out_s_T_393 = bits(io.in, 12, 12) node _io_out_s_T_394 = bits(io.in, 6, 4) node io_out_s_lo_41 = cat(_io_out_s_T_394, UInt<2>(0h0)) node io_out_s_hi_47 = cat(_io_out_s_T_392, _io_out_s_T_393) node _io_out_s_T_395 = cat(io_out_s_hi_47, io_out_s_lo_41) node _io_out_s_T_396 = bits(io.in, 11, 7) node io_out_s_lo_42 = cat(_io_out_s_T_396, io_out_s_load_opc) node io_out_s_hi_hi_35 = cat(_io_out_s_T_395, UInt<5>(0h2)) node io_out_s_hi_48 = cat(io_out_s_hi_hi_35, UInt<3>(0h2)) node _io_out_s_T_397 = cat(io_out_s_hi_48, io_out_s_lo_42) node _io_out_s_T_398 = bits(io.in, 11, 7) node _io_out_s_T_399 = bits(io.in, 6, 2) node _io_out_s_T_400 = bits(io.in, 31, 27) wire io_out_s_18 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_18.bits, _io_out_s_T_397 connect io_out_s_18.rd, _io_out_s_T_398 connect io_out_s_18.rs1, UInt<5>(0h2) connect io_out_s_18.rs2, _io_out_s_T_399 connect io_out_s_18.rs3, _io_out_s_T_400 node _io_out_s_T_401 = bits(io.in, 4, 2) node _io_out_s_T_402 = bits(io.in, 12, 12) node _io_out_s_T_403 = bits(io.in, 6, 5) node io_out_s_lo_43 = cat(_io_out_s_T_403, UInt<3>(0h0)) node io_out_s_hi_49 = cat(_io_out_s_T_401, _io_out_s_T_402) node _io_out_s_T_404 = cat(io_out_s_hi_49, io_out_s_lo_43) node _io_out_s_T_405 = bits(io.in, 11, 7) node io_out_s_lo_44 = cat(_io_out_s_T_405, io_out_s_load_opc) node io_out_s_hi_hi_36 = cat(_io_out_s_T_404, UInt<5>(0h2)) node io_out_s_hi_50 = cat(io_out_s_hi_hi_36, UInt<3>(0h3)) node _io_out_s_T_406 = cat(io_out_s_hi_50, io_out_s_lo_44) node _io_out_s_T_407 = bits(io.in, 11, 7) node _io_out_s_T_408 = bits(io.in, 6, 2) node _io_out_s_T_409 = bits(io.in, 31, 27) wire io_out_s_19 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_19.bits, _io_out_s_T_406 connect io_out_s_19.rd, _io_out_s_T_407 connect io_out_s_19.rs1, UInt<5>(0h2) connect io_out_s_19.rs2, _io_out_s_T_408 connect io_out_s_19.rs3, _io_out_s_T_409 node _io_out_s_mv_T = bits(io.in, 6, 2) node _io_out_s_mv_T_1 = bits(io.in, 11, 7) node io_out_s_mv_lo = cat(_io_out_s_mv_T_1, UInt<7>(0h33)) node io_out_s_mv_hi_hi = cat(_io_out_s_mv_T, UInt<5>(0h0)) node io_out_s_mv_hi = cat(io_out_s_mv_hi_hi, UInt<3>(0h0)) node _io_out_s_mv_T_2 = cat(io_out_s_mv_hi, io_out_s_mv_lo) node _io_out_s_mv_T_3 = bits(io.in, 11, 7) node _io_out_s_mv_T_4 = bits(io.in, 6, 2) node _io_out_s_mv_T_5 = bits(io.in, 31, 27) wire io_out_s_mv : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_mv.bits, _io_out_s_mv_T_2 connect io_out_s_mv.rd, _io_out_s_mv_T_3 connect io_out_s_mv.rs1, UInt<5>(0h0) connect io_out_s_mv.rs2, _io_out_s_mv_T_4 connect io_out_s_mv.rs3, _io_out_s_mv_T_5 node _io_out_s_add_T = bits(io.in, 6, 2) node _io_out_s_add_T_1 = bits(io.in, 11, 7) node _io_out_s_add_T_2 = bits(io.in, 11, 7) node io_out_s_add_lo = cat(_io_out_s_add_T_2, UInt<7>(0h33)) node io_out_s_add_hi_hi = cat(_io_out_s_add_T, _io_out_s_add_T_1) node io_out_s_add_hi = cat(io_out_s_add_hi_hi, UInt<3>(0h0)) node _io_out_s_add_T_3 = cat(io_out_s_add_hi, io_out_s_add_lo) node _io_out_s_add_T_4 = bits(io.in, 11, 7) node _io_out_s_add_T_5 = bits(io.in, 11, 7) node _io_out_s_add_T_6 = bits(io.in, 6, 2) node _io_out_s_add_T_7 = bits(io.in, 31, 27) wire io_out_s_add : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_add.bits, _io_out_s_add_T_3 connect io_out_s_add.rd, _io_out_s_add_T_4 connect io_out_s_add.rs1, _io_out_s_add_T_5 connect io_out_s_add.rs2, _io_out_s_add_T_6 connect io_out_s_add.rs3, _io_out_s_add_T_7 node _io_out_s_jr_T = bits(io.in, 6, 2) node _io_out_s_jr_T_1 = bits(io.in, 11, 7) node io_out_s_jr_lo = cat(UInt<5>(0h0), UInt<7>(0h67)) node io_out_s_jr_hi_hi = cat(_io_out_s_jr_T, _io_out_s_jr_T_1) node io_out_s_jr_hi = cat(io_out_s_jr_hi_hi, UInt<3>(0h0)) node io_out_s_jr = cat(io_out_s_jr_hi, io_out_s_jr_lo) node _io_out_s_reserved_T = shr(io_out_s_jr, 7) node io_out_s_reserved = cat(_io_out_s_reserved_T, UInt<7>(0h1f)) node _io_out_s_jr_reserved_T = bits(io.in, 11, 7) node _io_out_s_jr_reserved_T_1 = orr(_io_out_s_jr_reserved_T) node _io_out_s_jr_reserved_T_2 = mux(_io_out_s_jr_reserved_T_1, io_out_s_jr, io_out_s_reserved) node _io_out_s_jr_reserved_T_3 = bits(io.in, 11, 7) node _io_out_s_jr_reserved_T_4 = bits(io.in, 6, 2) node _io_out_s_jr_reserved_T_5 = bits(io.in, 31, 27) wire io_out_s_jr_reserved : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_jr_reserved.bits, _io_out_s_jr_reserved_T_2 connect io_out_s_jr_reserved.rd, UInt<5>(0h0) connect io_out_s_jr_reserved.rs1, _io_out_s_jr_reserved_T_3 connect io_out_s_jr_reserved.rs2, _io_out_s_jr_reserved_T_4 connect io_out_s_jr_reserved.rs3, _io_out_s_jr_reserved_T_5 node _io_out_s_jr_mv_T = bits(io.in, 6, 2) node _io_out_s_jr_mv_T_1 = orr(_io_out_s_jr_mv_T) node io_out_s_jr_mv = mux(_io_out_s_jr_mv_T_1, io_out_s_mv, io_out_s_jr_reserved) node _io_out_s_jalr_T = bits(io.in, 6, 2) node _io_out_s_jalr_T_1 = bits(io.in, 11, 7) node io_out_s_jalr_lo = cat(UInt<5>(0h1), UInt<7>(0h67)) node io_out_s_jalr_hi_hi = cat(_io_out_s_jalr_T, _io_out_s_jalr_T_1) node io_out_s_jalr_hi = cat(io_out_s_jalr_hi_hi, UInt<3>(0h0)) node io_out_s_jalr = cat(io_out_s_jalr_hi, io_out_s_jalr_lo) node _io_out_s_ebreak_T = shr(io_out_s_jr, 7) node _io_out_s_ebreak_T_1 = cat(_io_out_s_ebreak_T, UInt<7>(0h73)) node io_out_s_ebreak = or(_io_out_s_ebreak_T_1, UInt<21>(0h100000)) node _io_out_s_jalr_ebreak_T = bits(io.in, 11, 7) node _io_out_s_jalr_ebreak_T_1 = orr(_io_out_s_jalr_ebreak_T) node _io_out_s_jalr_ebreak_T_2 = mux(_io_out_s_jalr_ebreak_T_1, io_out_s_jalr, io_out_s_ebreak) node _io_out_s_jalr_ebreak_T_3 = bits(io.in, 11, 7) node _io_out_s_jalr_ebreak_T_4 = bits(io.in, 6, 2) node _io_out_s_jalr_ebreak_T_5 = bits(io.in, 31, 27) wire io_out_s_jalr_ebreak : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_jalr_ebreak.bits, _io_out_s_jalr_ebreak_T_2 connect io_out_s_jalr_ebreak.rd, UInt<5>(0h1) connect io_out_s_jalr_ebreak.rs1, _io_out_s_jalr_ebreak_T_3 connect io_out_s_jalr_ebreak.rs2, _io_out_s_jalr_ebreak_T_4 connect io_out_s_jalr_ebreak.rs3, _io_out_s_jalr_ebreak_T_5 node _io_out_s_jalr_add_T = bits(io.in, 6, 2) node _io_out_s_jalr_add_T_1 = orr(_io_out_s_jalr_add_T) node io_out_s_jalr_add = mux(_io_out_s_jalr_add_T_1, io_out_s_add, io_out_s_jalr_ebreak) node _io_out_s_T_410 = bits(io.in, 12, 12) node io_out_s_20 = mux(_io_out_s_T_410, io_out_s_jalr_add, io_out_s_jr_mv) node _io_out_s_T_411 = bits(io.in, 9, 7) node _io_out_s_T_412 = bits(io.in, 12, 10) node io_out_s_hi_51 = cat(_io_out_s_T_411, _io_out_s_T_412) node _io_out_s_T_413 = cat(io_out_s_hi_51, UInt<3>(0h0)) node _io_out_s_T_414 = shr(_io_out_s_T_413, 5) node _io_out_s_T_415 = bits(io.in, 6, 2) node _io_out_s_T_416 = bits(io.in, 9, 7) node _io_out_s_T_417 = bits(io.in, 12, 10) node io_out_s_hi_52 = cat(_io_out_s_T_416, _io_out_s_T_417) node _io_out_s_T_418 = cat(io_out_s_hi_52, UInt<3>(0h0)) node _io_out_s_T_419 = bits(_io_out_s_T_418, 4, 0) node io_out_s_lo_hi_20 = cat(UInt<3>(0h3), _io_out_s_T_419) node io_out_s_lo_45 = cat(io_out_s_lo_hi_20, UInt<7>(0h27)) node io_out_s_hi_hi_37 = cat(_io_out_s_T_414, _io_out_s_T_415) node io_out_s_hi_53 = cat(io_out_s_hi_hi_37, UInt<5>(0h2)) node _io_out_s_T_420 = cat(io_out_s_hi_53, io_out_s_lo_45) node _io_out_s_T_421 = bits(io.in, 11, 7) node _io_out_s_T_422 = bits(io.in, 6, 2) node _io_out_s_T_423 = bits(io.in, 31, 27) wire io_out_s_21 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_21.bits, _io_out_s_T_420 connect io_out_s_21.rd, _io_out_s_T_421 connect io_out_s_21.rs1, UInt<5>(0h2) connect io_out_s_21.rs2, _io_out_s_T_422 connect io_out_s_21.rs3, _io_out_s_T_423 node _io_out_s_T_424 = bits(io.in, 8, 7) node _io_out_s_T_425 = bits(io.in, 12, 9) node io_out_s_hi_54 = cat(_io_out_s_T_424, _io_out_s_T_425) node _io_out_s_T_426 = cat(io_out_s_hi_54, UInt<2>(0h0)) node _io_out_s_T_427 = shr(_io_out_s_T_426, 5) node _io_out_s_T_428 = bits(io.in, 6, 2) node _io_out_s_T_429 = bits(io.in, 8, 7) node _io_out_s_T_430 = bits(io.in, 12, 9) node io_out_s_hi_55 = cat(_io_out_s_T_429, _io_out_s_T_430) node _io_out_s_T_431 = cat(io_out_s_hi_55, UInt<2>(0h0)) node _io_out_s_T_432 = bits(_io_out_s_T_431, 4, 0) node io_out_s_lo_hi_21 = cat(UInt<3>(0h2), _io_out_s_T_432) node io_out_s_lo_46 = cat(io_out_s_lo_hi_21, UInt<7>(0h23)) node io_out_s_hi_hi_38 = cat(_io_out_s_T_427, _io_out_s_T_428) node io_out_s_hi_56 = cat(io_out_s_hi_hi_38, UInt<5>(0h2)) node _io_out_s_T_433 = cat(io_out_s_hi_56, io_out_s_lo_46) node _io_out_s_T_434 = bits(io.in, 11, 7) node _io_out_s_T_435 = bits(io.in, 6, 2) node _io_out_s_T_436 = bits(io.in, 31, 27) wire io_out_s_22 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_22.bits, _io_out_s_T_433 connect io_out_s_22.rd, _io_out_s_T_434 connect io_out_s_22.rs1, UInt<5>(0h2) connect io_out_s_22.rs2, _io_out_s_T_435 connect io_out_s_22.rs3, _io_out_s_T_436 node _io_out_s_T_437 = bits(io.in, 9, 7) node _io_out_s_T_438 = bits(io.in, 12, 10) node io_out_s_hi_57 = cat(_io_out_s_T_437, _io_out_s_T_438) node _io_out_s_T_439 = cat(io_out_s_hi_57, UInt<3>(0h0)) node _io_out_s_T_440 = shr(_io_out_s_T_439, 5) node _io_out_s_T_441 = bits(io.in, 6, 2) node _io_out_s_T_442 = bits(io.in, 9, 7) node _io_out_s_T_443 = bits(io.in, 12, 10) node io_out_s_hi_58 = cat(_io_out_s_T_442, _io_out_s_T_443) node _io_out_s_T_444 = cat(io_out_s_hi_58, UInt<3>(0h0)) node _io_out_s_T_445 = bits(_io_out_s_T_444, 4, 0) node io_out_s_lo_hi_22 = cat(UInt<3>(0h3), _io_out_s_T_445) node io_out_s_lo_47 = cat(io_out_s_lo_hi_22, UInt<7>(0h23)) node io_out_s_hi_hi_39 = cat(_io_out_s_T_440, _io_out_s_T_441) node io_out_s_hi_59 = cat(io_out_s_hi_hi_39, UInt<5>(0h2)) node _io_out_s_T_446 = cat(io_out_s_hi_59, io_out_s_lo_47) node _io_out_s_T_447 = bits(io.in, 11, 7) node _io_out_s_T_448 = bits(io.in, 6, 2) node _io_out_s_T_449 = bits(io.in, 31, 27) wire io_out_s_23 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_23.bits, _io_out_s_T_446 connect io_out_s_23.rd, _io_out_s_T_447 connect io_out_s_23.rs1, UInt<5>(0h2) connect io_out_s_23.rs2, _io_out_s_T_448 connect io_out_s_23.rs3, _io_out_s_T_449 node _io_out_s_T_450 = bits(io.in, 11, 7) node _io_out_s_T_451 = bits(io.in, 19, 15) node _io_out_s_T_452 = bits(io.in, 24, 20) node _io_out_s_T_453 = bits(io.in, 31, 27) wire io_out_s_24 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_24.bits, io.in connect io_out_s_24.rd, _io_out_s_T_450 connect io_out_s_24.rs1, _io_out_s_T_451 connect io_out_s_24.rs2, _io_out_s_T_452 connect io_out_s_24.rs3, _io_out_s_T_453 node _io_out_s_T_454 = bits(io.in, 11, 7) node _io_out_s_T_455 = bits(io.in, 19, 15) node _io_out_s_T_456 = bits(io.in, 24, 20) node _io_out_s_T_457 = bits(io.in, 31, 27) wire io_out_s_25 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_25.bits, io.in connect io_out_s_25.rd, _io_out_s_T_454 connect io_out_s_25.rs1, _io_out_s_T_455 connect io_out_s_25.rs2, _io_out_s_T_456 connect io_out_s_25.rs3, _io_out_s_T_457 node _io_out_s_T_458 = bits(io.in, 11, 7) node _io_out_s_T_459 = bits(io.in, 19, 15) node _io_out_s_T_460 = bits(io.in, 24, 20) node _io_out_s_T_461 = bits(io.in, 31, 27) wire io_out_s_26 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_26.bits, io.in connect io_out_s_26.rd, _io_out_s_T_458 connect io_out_s_26.rs1, _io_out_s_T_459 connect io_out_s_26.rs2, _io_out_s_T_460 connect io_out_s_26.rs3, _io_out_s_T_461 node _io_out_s_T_462 = bits(io.in, 11, 7) node _io_out_s_T_463 = bits(io.in, 19, 15) node _io_out_s_T_464 = bits(io.in, 24, 20) node _io_out_s_T_465 = bits(io.in, 31, 27) wire io_out_s_27 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_27.bits, io.in connect io_out_s_27.rd, _io_out_s_T_462 connect io_out_s_27.rs1, _io_out_s_T_463 connect io_out_s_27.rs2, _io_out_s_T_464 connect io_out_s_27.rs3, _io_out_s_T_465 node _io_out_s_T_466 = bits(io.in, 11, 7) node _io_out_s_T_467 = bits(io.in, 19, 15) node _io_out_s_T_468 = bits(io.in, 24, 20) node _io_out_s_T_469 = bits(io.in, 31, 27) wire io_out_s_28 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_28.bits, io.in connect io_out_s_28.rd, _io_out_s_T_466 connect io_out_s_28.rs1, _io_out_s_T_467 connect io_out_s_28.rs2, _io_out_s_T_468 connect io_out_s_28.rs3, _io_out_s_T_469 node _io_out_s_T_470 = bits(io.in, 11, 7) node _io_out_s_T_471 = bits(io.in, 19, 15) node _io_out_s_T_472 = bits(io.in, 24, 20) node _io_out_s_T_473 = bits(io.in, 31, 27) wire io_out_s_29 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_29.bits, io.in connect io_out_s_29.rd, _io_out_s_T_470 connect io_out_s_29.rs1, _io_out_s_T_471 connect io_out_s_29.rs2, _io_out_s_T_472 connect io_out_s_29.rs3, _io_out_s_T_473 node _io_out_s_T_474 = bits(io.in, 11, 7) node _io_out_s_T_475 = bits(io.in, 19, 15) node _io_out_s_T_476 = bits(io.in, 24, 20) node _io_out_s_T_477 = bits(io.in, 31, 27) wire io_out_s_30 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_30.bits, io.in connect io_out_s_30.rd, _io_out_s_T_474 connect io_out_s_30.rs1, _io_out_s_T_475 connect io_out_s_30.rs2, _io_out_s_T_476 connect io_out_s_30.rs3, _io_out_s_T_477 node _io_out_s_T_478 = bits(io.in, 11, 7) node _io_out_s_T_479 = bits(io.in, 19, 15) node _io_out_s_T_480 = bits(io.in, 24, 20) node _io_out_s_T_481 = bits(io.in, 31, 27) wire io_out_s_31 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_31.bits, io.in connect io_out_s_31.rd, _io_out_s_T_478 connect io_out_s_31.rs1, _io_out_s_T_479 connect io_out_s_31.rs2, _io_out_s_T_480 connect io_out_s_31.rs3, _io_out_s_T_481 node _io_out_T = bits(io.in, 1, 0) node _io_out_T_1 = bits(io.in, 15, 13) node _io_out_T_2 = cat(_io_out_T, _io_out_T_1) node _io_out_T_3 = eq(_io_out_T_2, UInt<1>(0h1)) node _io_out_T_4 = mux(_io_out_T_3, io_out_s_1, io_out_s_0) node _io_out_T_5 = eq(_io_out_T_2, UInt<2>(0h2)) node _io_out_T_6 = mux(_io_out_T_5, io_out_s_2, _io_out_T_4) node _io_out_T_7 = eq(_io_out_T_2, UInt<2>(0h3)) node _io_out_T_8 = mux(_io_out_T_7, io_out_s_3, _io_out_T_6) node _io_out_T_9 = eq(_io_out_T_2, UInt<3>(0h4)) node _io_out_T_10 = mux(_io_out_T_9, io_out_s_4, _io_out_T_8) node _io_out_T_11 = eq(_io_out_T_2, UInt<3>(0h5)) node _io_out_T_12 = mux(_io_out_T_11, io_out_s_5, _io_out_T_10) node _io_out_T_13 = eq(_io_out_T_2, UInt<3>(0h6)) node _io_out_T_14 = mux(_io_out_T_13, io_out_s_6, _io_out_T_12) node _io_out_T_15 = eq(_io_out_T_2, UInt<3>(0h7)) node _io_out_T_16 = mux(_io_out_T_15, io_out_s_7, _io_out_T_14) node _io_out_T_17 = eq(_io_out_T_2, UInt<4>(0h8)) node _io_out_T_18 = mux(_io_out_T_17, io_out_s_8, _io_out_T_16) node _io_out_T_19 = eq(_io_out_T_2, UInt<4>(0h9)) node _io_out_T_20 = mux(_io_out_T_19, io_out_s_9, _io_out_T_18) node _io_out_T_21 = eq(_io_out_T_2, UInt<4>(0ha)) node _io_out_T_22 = mux(_io_out_T_21, io_out_s_10, _io_out_T_20) node _io_out_T_23 = eq(_io_out_T_2, UInt<4>(0hb)) node _io_out_T_24 = mux(_io_out_T_23, io_out_s_11, _io_out_T_22) node _io_out_T_25 = eq(_io_out_T_2, UInt<4>(0hc)) node _io_out_T_26 = mux(_io_out_T_25, io_out_s_12, _io_out_T_24) node _io_out_T_27 = eq(_io_out_T_2, UInt<4>(0hd)) node _io_out_T_28 = mux(_io_out_T_27, io_out_s_13, _io_out_T_26) node _io_out_T_29 = eq(_io_out_T_2, UInt<4>(0he)) node _io_out_T_30 = mux(_io_out_T_29, io_out_s_14, _io_out_T_28) node _io_out_T_31 = eq(_io_out_T_2, UInt<4>(0hf)) node _io_out_T_32 = mux(_io_out_T_31, io_out_s_15, _io_out_T_30) node _io_out_T_33 = eq(_io_out_T_2, UInt<5>(0h10)) node _io_out_T_34 = mux(_io_out_T_33, io_out_s_16, _io_out_T_32) node _io_out_T_35 = eq(_io_out_T_2, UInt<5>(0h11)) node _io_out_T_36 = mux(_io_out_T_35, io_out_s_17, _io_out_T_34) node _io_out_T_37 = eq(_io_out_T_2, UInt<5>(0h12)) node _io_out_T_38 = mux(_io_out_T_37, io_out_s_18, _io_out_T_36) node _io_out_T_39 = eq(_io_out_T_2, UInt<5>(0h13)) node _io_out_T_40 = mux(_io_out_T_39, io_out_s_19, _io_out_T_38) node _io_out_T_41 = eq(_io_out_T_2, UInt<5>(0h14)) node _io_out_T_42 = mux(_io_out_T_41, io_out_s_20, _io_out_T_40) node _io_out_T_43 = eq(_io_out_T_2, UInt<5>(0h15)) node _io_out_T_44 = mux(_io_out_T_43, io_out_s_21, _io_out_T_42) node _io_out_T_45 = eq(_io_out_T_2, UInt<5>(0h16)) node _io_out_T_46 = mux(_io_out_T_45, io_out_s_22, _io_out_T_44) node _io_out_T_47 = eq(_io_out_T_2, UInt<5>(0h17)) node _io_out_T_48 = mux(_io_out_T_47, io_out_s_23, _io_out_T_46) node _io_out_T_49 = eq(_io_out_T_2, UInt<5>(0h18)) node _io_out_T_50 = mux(_io_out_T_49, io_out_s_24, _io_out_T_48) node _io_out_T_51 = eq(_io_out_T_2, UInt<5>(0h19)) node _io_out_T_52 = mux(_io_out_T_51, io_out_s_25, _io_out_T_50) node _io_out_T_53 = eq(_io_out_T_2, UInt<5>(0h1a)) node _io_out_T_54 = mux(_io_out_T_53, io_out_s_26, _io_out_T_52) node _io_out_T_55 = eq(_io_out_T_2, UInt<5>(0h1b)) node _io_out_T_56 = mux(_io_out_T_55, io_out_s_27, _io_out_T_54) node _io_out_T_57 = eq(_io_out_T_2, UInt<5>(0h1c)) node _io_out_T_58 = mux(_io_out_T_57, io_out_s_28, _io_out_T_56) node _io_out_T_59 = eq(_io_out_T_2, UInt<5>(0h1d)) node _io_out_T_60 = mux(_io_out_T_59, io_out_s_29, _io_out_T_58) node _io_out_T_61 = eq(_io_out_T_2, UInt<5>(0h1e)) node _io_out_T_62 = mux(_io_out_T_61, io_out_s_30, _io_out_T_60) node _io_out_T_63 = eq(_io_out_T_2, UInt<5>(0h1f)) node _io_out_T_64 = mux(_io_out_T_63, io_out_s_31, _io_out_T_62) connect io.out, _io_out_T_64 node _io_ill_s_T = bits(io.in, 12, 2) node _io_ill_s_T_1 = orr(_io_ill_s_T) node io_ill_s_0 = eq(_io_ill_s_T_1, UInt<1>(0h0)) node _io_ill_s_T_2 = bits(io.in, 11, 7) node io_ill_s_9 = eq(_io_ill_s_T_2, UInt<1>(0h0)) node _io_ill_s_T_3 = bits(io.in, 12, 12) node _io_ill_s_T_4 = bits(io.in, 6, 2) node _io_ill_s_T_5 = orr(_io_ill_s_T_4) node _io_ill_s_T_6 = or(_io_ill_s_T_3, _io_ill_s_T_5) node io_ill_s_11 = eq(_io_ill_s_T_6, UInt<1>(0h0)) node _io_ill_s_T_7 = bits(io.in, 12, 10) node _io_ill_s_T_8 = andr(_io_ill_s_T_7) node _io_ill_s_T_9 = bits(io.in, 6, 6) node _io_ill_s_T_10 = eq(_io_ill_s_T_9, UInt<1>(0h1)) node io_ill_s_12 = and(_io_ill_s_T_8, _io_ill_s_T_10) node _io_ill_s_T_11 = bits(io.in, 11, 7) node io_ill_s_18 = eq(_io_ill_s_T_11, UInt<1>(0h0)) node _io_ill_s_T_12 = bits(io.in, 11, 7) node io_ill_s_19 = eq(_io_ill_s_T_12, UInt<1>(0h0)) node _io_ill_s_T_13 = bits(io.in, 12, 2) node _io_ill_s_T_14 = orr(_io_ill_s_T_13) node io_ill_s_20 = eq(_io_ill_s_T_14, UInt<1>(0h0)) node _io_ill_T = bits(io.in, 1, 0) node _io_ill_T_1 = bits(io.in, 15, 13) node _io_ill_T_2 = cat(_io_ill_T, _io_ill_T_1) node _io_ill_T_3 = eq(_io_ill_T_2, UInt<1>(0h1)) node _io_ill_T_4 = mux(_io_ill_T_3, UInt<1>(0h0), io_ill_s_0) node _io_ill_T_5 = eq(_io_ill_T_2, UInt<2>(0h2)) node _io_ill_T_6 = mux(_io_ill_T_5, UInt<1>(0h0), _io_ill_T_4) node _io_ill_T_7 = eq(_io_ill_T_2, UInt<2>(0h3)) node _io_ill_T_8 = mux(_io_ill_T_7, UInt<1>(0h0), _io_ill_T_6) node _io_ill_T_9 = eq(_io_ill_T_2, UInt<3>(0h4)) node _io_ill_T_10 = mux(_io_ill_T_9, UInt<1>(0h1), _io_ill_T_8) node _io_ill_T_11 = eq(_io_ill_T_2, UInt<3>(0h5)) node _io_ill_T_12 = mux(_io_ill_T_11, UInt<1>(0h0), _io_ill_T_10) node _io_ill_T_13 = eq(_io_ill_T_2, UInt<3>(0h6)) node _io_ill_T_14 = mux(_io_ill_T_13, UInt<1>(0h0), _io_ill_T_12) node _io_ill_T_15 = eq(_io_ill_T_2, UInt<3>(0h7)) node _io_ill_T_16 = mux(_io_ill_T_15, UInt<1>(0h0), _io_ill_T_14) node _io_ill_T_17 = eq(_io_ill_T_2, UInt<4>(0h8)) node _io_ill_T_18 = mux(_io_ill_T_17, UInt<1>(0h0), _io_ill_T_16) node _io_ill_T_19 = eq(_io_ill_T_2, UInt<4>(0h9)) node _io_ill_T_20 = mux(_io_ill_T_19, io_ill_s_9, _io_ill_T_18) node _io_ill_T_21 = eq(_io_ill_T_2, UInt<4>(0ha)) node _io_ill_T_22 = mux(_io_ill_T_21, UInt<1>(0h0), _io_ill_T_20) node _io_ill_T_23 = eq(_io_ill_T_2, UInt<4>(0hb)) node _io_ill_T_24 = mux(_io_ill_T_23, io_ill_s_11, _io_ill_T_22) node _io_ill_T_25 = eq(_io_ill_T_2, UInt<4>(0hc)) node _io_ill_T_26 = mux(_io_ill_T_25, io_ill_s_12, _io_ill_T_24) node _io_ill_T_27 = eq(_io_ill_T_2, UInt<4>(0hd)) node _io_ill_T_28 = mux(_io_ill_T_27, UInt<1>(0h0), _io_ill_T_26) node _io_ill_T_29 = eq(_io_ill_T_2, UInt<4>(0he)) node _io_ill_T_30 = mux(_io_ill_T_29, UInt<1>(0h0), _io_ill_T_28) node _io_ill_T_31 = eq(_io_ill_T_2, UInt<4>(0hf)) node _io_ill_T_32 = mux(_io_ill_T_31, UInt<1>(0h0), _io_ill_T_30) node _io_ill_T_33 = eq(_io_ill_T_2, UInt<5>(0h10)) node _io_ill_T_34 = mux(_io_ill_T_33, UInt<1>(0h0), _io_ill_T_32) node _io_ill_T_35 = eq(_io_ill_T_2, UInt<5>(0h11)) node _io_ill_T_36 = mux(_io_ill_T_35, UInt<1>(0h0), _io_ill_T_34) node _io_ill_T_37 = eq(_io_ill_T_2, UInt<5>(0h12)) node _io_ill_T_38 = mux(_io_ill_T_37, io_ill_s_18, _io_ill_T_36) node _io_ill_T_39 = eq(_io_ill_T_2, UInt<5>(0h13)) node _io_ill_T_40 = mux(_io_ill_T_39, io_ill_s_19, _io_ill_T_38) node _io_ill_T_41 = eq(_io_ill_T_2, UInt<5>(0h14)) node _io_ill_T_42 = mux(_io_ill_T_41, io_ill_s_20, _io_ill_T_40) node _io_ill_T_43 = eq(_io_ill_T_2, UInt<5>(0h15)) node _io_ill_T_44 = mux(_io_ill_T_43, UInt<1>(0h0), _io_ill_T_42) node _io_ill_T_45 = eq(_io_ill_T_2, UInt<5>(0h16)) node _io_ill_T_46 = mux(_io_ill_T_45, UInt<1>(0h0), _io_ill_T_44) node _io_ill_T_47 = eq(_io_ill_T_2, UInt<5>(0h17)) node _io_ill_T_48 = mux(_io_ill_T_47, UInt<1>(0h0), _io_ill_T_46) node _io_ill_T_49 = eq(_io_ill_T_2, UInt<5>(0h18)) node _io_ill_T_50 = mux(_io_ill_T_49, UInt<1>(0h0), _io_ill_T_48) node _io_ill_T_51 = eq(_io_ill_T_2, UInt<5>(0h19)) node _io_ill_T_52 = mux(_io_ill_T_51, UInt<1>(0h0), _io_ill_T_50) node _io_ill_T_53 = eq(_io_ill_T_2, UInt<5>(0h1a)) node _io_ill_T_54 = mux(_io_ill_T_53, UInt<1>(0h0), _io_ill_T_52) node _io_ill_T_55 = eq(_io_ill_T_2, UInt<5>(0h1b)) node _io_ill_T_56 = mux(_io_ill_T_55, UInt<1>(0h0), _io_ill_T_54) node _io_ill_T_57 = eq(_io_ill_T_2, UInt<5>(0h1c)) node _io_ill_T_58 = mux(_io_ill_T_57, UInt<1>(0h0), _io_ill_T_56) node _io_ill_T_59 = eq(_io_ill_T_2, UInt<5>(0h1d)) node _io_ill_T_60 = mux(_io_ill_T_59, UInt<1>(0h0), _io_ill_T_58) node _io_ill_T_61 = eq(_io_ill_T_2, UInt<5>(0h1e)) node _io_ill_T_62 = mux(_io_ill_T_61, UInt<1>(0h0), _io_ill_T_60) node _io_ill_T_63 = eq(_io_ill_T_2, UInt<5>(0h1f)) node _io_ill_T_64 = mux(_io_ill_T_63, UInt<1>(0h0), _io_ill_T_62) connect io.ill, _io_ill_T_64	module RVCExpander_6( // @[RVC.scala:190:7] input clock, // @[RVC.scala:190:7] input reset, // @[RVC.scala:190:7] input [31:0] io_in, // @[RVC.scala:191:14] output [31:0] io_out_bits, // @[RVC.scala:191:14] output io_rvc // @[RVC.scala:191:14] ); wire [31:0] io_in_0 = io_in; // @[RVC.scala:190:7] wire [11:0] io_out_s_jr_lo = 12'h67; // @[RVC.scala:135:19] wire [4:0] io_out_s_10_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_13_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_14_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_mv_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_jr_reserved_rd = 5'h0; // @[RVC.scala:21:19] wire [11:0] io_out_s_jalr_lo = 12'hE7; // @[RVC.scala:139:21] wire [4:0] io_out_s_jalr_ebreak_rd = 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_17_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_18_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_19_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_21_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_22_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_23_rs1 = 5'h2; // @[package.scala:39:86] wire [31:0] io_out_s_24_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_25_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_26_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_27_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_28_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_29_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_30_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_31_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] _io_out_T_64_bits; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rd; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs1; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs2; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs3; // @[package.scala:39:76] wire _io_rvc_T_1; // @[RVC.scala:199:26] wire _io_ill_T_64; // @[package.scala:39:76] wire [31:0] io_out_bits_0; // @[RVC.scala:190:7] wire [4:0] io_out_rd; // @[RVC.scala:190:7] wire [4:0] io_out_rs1; // @[RVC.scala:190:7] wire [4:0] io_out_rs2; // @[RVC.scala:190:7] wire [4:0] io_out_rs3; // @[RVC.scala:190:7] wire io_rvc_0; // @[RVC.scala:190:7] wire io_ill; // @[RVC.scala:190:7] wire [1:0] _io_rvc_T = io_in_0[1:0]; // @[RVC.scala:190:7, :199:20] wire [1:0] _io_out_T = io_in_0[1:0]; // @[RVC.scala:154:12, :190:7, :199:20] wire [1:0] _io_ill_T = io_in_0[1:0]; // @[RVC.scala:186:12, :190:7, :199:20] assign _io_rvc_T_1 = _io_rvc_T != 2'h3; // @[RVC.scala:199:{20,26}] assign io_rvc_0 = _io_rvc_T_1; // @[RVC.scala:190:7, :199:26] wire [7:0] _io_out_s_opc_T = io_in_0[12:5]; // @[RVC.scala:53:22, :190:7] wire _io_out_s_opc_T_1 = \|_io_out_s_opc_T; // @[RVC.scala:53:{22,29}] wire [6:0] io_out_s_opc = _io_out_s_opc_T_1 ? 7'h13 : 7'h1F; // @[RVC.scala:53:{20,29}] wire [3:0] _io_out_s_T = io_in_0[10:7]; // @[RVC.scala:34:26, :190:7] wire [1:0] _io_out_s_T_1 = io_in_0[12:11]; // @[RVC.scala:34:35, :190:7] wire _io_out_s_T_2 = io_in_0[5]; // @[RVC.scala:34:45, :190:7] wire _io_out_s_T_28 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_59 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_68 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_101 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_110 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_185 = io_in_0[5]; // @[RVC.scala:34:45, :42:50, :190:7] wire _io_out_s_T_3 = io_in_0[6]; // @[RVC.scala:34:51, :190:7] wire _io_out_s_T_30 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_61 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_70 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_103 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_112 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_187 = io_in_0[6]; // @[RVC.scala:34:51, :42:62, :190:7] wire _io_out_s_T_249 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_260 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_271 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_282 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_ill_s_T_9 = io_in_0[6]; // @[RVC.scala:34:51, :169:69, :190:7] wire [2:0] io_out_s_lo = {_io_out_s_T_3, 2'h0}; // @[RVC.scala:34:{24,51}] wire [5:0] io_out_s_hi_hi = {_io_out_s_T, _io_out_s_T_1}; // @[RVC.scala:34:{24,26,35}] wire [6:0] io_out_s_hi = {io_out_s_hi_hi, _io_out_s_T_2}; // @[RVC.scala:34:{24,45}] wire [9:0] _io_out_s_T_4 = {io_out_s_hi, io_out_s_lo}; // @[RVC.scala:34:24] wire [2:0] _io_out_s_T_5 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_8 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_10 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_18 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_21 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_25 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_34 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_37 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_41 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_49 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_52 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_56 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_64 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_74 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_78 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_85 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_94 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_98 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_106 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_116 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_120 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_127 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_136 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_140 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_152 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_164 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_174 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_me_T_9 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_194 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_223 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_242 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_292 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_383 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [2:0] _io_out_s_T_401 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [4:0] _io_out_s_T_6 = {2'h1, _io_out_s_T_5}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_1 = {_io_out_s_T_6, io_out_s_opc}; // @[RVC.scala:31:17, :53:20, :54:15] wire [14:0] io_out_s_hi_hi_1 = {_io_out_s_T_4, 5'h2}; // @[package.scala:39:86] wire [17:0] io_out_s_hi_1 = {io_out_s_hi_hi_1, 3'h0}; // @[RVC.scala:54:15] wire [29:0] _io_out_s_T_7 = {io_out_s_hi_1, io_out_s_lo_1}; // @[RVC.scala:54:15] wire [4:0] _io_out_s_T_9 = {2'h1, _io_out_s_T_8}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rd = _io_out_s_T_9; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_11 = {2'h1, _io_out_s_T_10}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs2 = _io_out_s_T_11; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_12 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_27 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_43 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_58 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_80 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_100 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_122 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_142 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_154 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_166 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_176 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_me_T_11 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_196 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_244 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_294 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_334 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_372 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_382 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_391 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_400 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_409 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_mv_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_add_T_7 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jr_reserved_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_423 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_436 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_449 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_453 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_457 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_461 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_465 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_469 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_473 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_477 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_481 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] io_out_s_0_rs3 = _io_out_s_T_12; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_0_bits; // @[RVC.scala:21:19] assign io_out_s_0_bits = {2'h0, _io_out_s_T_7}; // @[RVC.scala:21:19, :22:14, :54:15] wire [1:0] _io_out_s_T_13 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_44 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_81 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_89 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_123 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_131 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_funct_T_1 = io_in_0[6:5]; // @[RVC.scala:36:20, :102:77, :190:7] wire [1:0] _io_out_s_sub_T = io_in_0[6:5]; // @[RVC.scala:36:20, :103:24, :190:7] wire [1:0] _io_out_s_T_297 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_305 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_315 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_323 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_337 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_345 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_355 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_363 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_385 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [1:0] _io_out_s_T_403 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [2:0] _io_out_s_T_14 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_29 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_45 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_60 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_69 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_82 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_90 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_102 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_111 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_124 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_132 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_412 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_417 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_438 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_443 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_ill_s_T_7 = io_in_0[12:10]; // @[RVC.scala:36:28, :169:22, :190:7] wire [4:0] io_out_s_hi_2 = {_io_out_s_T_13, _io_out_s_T_14}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_15 = {io_out_s_hi_2, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_16 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_23 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_32 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_39 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_47 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_54 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_66 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_76 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_87 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_96 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_108 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_118 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_129 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_138 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_200 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_202 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_208 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_210 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_218 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_220 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_225 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_227 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_238 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_240 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_290 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_311 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_330 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_332 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_351 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_370 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_411 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_416 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_437 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_442 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [4:0] _io_out_s_T_17 = {2'h1, _io_out_s_T_16}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_19 = {2'h1, _io_out_s_T_18}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_2 = {_io_out_s_T_19, 7'h7}; // @[RVC.scala:31:17, :58:23] wire [12:0] io_out_s_hi_hi_2 = {_io_out_s_T_15, _io_out_s_T_17}; // @[RVC.scala:30:17, :36:18, :58:23] wire [15:0] io_out_s_hi_3 = {io_out_s_hi_hi_2, 3'h3}; // @[RVC.scala:58:23] wire [27:0] _io_out_s_T_20 = {io_out_s_hi_3, io_out_s_lo_2}; // @[RVC.scala:58:23] wire [4:0] _io_out_s_T_22 = {2'h1, _io_out_s_T_21}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rd = _io_out_s_T_22; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_24 = {2'h1, _io_out_s_T_23}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs1 = _io_out_s_T_24; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_26 = {2'h1, _io_out_s_T_25}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs2 = _io_out_s_T_26; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_1_rs3 = _io_out_s_T_27; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_1_bits; // @[RVC.scala:21:19] assign io_out_s_1_bits = {4'h0, _io_out_s_T_20}; // @[RVC.scala:21:19, :22:14, :58:23] wire [2:0] io_out_s_lo_3 = {_io_out_s_T_30, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_4 = {_io_out_s_T_28, _io_out_s_T_29}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_31 = {io_out_s_hi_4, io_out_s_lo_3}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_33 = {2'h1, _io_out_s_T_32}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_35 = {2'h1, _io_out_s_T_34}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_4 = {_io_out_s_T_35, 7'h3}; // @[RVC.scala:31:17, :57:22] wire [11:0] io_out_s_hi_hi_3 = {_io_out_s_T_31, _io_out_s_T_33}; // @[RVC.scala:30:17, :35:18, :57:22] wire [14:0] io_out_s_hi_5 = {io_out_s_hi_hi_3, 3'h2}; // @[package.scala:39:86] wire [26:0] _io_out_s_T_36 = {io_out_s_hi_5, io_out_s_lo_4}; // @[RVC.scala:57:22] wire [4:0] _io_out_s_T_38 = {2'h1, _io_out_s_T_37}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rd = _io_out_s_T_38; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_40 = {2'h1, _io_out_s_T_39}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs1 = _io_out_s_T_40; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_42 = {2'h1, _io_out_s_T_41}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs2 = _io_out_s_T_42; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_2_rs3 = _io_out_s_T_43; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_2_bits; // @[RVC.scala:21:19] assign io_out_s_2_bits = {5'h0, _io_out_s_T_36}; // @[RVC.scala:21:19, :22:14, :57:22] wire [4:0] io_out_s_hi_6 = {_io_out_s_T_44, _io_out_s_T_45}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_46 = {io_out_s_hi_6, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_48 = {2'h1, _io_out_s_T_47}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_50 = {2'h1, _io_out_s_T_49}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_5 = {_io_out_s_T_50, 7'h3}; // @[RVC.scala:31:17, :56:22] wire [12:0] io_out_s_hi_hi_4 = {_io_out_s_T_46, _io_out_s_T_48}; // @[RVC.scala:30:17, :36:18, :56:22] wire [15:0] io_out_s_hi_7 = {io_out_s_hi_hi_4, 3'h3}; // @[RVC.scala:56:22] wire [27:0] _io_out_s_T_51 = {io_out_s_hi_7, io_out_s_lo_5}; // @[RVC.scala:56:22] wire [4:0] _io_out_s_T_53 = {2'h1, _io_out_s_T_52}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rd = _io_out_s_T_53; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_55 = {2'h1, _io_out_s_T_54}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs1 = _io_out_s_T_55; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_57 = {2'h1, _io_out_s_T_56}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs2 = _io_out_s_T_57; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_3_rs3 = _io_out_s_T_58; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_3_bits; // @[RVC.scala:21:19] assign io_out_s_3_bits = {4'h0, _io_out_s_T_51}; // @[RVC.scala:21:19, :22:14, :56:22] wire [2:0] io_out_s_lo_6 = {_io_out_s_T_61, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_8 = {_io_out_s_T_59, _io_out_s_T_60}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_62 = {io_out_s_hi_8, io_out_s_lo_6}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_63 = _io_out_s_T_62[6:5]; // @[RVC.scala:35:18, :63:32] wire [4:0] _io_out_s_T_65 = {2'h1, _io_out_s_T_64}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_67 = {2'h1, _io_out_s_T_66}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_7 = {_io_out_s_T_70, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_9 = {_io_out_s_T_68, _io_out_s_T_69}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_71 = {io_out_s_hi_9, io_out_s_lo_7}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_72 = _io_out_s_T_71[4:0]; // @[RVC.scala:35:18, :63:65] wire [7:0] io_out_s_lo_hi = {3'h2, _io_out_s_T_72}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_8 = {io_out_s_lo_hi, 7'h3F}; // @[RVC.scala:63:25] wire [6:0] io_out_s_hi_hi_5 = {_io_out_s_T_63, _io_out_s_T_65}; // @[RVC.scala:31:17, :63:{25,32}] wire [11:0] io_out_s_hi_10 = {io_out_s_hi_hi_5, _io_out_s_T_67}; // @[RVC.scala:30:17, :63:25] wire [26:0] _io_out_s_T_73 = {io_out_s_hi_10, io_out_s_lo_8}; // @[RVC.scala:63:25] wire [4:0] _io_out_s_T_75 = {2'h1, _io_out_s_T_74}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rd = _io_out_s_T_75; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_77 = {2'h1, _io_out_s_T_76}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs1 = _io_out_s_T_77; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_79 = {2'h1, _io_out_s_T_78}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs2 = _io_out_s_T_79; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_4_rs3 = _io_out_s_T_80; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_4_bits; // @[RVC.scala:21:19] assign io_out_s_4_bits = {5'h0, _io_out_s_T_73}; // @[RVC.scala:21:19, :22:14, :63:25] wire [4:0] io_out_s_hi_11 = {_io_out_s_T_81, _io_out_s_T_82}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_83 = {io_out_s_hi_11, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_84 = _io_out_s_T_83[7:5]; // @[RVC.scala:36:18, :66:30] wire [4:0] _io_out_s_T_86 = {2'h1, _io_out_s_T_85}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_88 = {2'h1, _io_out_s_T_87}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_12 = {_io_out_s_T_89, _io_out_s_T_90}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_91 = {io_out_s_hi_12, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_92 = _io_out_s_T_91[4:0]; // @[RVC.scala:36:18, :66:63] wire [7:0] io_out_s_lo_hi_1 = {3'h3, _io_out_s_T_92}; // @[RVC.scala:66:{23,63}] wire [14:0] io_out_s_lo_9 = {io_out_s_lo_hi_1, 7'h27}; // @[RVC.scala:66:23] wire [7:0] io_out_s_hi_hi_6 = {_io_out_s_T_84, _io_out_s_T_86}; // @[RVC.scala:31:17, :66:{23,30}] wire [12:0] io_out_s_hi_13 = {io_out_s_hi_hi_6, _io_out_s_T_88}; // @[RVC.scala:30:17, :66:23] wire [27:0] _io_out_s_T_93 = {io_out_s_hi_13, io_out_s_lo_9}; // @[RVC.scala:66:23] wire [4:0] _io_out_s_T_95 = {2'h1, _io_out_s_T_94}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rd = _io_out_s_T_95; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_97 = {2'h1, _io_out_s_T_96}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs1 = _io_out_s_T_97; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_99 = {2'h1, _io_out_s_T_98}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs2 = _io_out_s_T_99; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_5_rs3 = _io_out_s_T_100; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_5_bits; // @[RVC.scala:21:19] assign io_out_s_5_bits = {4'h0, _io_out_s_T_93}; // @[RVC.scala:21:19, :22:14, :66:23] wire [2:0] io_out_s_lo_10 = {_io_out_s_T_103, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_14 = {_io_out_s_T_101, _io_out_s_T_102}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_104 = {io_out_s_hi_14, io_out_s_lo_10}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_105 = _io_out_s_T_104[6:5]; // @[RVC.scala:35:18, :65:29] wire [4:0] _io_out_s_T_107 = {2'h1, _io_out_s_T_106}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_109 = {2'h1, _io_out_s_T_108}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_11 = {_io_out_s_T_112, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_15 = {_io_out_s_T_110, _io_out_s_T_111}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_113 = {io_out_s_hi_15, io_out_s_lo_11}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_114 = _io_out_s_T_113[4:0]; // @[RVC.scala:35:18, :65:62] wire [7:0] io_out_s_lo_hi_2 = {3'h2, _io_out_s_T_114}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_12 = {io_out_s_lo_hi_2, 7'h23}; // @[RVC.scala:65:22] wire [6:0] io_out_s_hi_hi_7 = {_io_out_s_T_105, _io_out_s_T_107}; // @[RVC.scala:31:17, :65:{22,29}] wire [11:0] io_out_s_hi_16 = {io_out_s_hi_hi_7, _io_out_s_T_109}; // @[RVC.scala:30:17, :65:22] wire [26:0] _io_out_s_T_115 = {io_out_s_hi_16, io_out_s_lo_12}; // @[RVC.scala:65:22] wire [4:0] _io_out_s_T_117 = {2'h1, _io_out_s_T_116}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rd = _io_out_s_T_117; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_119 = {2'h1, _io_out_s_T_118}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs1 = _io_out_s_T_119; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_121 = {2'h1, _io_out_s_T_120}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs2 = _io_out_s_T_121; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_6_rs3 = _io_out_s_T_122; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_6_bits; // @[RVC.scala:21:19] assign io_out_s_6_bits = {5'h0, _io_out_s_T_115}; // @[RVC.scala:21:19, :22:14, :65:22] wire [4:0] io_out_s_hi_17 = {_io_out_s_T_123, _io_out_s_T_124}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_125 = {io_out_s_hi_17, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_126 = _io_out_s_T_125[7:5]; // @[RVC.scala:36:18, :64:29] wire [4:0] _io_out_s_T_128 = {2'h1, _io_out_s_T_127}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_130 = {2'h1, _io_out_s_T_129}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_18 = {_io_out_s_T_131, _io_out_s_T_132}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_133 = {io_out_s_hi_18, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_134 = _io_out_s_T_133[4:0]; // @[RVC.scala:36:18, :64:62] wire [7:0] io_out_s_lo_hi_3 = {3'h3, _io_out_s_T_134}; // @[RVC.scala:64:{22,62}] wire [14:0] io_out_s_lo_13 = {io_out_s_lo_hi_3, 7'h23}; // @[RVC.scala:64:22] wire [7:0] io_out_s_hi_hi_8 = {_io_out_s_T_126, _io_out_s_T_128}; // @[RVC.scala:31:17, :64:{22,29}] wire [12:0] io_out_s_hi_19 = {io_out_s_hi_hi_8, _io_out_s_T_130}; // @[RVC.scala:30:17, :64:22] wire [27:0] _io_out_s_T_135 = {io_out_s_hi_19, io_out_s_lo_13}; // @[RVC.scala:64:22] wire [4:0] _io_out_s_T_137 = {2'h1, _io_out_s_T_136}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rd = _io_out_s_T_137; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_139 = {2'h1, _io_out_s_T_138}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs1 = _io_out_s_T_139; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_141 = {2'h1, _io_out_s_T_140}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs2 = _io_out_s_T_141; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_7_rs3 = _io_out_s_T_142; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_7_bits; // @[RVC.scala:21:19] assign io_out_s_7_bits = {4'h0, _io_out_s_T_135}; // @[RVC.scala:21:19, :22:14, :64:22] wire _io_out_s_T_143 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_155 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_167 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_opc_T_4 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_me_T = io_in_0[12]; // @[RVC.scala:41:30, :43:30, :190:7] wire _io_out_s_opc_T_9 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_182 = io_in_0[12]; // @[RVC.scala:42:34, :43:30, :190:7] wire _io_out_s_T_197 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_205 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_214 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_funct_T = io_in_0[12]; // @[RVC.scala:43:30, :102:70, :190:7] wire _io_out_s_opc_T_14 = io_in_0[12]; // @[RVC.scala:43:30, :104:24, :190:7] wire _io_out_s_T_245 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_256 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_267 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_278 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_295 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_303 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_313 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_321 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_335 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_343 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_353 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_361 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_373 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_384 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_393 = io_in_0[12]; // @[RVC.scala:37:30, :43:30, :190:7] wire _io_out_s_T_402 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_410 = io_in_0[12]; // @[RVC.scala:43:30, :143:12, :190:7] wire _io_ill_s_T_3 = io_in_0[12]; // @[RVC.scala:43:30, :168:19, :190:7] wire [6:0] _io_out_s_T_144 = {7{_io_out_s_T_143}}; // @[RVC.scala:43:{25,30}] wire [4:0] _io_out_s_T_145 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_157 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_169 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_opc_T_6 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_me_T_2 = io_in_0[6:2]; // @[RVC.scala:41:38, :43:38, :190:7] wire [4:0] _io_out_s_opc_T_11 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_198 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_206 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_216 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_374 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_381 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_390 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_399 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_408 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T_6 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_reserved_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_415 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_422 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_428 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_435 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_441 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_448 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_ill_s_T_4 = io_in_0[6:2]; // @[RVC.scala:43:38, :168:27, :190:7] wire [11:0] _io_out_s_T_146 = {_io_out_s_T_144, _io_out_s_T_145}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_147 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_148 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_150 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_151 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_opc_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_159 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_160 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_162 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_163 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_171 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_173 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_7 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_8 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_177 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_179 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_189 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_190 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_192 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_193 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_load_opc_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_376 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_377 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_379 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_380 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_387 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_389 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_396 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_398 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_405 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_407 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_4 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_421 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_434 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_447 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_450 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_454 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_458 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_462 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_466 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_470 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_474 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_478 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_ill_s_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_11 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_12 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [11:0] io_out_s_lo_14 = {_io_out_s_T_148, 7'h13}; // @[RVC.scala:33:13, :75:24] wire [16:0] io_out_s_hi_hi_9 = {_io_out_s_T_146, _io_out_s_T_147}; // @[RVC.scala:33:13, :43:20, :75:24] wire [19:0] io_out_s_hi_20 = {io_out_s_hi_hi_9, 3'h0}; // @[RVC.scala:75:24] wire [31:0] _io_out_s_T_149 = {io_out_s_hi_20, io_out_s_lo_14}; // @[RVC.scala:75:24] wire [31:0] io_out_s_8_bits = _io_out_s_T_149; // @[RVC.scala:21:19, :75:24] wire [4:0] io_out_s_8_rd = _io_out_s_T_150; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_8_rs1 = _io_out_s_T_151; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_153 = {2'h1, _io_out_s_T_152}; // @[package.scala:39:86] wire [4:0] io_out_s_8_rs2 = _io_out_s_T_153; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_8_rs3 = _io_out_s_T_154; // @[RVC.scala:20:101, :21:19] wire _io_out_s_opc_T_3 = \|_io_out_s_opc_T_2; // @[RVC.scala:33:13, :77:24] wire [6:0] io_out_s_opc_1 = {4'h3, ~_io_out_s_opc_T_3, 2'h3}; // @[RVC.scala:77:{20,24}] wire [6:0] _io_out_s_T_156 = {7{_io_out_s_T_155}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_158 = {_io_out_s_T_156, _io_out_s_T_157}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_15 = {_io_out_s_T_160, io_out_s_opc_1}; // @[RVC.scala:33:13, :77:20, :78:15] wire [16:0] io_out_s_hi_hi_10 = {_io_out_s_T_158, _io_out_s_T_159}; // @[RVC.scala:33:13, :43:20, :78:15] wire [19:0] io_out_s_hi_21 = {io_out_s_hi_hi_10, 3'h0}; // @[RVC.scala:78:15] wire [31:0] _io_out_s_T_161 = {io_out_s_hi_21, io_out_s_lo_15}; // @[RVC.scala:78:15] wire [31:0] io_out_s_9_bits = _io_out_s_T_161; // @[RVC.scala:21:19, :78:15] wire [4:0] io_out_s_9_rd = _io_out_s_T_162; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_9_rs1 = _io_out_s_T_163; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_165 = {2'h1, _io_out_s_T_164}; // @[package.scala:39:86] wire [4:0] io_out_s_9_rs2 = _io_out_s_T_165; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_9_rs3 = _io_out_s_T_166; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_T_168 = {7{_io_out_s_T_167}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_170 = {_io_out_s_T_168, _io_out_s_T_169}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_16 = {_io_out_s_T_171, 7'h13}; // @[RVC.scala:33:13, :84:22] wire [16:0] io_out_s_hi_hi_11 = {_io_out_s_T_170, 5'h0}; // @[RVC.scala:43:20, :84:22] wire [19:0] io_out_s_hi_22 = {io_out_s_hi_hi_11, 3'h0}; // @[RVC.scala:84:22] wire [31:0] _io_out_s_T_172 = {io_out_s_hi_22, io_out_s_lo_16}; // @[RVC.scala:84:22] wire [31:0] io_out_s_10_bits = _io_out_s_T_172; // @[RVC.scala:21:19, :84:22] wire [4:0] io_out_s_10_rd = _io_out_s_T_173; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_175 = {2'h1, _io_out_s_T_174}; // @[package.scala:39:86] wire [4:0] io_out_s_10_rs2 = _io_out_s_T_175; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_10_rs3 = _io_out_s_T_176; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_opc_T_5 = {7{_io_out_s_opc_T_4}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_7 = {_io_out_s_opc_T_5, _io_out_s_opc_T_6}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_8 = \|_io_out_s_opc_T_7; // @[RVC.scala:43:20, :90:29] wire [6:0] io_out_s_opc_2 = {3'h3, ~_io_out_s_opc_T_8, 3'h7}; // @[RVC.scala:90:{20,29}] wire [14:0] _io_out_s_me_T_1 = {15{_io_out_s_me_T}}; // @[RVC.scala:41:{24,30}] wire [19:0] io_out_s_me_hi = {_io_out_s_me_T_1, _io_out_s_me_T_2}; // @[RVC.scala:41:{19,24,38}] wire [31:0] _io_out_s_me_T_3 = {io_out_s_me_hi, 12'h0}; // @[RVC.scala:41:19] wire [19:0] _io_out_s_me_T_4 = _io_out_s_me_T_3[31:12]; // @[RVC.scala:41:19, :91:31] wire [24:0] io_out_s_me_hi_1 = {_io_out_s_me_T_4, _io_out_s_me_T_5}; // @[RVC.scala:33:13, :91:{24,31}] wire [31:0] _io_out_s_me_T_6 = {io_out_s_me_hi_1, io_out_s_opc_2}; // @[RVC.scala:90:20, :91:24] wire [31:0] io_out_s_me_bits = _io_out_s_me_T_6; // @[RVC.scala:21:19, :91:24] wire [4:0] io_out_s_me_rd = _io_out_s_me_T_7; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_me_rs1 = _io_out_s_me_T_8; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_me_T_10 = {2'h1, _io_out_s_me_T_9}; // @[package.scala:39:86] wire [4:0] io_out_s_me_rs2 = _io_out_s_me_T_10; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_me_rs3 = _io_out_s_me_T_11; // @[RVC.scala:20:101, :21:19] wire _io_out_s_T_178 = _io_out_s_T_177 == 5'h0; // @[RVC.scala:33:13, :92:14] wire _io_out_s_T_180 = _io_out_s_T_179 == 5'h2; // @[package.scala:39:86] wire _io_out_s_T_181 = _io_out_s_T_178 \| _io_out_s_T_180; // @[RVC.scala:92:{14,21,27}] wire [6:0] _io_out_s_opc_T_10 = {7{_io_out_s_opc_T_9}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_12 = {_io_out_s_opc_T_10, _io_out_s_opc_T_11}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_13 = \|_io_out_s_opc_T_12; // @[RVC.scala:43:20, :86:29] wire [6:0] io_out_s_opc_3 = _io_out_s_opc_T_13 ? 7'h13 : 7'h1F; // @[RVC.scala:86:{20,29}] wire [2:0] _io_out_s_T_183 = {3{_io_out_s_T_182}}; // @[RVC.scala:42:{29,34}] wire [1:0] _io_out_s_T_184 = io_in_0[4:3]; // @[RVC.scala:42:42, :190:7] wire [1:0] _io_out_s_T_300 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_308 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_318 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_326 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_340 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_348 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_358 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_366 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire _io_out_s_T_186 = io_in_0[2]; // @[RVC.scala:42:56, :190:7] wire _io_out_s_T_251 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_262 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_273 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_284 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_298 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_306 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_316 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_324 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_338 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_346 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_356 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_364 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire [1:0] io_out_s_lo_hi_4 = {_io_out_s_T_186, _io_out_s_T_187}; // @[RVC.scala:42:{24,56,62}] wire [5:0] io_out_s_lo_17 = {io_out_s_lo_hi_4, 4'h0}; // @[RVC.scala:42:24] wire [4:0] io_out_s_hi_hi_12 = {_io_out_s_T_183, _io_out_s_T_184}; // @[RVC.scala:42:{24,29,42}] wire [5:0] io_out_s_hi_23 = {io_out_s_hi_hi_12, _io_out_s_T_185}; // @[RVC.scala:42:{24,50}] wire [11:0] _io_out_s_T_188 = {io_out_s_hi_23, io_out_s_lo_17}; // @[RVC.scala:42:24] wire [11:0] io_out_s_lo_18 = {_io_out_s_T_190, io_out_s_opc_3}; // @[RVC.scala:33:13, :86:20, :87:15] wire [16:0] io_out_s_hi_hi_13 = {_io_out_s_T_188, _io_out_s_T_189}; // @[RVC.scala:33:13, :42:24, :87:15] wire [19:0] io_out_s_hi_24 = {io_out_s_hi_hi_13, 3'h0}; // @[RVC.scala:87:15] wire [31:0] _io_out_s_T_191 = {io_out_s_hi_24, io_out_s_lo_18}; // @[RVC.scala:87:15] wire [31:0] io_out_s_res_bits = _io_out_s_T_191; // @[RVC.scala:21:19, :87:15] wire [4:0] io_out_s_res_rd = _io_out_s_T_192; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_res_rs1 = _io_out_s_T_193; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_195 = {2'h1, _io_out_s_T_194}; // @[package.scala:39:86] wire [4:0] io_out_s_res_rs2 = _io_out_s_T_195; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_res_rs3 = _io_out_s_T_196; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_11_bits = _io_out_s_T_181 ? io_out_s_res_bits : io_out_s_me_bits; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rd = _io_out_s_T_181 ? io_out_s_res_rd : io_out_s_me_rd; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs1 = _io_out_s_T_181 ? io_out_s_res_rs1 : io_out_s_me_rs1; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs2 = _io_out_s_T_181 ? io_out_s_res_rs2 : io_out_s_me_rs2; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs3 = _io_out_s_T_181 ? io_out_s_res_rs3 : io_out_s_me_rs3; // @[RVC.scala:21:19, :92:{10,21}] wire [5:0] _io_out_s_T_199 = {_io_out_s_T_197, _io_out_s_T_198}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_201 = {2'h1, _io_out_s_T_200}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_203 = {2'h1, _io_out_s_T_202}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_19 = {_io_out_s_T_203, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_14 = {_io_out_s_T_199, _io_out_s_T_201}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_25 = {io_out_s_hi_hi_14, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_204 = {io_out_s_hi_25, io_out_s_lo_19}; // @[RVC.scala:98:21] wire [5:0] _io_out_s_T_207 = {_io_out_s_T_205, _io_out_s_T_206}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_209 = {2'h1, _io_out_s_T_208}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_211 = {2'h1, _io_out_s_T_210}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_20 = {_io_out_s_T_211, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_15 = {_io_out_s_T_207, _io_out_s_T_209}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_26 = {io_out_s_hi_hi_15, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_212 = {io_out_s_hi_26, io_out_s_lo_20}; // @[RVC.scala:98:21] wire [30:0] _io_out_s_T_213 = {5'h10, _io_out_s_T_212}; // @[RVC.scala:98:21, :99:23] wire [6:0] _io_out_s_T_215 = {7{_io_out_s_T_214}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_217 = {_io_out_s_T_215, _io_out_s_T_216}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_219 = {2'h1, _io_out_s_T_218}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_221 = {2'h1, _io_out_s_T_220}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_21 = {_io_out_s_T_221, 7'h13}; // @[RVC.scala:30:17, :100:21] wire [16:0] io_out_s_hi_hi_16 = {_io_out_s_T_217, _io_out_s_T_219}; // @[RVC.scala:30:17, :43:20, :100:21] wire [19:0] io_out_s_hi_27 = {io_out_s_hi_hi_16, 3'h7}; // @[RVC.scala:100:21] wire [31:0] _io_out_s_T_222 = {io_out_s_hi_27, io_out_s_lo_21}; // @[RVC.scala:100:21] wire [2:0] _io_out_s_funct_T_2 = {_io_out_s_funct_T, _io_out_s_funct_T_1}; // @[RVC.scala:102:{68,70,77}] wire _io_out_s_funct_T_3 = _io_out_s_funct_T_2 == 3'h1; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_3, 2'h0}; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_5 = _io_out_s_funct_T_2 == 3'h2; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_6 = _io_out_s_funct_T_5 ? 3'h6 : _io_out_s_funct_T_4; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_7 = _io_out_s_funct_T_2 == 3'h3; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_8 = _io_out_s_funct_T_7 ? 3'h7 : _io_out_s_funct_T_6; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_9 = _io_out_s_funct_T_2 == 3'h4; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_10 = _io_out_s_funct_T_9 ? 3'h0 : _io_out_s_funct_T_8; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_11 = _io_out_s_funct_T_2 == 3'h5; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_12 = _io_out_s_funct_T_11 ? 3'h0 : _io_out_s_funct_T_10; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_13 = _io_out_s_funct_T_2 == 3'h6; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_14 = _io_out_s_funct_T_13 ? 3'h2 : _io_out_s_funct_T_12; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_15 = &_io_out_s_funct_T_2; // @[package.scala:39:86] wire [2:0] io_out_s_funct = _io_out_s_funct_T_15 ? 3'h3 : _io_out_s_funct_T_14; // @[package.scala:39:{76,86}] wire _io_out_s_sub_T_1 = _io_out_s_sub_T == 2'h0; // @[RVC.scala:103:{24,30}] wire [30:0] io_out_s_sub = {_io_out_s_sub_T_1, 30'h0}; // @[RVC.scala:103:{22,30}] wire [6:0] io_out_s_opc_4 = {3'h3, _io_out_s_opc_T_14, 3'h3}; // @[RVC.scala:104:{22,24}] wire [4:0] _io_out_s_T_224 = {2'h1, _io_out_s_T_223}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_226 = {2'h1, _io_out_s_T_225}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_228 = {2'h1, _io_out_s_T_227}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_22 = {_io_out_s_T_228, io_out_s_opc_4}; // @[RVC.scala:30:17, :104:22, :105:12] wire [9:0] io_out_s_hi_hi_17 = {_io_out_s_T_224, _io_out_s_T_226}; // @[RVC.scala:30:17, :31:17, :105:12] wire [12:0] io_out_s_hi_28 = {io_out_s_hi_hi_17, io_out_s_funct}; // @[package.scala:39:76] wire [24:0] _io_out_s_T_229 = {io_out_s_hi_28, io_out_s_lo_22}; // @[RVC.scala:105:12] wire [30:0] _io_out_s_T_230 = {6'h0, _io_out_s_T_229} \| io_out_s_sub; // @[RVC.scala:103:22, :105:{12,43}] wire [1:0] _io_out_s_T_231 = io_in_0[11:10]; // @[RVC.scala:107:42, :190:7] wire [1:0] _io_out_s_T_299 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_307 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_317 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_325 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_339 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_347 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_357 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_365 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire _io_out_s_T_232 = _io_out_s_T_231 == 2'h1; // @[package.scala:39:86] wire [30:0] _io_out_s_T_233 = _io_out_s_T_232 ? _io_out_s_T_213 : {5'h0, _io_out_s_T_204}; // @[package.scala:39:{76,86}] wire _io_out_s_T_234 = _io_out_s_T_231 == 2'h2; // @[package.scala:39:86] wire [31:0] _io_out_s_T_235 = _io_out_s_T_234 ? _io_out_s_T_222 : {1'h0, _io_out_s_T_233}; // @[package.scala:39:{76,86}] wire _io_out_s_T_236 = &_io_out_s_T_231; // @[package.scala:39:86] wire [31:0] _io_out_s_T_237 = _io_out_s_T_236 ? {1'h0, _io_out_s_T_230} : _io_out_s_T_235; // @[package.scala:39:{76,86}] wire [31:0] io_out_s_12_bits = _io_out_s_T_237; // @[package.scala:39:76] wire [4:0] _io_out_s_T_239 = {2'h1, _io_out_s_T_238}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rd = _io_out_s_T_239; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_241 = {2'h1, _io_out_s_T_240}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs1 = _io_out_s_T_241; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_243 = {2'h1, _io_out_s_T_242}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs2 = _io_out_s_T_243; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_12_rs3 = _io_out_s_T_244; // @[RVC.scala:20:101, :21:19] wire [9:0] _io_out_s_T_246 = {10{_io_out_s_T_245}}; // @[RVC.scala:44:{22,28}] wire _io_out_s_T_247 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_258 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_269 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_280 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire [1:0] _io_out_s_T_248 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_259 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_270 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_281 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire _io_out_s_T_250 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_261 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_272 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_283 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_252 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_263 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_274 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_285 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire [2:0] _io_out_s_T_253 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_264 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_275 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_286 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [3:0] io_out_s_lo_lo = {_io_out_s_T_253, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_5 = {_io_out_s_T_251, _io_out_s_T_252}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_23 = {io_out_s_lo_hi_5, io_out_s_lo_lo}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo = {_io_out_s_T_249, _io_out_s_T_250}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi = {_io_out_s_T_246, _io_out_s_T_247}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_18 = {io_out_s_hi_hi_hi, _io_out_s_T_248}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_29 = {io_out_s_hi_hi_18, io_out_s_hi_lo}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_254 = {io_out_s_hi_29, io_out_s_lo_23}; // @[RVC.scala:44:17] wire _io_out_s_T_255 = _io_out_s_T_254[20]; // @[RVC.scala:44:17, :94:26] wire [9:0] _io_out_s_T_257 = {10{_io_out_s_T_256}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_1 = {_io_out_s_T_264, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_6 = {_io_out_s_T_262, _io_out_s_T_263}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_24 = {io_out_s_lo_hi_6, io_out_s_lo_lo_1}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_1 = {_io_out_s_T_260, _io_out_s_T_261}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_1 = {_io_out_s_T_257, _io_out_s_T_258}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_19 = {io_out_s_hi_hi_hi_1, _io_out_s_T_259}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_30 = {io_out_s_hi_hi_19, io_out_s_hi_lo_1}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_265 = {io_out_s_hi_30, io_out_s_lo_24}; // @[RVC.scala:44:17] wire [9:0] _io_out_s_T_266 = _io_out_s_T_265[10:1]; // @[RVC.scala:44:17, :94:36] wire [9:0] _io_out_s_T_268 = {10{_io_out_s_T_267}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_2 = {_io_out_s_T_275, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_7 = {_io_out_s_T_273, _io_out_s_T_274}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_25 = {io_out_s_lo_hi_7, io_out_s_lo_lo_2}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_2 = {_io_out_s_T_271, _io_out_s_T_272}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_2 = {_io_out_s_T_268, _io_out_s_T_269}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_20 = {io_out_s_hi_hi_hi_2, _io_out_s_T_270}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_31 = {io_out_s_hi_hi_20, io_out_s_hi_lo_2}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_276 = {io_out_s_hi_31, io_out_s_lo_25}; // @[RVC.scala:44:17] wire _io_out_s_T_277 = _io_out_s_T_276[11]; // @[RVC.scala:44:17, :94:48] wire [9:0] _io_out_s_T_279 = {10{_io_out_s_T_278}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_3 = {_io_out_s_T_286, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_8 = {_io_out_s_T_284, _io_out_s_T_285}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_26 = {io_out_s_lo_hi_8, io_out_s_lo_lo_3}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_3 = {_io_out_s_T_282, _io_out_s_T_283}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_3 = {_io_out_s_T_279, _io_out_s_T_280}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_21 = {io_out_s_hi_hi_hi_3, _io_out_s_T_281}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_32 = {io_out_s_hi_hi_21, io_out_s_hi_lo_3}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_287 = {io_out_s_hi_32, io_out_s_lo_26}; // @[RVC.scala:44:17] wire [7:0] _io_out_s_T_288 = _io_out_s_T_287[19:12]; // @[RVC.scala:44:17, :94:58] wire [12:0] io_out_s_lo_hi_9 = {_io_out_s_T_288, 5'h0}; // @[RVC.scala:94:{21,58}] wire [19:0] io_out_s_lo_27 = {io_out_s_lo_hi_9, 7'h6F}; // @[RVC.scala:94:21] wire [10:0] io_out_s_hi_hi_22 = {_io_out_s_T_255, _io_out_s_T_266}; // @[RVC.scala:94:{21,26,36}] wire [11:0] io_out_s_hi_33 = {io_out_s_hi_hi_22, _io_out_s_T_277}; // @[RVC.scala:94:{21,48}] wire [31:0] _io_out_s_T_289 = {io_out_s_hi_33, io_out_s_lo_27}; // @[RVC.scala:94:21] wire [31:0] io_out_s_13_bits = _io_out_s_T_289; // @[RVC.scala:21:19, :94:21] wire [4:0] _io_out_s_T_291 = {2'h1, _io_out_s_T_290}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs1 = _io_out_s_T_291; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_293 = {2'h1, _io_out_s_T_292}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs2 = _io_out_s_T_293; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_13_rs3 = _io_out_s_T_294; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_296 = {5{_io_out_s_T_295}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_10 = {_io_out_s_T_299, _io_out_s_T_300}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_28 = {io_out_s_lo_hi_10, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_23 = {_io_out_s_T_296, _io_out_s_T_297}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_34 = {io_out_s_hi_hi_23, _io_out_s_T_298}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_301 = {io_out_s_hi_34, io_out_s_lo_28}; // @[RVC.scala:45:17] wire _io_out_s_T_302 = _io_out_s_T_301[12]; // @[RVC.scala:45:17, :95:29] wire [4:0] _io_out_s_T_304 = {5{_io_out_s_T_303}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_11 = {_io_out_s_T_307, _io_out_s_T_308}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_29 = {io_out_s_lo_hi_11, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_24 = {_io_out_s_T_304, _io_out_s_T_305}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_35 = {io_out_s_hi_hi_24, _io_out_s_T_306}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_309 = {io_out_s_hi_35, io_out_s_lo_29}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_310 = _io_out_s_T_309[10:5]; // @[RVC.scala:45:17, :95:39] wire [4:0] _io_out_s_T_312 = {2'h1, _io_out_s_T_311}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_314 = {5{_io_out_s_T_313}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_12 = {_io_out_s_T_317, _io_out_s_T_318}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_30 = {io_out_s_lo_hi_12, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_25 = {_io_out_s_T_314, _io_out_s_T_315}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_36 = {io_out_s_hi_hi_25, _io_out_s_T_316}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_319 = {io_out_s_hi_36, io_out_s_lo_30}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_320 = _io_out_s_T_319[4:1]; // @[RVC.scala:45:17, :95:71] wire [4:0] _io_out_s_T_322 = {5{_io_out_s_T_321}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_13 = {_io_out_s_T_325, _io_out_s_T_326}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_31 = {io_out_s_lo_hi_13, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_26 = {_io_out_s_T_322, _io_out_s_T_323}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_37 = {io_out_s_hi_hi_26, _io_out_s_T_324}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_327 = {io_out_s_hi_37, io_out_s_lo_31}; // @[RVC.scala:45:17] wire _io_out_s_T_328 = _io_out_s_T_327[11]; // @[RVC.scala:45:17, :95:82] wire [7:0] io_out_s_lo_lo_4 = {_io_out_s_T_328, 7'h63}; // @[RVC.scala:95:{24,82}] wire [6:0] io_out_s_lo_hi_14 = {3'h0, _io_out_s_T_320}; // @[RVC.scala:95:{24,71}] wire [14:0] io_out_s_lo_32 = {io_out_s_lo_hi_14, io_out_s_lo_lo_4}; // @[RVC.scala:95:24] wire [9:0] io_out_s_hi_lo_4 = {5'h0, _io_out_s_T_312}; // @[RVC.scala:30:17, :95:24] wire [6:0] io_out_s_hi_hi_27 = {_io_out_s_T_302, _io_out_s_T_310}; // @[RVC.scala:95:{24,29,39}] wire [16:0] io_out_s_hi_38 = {io_out_s_hi_hi_27, io_out_s_hi_lo_4}; // @[RVC.scala:95:24] wire [31:0] _io_out_s_T_329 = {io_out_s_hi_38, io_out_s_lo_32}; // @[RVC.scala:95:24] wire [31:0] io_out_s_14_bits = _io_out_s_T_329; // @[RVC.scala:21:19, :95:24] wire [4:0] _io_out_s_T_331 = {2'h1, _io_out_s_T_330}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rd = _io_out_s_T_331; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_333 = {2'h1, _io_out_s_T_332}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rs1 = _io_out_s_T_333; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_14_rs3 = _io_out_s_T_334; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_336 = {5{_io_out_s_T_335}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_15 = {_io_out_s_T_339, _io_out_s_T_340}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_33 = {io_out_s_lo_hi_15, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_28 = {_io_out_s_T_336, _io_out_s_T_337}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_39 = {io_out_s_hi_hi_28, _io_out_s_T_338}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_341 = {io_out_s_hi_39, io_out_s_lo_33}; // @[RVC.scala:45:17] wire _io_out_s_T_342 = _io_out_s_T_341[12]; // @[RVC.scala:45:17, :96:29] wire [4:0] _io_out_s_T_344 = {5{_io_out_s_T_343}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_16 = {_io_out_s_T_347, _io_out_s_T_348}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_34 = {io_out_s_lo_hi_16, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_29 = {_io_out_s_T_344, _io_out_s_T_345}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_40 = {io_out_s_hi_hi_29, _io_out_s_T_346}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_349 = {io_out_s_hi_40, io_out_s_lo_34}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_350 = _io_out_s_T_349[10:5]; // @[RVC.scala:45:17, :96:39] wire [4:0] _io_out_s_T_352 = {2'h1, _io_out_s_T_351}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_354 = {5{_io_out_s_T_353}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_17 = {_io_out_s_T_357, _io_out_s_T_358}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_35 = {io_out_s_lo_hi_17, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_30 = {_io_out_s_T_354, _io_out_s_T_355}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_41 = {io_out_s_hi_hi_30, _io_out_s_T_356}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_359 = {io_out_s_hi_41, io_out_s_lo_35}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_360 = _io_out_s_T_359[4:1]; // @[RVC.scala:45:17, :96:71] wire [4:0] _io_out_s_T_362 = {5{_io_out_s_T_361}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_18 = {_io_out_s_T_365, _io_out_s_T_366}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_36 = {io_out_s_lo_hi_18, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_31 = {_io_out_s_T_362, _io_out_s_T_363}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_42 = {io_out_s_hi_hi_31, _io_out_s_T_364}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_367 = {io_out_s_hi_42, io_out_s_lo_36}; // @[RVC.scala:45:17] wire _io_out_s_T_368 = _io_out_s_T_367[11]; // @[RVC.scala:45:17, :96:82] wire [7:0] io_out_s_lo_lo_5 = {_io_out_s_T_368, 7'h63}; // @[RVC.scala:96:{24,82}] wire [6:0] io_out_s_lo_hi_19 = {3'h1, _io_out_s_T_360}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_37 = {io_out_s_lo_hi_19, io_out_s_lo_lo_5}; // @[RVC.scala:96:24] wire [9:0] io_out_s_hi_lo_5 = {5'h0, _io_out_s_T_352}; // @[RVC.scala:30:17, :96:24] wire [6:0] io_out_s_hi_hi_32 = {_io_out_s_T_342, _io_out_s_T_350}; // @[RVC.scala:96:{24,29,39}] wire [16:0] io_out_s_hi_43 = {io_out_s_hi_hi_32, io_out_s_hi_lo_5}; // @[RVC.scala:96:24] wire [31:0] _io_out_s_T_369 = {io_out_s_hi_43, io_out_s_lo_37}; // @[RVC.scala:96:24] wire [31:0] io_out_s_15_bits = _io_out_s_T_369; // @[RVC.scala:21:19, :96:24] wire [4:0] _io_out_s_T_371 = {2'h1, _io_out_s_T_370}; // @[package.scala:39:86] wire [4:0] io_out_s_15_rs1 = _io_out_s_T_371; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_15_rs3 = _io_out_s_T_372; // @[RVC.scala:20:101, :21:19] wire _io_out_s_load_opc_T_1 = \|_io_out_s_load_opc_T; // @[RVC.scala:33:13, :113:27] wire [6:0] io_out_s_load_opc = _io_out_s_load_opc_T_1 ? 7'h3 : 7'h1F; // @[RVC.scala:113:{23,27}] wire [5:0] _io_out_s_T_375 = {_io_out_s_T_373, _io_out_s_T_374}; // @[RVC.scala:46:{18,20,27}] wire [11:0] io_out_s_lo_38 = {_io_out_s_T_377, 7'h13}; // @[RVC.scala:33:13, :114:24] wire [10:0] io_out_s_hi_hi_33 = {_io_out_s_T_375, _io_out_s_T_376}; // @[RVC.scala:33:13, :46:18, :114:24] wire [13:0] io_out_s_hi_44 = {io_out_s_hi_hi_33, 3'h1}; // @[package.scala:39:86] wire [25:0] _io_out_s_T_378 = {io_out_s_hi_44, io_out_s_lo_38}; // @[RVC.scala:114:24] wire [4:0] io_out_s_16_rd = _io_out_s_T_379; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs1 = _io_out_s_T_380; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs2 = _io_out_s_T_381; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_16_rs3 = _io_out_s_T_382; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_16_bits; // @[RVC.scala:21:19] assign io_out_s_16_bits = {6'h0, _io_out_s_T_378}; // @[RVC.scala:21:19, :22:14, :105:43, :114:24] wire [4:0] io_out_s_lo_39 = {_io_out_s_T_385, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_45 = {_io_out_s_T_383, _io_out_s_T_384}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_386 = {io_out_s_hi_45, io_out_s_lo_39}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_40 = {_io_out_s_T_387, 7'h7}; // @[RVC.scala:33:13, :117:25] wire [13:0] io_out_s_hi_hi_34 = {_io_out_s_T_386, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_46 = {io_out_s_hi_hi_34, 3'h3}; // @[RVC.scala:117:25] wire [28:0] _io_out_s_T_388 = {io_out_s_hi_46, io_out_s_lo_40}; // @[RVC.scala:117:25] wire [4:0] io_out_s_17_rd = _io_out_s_T_389; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_17_rs2 = _io_out_s_T_390; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_17_rs3 = _io_out_s_T_391; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_17_bits; // @[RVC.scala:21:19] assign io_out_s_17_bits = {3'h0, _io_out_s_T_388}; // @[RVC.scala:21:19, :22:14, :117:25] wire [1:0] _io_out_s_T_392 = io_in_0[3:2]; // @[RVC.scala:37:22, :190:7] wire [2:0] _io_out_s_T_394 = io_in_0[6:4]; // @[RVC.scala:37:37, :190:7] wire [4:0] io_out_s_lo_41 = {_io_out_s_T_394, 2'h0}; // @[RVC.scala:37:{20,37}] wire [2:0] io_out_s_hi_47 = {_io_out_s_T_392, _io_out_s_T_393}; // @[RVC.scala:37:{20,22,30}] wire [7:0] _io_out_s_T_395 = {io_out_s_hi_47, io_out_s_lo_41}; // @[RVC.scala:37:20] wire [11:0] io_out_s_lo_42 = {_io_out_s_T_396, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :116:24] wire [12:0] io_out_s_hi_hi_35 = {_io_out_s_T_395, 5'h2}; // @[package.scala:39:86] wire [15:0] io_out_s_hi_48 = {io_out_s_hi_hi_35, 3'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_397 = {io_out_s_hi_48, io_out_s_lo_42}; // @[RVC.scala:116:24] wire [4:0] io_out_s_18_rd = _io_out_s_T_398; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_18_rs2 = _io_out_s_T_399; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_18_rs3 = _io_out_s_T_400; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_18_bits; // @[RVC.scala:21:19] assign io_out_s_18_bits = {4'h0, _io_out_s_T_397}; // @[RVC.scala:21:19, :22:14, :116:24] wire [4:0] io_out_s_lo_43 = {_io_out_s_T_403, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_49 = {_io_out_s_T_401, _io_out_s_T_402}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_404 = {io_out_s_hi_49, io_out_s_lo_43}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_44 = {_io_out_s_T_405, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :115:24] wire [13:0] io_out_s_hi_hi_36 = {_io_out_s_T_404, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_50 = {io_out_s_hi_hi_36, 3'h3}; // @[RVC.scala:115:24] wire [28:0] _io_out_s_T_406 = {io_out_s_hi_50, io_out_s_lo_44}; // @[RVC.scala:115:24] wire [4:0] io_out_s_19_rd = _io_out_s_T_407; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_19_rs2 = _io_out_s_T_408; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_19_rs3 = _io_out_s_T_409; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_19_bits; // @[RVC.scala:21:19] assign io_out_s_19_bits = {3'h0, _io_out_s_T_406}; // @[RVC.scala:21:19, :22:14, :115:24] wire [11:0] io_out_s_mv_lo = {_io_out_s_mv_T_1, 7'h33}; // @[RVC.scala:33:13, :132:22] wire [9:0] io_out_s_mv_hi_hi = {_io_out_s_mv_T, 5'h0}; // @[RVC.scala:32:14, :132:22] wire [12:0] io_out_s_mv_hi = {io_out_s_mv_hi_hi, 3'h0}; // @[RVC.scala:132:22] wire [24:0] _io_out_s_mv_T_2 = {io_out_s_mv_hi, io_out_s_mv_lo}; // @[RVC.scala:132:22] wire [4:0] io_out_s_mv_rd = _io_out_s_mv_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_mv_rs2 = _io_out_s_mv_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_mv_rs3 = _io_out_s_mv_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_mv_bits; // @[RVC.scala:21:19] assign io_out_s_mv_bits = {7'h0, _io_out_s_mv_T_2}; // @[RVC.scala:21:19, :22:14, :132:22] wire [11:0] io_out_s_add_lo = {_io_out_s_add_T_2, 7'h33}; // @[RVC.scala:33:13, :134:25] wire [9:0] io_out_s_add_hi_hi = {_io_out_s_add_T, _io_out_s_add_T_1}; // @[RVC.scala:32:14, :33:13, :134:25] wire [12:0] io_out_s_add_hi = {io_out_s_add_hi_hi, 3'h0}; // @[RVC.scala:134:25] wire [24:0] _io_out_s_add_T_3 = {io_out_s_add_hi, io_out_s_add_lo}; // @[RVC.scala:134:25] wire [4:0] io_out_s_add_rd = _io_out_s_add_T_4; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs1 = _io_out_s_add_T_5; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs2 = _io_out_s_add_T_6; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_add_rs3 = _io_out_s_add_T_7; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_add_bits; // @[RVC.scala:21:19] assign io_out_s_add_bits = {7'h0, _io_out_s_add_T_3}; // @[RVC.scala:21:19, :22:14, :134:25] wire [9:0] io_out_s_jr_hi_hi = {_io_out_s_jr_T, _io_out_s_jr_T_1}; // @[RVC.scala:32:14, :33:13, :135:19] wire [12:0] io_out_s_jr_hi = {io_out_s_jr_hi_hi, 3'h0}; // @[RVC.scala:135:19] wire [24:0] io_out_s_jr = {io_out_s_jr_hi, 12'h67}; // @[RVC.scala:135:19] wire [17:0] _io_out_s_reserved_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29] wire [17:0] _io_out_s_ebreak_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29, :140:27] wire [24:0] io_out_s_reserved = {_io_out_s_reserved_T, 7'h1F}; // @[RVC.scala:136:{25,29}] wire _io_out_s_jr_reserved_T_1 = \|_io_out_s_jr_reserved_T; // @[RVC.scala:33:13, :137:37] wire [24:0] _io_out_s_jr_reserved_T_2 = _io_out_s_jr_reserved_T_1 ? io_out_s_jr : io_out_s_reserved; // @[RVC.scala:135:19, :136:25, :137:{33,37}] wire [4:0] io_out_s_jr_reserved_rs1 = _io_out_s_jr_reserved_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jr_reserved_rs2 = _io_out_s_jr_reserved_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jr_reserved_rs3 = _io_out_s_jr_reserved_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jr_reserved_bits; // @[RVC.scala:21:19] assign io_out_s_jr_reserved_bits = {7'h0, _io_out_s_jr_reserved_T_2}; // @[RVC.scala:21:19, :22:14, :137:33] wire _io_out_s_jr_mv_T_1 = \|_io_out_s_jr_mv_T; // @[RVC.scala:32:14, :138:27] wire [31:0] io_out_s_jr_mv_bits = _io_out_s_jr_mv_T_1 ? io_out_s_mv_bits : io_out_s_jr_reserved_bits; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rd = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rd : 5'h0; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs1 = _io_out_s_jr_mv_T_1 ? 5'h0 : io_out_s_jr_reserved_rs1; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs2 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs2 : io_out_s_jr_reserved_rs2; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs3 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs3 : io_out_s_jr_reserved_rs3; // @[RVC.scala:21:19, :138:{22,27}] wire [9:0] io_out_s_jalr_hi_hi = {_io_out_s_jalr_T, _io_out_s_jalr_T_1}; // @[RVC.scala:32:14, :33:13, :139:21] wire [12:0] io_out_s_jalr_hi = {io_out_s_jalr_hi_hi, 3'h0}; // @[RVC.scala:139:21] wire [24:0] io_out_s_jalr = {io_out_s_jalr_hi, 12'hE7}; // @[RVC.scala:139:21] wire [24:0] _io_out_s_ebreak_T_1 = {_io_out_s_ebreak_T, 7'h73}; // @[RVC.scala:140:{23,27}] wire [24:0] io_out_s_ebreak = {_io_out_s_ebreak_T_1[24:21], _io_out_s_ebreak_T_1[20:0] \| 21'h100000}; // @[RVC.scala:140:{23,46}] wire _io_out_s_jalr_ebreak_T_1 = \|_io_out_s_jalr_ebreak_T; // @[RVC.scala:33:13, :141:37] wire [24:0] _io_out_s_jalr_ebreak_T_2 = _io_out_s_jalr_ebreak_T_1 ? io_out_s_jalr : io_out_s_ebreak; // @[RVC.scala:139:21, :140:46, :141:{33,37}] wire [4:0] io_out_s_jalr_ebreak_rs1 = _io_out_s_jalr_ebreak_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jalr_ebreak_rs2 = _io_out_s_jalr_ebreak_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jalr_ebreak_rs3 = _io_out_s_jalr_ebreak_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19] assign io_out_s_jalr_ebreak_bits = {7'h0, _io_out_s_jalr_ebreak_T_2}; // @[RVC.scala:21:19, :22:14, :141:33] wire _io_out_s_jalr_add_T_1 = \|_io_out_s_jalr_add_T; // @[RVC.scala:32:14, :142:30] wire [31:0] io_out_s_jalr_add_bits = _io_out_s_jalr_add_T_1 ? io_out_s_add_bits : io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rd = _io_out_s_jalr_add_T_1 ? io_out_s_add_rd : 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_jalr_add_rs1 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs1 : io_out_s_jalr_ebreak_rs1; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs2 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs2 : io_out_s_jalr_ebreak_rs2; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs3 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs3 : io_out_s_jalr_ebreak_rs3; // @[RVC.scala:21:19, :142:{25,30}] wire [31:0] io_out_s_20_bits = _io_out_s_T_410 ? io_out_s_jalr_add_bits : io_out_s_jr_mv_bits; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rd = _io_out_s_T_410 ? io_out_s_jalr_add_rd : io_out_s_jr_mv_rd; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs1 = _io_out_s_T_410 ? io_out_s_jalr_add_rs1 : io_out_s_jr_mv_rs1; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs2 = _io_out_s_T_410 ? io_out_s_jalr_add_rs2 : io_out_s_jr_mv_rs2; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs3 = _io_out_s_T_410 ? io_out_s_jalr_add_rs3 : io_out_s_jr_mv_rs3; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [5:0] io_out_s_hi_51 = {_io_out_s_T_411, _io_out_s_T_412}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_413 = {io_out_s_hi_51, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_414 = _io_out_s_T_413[8:5]; // @[RVC.scala:40:20, :124:34] wire [5:0] io_out_s_hi_52 = {_io_out_s_T_416, _io_out_s_T_417}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_418 = {io_out_s_hi_52, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_419 = _io_out_s_T_418[4:0]; // @[RVC.scala:40:20, :124:66] wire [7:0] io_out_s_lo_hi_20 = {3'h3, _io_out_s_T_419}; // @[RVC.scala:124:{25,66}] wire [14:0] io_out_s_lo_45 = {io_out_s_lo_hi_20, 7'h27}; // @[RVC.scala:124:25] wire [8:0] io_out_s_hi_hi_37 = {_io_out_s_T_414, _io_out_s_T_415}; // @[RVC.scala:32:14, :124:{25,34}] wire [13:0] io_out_s_hi_53 = {io_out_s_hi_hi_37, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_420 = {io_out_s_hi_53, io_out_s_lo_45}; // @[RVC.scala:124:25] wire [4:0] io_out_s_21_rd = _io_out_s_T_421; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_21_rs2 = _io_out_s_T_422; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_21_rs3 = _io_out_s_T_423; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_21_bits; // @[RVC.scala:21:19] assign io_out_s_21_bits = {3'h0, _io_out_s_T_420}; // @[RVC.scala:21:19, :22:14, :124:25] wire [1:0] _io_out_s_T_424 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [1:0] _io_out_s_T_429 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [3:0] _io_out_s_T_425 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [3:0] _io_out_s_T_430 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [5:0] io_out_s_hi_54 = {_io_out_s_T_424, _io_out_s_T_425}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_426 = {io_out_s_hi_54, 2'h0}; // @[RVC.scala:39:20] wire [2:0] _io_out_s_T_427 = _io_out_s_T_426[7:5]; // @[RVC.scala:39:20, :123:33] wire [5:0] io_out_s_hi_55 = {_io_out_s_T_429, _io_out_s_T_430}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_431 = {io_out_s_hi_55, 2'h0}; // @[RVC.scala:39:20] wire [4:0] _io_out_s_T_432 = _io_out_s_T_431[4:0]; // @[RVC.scala:39:20, :123:65] wire [7:0] io_out_s_lo_hi_21 = {3'h2, _io_out_s_T_432}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_46 = {io_out_s_lo_hi_21, 7'h23}; // @[RVC.scala:123:24] wire [7:0] io_out_s_hi_hi_38 = {_io_out_s_T_427, _io_out_s_T_428}; // @[RVC.scala:32:14, :123:{24,33}] wire [12:0] io_out_s_hi_56 = {io_out_s_hi_hi_38, 5'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_433 = {io_out_s_hi_56, io_out_s_lo_46}; // @[RVC.scala:123:24] wire [4:0] io_out_s_22_rd = _io_out_s_T_434; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_22_rs2 = _io_out_s_T_435; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_22_rs3 = _io_out_s_T_436; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_22_bits; // @[RVC.scala:21:19] assign io_out_s_22_bits = {4'h0, _io_out_s_T_433}; // @[RVC.scala:21:19, :22:14, :123:24] wire [5:0] io_out_s_hi_57 = {_io_out_s_T_437, _io_out_s_T_438}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_439 = {io_out_s_hi_57, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_440 = _io_out_s_T_439[8:5]; // @[RVC.scala:40:20, :122:33] wire [5:0] io_out_s_hi_58 = {_io_out_s_T_442, _io_out_s_T_443}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_444 = {io_out_s_hi_58, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_445 = _io_out_s_T_444[4:0]; // @[RVC.scala:40:20, :122:65] wire [7:0] io_out_s_lo_hi_22 = {3'h3, _io_out_s_T_445}; // @[RVC.scala:122:{24,65}] wire [14:0] io_out_s_lo_47 = {io_out_s_lo_hi_22, 7'h23}; // @[RVC.scala:122:24] wire [8:0] io_out_s_hi_hi_39 = {_io_out_s_T_440, _io_out_s_T_441}; // @[RVC.scala:32:14, :122:{24,33}] wire [13:0] io_out_s_hi_59 = {io_out_s_hi_hi_39, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_446 = {io_out_s_hi_59, io_out_s_lo_47}; // @[RVC.scala:122:24] wire [4:0] io_out_s_23_rd = _io_out_s_T_447; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_23_rs2 = _io_out_s_T_448; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_23_rs3 = _io_out_s_T_449; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_23_bits; // @[RVC.scala:21:19] assign io_out_s_23_bits = {3'h0, _io_out_s_T_446}; // @[RVC.scala:21:19, :22:14, :122:24] wire [4:0] io_out_s_24_rd = _io_out_s_T_450; // @[RVC.scala:20:36, :21:19] wire [4:0] _io_out_s_T_451 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_455 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_459 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_463 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_467 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_471 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_475 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_479 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] io_out_s_24_rs1 = _io_out_s_T_451; // @[RVC.scala:20:57, :21:19] wire [4:0] _io_out_s_T_452 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_456 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_460 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_464 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_468 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_472 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_476 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_480 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] io_out_s_24_rs2 = _io_out_s_T_452; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_24_rs3 = _io_out_s_T_453; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_25_rd = _io_out_s_T_454; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_25_rs1 = _io_out_s_T_455; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_25_rs2 = _io_out_s_T_456; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_25_rs3 = _io_out_s_T_457; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_26_rd = _io_out_s_T_458; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_26_rs1 = _io_out_s_T_459; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_26_rs2 = _io_out_s_T_460; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_26_rs3 = _io_out_s_T_461; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_27_rd = _io_out_s_T_462; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_27_rs1 = _io_out_s_T_463; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_27_rs2 = _io_out_s_T_464; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_27_rs3 = _io_out_s_T_465; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_28_rd = _io_out_s_T_466; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_28_rs1 = _io_out_s_T_467; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_28_rs2 = _io_out_s_T_468; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_28_rs3 = _io_out_s_T_469; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_29_rd = _io_out_s_T_470; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_29_rs1 = _io_out_s_T_471; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_29_rs2 = _io_out_s_T_472; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_29_rs3 = _io_out_s_T_473; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_30_rd = _io_out_s_T_474; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_30_rs1 = _io_out_s_T_475; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_30_rs2 = _io_out_s_T_476; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_30_rs3 = _io_out_s_T_477; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_31_rd = _io_out_s_T_478; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_31_rs1 = _io_out_s_T_479; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_31_rs2 = _io_out_s_T_480; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_31_rs3 = _io_out_s_T_481; // @[RVC.scala:20:101, :21:19] wire [2:0] _io_out_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :190:7] wire [2:0] _io_ill_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :186:20, :190:7] wire [4:0] _io_out_T_2 = {_io_out_T, _io_out_T_1}; // @[RVC.scala:154:{10,12,20}] wire _io_out_T_3 = _io_out_T_2 == 5'h1; // @[package.scala:39:86] wire [31:0] _io_out_T_4_bits = _io_out_T_3 ? io_out_s_1_bits : io_out_s_0_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rd = _io_out_T_3 ? io_out_s_1_rd : io_out_s_0_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs1 = _io_out_T_3 ? io_out_s_1_rs1 : 5'h2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs2 = _io_out_T_3 ? io_out_s_1_rs2 : io_out_s_0_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs3 = _io_out_T_3 ? io_out_s_1_rs3 : io_out_s_0_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_5 = _io_out_T_2 == 5'h2; // @[package.scala:39:86] wire [31:0] _io_out_T_6_bits = _io_out_T_5 ? io_out_s_2_bits : _io_out_T_4_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rd = _io_out_T_5 ? io_out_s_2_rd : _io_out_T_4_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs1 = _io_out_T_5 ? io_out_s_2_rs1 : _io_out_T_4_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs2 = _io_out_T_5 ? io_out_s_2_rs2 : _io_out_T_4_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs3 = _io_out_T_5 ? io_out_s_2_rs3 : _io_out_T_4_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_7 = _io_out_T_2 == 5'h3; // @[package.scala:39:86] wire [31:0] _io_out_T_8_bits = _io_out_T_7 ? io_out_s_3_bits : _io_out_T_6_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rd = _io_out_T_7 ? io_out_s_3_rd : _io_out_T_6_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs1 = _io_out_T_7 ? io_out_s_3_rs1 : _io_out_T_6_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs2 = _io_out_T_7 ? io_out_s_3_rs2 : _io_out_T_6_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs3 = _io_out_T_7 ? io_out_s_3_rs3 : _io_out_T_6_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_9 = _io_out_T_2 == 5'h4; // @[package.scala:39:86] wire [31:0] _io_out_T_10_bits = _io_out_T_9 ? io_out_s_4_bits : _io_out_T_8_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rd = _io_out_T_9 ? io_out_s_4_rd : _io_out_T_8_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs1 = _io_out_T_9 ? io_out_s_4_rs1 : _io_out_T_8_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs2 = _io_out_T_9 ? io_out_s_4_rs2 : _io_out_T_8_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs3 = _io_out_T_9 ? io_out_s_4_rs3 : _io_out_T_8_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_11 = _io_out_T_2 == 5'h5; // @[package.scala:39:86] wire [31:0] _io_out_T_12_bits = _io_out_T_11 ? io_out_s_5_bits : _io_out_T_10_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rd = _io_out_T_11 ? io_out_s_5_rd : _io_out_T_10_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs1 = _io_out_T_11 ? io_out_s_5_rs1 : _io_out_T_10_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs2 = _io_out_T_11 ? io_out_s_5_rs2 : _io_out_T_10_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs3 = _io_out_T_11 ? io_out_s_5_rs3 : _io_out_T_10_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_13 = _io_out_T_2 == 5'h6; // @[package.scala:39:86] wire [31:0] _io_out_T_14_bits = _io_out_T_13 ? io_out_s_6_bits : _io_out_T_12_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rd = _io_out_T_13 ? io_out_s_6_rd : _io_out_T_12_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs1 = _io_out_T_13 ? io_out_s_6_rs1 : _io_out_T_12_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs2 = _io_out_T_13 ? io_out_s_6_rs2 : _io_out_T_12_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs3 = _io_out_T_13 ? io_out_s_6_rs3 : _io_out_T_12_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_15 = _io_out_T_2 == 5'h7; // @[package.scala:39:86] wire [31:0] _io_out_T_16_bits = _io_out_T_15 ? io_out_s_7_bits : _io_out_T_14_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rd = _io_out_T_15 ? io_out_s_7_rd : _io_out_T_14_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs1 = _io_out_T_15 ? io_out_s_7_rs1 : _io_out_T_14_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs2 = _io_out_T_15 ? io_out_s_7_rs2 : _io_out_T_14_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs3 = _io_out_T_15 ? io_out_s_7_rs3 : _io_out_T_14_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_17 = _io_out_T_2 == 5'h8; // @[package.scala:39:86] wire [31:0] _io_out_T_18_bits = _io_out_T_17 ? io_out_s_8_bits : _io_out_T_16_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rd = _io_out_T_17 ? io_out_s_8_rd : _io_out_T_16_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs1 = _io_out_T_17 ? io_out_s_8_rs1 : _io_out_T_16_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs2 = _io_out_T_17 ? io_out_s_8_rs2 : _io_out_T_16_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs3 = _io_out_T_17 ? io_out_s_8_rs3 : _io_out_T_16_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_19 = _io_out_T_2 == 5'h9; // @[package.scala:39:86] wire [31:0] _io_out_T_20_bits = _io_out_T_19 ? io_out_s_9_bits : _io_out_T_18_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rd = _io_out_T_19 ? io_out_s_9_rd : _io_out_T_18_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs1 = _io_out_T_19 ? io_out_s_9_rs1 : _io_out_T_18_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs2 = _io_out_T_19 ? io_out_s_9_rs2 : _io_out_T_18_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs3 = _io_out_T_19 ? io_out_s_9_rs3 : _io_out_T_18_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_21 = _io_out_T_2 == 5'hA; // @[package.scala:39:86] wire [31:0] _io_out_T_22_bits = _io_out_T_21 ? io_out_s_10_bits : _io_out_T_20_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rd = _io_out_T_21 ? io_out_s_10_rd : _io_out_T_20_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs1 = _io_out_T_21 ? 5'h0 : _io_out_T_20_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs2 = _io_out_T_21 ? io_out_s_10_rs2 : _io_out_T_20_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs3 = _io_out_T_21 ? io_out_s_10_rs3 : _io_out_T_20_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_23 = _io_out_T_2 == 5'hB; // @[package.scala:39:86] wire [31:0] _io_out_T_24_bits = _io_out_T_23 ? io_out_s_11_bits : _io_out_T_22_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rd = _io_out_T_23 ? io_out_s_11_rd : _io_out_T_22_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs1 = _io_out_T_23 ? io_out_s_11_rs1 : _io_out_T_22_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs2 = _io_out_T_23 ? io_out_s_11_rs2 : _io_out_T_22_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs3 = _io_out_T_23 ? io_out_s_11_rs3 : _io_out_T_22_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_25 = _io_out_T_2 == 5'hC; // @[package.scala:39:86] wire [31:0] _io_out_T_26_bits = _io_out_T_25 ? io_out_s_12_bits : _io_out_T_24_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rd = _io_out_T_25 ? io_out_s_12_rd : _io_out_T_24_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs1 = _io_out_T_25 ? io_out_s_12_rs1 : _io_out_T_24_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs2 = _io_out_T_25 ? io_out_s_12_rs2 : _io_out_T_24_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs3 = _io_out_T_25 ? io_out_s_12_rs3 : _io_out_T_24_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_27 = _io_out_T_2 == 5'hD; // @[package.scala:39:86] wire [31:0] _io_out_T_28_bits = _io_out_T_27 ? io_out_s_13_bits : _io_out_T_26_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rd = _io_out_T_27 ? 5'h0 : _io_out_T_26_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs1 = _io_out_T_27 ? io_out_s_13_rs1 : _io_out_T_26_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs2 = _io_out_T_27 ? io_out_s_13_rs2 : _io_out_T_26_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs3 = _io_out_T_27 ? io_out_s_13_rs3 : _io_out_T_26_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_29 = _io_out_T_2 == 5'hE; // @[package.scala:39:86] wire [31:0] _io_out_T_30_bits = _io_out_T_29 ? io_out_s_14_bits : _io_out_T_28_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rd = _io_out_T_29 ? io_out_s_14_rd : _io_out_T_28_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs1 = _io_out_T_29 ? io_out_s_14_rs1 : _io_out_T_28_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs2 = _io_out_T_29 ? 5'h0 : _io_out_T_28_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs3 = _io_out_T_29 ? io_out_s_14_rs3 : _io_out_T_28_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_31 = _io_out_T_2 == 5'hF; // @[package.scala:39:86] wire [31:0] _io_out_T_32_bits = _io_out_T_31 ? io_out_s_15_bits : _io_out_T_30_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rd = _io_out_T_31 ? 5'h0 : _io_out_T_30_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs1 = _io_out_T_31 ? io_out_s_15_rs1 : _io_out_T_30_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs2 = _io_out_T_31 ? 5'h0 : _io_out_T_30_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs3 = _io_out_T_31 ? io_out_s_15_rs3 : _io_out_T_30_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_33 = _io_out_T_2 == 5'h10; // @[package.scala:39:86] wire [31:0] _io_out_T_34_bits = _io_out_T_33 ? io_out_s_16_bits : _io_out_T_32_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rd = _io_out_T_33 ? io_out_s_16_rd : _io_out_T_32_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs1 = _io_out_T_33 ? io_out_s_16_rs1 : _io_out_T_32_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs2 = _io_out_T_33 ? io_out_s_16_rs2 : _io_out_T_32_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs3 = _io_out_T_33 ? io_out_s_16_rs3 : _io_out_T_32_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_35 = _io_out_T_2 == 5'h11; // @[package.scala:39:86] wire [31:0] _io_out_T_36_bits = _io_out_T_35 ? io_out_s_17_bits : _io_out_T_34_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rd = _io_out_T_35 ? io_out_s_17_rd : _io_out_T_34_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs1 = _io_out_T_35 ? 5'h2 : _io_out_T_34_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs2 = _io_out_T_35 ? io_out_s_17_rs2 : _io_out_T_34_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs3 = _io_out_T_35 ? io_out_s_17_rs3 : _io_out_T_34_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_37 = _io_out_T_2 == 5'h12; // @[package.scala:39:86] wire [31:0] _io_out_T_38_bits = _io_out_T_37 ? io_out_s_18_bits : _io_out_T_36_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rd = _io_out_T_37 ? io_out_s_18_rd : _io_out_T_36_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs1 = _io_out_T_37 ? 5'h2 : _io_out_T_36_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs2 = _io_out_T_37 ? io_out_s_18_rs2 : _io_out_T_36_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs3 = _io_out_T_37 ? io_out_s_18_rs3 : _io_out_T_36_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_39 = _io_out_T_2 == 5'h13; // @[package.scala:39:86] wire [31:0] _io_out_T_40_bits = _io_out_T_39 ? io_out_s_19_bits : _io_out_T_38_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rd = _io_out_T_39 ? io_out_s_19_rd : _io_out_T_38_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs1 = _io_out_T_39 ? 5'h2 : _io_out_T_38_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs2 = _io_out_T_39 ? io_out_s_19_rs2 : _io_out_T_38_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs3 = _io_out_T_39 ? io_out_s_19_rs3 : _io_out_T_38_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_41 = _io_out_T_2 == 5'h14; // @[package.scala:39:86] wire [31:0] _io_out_T_42_bits = _io_out_T_41 ? io_out_s_20_bits : _io_out_T_40_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rd = _io_out_T_41 ? io_out_s_20_rd : _io_out_T_40_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs1 = _io_out_T_41 ? io_out_s_20_rs1 : _io_out_T_40_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs2 = _io_out_T_41 ? io_out_s_20_rs2 : _io_out_T_40_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs3 = _io_out_T_41 ? io_out_s_20_rs3 : _io_out_T_40_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_43 = _io_out_T_2 == 5'h15; // @[package.scala:39:86] wire [31:0] _io_out_T_44_bits = _io_out_T_43 ? io_out_s_21_bits : _io_out_T_42_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rd = _io_out_T_43 ? io_out_s_21_rd : _io_out_T_42_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs1 = _io_out_T_43 ? 5'h2 : _io_out_T_42_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs2 = _io_out_T_43 ? io_out_s_21_rs2 : _io_out_T_42_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs3 = _io_out_T_43 ? io_out_s_21_rs3 : _io_out_T_42_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_45 = _io_out_T_2 == 5'h16; // @[package.scala:39:86] wire [31:0] _io_out_T_46_bits = _io_out_T_45 ? io_out_s_22_bits : _io_out_T_44_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rd = _io_out_T_45 ? io_out_s_22_rd : _io_out_T_44_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs1 = _io_out_T_45 ? 5'h2 : _io_out_T_44_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs2 = _io_out_T_45 ? io_out_s_22_rs2 : _io_out_T_44_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs3 = _io_out_T_45 ? io_out_s_22_rs3 : _io_out_T_44_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_47 = _io_out_T_2 == 5'h17; // @[package.scala:39:86] wire [31:0] _io_out_T_48_bits = _io_out_T_47 ? io_out_s_23_bits : _io_out_T_46_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rd = _io_out_T_47 ? io_out_s_23_rd : _io_out_T_46_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs1 = _io_out_T_47 ? 5'h2 : _io_out_T_46_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs2 = _io_out_T_47 ? io_out_s_23_rs2 : _io_out_T_46_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs3 = _io_out_T_47 ? io_out_s_23_rs3 : _io_out_T_46_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_49 = _io_out_T_2 == 5'h18; // @[package.scala:39:86] wire [31:0] _io_out_T_50_bits = _io_out_T_49 ? io_out_s_24_bits : _io_out_T_48_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rd = _io_out_T_49 ? io_out_s_24_rd : _io_out_T_48_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs1 = _io_out_T_49 ? io_out_s_24_rs1 : _io_out_T_48_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs2 = _io_out_T_49 ? io_out_s_24_rs2 : _io_out_T_48_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs3 = _io_out_T_49 ? io_out_s_24_rs3 : _io_out_T_48_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_51 = _io_out_T_2 == 5'h19; // @[package.scala:39:86] wire [31:0] _io_out_T_52_bits = _io_out_T_51 ? io_out_s_25_bits : _io_out_T_50_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rd = _io_out_T_51 ? io_out_s_25_rd : _io_out_T_50_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs1 = _io_out_T_51 ? io_out_s_25_rs1 : _io_out_T_50_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs2 = _io_out_T_51 ? io_out_s_25_rs2 : _io_out_T_50_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs3 = _io_out_T_51 ? io_out_s_25_rs3 : _io_out_T_50_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_53 = _io_out_T_2 == 5'h1A; // @[package.scala:39:86] wire [31:0] _io_out_T_54_bits = _io_out_T_53 ? io_out_s_26_bits : _io_out_T_52_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rd = _io_out_T_53 ? io_out_s_26_rd : _io_out_T_52_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs1 = _io_out_T_53 ? io_out_s_26_rs1 : _io_out_T_52_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs2 = _io_out_T_53 ? io_out_s_26_rs2 : _io_out_T_52_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs3 = _io_out_T_53 ? io_out_s_26_rs3 : _io_out_T_52_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_55 = _io_out_T_2 == 5'h1B; // @[package.scala:39:86] wire [31:0] _io_out_T_56_bits = _io_out_T_55 ? io_out_s_27_bits : _io_out_T_54_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rd = _io_out_T_55 ? io_out_s_27_rd : _io_out_T_54_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs1 = _io_out_T_55 ? io_out_s_27_rs1 : _io_out_T_54_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs2 = _io_out_T_55 ? io_out_s_27_rs2 : _io_out_T_54_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs3 = _io_out_T_55 ? io_out_s_27_rs3 : _io_out_T_54_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_57 = _io_out_T_2 == 5'h1C; // @[package.scala:39:86] wire [31:0] _io_out_T_58_bits = _io_out_T_57 ? io_out_s_28_bits : _io_out_T_56_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rd = _io_out_T_57 ? io_out_s_28_rd : _io_out_T_56_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs1 = _io_out_T_57 ? io_out_s_28_rs1 : _io_out_T_56_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs2 = _io_out_T_57 ? io_out_s_28_rs2 : _io_out_T_56_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs3 = _io_out_T_57 ? io_out_s_28_rs3 : _io_out_T_56_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_59 = _io_out_T_2 == 5'h1D; // @[package.scala:39:86] wire [31:0] _io_out_T_60_bits = _io_out_T_59 ? io_out_s_29_bits : _io_out_T_58_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rd = _io_out_T_59 ? io_out_s_29_rd : _io_out_T_58_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs1 = _io_out_T_59 ? io_out_s_29_rs1 : _io_out_T_58_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs2 = _io_out_T_59 ? io_out_s_29_rs2 : _io_out_T_58_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs3 = _io_out_T_59 ? io_out_s_29_rs3 : _io_out_T_58_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_61 = _io_out_T_2 == 5'h1E; // @[package.scala:39:86] wire [31:0] _io_out_T_62_bits = _io_out_T_61 ? io_out_s_30_bits : _io_out_T_60_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rd = _io_out_T_61 ? io_out_s_30_rd : _io_out_T_60_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs1 = _io_out_T_61 ? io_out_s_30_rs1 : _io_out_T_60_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs2 = _io_out_T_61 ? io_out_s_30_rs2 : _io_out_T_60_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs3 = _io_out_T_61 ? io_out_s_30_rs3 : _io_out_T_60_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_63 = &_io_out_T_2; // @[package.scala:39:86] assign _io_out_T_64_bits = _io_out_T_63 ? io_out_s_31_bits : _io_out_T_62_bits; // @[package.scala:39:{76,86}] assign _io_out_T_64_rd = _io_out_T_63 ? io_out_s_31_rd : _io_out_T_62_rd; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs1 = _io_out_T_63 ? io_out_s_31_rs1 : _io_out_T_62_rs1; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs2 = _io_out_T_63 ? io_out_s_31_rs2 : _io_out_T_62_rs2; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs3 = _io_out_T_63 ? io_out_s_31_rs3 : _io_out_T_62_rs3; // @[package.scala:39:{76,86}] assign io_out_bits_0 = _io_out_T_64_bits; // @[package.scala:39:76] assign io_out_rd = _io_out_T_64_rd; // @[package.scala:39:76] assign io_out_rs1 = _io_out_T_64_rs1; // @[package.scala:39:76] assign io_out_rs2 = _io_out_T_64_rs2; // @[package.scala:39:76] assign io_out_rs3 = _io_out_T_64_rs3; // @[package.scala:39:76] wire [10:0] _io_ill_s_T = io_in_0[12:2]; // @[RVC.scala:158:19, :190:7] wire [10:0] _io_ill_s_T_13 = io_in_0[12:2]; // @[RVC.scala:158:19, :177:21, :190:7] wire _io_ill_s_T_1 = \|_io_ill_s_T; // @[RVC.scala:158:{19,27}] wire io_ill_s_0 = ~_io_ill_s_T_1; // @[RVC.scala:158:{16,27}] wire io_ill_s_9 = _io_ill_s_T_2 == 5'h0; // @[RVC.scala:33:13, :167:47] wire _io_ill_s_T_5 = \|_io_ill_s_T_4; // @[RVC.scala:168:{27,34}] wire _io_ill_s_T_6 = _io_ill_s_T_3 \| _io_ill_s_T_5; // @[RVC.scala:168:{19,24,34}] wire io_ill_s_11 = ~_io_ill_s_T_6; // @[RVC.scala:168:{16,24}] wire _io_ill_s_T_8 = &_io_ill_s_T_7; // @[RVC.scala:169:{22,31}] wire _io_ill_s_T_10 = _io_ill_s_T_9; // @[RVC.scala:169:{69,73}] wire io_ill_s_12 = _io_ill_s_T_8 & _io_ill_s_T_10; // @[RVC.scala:169:{31,36,73}] wire io_ill_s_18 = _io_ill_s_T_11 == 5'h0; // @[RVC.scala:33:13, :175:18] wire io_ill_s_19 = _io_ill_s_T_12 == 5'h0; // @[RVC.scala:33:13, :175:18] wire _io_ill_s_T_14 = \|_io_ill_s_T_13; // @[RVC.scala:177:{21,29}] wire io_ill_s_20 = ~_io_ill_s_T_14; // @[RVC.scala:177:{18,29}] wire [4:0] _io_ill_T_2 = {_io_ill_T, _io_ill_T_1}; // @[RVC.scala:186:{10,12,20}] wire _io_ill_T_3 = _io_ill_T_2 == 5'h1; // @[package.scala:39:86] wire _io_ill_T_4 = ~_io_ill_T_3 & io_ill_s_0; // @[package.scala:39:{76,86}] wire _io_ill_T_5 = _io_ill_T_2 == 5'h2; // @[package.scala:39:86] wire _io_ill_T_6 = ~_io_ill_T_5 & _io_ill_T_4; // @[package.scala:39:{76,86}] wire _io_ill_T_7 = _io_ill_T_2 == 5'h3; // @[package.scala:39:86] wire _io_ill_T_8 = ~_io_ill_T_7 & _io_ill_T_6; // @[package.scala:39:{76,86}] wire _io_ill_T_9 = _io_ill_T_2 == 5'h4; // @[package.scala:39:86] wire _io_ill_T_10 = _io_ill_T_9 \| _io_ill_T_8; // @[package.scala:39:{76,86}] wire _io_ill_T_11 = _io_ill_T_2 == 5'h5; // @[package.scala:39:86] wire _io_ill_T_12 = ~_io_ill_T_11 & _io_ill_T_10; // @[package.scala:39:{76,86}] wire _io_ill_T_13 = _io_ill_T_2 == 5'h6; // @[package.scala:39:86] wire _io_ill_T_14 = ~_io_ill_T_13 & _io_ill_T_12; // @[package.scala:39:{76,86}] wire _io_ill_T_15 = _io_ill_T_2 == 5'h7; // @[package.scala:39:86] wire _io_ill_T_16 = ~_io_ill_T_15 & _io_ill_T_14; // @[package.scala:39:{76,86}] wire _io_ill_T_17 = _io_ill_T_2 == 5'h8; // @[package.scala:39:86] wire _io_ill_T_18 = ~_io_ill_T_17 & _io_ill_T_16; // @[package.scala:39:{76,86}] wire _io_ill_T_19 = _io_ill_T_2 == 5'h9; // @[package.scala:39:86] wire _io_ill_T_20 = _io_ill_T_19 ? io_ill_s_9 : _io_ill_T_18; // @[package.scala:39:{76,86}] wire _io_ill_T_21 = _io_ill_T_2 == 5'hA; // @[package.scala:39:86] wire _io_ill_T_22 = ~_io_ill_T_21 & _io_ill_T_20; // @[package.scala:39:{76,86}] wire _io_ill_T_23 = _io_ill_T_2 == 5'hB; // @[package.scala:39:86] wire _io_ill_T_24 = _io_ill_T_23 ? io_ill_s_11 : _io_ill_T_22; // @[package.scala:39:{76,86}] wire _io_ill_T_25 = _io_ill_T_2 == 5'hC; // @[package.scala:39:86] wire _io_ill_T_26 = _io_ill_T_25 ? io_ill_s_12 : _io_ill_T_24; // @[package.scala:39:{76,86}] wire _io_ill_T_27 = _io_ill_T_2 == 5'hD; // @[package.scala:39:86] wire _io_ill_T_28 = ~_io_ill_T_27 & _io_ill_T_26; // @[package.scala:39:{76,86}] wire _io_ill_T_29 = _io_ill_T_2 == 5'hE; // @[package.scala:39:86] wire _io_ill_T_30 = ~_io_ill_T_29 & _io_ill_T_28; // @[package.scala:39:{76,86}] wire _io_ill_T_31 = _io_ill_T_2 == 5'hF; // @[package.scala:39:86] wire _io_ill_T_32 = ~_io_ill_T_31 & _io_ill_T_30; // @[package.scala:39:{76,86}] wire _io_ill_T_33 = _io_ill_T_2 == 5'h10; // @[package.scala:39:86] wire _io_ill_T_34 = ~_io_ill_T_33 & _io_ill_T_32; // @[package.scala:39:{76,86}] wire _io_ill_T_35 = _io_ill_T_2 == 5'h11; // @[package.scala:39:86] wire _io_ill_T_36 = ~_io_ill_T_35 & _io_ill_T_34; // @[package.scala:39:{76,86}] wire _io_ill_T_37 = _io_ill_T_2 == 5'h12; // @[package.scala:39:86] wire _io_ill_T_38 = _io_ill_T_37 ? io_ill_s_18 : _io_ill_T_36; // @[package.scala:39:{76,86}] wire _io_ill_T_39 = _io_ill_T_2 == 5'h13; // @[package.scala:39:86] wire _io_ill_T_40 = _io_ill_T_39 ? io_ill_s_19 : _io_ill_T_38; // @[package.scala:39:{76,86}] wire _io_ill_T_41 = _io_ill_T_2 == 5'h14; // @[package.scala:39:86] wire _io_ill_T_42 = _io_ill_T_41 ? io_ill_s_20 : _io_ill_T_40; // @[package.scala:39:{76,86}] wire _io_ill_T_43 = _io_ill_T_2 == 5'h15; // @[package.scala:39:86] wire _io_ill_T_44 = ~_io_ill_T_43 & _io_ill_T_42; // @[package.scala:39:{76,86}] wire _io_ill_T_45 = _io_ill_T_2 == 5'h16; // @[package.scala:39:86] wire _io_ill_T_46 = ~_io_ill_T_45 & _io_ill_T_44; // @[package.scala:39:{76,86}] wire _io_ill_T_47 = _io_ill_T_2 == 5'h17; // @[package.scala:39:86] wire _io_ill_T_48 = ~_io_ill_T_47 & _io_ill_T_46; // @[package.scala:39:{76,86}] wire _io_ill_T_49 = _io_ill_T_2 == 5'h18; // @[package.scala:39:86] wire _io_ill_T_50 = ~_io_ill_T_49 & _io_ill_T_48; // @[package.scala:39:{76,86}] wire _io_ill_T_51 = _io_ill_T_2 == 5'h19; // @[package.scala:39:86] wire _io_ill_T_52 = ~_io_ill_T_51 & _io_ill_T_50; // @[package.scala:39:{76,86}] wire _io_ill_T_53 = _io_ill_T_2 == 5'h1A; // @[package.scala:39:86] wire _io_ill_T_54 = ~_io_ill_T_53 & _io_ill_T_52; // @[package.scala:39:{76,86}] wire _io_ill_T_55 = _io_ill_T_2 == 5'h1B; // @[package.scala:39:86] wire _io_ill_T_56 = ~_io_ill_T_55 & _io_ill_T_54; // @[package.scala:39:{76,86}] wire _io_ill_T_57 = _io_ill_T_2 == 5'h1C; // @[package.scala:39:86] wire _io_ill_T_58 = ~_io_ill_T_57 & _io_ill_T_56; // @[package.scala:39:{76,86}] wire _io_ill_T_59 = _io_ill_T_2 == 5'h1D; // @[package.scala:39:86] wire _io_ill_T_60 = ~_io_ill_T_59 & _io_ill_T_58; // @[package.scala:39:{76,86}] wire _io_ill_T_61 = _io_ill_T_2 == 5'h1E; // @[package.scala:39:86] wire _io_ill_T_62 = ~_io_ill_T_61 & _io_ill_T_60; // @[package.scala:39:{76,86}] wire _io_ill_T_63 = &_io_ill_T_2; // @[package.scala:39:86] assign _io_ill_T_64 = ~_io_ill_T_63 & _io_ill_T_62; // @[package.scala:39:{76,86}] assign io_ill = _io_ill_T_64; // @[package.scala:39:76] assign io_out_bits = io_out_bits_0; // @[RVC.scala:190:7] assign io_rvc = io_rvc_0; // @[RVC.scala:190:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a26d64s9k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_7 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a26d64s9k1z2u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a26d64s9k1z2u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<9>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<9>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<9>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<9>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_16 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_17 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBuffer_a26d64s9k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_7 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s9k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s9k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulDiv_7 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { fn : UInt<5>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, full_data : UInt<128>, tag : UInt<5>}}} regreset state : UInt<3>, clock, reset, UInt<3>(0h0) reg req : { fn : UInt<5>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock reg count : UInt<7>, clock reg neg_out : UInt<1>, clock reg isHi : UInt<1>, clock reg resHi : UInt<1>, clock reg divisor : UInt<65>, clock reg remainder : UInt<130>, clock wire decoded_plaInput : UInt<3> node decoded_invInputs = not(decoded_plaInput) wire decoded : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_3_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_4_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 2, 2) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 2, 2) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_1_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_plaInput, 2, 2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_4_2) node decoded_orMatrixOutputs_lo = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded, decoded_invMatrixOutputs connect decoded_plaInput, io.req.bits.fn node _T = bits(decoded, 3, 3) node _T_1 = bits(decoded, 2, 2) node _T_2 = bits(decoded, 1, 1) node _T_3 = bits(decoded, 0, 0) node cmdMul = bits(_T, 0, 0) node cmdHi = bits(_T_1, 0, 0) node lhsSigned = bits(_T_2, 0, 0) node rhsSigned = bits(_T_3, 0, 0) node _T_4 = eq(io.req.bits.dw, UInt<1>(0h0)) node _T_5 = and(UInt<1>(0h1), _T_4) node _sign_T = bits(io.req.bits.in1, 31, 31) node _sign_T_1 = bits(io.req.bits.in1, 63, 63) node _sign_T_2 = mux(_T_5, _sign_T, _sign_T_1) node lhs_sign = and(lhsSigned, _sign_T_2) node _hi_T = mux(lhs_sign, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hi_T_1 = bits(io.req.bits.in1, 63, 32) node hi = mux(_T_5, _hi_T, _hi_T_1) node _T_6 = bits(io.req.bits.in1, 31, 0) node lhs_in = cat(hi, _T_6) node _T_7 = eq(io.req.bits.dw, UInt<1>(0h0)) node _T_8 = and(UInt<1>(0h1), _T_7) node _sign_T_3 = bits(io.req.bits.in2, 31, 31) node _sign_T_4 = bits(io.req.bits.in2, 63, 63) node _sign_T_5 = mux(_T_8, _sign_T_3, _sign_T_4) node rhs_sign = and(rhsSigned, _sign_T_5) node _hi_T_2 = mux(rhs_sign, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hi_T_3 = bits(io.req.bits.in2, 63, 32) node hi_1 = mux(_T_8, _hi_T_2, _hi_T_3) node _T_9 = bits(io.req.bits.in2, 31, 0) node rhs_in = cat(hi_1, _T_9) node _subtractor_T = bits(remainder, 128, 64) node _subtractor_T_1 = sub(_subtractor_T, divisor) node subtractor = tail(_subtractor_T_1, 1) node _result_T = bits(remainder, 128, 65) node _result_T_1 = bits(remainder, 63, 0) node result = mux(resHi, _result_T, _result_T_1) node _negated_remainder_T = sub(UInt<1>(0h0), result) node negated_remainder = tail(_negated_remainder_T, 1) node _T_10 = eq(state, UInt<3>(0h1)) when _T_10 : node _T_11 = bits(remainder, 63, 63) when _T_11 : connect remainder, negated_remainder node _T_12 = bits(divisor, 63, 63) when _T_12 : connect divisor, subtractor connect state, UInt<3>(0h3) node _T_13 = eq(state, UInt<3>(0h5)) when _T_13 : connect remainder, negated_remainder connect state, UInt<3>(0h7) connect resHi, UInt<1>(0h0) node _T_14 = eq(state, UInt<3>(0h2)) when _T_14 : node _mulReg_T = bits(remainder, 129, 65) node _mulReg_T_1 = bits(remainder, 63, 0) node mulReg = cat(_mulReg_T, _mulReg_T_1) node mplierSign = bits(remainder, 64, 64) node mplier = bits(mulReg, 63, 0) node _accum_T = bits(mulReg, 128, 64) node accum = asSInt(_accum_T) node mpcand = asSInt(divisor) node _prod_T = bits(mplier, 7, 0) node _prod_T_1 = cat(mplierSign, _prod_T) node _prod_T_2 = asSInt(_prod_T_1) node _prod_T_3 = mul(_prod_T_2, mpcand) node _prod_T_4 = add(_prod_T_3, accum) node _prod_T_5 = tail(_prod_T_4, 1) node prod = asSInt(_prod_T_5) node _nextMulReg_T = bits(mplier, 63, 8) node nextMulReg_hi = asUInt(prod) node nextMulReg = cat(nextMulReg_hi, _nextMulReg_T) node _nextMplierSign_T = eq(count, UInt<3>(0h6)) node nextMplierSign = and(_nextMplierSign_T, neg_out) node _eOutMask_T = mul(count, UInt<4>(0h8)) node _eOutMask_T_1 = bits(_eOutMask_T, 5, 0) node _eOutMask_T_2 = dshr(asSInt(UInt<65>(0h10000000000000000)), _eOutMask_T_1) node eOutMask = bits(_eOutMask_T_2, 63, 0) node _eOut_T = neq(count, UInt<3>(0h7)) node _eOut_T_1 = and(UInt<1>(0h1), _eOut_T) node _eOut_T_2 = neq(count, UInt<1>(0h0)) node _eOut_T_3 = and(_eOut_T_1, _eOut_T_2) node _eOut_T_4 = eq(isHi, UInt<1>(0h0)) node _eOut_T_5 = and(_eOut_T_3, _eOut_T_4) node _eOut_T_6 = not(eOutMask) node _eOut_T_7 = and(mplier, _eOut_T_6) node _eOut_T_8 = eq(_eOut_T_7, UInt<1>(0h0)) node eOut = and(_eOut_T_5, _eOut_T_8) node _eOutRes_T = mul(count, UInt<4>(0h8)) node _eOutRes_T_1 = sub(UInt<7>(0h40), _eOutRes_T) node _eOutRes_T_2 = tail(_eOutRes_T_1, 1) node _eOutRes_T_3 = bits(_eOutRes_T_2, 5, 0) node eOutRes = dshr(mulReg, _eOutRes_T_3) node _nextMulReg1_T = bits(nextMulReg, 128, 64) node _nextMulReg1_T_1 = mux(eOut, eOutRes, nextMulReg) node _nextMulReg1_T_2 = bits(_nextMulReg1_T_1, 63, 0) node nextMulReg1 = cat(_nextMulReg1_T, _nextMulReg1_T_2) node _remainder_T = shr(nextMulReg1, 64) node _remainder_T_1 = bits(nextMulReg1, 63, 0) node remainder_hi = cat(_remainder_T, nextMplierSign) node _remainder_T_2 = cat(remainder_hi, _remainder_T_1) connect remainder, _remainder_T_2 node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 node _T_15 = eq(count, UInt<3>(0h7)) node _T_16 = or(eOut, _T_15) when _T_16 : connect state, UInt<3>(0h6) connect resHi, isHi node _T_17 = eq(state, UInt<3>(0h3)) when _T_17 : node unrolls_less = bits(subtractor, 64, 64) node _unrolls_T = bits(remainder, 127, 64) node _unrolls_T_1 = bits(subtractor, 63, 0) node _unrolls_T_2 = mux(unrolls_less, _unrolls_T, _unrolls_T_1) node _unrolls_T_3 = bits(remainder, 63, 0) node _unrolls_T_4 = eq(unrolls_less, UInt<1>(0h0)) node unrolls_hi = cat(_unrolls_T_2, _unrolls_T_3) node unrolls_0 = cat(unrolls_hi, _unrolls_T_4) connect remainder, unrolls_0 node _T_18 = eq(count, UInt<7>(0h40)) when _T_18 : node _state_T = mux(neg_out, UInt<3>(0h5), UInt<3>(0h7)) connect state, _state_T connect resHi, isHi node _count_T_2 = add(count, UInt<1>(0h1)) node _count_T_3 = tail(_count_T_2, 1) connect count, _count_T_3 node _divby0_T = eq(count, UInt<1>(0h0)) node _divby0_T_1 = bits(subtractor, 64, 64) node _divby0_T_2 = eq(_divby0_T_1, UInt<1>(0h0)) node divby0 = and(_divby0_T, _divby0_T_2) node alignMask = not(UInt<6>(0h0)) node _divisorMSB_T = bits(divisor, 63, 0) node divisorMSB_hi = bits(_divisorMSB_T, 63, 32) node divisorMSB_lo = bits(_divisorMSB_T, 31, 0) node divisorMSB_useHi = orr(divisorMSB_hi) node divisorMSB_hi_1 = bits(divisorMSB_hi, 31, 16) node divisorMSB_lo_1 = bits(divisorMSB_hi, 15, 0) node divisorMSB_useHi_1 = orr(divisorMSB_hi_1) node divisorMSB_hi_2 = bits(divisorMSB_hi_1, 15, 8) node divisorMSB_lo_2 = bits(divisorMSB_hi_1, 7, 0) node divisorMSB_useHi_2 = orr(divisorMSB_hi_2) node divisorMSB_hi_3 = bits(divisorMSB_hi_2, 7, 4) node divisorMSB_lo_3 = bits(divisorMSB_hi_2, 3, 0) node divisorMSB_useHi_3 = orr(divisorMSB_hi_3) node _divisorMSB_T_1 = bits(divisorMSB_hi_3, 3, 3) node _divisorMSB_T_2 = bits(divisorMSB_hi_3, 2, 2) node _divisorMSB_T_3 = bits(divisorMSB_hi_3, 1, 1) node _divisorMSB_T_4 = mux(_divisorMSB_T_2, UInt<2>(0h2), _divisorMSB_T_3) node _divisorMSB_T_5 = mux(_divisorMSB_T_1, UInt<2>(0h3), _divisorMSB_T_4) node _divisorMSB_T_6 = bits(divisorMSB_lo_3, 3, 3) node _divisorMSB_T_7 = bits(divisorMSB_lo_3, 2, 2) node _divisorMSB_T_8 = bits(divisorMSB_lo_3, 1, 1) node _divisorMSB_T_9 = mux(_divisorMSB_T_7, UInt<2>(0h2), _divisorMSB_T_8) node _divisorMSB_T_10 = mux(_divisorMSB_T_6, UInt<2>(0h3), _divisorMSB_T_9) node _divisorMSB_T_11 = mux(divisorMSB_useHi_3, _divisorMSB_T_5, _divisorMSB_T_10) node _divisorMSB_T_12 = cat(divisorMSB_useHi_3, _divisorMSB_T_11) node divisorMSB_hi_4 = bits(divisorMSB_lo_2, 7, 4) node divisorMSB_lo_4 = bits(divisorMSB_lo_2, 3, 0) node divisorMSB_useHi_4 = orr(divisorMSB_hi_4) node _divisorMSB_T_13 = bits(divisorMSB_hi_4, 3, 3) node _divisorMSB_T_14 = bits(divisorMSB_hi_4, 2, 2) node _divisorMSB_T_15 = bits(divisorMSB_hi_4, 1, 1) node _divisorMSB_T_16 = mux(_divisorMSB_T_14, UInt<2>(0h2), _divisorMSB_T_15) node _divisorMSB_T_17 = mux(_divisorMSB_T_13, UInt<2>(0h3), _divisorMSB_T_16) node _divisorMSB_T_18 = bits(divisorMSB_lo_4, 3, 3) node _divisorMSB_T_19 = bits(divisorMSB_lo_4, 2, 2) node _divisorMSB_T_20 = bits(divisorMSB_lo_4, 1, 1) node _divisorMSB_T_21 = mux(_divisorMSB_T_19, UInt<2>(0h2), _divisorMSB_T_20) node _divisorMSB_T_22 = mux(_divisorMSB_T_18, UInt<2>(0h3), _divisorMSB_T_21) node _divisorMSB_T_23 = mux(divisorMSB_useHi_4, _divisorMSB_T_17, _divisorMSB_T_22) node _divisorMSB_T_24 = cat(divisorMSB_useHi_4, _divisorMSB_T_23) node _divisorMSB_T_25 = mux(divisorMSB_useHi_2, _divisorMSB_T_12, _divisorMSB_T_24) node _divisorMSB_T_26 = cat(divisorMSB_useHi_2, _divisorMSB_T_25) node divisorMSB_hi_5 = bits(divisorMSB_lo_1, 15, 8) node divisorMSB_lo_5 = bits(divisorMSB_lo_1, 7, 0) node divisorMSB_useHi_5 = orr(divisorMSB_hi_5) node divisorMSB_hi_6 = bits(divisorMSB_hi_5, 7, 4) node divisorMSB_lo_6 = bits(divisorMSB_hi_5, 3, 0) node divisorMSB_useHi_6 = orr(divisorMSB_hi_6) node _divisorMSB_T_27 = bits(divisorMSB_hi_6, 3, 3) node _divisorMSB_T_28 = bits(divisorMSB_hi_6, 2, 2) node _divisorMSB_T_29 = bits(divisorMSB_hi_6, 1, 1) node _divisorMSB_T_30 = mux(_divisorMSB_T_28, UInt<2>(0h2), _divisorMSB_T_29) node _divisorMSB_T_31 = mux(_divisorMSB_T_27, UInt<2>(0h3), _divisorMSB_T_30) node _divisorMSB_T_32 = bits(divisorMSB_lo_6, 3, 3) node _divisorMSB_T_33 = bits(divisorMSB_lo_6, 2, 2) node _divisorMSB_T_34 = bits(divisorMSB_lo_6, 1, 1) node _divisorMSB_T_35 = mux(_divisorMSB_T_33, UInt<2>(0h2), _divisorMSB_T_34) node _divisorMSB_T_36 = mux(_divisorMSB_T_32, UInt<2>(0h3), _divisorMSB_T_35) node _divisorMSB_T_37 = mux(divisorMSB_useHi_6, _divisorMSB_T_31, _divisorMSB_T_36) node _divisorMSB_T_38 = cat(divisorMSB_useHi_6, _divisorMSB_T_37) node divisorMSB_hi_7 = bits(divisorMSB_lo_5, 7, 4) node divisorMSB_lo_7 = bits(divisorMSB_lo_5, 3, 0) node divisorMSB_useHi_7 = orr(divisorMSB_hi_7) node _divisorMSB_T_39 = bits(divisorMSB_hi_7, 3, 3) node _divisorMSB_T_40 = bits(divisorMSB_hi_7, 2, 2) node _divisorMSB_T_41 = bits(divisorMSB_hi_7, 1, 1) node _divisorMSB_T_42 = mux(_divisorMSB_T_40, UInt<2>(0h2), _divisorMSB_T_41) node _divisorMSB_T_43 = mux(_divisorMSB_T_39, UInt<2>(0h3), _divisorMSB_T_42) node _divisorMSB_T_44 = bits(divisorMSB_lo_7, 3, 3) node _divisorMSB_T_45 = bits(divisorMSB_lo_7, 2, 2) node _divisorMSB_T_46 = bits(divisorMSB_lo_7, 1, 1) node _divisorMSB_T_47 = mux(_divisorMSB_T_45, UInt<2>(0h2), _divisorMSB_T_46) node _divisorMSB_T_48 = mux(_divisorMSB_T_44, UInt<2>(0h3), _divisorMSB_T_47) node _divisorMSB_T_49 = mux(divisorMSB_useHi_7, _divisorMSB_T_43, _divisorMSB_T_48) node _divisorMSB_T_50 = cat(divisorMSB_useHi_7, _divisorMSB_T_49) node _divisorMSB_T_51 = mux(divisorMSB_useHi_5, _divisorMSB_T_38, _divisorMSB_T_50) node _divisorMSB_T_52 = cat(divisorMSB_useHi_5, _divisorMSB_T_51) node _divisorMSB_T_53 = mux(divisorMSB_useHi_1, _divisorMSB_T_26, _divisorMSB_T_52) node _divisorMSB_T_54 = cat(divisorMSB_useHi_1, _divisorMSB_T_53) node divisorMSB_hi_8 = bits(divisorMSB_lo, 31, 16) node divisorMSB_lo_8 = bits(divisorMSB_lo, 15, 0) node divisorMSB_useHi_8 = orr(divisorMSB_hi_8) node divisorMSB_hi_9 = bits(divisorMSB_hi_8, 15, 8) node divisorMSB_lo_9 = bits(divisorMSB_hi_8, 7, 0) node divisorMSB_useHi_9 = orr(divisorMSB_hi_9) node divisorMSB_hi_10 = bits(divisorMSB_hi_9, 7, 4) node divisorMSB_lo_10 = bits(divisorMSB_hi_9, 3, 0) node divisorMSB_useHi_10 = orr(divisorMSB_hi_10) node _divisorMSB_T_55 = bits(divisorMSB_hi_10, 3, 3) node _divisorMSB_T_56 = bits(divisorMSB_hi_10, 2, 2) node _divisorMSB_T_57 = bits(divisorMSB_hi_10, 1, 1) node _divisorMSB_T_58 = mux(_divisorMSB_T_56, UInt<2>(0h2), _divisorMSB_T_57) node _divisorMSB_T_59 = mux(_divisorMSB_T_55, UInt<2>(0h3), _divisorMSB_T_58) node _divisorMSB_T_60 = bits(divisorMSB_lo_10, 3, 3) node _divisorMSB_T_61 = bits(divisorMSB_lo_10, 2, 2) node _divisorMSB_T_62 = bits(divisorMSB_lo_10, 1, 1) node _divisorMSB_T_63 = mux(_divisorMSB_T_61, UInt<2>(0h2), _divisorMSB_T_62) node _divisorMSB_T_64 = mux(_divisorMSB_T_60, UInt<2>(0h3), _divisorMSB_T_63) node _divisorMSB_T_65 = mux(divisorMSB_useHi_10, _divisorMSB_T_59, _divisorMSB_T_64) node _divisorMSB_T_66 = cat(divisorMSB_useHi_10, _divisorMSB_T_65) node divisorMSB_hi_11 = bits(divisorMSB_lo_9, 7, 4) node divisorMSB_lo_11 = bits(divisorMSB_lo_9, 3, 0) node divisorMSB_useHi_11 = orr(divisorMSB_hi_11) node _divisorMSB_T_67 = bits(divisorMSB_hi_11, 3, 3) node _divisorMSB_T_68 = bits(divisorMSB_hi_11, 2, 2) node _divisorMSB_T_69 = bits(divisorMSB_hi_11, 1, 1) node _divisorMSB_T_70 = mux(_divisorMSB_T_68, UInt<2>(0h2), _divisorMSB_T_69) node _divisorMSB_T_71 = mux(_divisorMSB_T_67, UInt<2>(0h3), _divisorMSB_T_70) node _divisorMSB_T_72 = bits(divisorMSB_lo_11, 3, 3) node _divisorMSB_T_73 = bits(divisorMSB_lo_11, 2, 2) node _divisorMSB_T_74 = bits(divisorMSB_lo_11, 1, 1) node _divisorMSB_T_75 = mux(_divisorMSB_T_73, UInt<2>(0h2), _divisorMSB_T_74) node _divisorMSB_T_76 = mux(_divisorMSB_T_72, UInt<2>(0h3), _divisorMSB_T_75) node _divisorMSB_T_77 = mux(divisorMSB_useHi_11, _divisorMSB_T_71, _divisorMSB_T_76) node _divisorMSB_T_78 = cat(divisorMSB_useHi_11, _divisorMSB_T_77) node _divisorMSB_T_79 = mux(divisorMSB_useHi_9, _divisorMSB_T_66, _divisorMSB_T_78) node _divisorMSB_T_80 = cat(divisorMSB_useHi_9, _divisorMSB_T_79) node divisorMSB_hi_12 = bits(divisorMSB_lo_8, 15, 8) node divisorMSB_lo_12 = bits(divisorMSB_lo_8, 7, 0) node divisorMSB_useHi_12 = orr(divisorMSB_hi_12) node divisorMSB_hi_13 = bits(divisorMSB_hi_12, 7, 4) node divisorMSB_lo_13 = bits(divisorMSB_hi_12, 3, 0) node divisorMSB_useHi_13 = orr(divisorMSB_hi_13) node _divisorMSB_T_81 = bits(divisorMSB_hi_13, 3, 3) node _divisorMSB_T_82 = bits(divisorMSB_hi_13, 2, 2) node _divisorMSB_T_83 = bits(divisorMSB_hi_13, 1, 1) node _divisorMSB_T_84 = mux(_divisorMSB_T_82, UInt<2>(0h2), _divisorMSB_T_83) node _divisorMSB_T_85 = mux(_divisorMSB_T_81, UInt<2>(0h3), _divisorMSB_T_84) node _divisorMSB_T_86 = bits(divisorMSB_lo_13, 3, 3) node _divisorMSB_T_87 = bits(divisorMSB_lo_13, 2, 2) node _divisorMSB_T_88 = bits(divisorMSB_lo_13, 1, 1) node _divisorMSB_T_89 = mux(_divisorMSB_T_87, UInt<2>(0h2), _divisorMSB_T_88) node _divisorMSB_T_90 = mux(_divisorMSB_T_86, UInt<2>(0h3), _divisorMSB_T_89) node _divisorMSB_T_91 = mux(divisorMSB_useHi_13, _divisorMSB_T_85, _divisorMSB_T_90) node _divisorMSB_T_92 = cat(divisorMSB_useHi_13, _divisorMSB_T_91) node divisorMSB_hi_14 = bits(divisorMSB_lo_12, 7, 4) node divisorMSB_lo_14 = bits(divisorMSB_lo_12, 3, 0) node divisorMSB_useHi_14 = orr(divisorMSB_hi_14) node _divisorMSB_T_93 = bits(divisorMSB_hi_14, 3, 3) node _divisorMSB_T_94 = bits(divisorMSB_hi_14, 2, 2) node _divisorMSB_T_95 = bits(divisorMSB_hi_14, 1, 1) node _divisorMSB_T_96 = mux(_divisorMSB_T_94, UInt<2>(0h2), _divisorMSB_T_95) node _divisorMSB_T_97 = mux(_divisorMSB_T_93, UInt<2>(0h3), _divisorMSB_T_96) node _divisorMSB_T_98 = bits(divisorMSB_lo_14, 3, 3) node _divisorMSB_T_99 = bits(divisorMSB_lo_14, 2, 2) node _divisorMSB_T_100 = bits(divisorMSB_lo_14, 1, 1) node _divisorMSB_T_101 = mux(_divisorMSB_T_99, UInt<2>(0h2), _divisorMSB_T_100) node _divisorMSB_T_102 = mux(_divisorMSB_T_98, UInt<2>(0h3), _divisorMSB_T_101) node _divisorMSB_T_103 = mux(divisorMSB_useHi_14, _divisorMSB_T_97, _divisorMSB_T_102) node _divisorMSB_T_104 = cat(divisorMSB_useHi_14, _divisorMSB_T_103) node _divisorMSB_T_105 = mux(divisorMSB_useHi_12, _divisorMSB_T_92, _divisorMSB_T_104) node _divisorMSB_T_106 = cat(divisorMSB_useHi_12, _divisorMSB_T_105) node _divisorMSB_T_107 = mux(divisorMSB_useHi_8, _divisorMSB_T_80, _divisorMSB_T_106) node _divisorMSB_T_108 = cat(divisorMSB_useHi_8, _divisorMSB_T_107) node _divisorMSB_T_109 = mux(divisorMSB_useHi, _divisorMSB_T_54, _divisorMSB_T_108) node _divisorMSB_T_110 = cat(divisorMSB_useHi, _divisorMSB_T_109) node divisorMSB = and(_divisorMSB_T_110, alignMask) node _dividendMSB_T = bits(remainder, 63, 0) node dividendMSB_hi = bits(_dividendMSB_T, 63, 32) node dividendMSB_lo = bits(_dividendMSB_T, 31, 0) node dividendMSB_useHi = orr(dividendMSB_hi) node dividendMSB_hi_1 = bits(dividendMSB_hi, 31, 16) node dividendMSB_lo_1 = bits(dividendMSB_hi, 15, 0) node dividendMSB_useHi_1 = orr(dividendMSB_hi_1) node dividendMSB_hi_2 = bits(dividendMSB_hi_1, 15, 8) node dividendMSB_lo_2 = bits(dividendMSB_hi_1, 7, 0) node dividendMSB_useHi_2 = orr(dividendMSB_hi_2) node dividendMSB_hi_3 = bits(dividendMSB_hi_2, 7, 4) node dividendMSB_lo_3 = bits(dividendMSB_hi_2, 3, 0) node dividendMSB_useHi_3 = orr(dividendMSB_hi_3) node _dividendMSB_T_1 = bits(dividendMSB_hi_3, 3, 3) node _dividendMSB_T_2 = bits(dividendMSB_hi_3, 2, 2) node _dividendMSB_T_3 = bits(dividendMSB_hi_3, 1, 1) node _dividendMSB_T_4 = mux(_dividendMSB_T_2, UInt<2>(0h2), _dividendMSB_T_3) node _dividendMSB_T_5 = mux(_dividendMSB_T_1, UInt<2>(0h3), _dividendMSB_T_4) node _dividendMSB_T_6 = bits(dividendMSB_lo_3, 3, 3) node _dividendMSB_T_7 = bits(dividendMSB_lo_3, 2, 2) node _dividendMSB_T_8 = bits(dividendMSB_lo_3, 1, 1) node _dividendMSB_T_9 = mux(_dividendMSB_T_7, UInt<2>(0h2), _dividendMSB_T_8) node _dividendMSB_T_10 = mux(_dividendMSB_T_6, UInt<2>(0h3), _dividendMSB_T_9) node _dividendMSB_T_11 = mux(dividendMSB_useHi_3, _dividendMSB_T_5, _dividendMSB_T_10) node _dividendMSB_T_12 = cat(dividendMSB_useHi_3, _dividendMSB_T_11) node dividendMSB_hi_4 = bits(dividendMSB_lo_2, 7, 4) node dividendMSB_lo_4 = bits(dividendMSB_lo_2, 3, 0) node dividendMSB_useHi_4 = orr(dividendMSB_hi_4) node _dividendMSB_T_13 = bits(dividendMSB_hi_4, 3, 3) node _dividendMSB_T_14 = bits(dividendMSB_hi_4, 2, 2) node _dividendMSB_T_15 = bits(dividendMSB_hi_4, 1, 1) node _dividendMSB_T_16 = mux(_dividendMSB_T_14, UInt<2>(0h2), _dividendMSB_T_15) node _dividendMSB_T_17 = mux(_dividendMSB_T_13, UInt<2>(0h3), _dividendMSB_T_16) node _dividendMSB_T_18 = bits(dividendMSB_lo_4, 3, 3) node _dividendMSB_T_19 = bits(dividendMSB_lo_4, 2, 2) node _dividendMSB_T_20 = bits(dividendMSB_lo_4, 1, 1) node _dividendMSB_T_21 = mux(_dividendMSB_T_19, UInt<2>(0h2), _dividendMSB_T_20) node _dividendMSB_T_22 = mux(_dividendMSB_T_18, UInt<2>(0h3), _dividendMSB_T_21) node _dividendMSB_T_23 = mux(dividendMSB_useHi_4, _dividendMSB_T_17, _dividendMSB_T_22) node _dividendMSB_T_24 = cat(dividendMSB_useHi_4, _dividendMSB_T_23) node _dividendMSB_T_25 = mux(dividendMSB_useHi_2, _dividendMSB_T_12, _dividendMSB_T_24) node _dividendMSB_T_26 = cat(dividendMSB_useHi_2, _dividendMSB_T_25) node dividendMSB_hi_5 = bits(dividendMSB_lo_1, 15, 8) node dividendMSB_lo_5 = bits(dividendMSB_lo_1, 7, 0) node dividendMSB_useHi_5 = orr(dividendMSB_hi_5) node dividendMSB_hi_6 = bits(dividendMSB_hi_5, 7, 4) node dividendMSB_lo_6 = bits(dividendMSB_hi_5, 3, 0) node dividendMSB_useHi_6 = orr(dividendMSB_hi_6) node _dividendMSB_T_27 = bits(dividendMSB_hi_6, 3, 3) node _dividendMSB_T_28 = bits(dividendMSB_hi_6, 2, 2) node _dividendMSB_T_29 = bits(dividendMSB_hi_6, 1, 1) node _dividendMSB_T_30 = mux(_dividendMSB_T_28, UInt<2>(0h2), _dividendMSB_T_29) node _dividendMSB_T_31 = mux(_dividendMSB_T_27, UInt<2>(0h3), _dividendMSB_T_30) node _dividendMSB_T_32 = bits(dividendMSB_lo_6, 3, 3) node _dividendMSB_T_33 = bits(dividendMSB_lo_6, 2, 2) node _dividendMSB_T_34 = bits(dividendMSB_lo_6, 1, 1) node _dividendMSB_T_35 = mux(_dividendMSB_T_33, UInt<2>(0h2), _dividendMSB_T_34) node _dividendMSB_T_36 = mux(_dividendMSB_T_32, UInt<2>(0h3), _dividendMSB_T_35) node _dividendMSB_T_37 = mux(dividendMSB_useHi_6, _dividendMSB_T_31, _dividendMSB_T_36) node _dividendMSB_T_38 = cat(dividendMSB_useHi_6, _dividendMSB_T_37) node dividendMSB_hi_7 = bits(dividendMSB_lo_5, 7, 4) node dividendMSB_lo_7 = bits(dividendMSB_lo_5, 3, 0) node dividendMSB_useHi_7 = orr(dividendMSB_hi_7) node _dividendMSB_T_39 = bits(dividendMSB_hi_7, 3, 3) node _dividendMSB_T_40 = bits(dividendMSB_hi_7, 2, 2) node _dividendMSB_T_41 = bits(dividendMSB_hi_7, 1, 1) node _dividendMSB_T_42 = mux(_dividendMSB_T_40, UInt<2>(0h2), _dividendMSB_T_41) node _dividendMSB_T_43 = mux(_dividendMSB_T_39, UInt<2>(0h3), _dividendMSB_T_42) node _dividendMSB_T_44 = bits(dividendMSB_lo_7, 3, 3) node _dividendMSB_T_45 = bits(dividendMSB_lo_7, 2, 2) node _dividendMSB_T_46 = bits(dividendMSB_lo_7, 1, 1) node _dividendMSB_T_47 = mux(_dividendMSB_T_45, UInt<2>(0h2), _dividendMSB_T_46) node _dividendMSB_T_48 = mux(_dividendMSB_T_44, UInt<2>(0h3), _dividendMSB_T_47) node _dividendMSB_T_49 = mux(dividendMSB_useHi_7, _dividendMSB_T_43, _dividendMSB_T_48) node _dividendMSB_T_50 = cat(dividendMSB_useHi_7, _dividendMSB_T_49) node _dividendMSB_T_51 = mux(dividendMSB_useHi_5, _dividendMSB_T_38, _dividendMSB_T_50) node _dividendMSB_T_52 = cat(dividendMSB_useHi_5, _dividendMSB_T_51) node _dividendMSB_T_53 = mux(dividendMSB_useHi_1, _dividendMSB_T_26, _dividendMSB_T_52) node _dividendMSB_T_54 = cat(dividendMSB_useHi_1, _dividendMSB_T_53) node dividendMSB_hi_8 = bits(dividendMSB_lo, 31, 16) node dividendMSB_lo_8 = bits(dividendMSB_lo, 15, 0) node dividendMSB_useHi_8 = orr(dividendMSB_hi_8) node dividendMSB_hi_9 = bits(dividendMSB_hi_8, 15, 8) node dividendMSB_lo_9 = bits(dividendMSB_hi_8, 7, 0) node dividendMSB_useHi_9 = orr(dividendMSB_hi_9) node dividendMSB_hi_10 = bits(dividendMSB_hi_9, 7, 4) node dividendMSB_lo_10 = bits(dividendMSB_hi_9, 3, 0) node dividendMSB_useHi_10 = orr(dividendMSB_hi_10) node _dividendMSB_T_55 = bits(dividendMSB_hi_10, 3, 3) node _dividendMSB_T_56 = bits(dividendMSB_hi_10, 2, 2) node _dividendMSB_T_57 = bits(dividendMSB_hi_10, 1, 1) node _dividendMSB_T_58 = mux(_dividendMSB_T_56, UInt<2>(0h2), _dividendMSB_T_57) node _dividendMSB_T_59 = mux(_dividendMSB_T_55, UInt<2>(0h3), _dividendMSB_T_58) node _dividendMSB_T_60 = bits(dividendMSB_lo_10, 3, 3) node _dividendMSB_T_61 = bits(dividendMSB_lo_10, 2, 2) node _dividendMSB_T_62 = bits(dividendMSB_lo_10, 1, 1) node _dividendMSB_T_63 = mux(_dividendMSB_T_61, UInt<2>(0h2), _dividendMSB_T_62) node _dividendMSB_T_64 = mux(_dividendMSB_T_60, UInt<2>(0h3), _dividendMSB_T_63) node _dividendMSB_T_65 = mux(dividendMSB_useHi_10, _dividendMSB_T_59, _dividendMSB_T_64) node _dividendMSB_T_66 = cat(dividendMSB_useHi_10, _dividendMSB_T_65) node dividendMSB_hi_11 = bits(dividendMSB_lo_9, 7, 4) node dividendMSB_lo_11 = bits(dividendMSB_lo_9, 3, 0) node dividendMSB_useHi_11 = orr(dividendMSB_hi_11) node _dividendMSB_T_67 = bits(dividendMSB_hi_11, 3, 3) node _dividendMSB_T_68 = bits(dividendMSB_hi_11, 2, 2) node _dividendMSB_T_69 = bits(dividendMSB_hi_11, 1, 1) node _dividendMSB_T_70 = mux(_dividendMSB_T_68, UInt<2>(0h2), _dividendMSB_T_69) node _dividendMSB_T_71 = mux(_dividendMSB_T_67, UInt<2>(0h3), _dividendMSB_T_70) node _dividendMSB_T_72 = bits(dividendMSB_lo_11, 3, 3) node _dividendMSB_T_73 = bits(dividendMSB_lo_11, 2, 2) node _dividendMSB_T_74 = bits(dividendMSB_lo_11, 1, 1) node _dividendMSB_T_75 = mux(_dividendMSB_T_73, UInt<2>(0h2), _dividendMSB_T_74) node _dividendMSB_T_76 = mux(_dividendMSB_T_72, UInt<2>(0h3), _dividendMSB_T_75) node _dividendMSB_T_77 = mux(dividendMSB_useHi_11, _dividendMSB_T_71, _dividendMSB_T_76) node _dividendMSB_T_78 = cat(dividendMSB_useHi_11, _dividendMSB_T_77) node _dividendMSB_T_79 = mux(dividendMSB_useHi_9, _dividendMSB_T_66, _dividendMSB_T_78) node _dividendMSB_T_80 = cat(dividendMSB_useHi_9, _dividendMSB_T_79) node dividendMSB_hi_12 = bits(dividendMSB_lo_8, 15, 8) node dividendMSB_lo_12 = bits(dividendMSB_lo_8, 7, 0) node dividendMSB_useHi_12 = orr(dividendMSB_hi_12) node dividendMSB_hi_13 = bits(dividendMSB_hi_12, 7, 4) node dividendMSB_lo_13 = bits(dividendMSB_hi_12, 3, 0) node dividendMSB_useHi_13 = orr(dividendMSB_hi_13) node _dividendMSB_T_81 = bits(dividendMSB_hi_13, 3, 3) node _dividendMSB_T_82 = bits(dividendMSB_hi_13, 2, 2) node _dividendMSB_T_83 = bits(dividendMSB_hi_13, 1, 1) node _dividendMSB_T_84 = mux(_dividendMSB_T_82, UInt<2>(0h2), _dividendMSB_T_83) node _dividendMSB_T_85 = mux(_dividendMSB_T_81, UInt<2>(0h3), _dividendMSB_T_84) node _dividendMSB_T_86 = bits(dividendMSB_lo_13, 3, 3) node _dividendMSB_T_87 = bits(dividendMSB_lo_13, 2, 2) node _dividendMSB_T_88 = bits(dividendMSB_lo_13, 1, 1) node _dividendMSB_T_89 = mux(_dividendMSB_T_87, UInt<2>(0h2), _dividendMSB_T_88) node _dividendMSB_T_90 = mux(_dividendMSB_T_86, UInt<2>(0h3), _dividendMSB_T_89) node _dividendMSB_T_91 = mux(dividendMSB_useHi_13, _dividendMSB_T_85, _dividendMSB_T_90) node _dividendMSB_T_92 = cat(dividendMSB_useHi_13, _dividendMSB_T_91) node dividendMSB_hi_14 = bits(dividendMSB_lo_12, 7, 4) node dividendMSB_lo_14 = bits(dividendMSB_lo_12, 3, 0) node dividendMSB_useHi_14 = orr(dividendMSB_hi_14) node _dividendMSB_T_93 = bits(dividendMSB_hi_14, 3, 3) node _dividendMSB_T_94 = bits(dividendMSB_hi_14, 2, 2) node _dividendMSB_T_95 = bits(dividendMSB_hi_14, 1, 1) node _dividendMSB_T_96 = mux(_dividendMSB_T_94, UInt<2>(0h2), _dividendMSB_T_95) node _dividendMSB_T_97 = mux(_dividendMSB_T_93, UInt<2>(0h3), _dividendMSB_T_96) node _dividendMSB_T_98 = bits(dividendMSB_lo_14, 3, 3) node _dividendMSB_T_99 = bits(dividendMSB_lo_14, 2, 2) node _dividendMSB_T_100 = bits(dividendMSB_lo_14, 1, 1) node _dividendMSB_T_101 = mux(_dividendMSB_T_99, UInt<2>(0h2), _dividendMSB_T_100) node _dividendMSB_T_102 = mux(_dividendMSB_T_98, UInt<2>(0h3), _dividendMSB_T_101) node _dividendMSB_T_103 = mux(dividendMSB_useHi_14, _dividendMSB_T_97, _dividendMSB_T_102) node _dividendMSB_T_104 = cat(dividendMSB_useHi_14, _dividendMSB_T_103) node _dividendMSB_T_105 = mux(dividendMSB_useHi_12, _dividendMSB_T_92, _dividendMSB_T_104) node _dividendMSB_T_106 = cat(dividendMSB_useHi_12, _dividendMSB_T_105) node _dividendMSB_T_107 = mux(dividendMSB_useHi_8, _dividendMSB_T_80, _dividendMSB_T_106) node _dividendMSB_T_108 = cat(dividendMSB_useHi_8, _dividendMSB_T_107) node _dividendMSB_T_109 = mux(dividendMSB_useHi, _dividendMSB_T_54, _dividendMSB_T_108) node _dividendMSB_T_110 = cat(dividendMSB_useHi, _dividendMSB_T_109) node _dividendMSB_T_111 = not(alignMask) node dividendMSB = or(_dividendMSB_T_110, _dividendMSB_T_111) node _eOutPos_T = sub(dividendMSB, divisorMSB) node _eOutPos_T_1 = tail(_eOutPos_T, 1) node eOutPos = not(_eOutPos_T_1) node _eOut_T_9 = eq(count, UInt<1>(0h0)) node _eOut_T_10 = eq(divby0, UInt<1>(0h0)) node _eOut_T_11 = and(_eOut_T_9, _eOut_T_10) node _eOut_T_12 = geq(eOutPos, UInt<1>(0h1)) node eOut_1 = and(_eOut_T_11, _eOut_T_12) when eOut_1 : node _remainder_T_3 = bits(remainder, 63, 0) node _remainder_T_4 = dshl(_remainder_T_3, eOutPos) connect remainder, _remainder_T_4 node _count_T_4 = shr(eOutPos, 0) connect count, _count_T_4 node _T_19 = eq(isHi, UInt<1>(0h0)) node _T_20 = and(divby0, _T_19) when _T_20 : connect neg_out, UInt<1>(0h0) node _T_21 = and(io.resp.ready, io.resp.valid) node _T_22 = or(_T_21, io.kill) when _T_22 : connect state, UInt<3>(0h0) node _T_23 = and(io.req.ready, io.req.valid) when _T_23 : node _state_T_1 = or(lhs_sign, rhs_sign) node _state_T_2 = mux(_state_T_1, UInt<3>(0h1), UInt<3>(0h3)) node _state_T_3 = mux(cmdMul, UInt<3>(0h2), _state_T_2) connect state, _state_T_3 connect isHi, cmdHi connect resHi, UInt<1>(0h0) node _count_T_5 = eq(io.req.bits.dw, UInt<1>(0h0)) node _count_T_6 = and(UInt<1>(0h1), _count_T_5) node _count_T_7 = and(cmdMul, _count_T_6) node _count_T_8 = mux(_count_T_7, UInt<3>(0h4), UInt<1>(0h0)) connect count, _count_T_8 node _neg_out_T = neq(lhs_sign, rhs_sign) node _neg_out_T_1 = mux(cmdHi, lhs_sign, _neg_out_T) connect neg_out, _neg_out_T_1 node _divisor_T = cat(rhs_sign, rhs_in) connect divisor, _divisor_T connect remainder, lhs_in connect req, io.req.bits node _outMul_T = xor(UInt<3>(0h6), UInt<3>(0h7)) node _outMul_T_1 = and(state, _outMul_T) node _outMul_T_2 = not(UInt<3>(0h7)) node _outMul_T_3 = and(UInt<3>(0h6), _outMul_T_2) node outMul = eq(_outMul_T_1, _outMul_T_3) node _loOut_T = eq(req.dw, UInt<1>(0h0)) node _loOut_T_1 = and(UInt<1>(0h1), _loOut_T) node _loOut_T_2 = and(UInt<1>(0h1), _loOut_T_1) node _loOut_T_3 = and(_loOut_T_2, outMul) node _loOut_T_4 = bits(result, 63, 32) node _loOut_T_5 = bits(result, 31, 0) node loOut = mux(_loOut_T_3, _loOut_T_4, _loOut_T_5) node _hiOut_T = eq(req.dw, UInt<1>(0h0)) node _hiOut_T_1 = and(UInt<1>(0h1), _hiOut_T) node _hiOut_T_2 = bits(loOut, 31, 31) node _hiOut_T_3 = mux(_hiOut_T_2, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hiOut_T_4 = bits(result, 63, 32) node hiOut = mux(_hiOut_T_1, _hiOut_T_3, _hiOut_T_4) connect io.resp.bits.tag, req.tag node _io_resp_bits_data_T = cat(hiOut, loOut) connect io.resp.bits.data, _io_resp_bits_data_T node _io_resp_bits_full_data_T = bits(remainder, 128, 65) node _io_resp_bits_full_data_T_1 = bits(remainder, 63, 0) node _io_resp_bits_full_data_T_2 = cat(_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1) connect io.resp.bits.full_data, _io_resp_bits_full_data_T_2 node _io_resp_valid_T = eq(state, UInt<3>(0h6)) node _io_resp_valid_T_1 = eq(state, UInt<3>(0h7)) node _io_resp_valid_T_2 = or(_io_resp_valid_T, _io_resp_valid_T_1) connect io.resp.valid, _io_resp_valid_T_2 node _io_req_ready_T = eq(state, UInt<3>(0h0)) connect io.req.ready, _io_req_ready_T	module MulDiv_7( // @[Multiplier.scala:40:7] input clock, // @[Multiplier.scala:40:7] input reset, // @[Multiplier.scala:40:7] output io_req_ready, // @[Multiplier.scala:45:14] input io_req_valid, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_fn, // @[Multiplier.scala:45:14] input io_req_bits_dw, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in1, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in2, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_tag, // @[Multiplier.scala:45:14] input io_kill, // @[Multiplier.scala:45:14] input io_resp_ready, // @[Multiplier.scala:45:14] output io_resp_valid, // @[Multiplier.scala:45:14] output [63:0] io_resp_bits_data, // @[Multiplier.scala:45:14] output [4:0] io_resp_bits_tag // @[Multiplier.scala:45:14] ); wire io_req_valid_0 = io_req_valid; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_fn_0 = io_req_bits_fn; // @[Multiplier.scala:40:7] wire io_req_bits_dw_0 = io_req_bits_dw; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in1_0 = io_req_bits_in1; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in2_0 = io_req_bits_in2; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_tag_0 = io_req_bits_tag; // @[Multiplier.scala:40:7] wire io_kill_0 = io_kill; // @[Multiplier.scala:40:7] wire io_resp_ready_0 = io_resp_ready; // @[Multiplier.scala:40:7] wire [5:0] alignMask = 6'h3F; // @[Multiplier.scala:149:23] wire [5:0] _dividendMSB_T_111 = 6'h0; // @[Multiplier.scala:151:53] wire [2:0] _outMul_T = 3'h1; // @[Multiplier.scala:175:37] wire [2:0] _outMul_T_2 = 3'h0; // @[Multiplier.scala:175:70] wire [2:0] _outMul_T_3 = 3'h0; // @[Multiplier.scala:175:68] wire _io_req_ready_T; // @[Multiplier.scala:183:25] wire _io_resp_valid_T_2; // @[Multiplier.scala:182:42] wire [63:0] _io_resp_bits_data_T; // @[Multiplier.scala:180:27] wire [127:0] _io_resp_bits_full_data_T_2; // @[Multiplier.scala:181:32] wire io_req_ready_0; // @[Multiplier.scala:40:7] wire [63:0] io_resp_bits_data_0; // @[Multiplier.scala:40:7] wire [127:0] io_resp_bits_full_data; // @[Multiplier.scala:40:7] wire [4:0] io_resp_bits_tag_0; // @[Multiplier.scala:40:7] wire io_resp_valid_0; // @[Multiplier.scala:40:7] reg [2:0] state; // @[Multiplier.scala:51:22] reg [4:0] req_fn; // @[Multiplier.scala:53:16] reg req_dw; // @[Multiplier.scala:53:16] reg [63:0] req_in1; // @[Multiplier.scala:53:16] reg [63:0] req_in2; // @[Multiplier.scala:53:16] reg [4:0] req_tag; // @[Multiplier.scala:53:16] assign io_resp_bits_tag_0 = req_tag; // @[Multiplier.scala:40:7, :53:16] reg [6:0] count; // @[Multiplier.scala:54:18] reg neg_out; // @[Multiplier.scala:57:20] reg isHi; // @[Multiplier.scala:58:17] reg resHi; // @[Multiplier.scala:59:18] reg [64:0] divisor; // @[Multiplier.scala:60:20] wire [64:0] mpcand = divisor; // @[Multiplier.scala:60:20, :111:26] reg [129:0] remainder; // @[Multiplier.scala:61:22] wire [2:0] decoded_plaInput; // @[pla.scala:77:22] wire [2:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [3:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [3:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_3_2 = decoded_andMatrixOutputs_andMatrixInput_0; // @[pla.scala:91:29, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_4_2 = decoded_andMatrixOutputs_andMatrixInput_0_1; // @[pla.scala:91:29, :98:70] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire [1:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_1_2 = decoded_andMatrixOutputs_andMatrixInput_0_4; // @[pla.scala:90:45, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T = {decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_1 = \|_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_2 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_3 = \|_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_4 = {decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_5 = \|_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo = {_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_plaInput = io_req_bits_fn_0[2:0]; // @[pla.scala:77:22] wire cmdMul = decoded[3]; // @[pla.scala:81:23] wire cmdHi = decoded[2]; // @[pla.scala:81:23] wire lhsSigned = decoded[1]; // @[pla.scala:81:23] wire rhsSigned = decoded[0]; // @[pla.scala:81:23] wire _count_T_5 = ~io_req_bits_dw_0; // @[Multiplier.scala:40:7, :78:60] wire _sign_T = io_req_bits_in1_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_1 = io_req_bits_in1_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_2 = io_req_bits_dw_0 ? _sign_T_1 : _sign_T; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire lhs_sign = lhsSigned & _sign_T_2; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T = {32{lhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_1 = io_req_bits_in1_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi = io_req_bits_dw_0 ? _hi_T_1 : _hi_T; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] lhs_in = {hi, io_req_bits_in1_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire _sign_T_3 = io_req_bits_in2_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_4 = io_req_bits_in2_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_5 = io_req_bits_dw_0 ? _sign_T_4 : _sign_T_3; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire rhs_sign = rhsSigned & _sign_T_5; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T_2 = {32{rhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_3 = io_req_bits_in2_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi_1 = io_req_bits_dw_0 ? _hi_T_3 : _hi_T_2; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] rhs_in = {hi_1, io_req_bits_in2_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire [64:0] _subtractor_T = remainder[128:64]; // @[Multiplier.scala:61:22, :88:29] wire [65:0] _subtractor_T_1 = {1'h0, _subtractor_T} - {1'h0, divisor}; // @[Multiplier.scala:60:20, :88:{29,37}] wire [64:0] subtractor = _subtractor_T_1[64:0]; // @[Multiplier.scala:88:37] wire [63:0] _result_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36] wire [63:0] _io_resp_bits_full_data_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36, :181:42] wire [63:0] _result_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57] wire [63:0] _mulReg_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :107:55] wire [63:0] _unrolls_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :134:58] wire [63:0] _dividendMSB_T = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :151:39] wire [63:0] _remainder_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :155:31] wire [63:0] _io_resp_bits_full_data_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :181:63] wire [63:0] result = resHi ? _result_T : _result_T_1; // @[Multiplier.scala:59:18, :89:{19,36,57}] wire [64:0] _negated_remainder_T = 65'h0 - {1'h0, result}; // @[Multiplier.scala:89:19, :90:27] wire [63:0] negated_remainder = _negated_remainder_T[63:0]; // @[Multiplier.scala:90:27] wire [64:0] _mulReg_T = remainder[129:65]; // @[Multiplier.scala:61:22, :107:31] wire [128:0] mulReg = {_mulReg_T, _mulReg_T_1}; // @[Multiplier.scala:107:{21,31,55}] wire mplierSign = remainder[64]; // @[Multiplier.scala:61:22, :108:31] wire [63:0] mplier = mulReg[63:0]; // @[Multiplier.scala:107:21, :109:24] wire [64:0] _accum_T = mulReg[128:64]; // @[Multiplier.scala:107:21, :110:23] wire [64:0] accum = _accum_T; // @[Multiplier.scala:110:{23,37}] wire [7:0] _prod_T = mplier[7:0]; // @[Multiplier.scala:109:24, :112:38] wire [8:0] _prod_T_1 = {mplierSign, _prod_T}; // @[Multiplier.scala:108:31, :112:{19,38}] wire [8:0] _prod_T_2 = _prod_T_1; // @[Multiplier.scala:112:{19,60}] wire [73:0] _prod_T_3 = {{65{_prod_T_2[8]}}, _prod_T_2} * {{9{mpcand[64]}}, mpcand}; // @[Multiplier.scala:111:26, :112:{60,67}] wire [74:0] _prod_T_4 = {_prod_T_3[73], _prod_T_3} + {{10{accum[64]}}, accum}; // @[Multiplier.scala:110:37, :112:{67,76}] wire [73:0] _prod_T_5 = _prod_T_4[73:0]; // @[Multiplier.scala:112:76] wire [73:0] prod = _prod_T_5; // @[Multiplier.scala:112:76] wire [73:0] nextMulReg_hi = prod; // @[Multiplier.scala:112:76, :113:25] wire [55:0] _nextMulReg_T = mplier[63:8]; // @[Multiplier.scala:109:24, :113:38] wire [129:0] nextMulReg = {nextMulReg_hi, _nextMulReg_T}; // @[Multiplier.scala:113:{25,38}] wire _nextMplierSign_T = count == 7'h6; // @[Multiplier.scala:54:18, :114:32] wire nextMplierSign = _nextMplierSign_T & neg_out; // @[Multiplier.scala:57:20, :114:{32,61}] wire [10:0] _GEN = {1'h0, count, 3'h0}; // @[Multiplier.scala:54:18, :116:54] wire [10:0] _eOutMask_T; // @[Multiplier.scala:116:54] assign _eOutMask_T = _GEN; // @[Multiplier.scala:116:54] wire [10:0] _eOutRes_T; // @[Multiplier.scala:119:46] assign _eOutRes_T = _GEN; // @[Multiplier.scala:116:54, :119:46] wire [5:0] _eOutMask_T_1 = _eOutMask_T[5:0]; // @[Multiplier.scala:116:{54,72}] wire [64:0] _eOutMask_T_2 = $signed(65'sh10000000000000000 >>> _eOutMask_T_1); // @[Multiplier.scala:116:{44,72}] wire [63:0] eOutMask = _eOutMask_T_2[63:0]; // @[Multiplier.scala:116:{44,91}] wire _eOut_T = count != 7'h7; // @[Multiplier.scala:54:18, :117:45] wire _eOut_T_1 = _eOut_T; // @[Multiplier.scala:117:{36,45}] wire _eOut_T_2 = \|count; // @[Multiplier.scala:54:18, :117:83] wire _eOut_T_3 = _eOut_T_1 & _eOut_T_2; // @[Multiplier.scala:117:{36,74,83}] wire _eOut_T_4 = ~isHi; // @[Multiplier.scala:58:17, :118:7] wire _eOut_T_5 = _eOut_T_3 & _eOut_T_4; // @[Multiplier.scala:117:{74,91}, :118:7] wire [63:0] _eOut_T_6 = ~eOutMask; // @[Multiplier.scala:116:91, :118:26] wire [63:0] _eOut_T_7 = mplier & _eOut_T_6; // @[Multiplier.scala:109:24, :118:{24,26}] wire _eOut_T_8 = _eOut_T_7 == 64'h0; // @[Multiplier.scala:118:{24,37}] wire eOut = _eOut_T_5 & _eOut_T_8; // @[Multiplier.scala:117:91, :118:{13,37}] wire [11:0] _eOutRes_T_1 = 12'h40 - {1'h0, _eOutRes_T}; // @[Multiplier.scala:119:{38,46}] wire [10:0] _eOutRes_T_2 = _eOutRes_T_1[10:0]; // @[Multiplier.scala:119:38] wire [5:0] _eOutRes_T_3 = _eOutRes_T_2[5:0]; // @[Multiplier.scala:119:{38,64}] wire [128:0] eOutRes = mulReg >> _eOutRes_T_3; // @[Multiplier.scala:107:21, :119:{27,64}] wire [64:0] _nextMulReg1_T = nextMulReg[128:64]; // @[Multiplier.scala:113:25, :120:37] wire [129:0] _nextMulReg1_T_1 = eOut ? {1'h0, eOutRes} : nextMulReg; // @[Multiplier.scala:113:25, :118:13, :119:27, :120:55] wire [63:0] _nextMulReg1_T_2 = _nextMulReg1_T_1[63:0]; // @[Multiplier.scala:120:{55,82}] wire [128:0] nextMulReg1 = {_nextMulReg1_T, _nextMulReg1_T_2}; // @[Multiplier.scala:120:{26,37,82}] wire [64:0] _remainder_T = nextMulReg1[128:64]; // @[Multiplier.scala:120:26, :121:34] wire [63:0] _remainder_T_1 = nextMulReg1[63:0]; // @[Multiplier.scala:120:26, :121:67] wire [65:0] remainder_hi = {_remainder_T, nextMplierSign}; // @[Multiplier.scala:114:61, :121:{21,34}] wire [129:0] _remainder_T_2 = {remainder_hi, _remainder_T_1}; // @[Multiplier.scala:121:{21,67}] wire [7:0] _GEN_0 = {1'h0, count} + 8'h1; // @[Multiplier.scala:54:18, :123:20] wire [7:0] _count_T; // @[Multiplier.scala:123:20] assign _count_T = _GEN_0; // @[Multiplier.scala:123:20] wire [7:0] _count_T_2; // @[Multiplier.scala:144:20] assign _count_T_2 = _GEN_0; // @[Multiplier.scala:123:20, :144:20] wire [6:0] _count_T_1 = _count_T[6:0]; // @[Multiplier.scala:123:20] wire unrolls_less = subtractor[64]; // @[Multiplier.scala:88:37, :133:28] wire _divby0_T_1 = subtractor[64]; // @[Multiplier.scala:88:37, :133:28, :146:46] wire [63:0] _unrolls_T = remainder[127:64]; // @[Multiplier.scala:61:22, :134:24] wire [63:0] _unrolls_T_1 = subtractor[63:0]; // @[Multiplier.scala:88:37, :134:45] wire [63:0] _unrolls_T_2 = unrolls_less ? _unrolls_T : _unrolls_T_1; // @[Multiplier.scala:133:28, :134:{14,24,45}] wire _unrolls_T_4 = ~unrolls_less; // @[Multiplier.scala:133:28, :134:67] wire [127:0] unrolls_hi = {_unrolls_T_2, _unrolls_T_3}; // @[Multiplier.scala:134:{10,14,58}] wire [128:0] unrolls_0 = {unrolls_hi, _unrolls_T_4}; // @[Multiplier.scala:134:{10,67}] wire [2:0] _state_T = {1'h1, ~neg_out, 1'h1}; // @[Multiplier.scala:57:20, :139:19] wire [6:0] _count_T_3 = _count_T_2[6:0]; // @[Multiplier.scala:144:20] wire _divby0_T = ~(\|count); // @[Multiplier.scala:54:18, :117:83, :146:24] wire _divby0_T_2 = ~_divby0_T_1; // @[Multiplier.scala:146:{35,46}] wire divby0 = _divby0_T & _divby0_T_2; // @[Multiplier.scala:146:{24,32,35}] wire [63:0] _divisorMSB_T = divisor[63:0]; // @[Multiplier.scala:60:20, :150:36] wire [31:0] divisorMSB_hi = _divisorMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] divisorMSB_lo = _divisorMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi = \|divisorMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] divisorMSB_hi_1 = divisorMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] divisorMSB_lo_1 = divisorMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_1 = \|divisorMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_2 = divisorMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_2 = divisorMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_2 = \|divisorMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_3 = divisorMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_3 = divisorMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_3 = \|divisorMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_1 = divisorMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_2 = divisorMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_3 = divisorMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_4 = _divisorMSB_T_2 ? 2'h2 : {1'h0, _divisorMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_5 = _divisorMSB_T_1 ? 2'h3 : _divisorMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_6 = divisorMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_7 = divisorMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_8 = divisorMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_9 = _divisorMSB_T_7 ? 2'h2 : {1'h0, _divisorMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_10 = _divisorMSB_T_6 ? 2'h3 : _divisorMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_11 = divisorMSB_useHi_3 ? _divisorMSB_T_5 : _divisorMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_12 = {divisorMSB_useHi_3, _divisorMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_4 = divisorMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_4 = divisorMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_4 = \|divisorMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_13 = divisorMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_14 = divisorMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_15 = divisorMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_16 = _divisorMSB_T_14 ? 2'h2 : {1'h0, _divisorMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_17 = _divisorMSB_T_13 ? 2'h3 : _divisorMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_18 = divisorMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_19 = divisorMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_20 = divisorMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_21 = _divisorMSB_T_19 ? 2'h2 : {1'h0, _divisorMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_22 = _divisorMSB_T_18 ? 2'h3 : _divisorMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_23 = divisorMSB_useHi_4 ? _divisorMSB_T_17 : _divisorMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_24 = {divisorMSB_useHi_4, _divisorMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_25 = divisorMSB_useHi_2 ? _divisorMSB_T_12 : _divisorMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_26 = {divisorMSB_useHi_2, _divisorMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_5 = divisorMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_5 = divisorMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_5 = \|divisorMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_6 = divisorMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_6 = divisorMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_6 = \|divisorMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_27 = divisorMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_28 = divisorMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_29 = divisorMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_30 = _divisorMSB_T_28 ? 2'h2 : {1'h0, _divisorMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_31 = _divisorMSB_T_27 ? 2'h3 : _divisorMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_32 = divisorMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_33 = divisorMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_34 = divisorMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_35 = _divisorMSB_T_33 ? 2'h2 : {1'h0, _divisorMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_36 = _divisorMSB_T_32 ? 2'h3 : _divisorMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_37 = divisorMSB_useHi_6 ? _divisorMSB_T_31 : _divisorMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_38 = {divisorMSB_useHi_6, _divisorMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_7 = divisorMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_7 = divisorMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_7 = \|divisorMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_39 = divisorMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_40 = divisorMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_41 = divisorMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_42 = _divisorMSB_T_40 ? 2'h2 : {1'h0, _divisorMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_43 = _divisorMSB_T_39 ? 2'h3 : _divisorMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_44 = divisorMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_45 = divisorMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_46 = divisorMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_47 = _divisorMSB_T_45 ? 2'h2 : {1'h0, _divisorMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_48 = _divisorMSB_T_44 ? 2'h3 : _divisorMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_49 = divisorMSB_useHi_7 ? _divisorMSB_T_43 : _divisorMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_50 = {divisorMSB_useHi_7, _divisorMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_51 = divisorMSB_useHi_5 ? _divisorMSB_T_38 : _divisorMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_52 = {divisorMSB_useHi_5, _divisorMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_53 = divisorMSB_useHi_1 ? _divisorMSB_T_26 : _divisorMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_54 = {divisorMSB_useHi_1, _divisorMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] divisorMSB_hi_8 = divisorMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] divisorMSB_lo_8 = divisorMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_8 = \|divisorMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_9 = divisorMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_9 = divisorMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_9 = \|divisorMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_10 = divisorMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_10 = divisorMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_10 = \|divisorMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_55 = divisorMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_56 = divisorMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_57 = divisorMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_58 = _divisorMSB_T_56 ? 2'h2 : {1'h0, _divisorMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_59 = _divisorMSB_T_55 ? 2'h3 : _divisorMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_60 = divisorMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_61 = divisorMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_62 = divisorMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_63 = _divisorMSB_T_61 ? 2'h2 : {1'h0, _divisorMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_64 = _divisorMSB_T_60 ? 2'h3 : _divisorMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_65 = divisorMSB_useHi_10 ? _divisorMSB_T_59 : _divisorMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_66 = {divisorMSB_useHi_10, _divisorMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_11 = divisorMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_11 = divisorMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_11 = \|divisorMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_67 = divisorMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_68 = divisorMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_69 = divisorMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_70 = _divisorMSB_T_68 ? 2'h2 : {1'h0, _divisorMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_71 = _divisorMSB_T_67 ? 2'h3 : _divisorMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_72 = divisorMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_73 = divisorMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_74 = divisorMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_75 = _divisorMSB_T_73 ? 2'h2 : {1'h0, _divisorMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_76 = _divisorMSB_T_72 ? 2'h3 : _divisorMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_77 = divisorMSB_useHi_11 ? _divisorMSB_T_71 : _divisorMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_78 = {divisorMSB_useHi_11, _divisorMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_79 = divisorMSB_useHi_9 ? _divisorMSB_T_66 : _divisorMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_80 = {divisorMSB_useHi_9, _divisorMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_12 = divisorMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_12 = divisorMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_12 = \|divisorMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_13 = divisorMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_13 = divisorMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_13 = \|divisorMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_81 = divisorMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_82 = divisorMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_83 = divisorMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_84 = _divisorMSB_T_82 ? 2'h2 : {1'h0, _divisorMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_85 = _divisorMSB_T_81 ? 2'h3 : _divisorMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_86 = divisorMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_87 = divisorMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_88 = divisorMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_89 = _divisorMSB_T_87 ? 2'h2 : {1'h0, _divisorMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_90 = _divisorMSB_T_86 ? 2'h3 : _divisorMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_91 = divisorMSB_useHi_13 ? _divisorMSB_T_85 : _divisorMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_92 = {divisorMSB_useHi_13, _divisorMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_14 = divisorMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_14 = divisorMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_14 = \|divisorMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_93 = divisorMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_94 = divisorMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_95 = divisorMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_96 = _divisorMSB_T_94 ? 2'h2 : {1'h0, _divisorMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_97 = _divisorMSB_T_93 ? 2'h3 : _divisorMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_98 = divisorMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_99 = divisorMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_100 = divisorMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_101 = _divisorMSB_T_99 ? 2'h2 : {1'h0, _divisorMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_102 = _divisorMSB_T_98 ? 2'h3 : _divisorMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_103 = divisorMSB_useHi_14 ? _divisorMSB_T_97 : _divisorMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_104 = {divisorMSB_useHi_14, _divisorMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_105 = divisorMSB_useHi_12 ? _divisorMSB_T_92 : _divisorMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_106 = {divisorMSB_useHi_12, _divisorMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_107 = divisorMSB_useHi_8 ? _divisorMSB_T_80 : _divisorMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_108 = {divisorMSB_useHi_8, _divisorMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_109 = divisorMSB_useHi ? _divisorMSB_T_54 : _divisorMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _divisorMSB_T_110 = {divisorMSB_useHi, _divisorMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] divisorMSB = _divisorMSB_T_110; // @[CircuitMath.scala:36:10] wire [31:0] dividendMSB_hi = _dividendMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] dividendMSB_lo = _dividendMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi = \|dividendMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] dividendMSB_hi_1 = dividendMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] dividendMSB_lo_1 = dividendMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_1 = \|dividendMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_2 = dividendMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_2 = dividendMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_2 = \|dividendMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_3 = dividendMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_3 = dividendMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_3 = \|dividendMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_1 = dividendMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_2 = dividendMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_3 = dividendMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_4 = _dividendMSB_T_2 ? 2'h2 : {1'h0, _dividendMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_5 = _dividendMSB_T_1 ? 2'h3 : _dividendMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_6 = dividendMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_7 = dividendMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_8 = dividendMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_9 = _dividendMSB_T_7 ? 2'h2 : {1'h0, _dividendMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_10 = _dividendMSB_T_6 ? 2'h3 : _dividendMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_11 = dividendMSB_useHi_3 ? _dividendMSB_T_5 : _dividendMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_12 = {dividendMSB_useHi_3, _dividendMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_4 = dividendMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_4 = dividendMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_4 = \|dividendMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_13 = dividendMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_14 = dividendMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_15 = dividendMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_16 = _dividendMSB_T_14 ? 2'h2 : {1'h0, _dividendMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_17 = _dividendMSB_T_13 ? 2'h3 : _dividendMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_18 = dividendMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_19 = dividendMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_20 = dividendMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_21 = _dividendMSB_T_19 ? 2'h2 : {1'h0, _dividendMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_22 = _dividendMSB_T_18 ? 2'h3 : _dividendMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_23 = dividendMSB_useHi_4 ? _dividendMSB_T_17 : _dividendMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_24 = {dividendMSB_useHi_4, _dividendMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_25 = dividendMSB_useHi_2 ? _dividendMSB_T_12 : _dividendMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_26 = {dividendMSB_useHi_2, _dividendMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_5 = dividendMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_5 = dividendMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_5 = \|dividendMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_6 = dividendMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_6 = dividendMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_6 = \|dividendMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_27 = dividendMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_28 = dividendMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_29 = dividendMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_30 = _dividendMSB_T_28 ? 2'h2 : {1'h0, _dividendMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_31 = _dividendMSB_T_27 ? 2'h3 : _dividendMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_32 = dividendMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_33 = dividendMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_34 = dividendMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_35 = _dividendMSB_T_33 ? 2'h2 : {1'h0, _dividendMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_36 = _dividendMSB_T_32 ? 2'h3 : _dividendMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_37 = dividendMSB_useHi_6 ? _dividendMSB_T_31 : _dividendMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_38 = {dividendMSB_useHi_6, _dividendMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_7 = dividendMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_7 = dividendMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_7 = \|dividendMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_39 = dividendMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_40 = dividendMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_41 = dividendMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_42 = _dividendMSB_T_40 ? 2'h2 : {1'h0, _dividendMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_43 = _dividendMSB_T_39 ? 2'h3 : _dividendMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_44 = dividendMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_45 = dividendMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_46 = dividendMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_47 = _dividendMSB_T_45 ? 2'h2 : {1'h0, _dividendMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_48 = _dividendMSB_T_44 ? 2'h3 : _dividendMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_49 = dividendMSB_useHi_7 ? _dividendMSB_T_43 : _dividendMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_50 = {dividendMSB_useHi_7, _dividendMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_51 = dividendMSB_useHi_5 ? _dividendMSB_T_38 : _dividendMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_52 = {dividendMSB_useHi_5, _dividendMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_53 = dividendMSB_useHi_1 ? _dividendMSB_T_26 : _dividendMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_54 = {dividendMSB_useHi_1, _dividendMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] dividendMSB_hi_8 = dividendMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] dividendMSB_lo_8 = dividendMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_8 = \|dividendMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_9 = dividendMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_9 = dividendMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_9 = \|dividendMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_10 = dividendMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_10 = dividendMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_10 = \|dividendMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_55 = dividendMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_56 = dividendMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_57 = dividendMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_58 = _dividendMSB_T_56 ? 2'h2 : {1'h0, _dividendMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_59 = _dividendMSB_T_55 ? 2'h3 : _dividendMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_60 = dividendMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_61 = dividendMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_62 = dividendMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_63 = _dividendMSB_T_61 ? 2'h2 : {1'h0, _dividendMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_64 = _dividendMSB_T_60 ? 2'h3 : _dividendMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_65 = dividendMSB_useHi_10 ? _dividendMSB_T_59 : _dividendMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_66 = {dividendMSB_useHi_10, _dividendMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_11 = dividendMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_11 = dividendMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_11 = \|dividendMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_67 = dividendMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_68 = dividendMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_69 = dividendMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_70 = _dividendMSB_T_68 ? 2'h2 : {1'h0, _dividendMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_71 = _dividendMSB_T_67 ? 2'h3 : _dividendMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_72 = dividendMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_73 = dividendMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_74 = dividendMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_75 = _dividendMSB_T_73 ? 2'h2 : {1'h0, _dividendMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_76 = _dividendMSB_T_72 ? 2'h3 : _dividendMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_77 = dividendMSB_useHi_11 ? _dividendMSB_T_71 : _dividendMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_78 = {dividendMSB_useHi_11, _dividendMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_79 = dividendMSB_useHi_9 ? _dividendMSB_T_66 : _dividendMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_80 = {dividendMSB_useHi_9, _dividendMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_12 = dividendMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_12 = dividendMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_12 = \|dividendMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_13 = dividendMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_13 = dividendMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_13 = \|dividendMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_81 = dividendMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_82 = dividendMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_83 = dividendMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_84 = _dividendMSB_T_82 ? 2'h2 : {1'h0, _dividendMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_85 = _dividendMSB_T_81 ? 2'h3 : _dividendMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_86 = dividendMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_87 = dividendMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_88 = dividendMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_89 = _dividendMSB_T_87 ? 2'h2 : {1'h0, _dividendMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_90 = _dividendMSB_T_86 ? 2'h3 : _dividendMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_91 = dividendMSB_useHi_13 ? _dividendMSB_T_85 : _dividendMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_92 = {dividendMSB_useHi_13, _dividendMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_14 = dividendMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_14 = dividendMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_14 = \|dividendMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_93 = dividendMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_94 = dividendMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_95 = dividendMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_96 = _dividendMSB_T_94 ? 2'h2 : {1'h0, _dividendMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_97 = _dividendMSB_T_93 ? 2'h3 : _dividendMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_98 = dividendMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_99 = dividendMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_100 = dividendMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_101 = _dividendMSB_T_99 ? 2'h2 : {1'h0, _dividendMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_102 = _dividendMSB_T_98 ? 2'h3 : _dividendMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_103 = dividendMSB_useHi_14 ? _dividendMSB_T_97 : _dividendMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_104 = {dividendMSB_useHi_14, _dividendMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_105 = dividendMSB_useHi_12 ? _dividendMSB_T_92 : _dividendMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_106 = {dividendMSB_useHi_12, _dividendMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_107 = dividendMSB_useHi_8 ? _dividendMSB_T_80 : _dividendMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_108 = {dividendMSB_useHi_8, _dividendMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_109 = dividendMSB_useHi ? _dividendMSB_T_54 : _dividendMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _dividendMSB_T_110 = {dividendMSB_useHi, _dividendMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] dividendMSB = _dividendMSB_T_110; // @[CircuitMath.scala:36:10] wire [6:0] _eOutPos_T = {1'h0, dividendMSB} - {1'h0, divisorMSB}; // @[Multiplier.scala:150:48, :151:51, :152:35] wire [5:0] _eOutPos_T_1 = _eOutPos_T[5:0]; // @[Multiplier.scala:152:35] wire [5:0] eOutPos = ~_eOutPos_T_1; // @[Multiplier.scala:152:{21,35}] wire [5:0] _count_T_4 = eOutPos; // @[Multiplier.scala:152:21, :156:26] wire _eOut_T_9 = ~(\|count); // @[Multiplier.scala:54:18, :117:83, :146:24, :153:24] wire _eOut_T_10 = ~divby0; // @[Multiplier.scala:146:32, :153:35] wire _eOut_T_11 = _eOut_T_9 & _eOut_T_10; // @[Multiplier.scala:153:{24,32,35}] wire _eOut_T_12 = \|eOutPos; // @[Multiplier.scala:152:21, :153:54] wire eOut_1 = _eOut_T_11 & _eOut_T_12; // @[Multiplier.scala:153:{32,43,54}] wire [126:0] _remainder_T_4 = {63'h0, _remainder_T_3} << eOutPos; // @[Multiplier.scala:152:21, :155:{31,39}] wire _state_T_1 = lhs_sign \| rhs_sign; // @[Multiplier.scala:81:23, :165:46] wire [2:0] _state_T_2 = {1'h0, ~_state_T_1, 1'h1}; // @[Multiplier.scala:165:{36,46}] wire [2:0] _state_T_3 = cmdMul ? 3'h2 : _state_T_2; // @[Multiplier.scala:75:107, :165:{17,36}] wire _count_T_6 = _count_T_5; // @[Multiplier.scala:78:{50,60}] wire _count_T_7 = cmdMul & _count_T_6; // @[Multiplier.scala:75:107, :78:50, :168:46] wire [2:0] _count_T_8 = {_count_T_7, 2'h0}; // @[Multiplier.scala:168:{38,46}] wire _neg_out_T = lhs_sign != rhs_sign; // @[Multiplier.scala:81:23, :169:46] wire _neg_out_T_1 = cmdHi ? lhs_sign : _neg_out_T; // @[Multiplier.scala:75:107, :81:23, :169:{19,46}] wire [64:0] _divisor_T = {rhs_sign, rhs_in}; // @[Multiplier.scala:81:23, :83:9, :170:19] wire [2:0] _outMul_T_1 = state & 3'h1; // @[Multiplier.scala:51:22, :175:23] wire outMul = _outMul_T_1 == 3'h0; // @[Multiplier.scala:175:{23,52}] wire _loOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _loOut_T_1 = _loOut_T; // @[Multiplier.scala:78:{50,60}] wire _loOut_T_2 = _loOut_T_1; // @[Multiplier.scala:78:50, :176:30] wire _loOut_T_3 = _loOut_T_2 & outMul; // @[Multiplier.scala:175:52, :176:{30,48}] wire [31:0] _loOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65] wire [31:0] _hiOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65, :177:66] wire [31:0] _loOut_T_5 = result[31:0]; // @[Multiplier.scala:89:19, :176:82] wire [31:0] loOut = _loOut_T_3 ? _loOut_T_4 : _loOut_T_5; // @[Multiplier.scala:176:{18,48,65,82}] wire _hiOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _hiOut_T_1 = _hiOut_T; // @[Multiplier.scala:78:{50,60}] wire _hiOut_T_2 = loOut[31]; // @[Multiplier.scala:176:18, :177:50] wire [31:0] _hiOut_T_3 = {32{_hiOut_T_2}}; // @[Multiplier.scala:177:{39,50}] wire [31:0] hiOut = _hiOut_T_1 ? _hiOut_T_3 : _hiOut_T_4; // @[Multiplier.scala:78:50, :177:{18,39,66}] assign _io_resp_bits_data_T = {hiOut, loOut}; // @[Multiplier.scala:176:18, :177:18, :180:27] assign io_resp_bits_data_0 = _io_resp_bits_data_T; // @[Multiplier.scala:40:7, :180:27] assign _io_resp_bits_full_data_T_2 = {_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1}; // @[Multiplier.scala:181:{32,42,63}] assign io_resp_bits_full_data = _io_resp_bits_full_data_T_2; // @[Multiplier.scala:40:7, :181:32] wire _io_resp_valid_T = state == 3'h6; // @[Multiplier.scala:51:22, :182:27] wire _io_resp_valid_T_1 = &state; // @[Multiplier.scala:51:22, :182:51] assign _io_resp_valid_T_2 = _io_resp_valid_T \| _io_resp_valid_T_1; // @[Multiplier.scala:182:{27,42,51}] assign io_resp_valid_0 = _io_resp_valid_T_2; // @[Multiplier.scala:40:7, :182:42] assign _io_req_ready_T = state == 3'h0; // @[Multiplier.scala:51:22, :183:25] assign io_req_ready_0 = _io_req_ready_T; // @[Multiplier.scala:40:7, :183:25] wire _T_10 = state == 3'h1; // @[Multiplier.scala:51:22, :92:39] wire _T_13 = state == 3'h5; // @[Multiplier.scala:51:22, :101:39] wire _T_14 = state == 3'h2; // @[Multiplier.scala:51:22, :106:39] wire _GEN_1 = _T_14 & (eOut \| count == 7'h7); // @[Multiplier.scala:54:18, :101:57, :106:{39,50}, :118:13, :124:{16,25,55}, :125:13] wire _T_17 = state == 3'h3; // @[Multiplier.scala:51:22, :129:39] wire _T_18 = count == 7'h40; // @[Multiplier.scala:54:18, :138:17] wire _T_23 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Multiplier.scala:40:7] if (reset) // @[Multiplier.scala:40:7] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_23) // @[Decoupled.scala:51:35] state <= _state_T_3; // @[Multiplier.scala:51:22, :165:17] else if (io_resp_ready_0 & io_resp_valid_0 \| io_kill_0) // @[Decoupled.scala:51:35] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_17 & _T_18) // @[Multiplier.scala:106:50, :129:{39,50}, :138:{17,42}, :139:13] state <= _state_T; // @[Multiplier.scala:51:22, :139:19] else if (_GEN_1) // @[Multiplier.scala:101:57, :106:50, :124:55, :125:13] state <= 3'h6; // @[Multiplier.scala:51:22] else if (_T_13) // @[Multiplier.scala:101:39] state <= 3'h7; // @[Multiplier.scala:51:22] else if (_T_10) // @[Multiplier.scala:92:39] state <= 3'h3; // @[Multiplier.scala:51:22] if (_T_23) begin // @[Decoupled.scala:51:35] req_fn <= io_req_bits_fn_0; // @[Multiplier.scala:40:7, :53:16] req_dw <= io_req_bits_dw_0; // @[Multiplier.scala:40:7, :53:16] req_in1 <= io_req_bits_in1_0; // @[Multiplier.scala:40:7, :53:16] req_in2 <= io_req_bits_in2_0; // @[Multiplier.scala:40:7, :53:16] req_tag <= io_req_bits_tag_0; // @[Multiplier.scala:40:7, :53:16] count <= {4'h0, _count_T_8}; // @[Multiplier.scala:54:18, :114:32, :168:{11,38}] isHi <= cmdHi; // @[Multiplier.scala:58:17, :75:107] divisor <= _divisor_T; // @[Multiplier.scala:60:20, :170:19] remainder <= {66'h0, lhs_in}; // @[Multiplier.scala:61:22, :83:9, :94:17, :171:15] end else begin // @[Decoupled.scala:51:35] if (_T_17) begin // @[Multiplier.scala:129:39] count <= eOut_1 ? {1'h0, _count_T_4} : _count_T_3; // @[Multiplier.scala:54:18, :144:{11,20}, :153:43, :154:19, :156:{15,26}] remainder <= eOut_1 ? {3'h0, _remainder_T_4} : {1'h0, unrolls_0}; // @[Multiplier.scala:61:22, :134:10, :137:15, :153:43, :154:19, :155:{19,39}] end else if (_T_14) begin // @[Multiplier.scala:106:39] count <= _count_T_1; // @[Multiplier.scala:54:18, :123:20] remainder <= _remainder_T_2; // @[Multiplier.scala:61:22, :121:21] end else if (_T_13 \| _T_10 & remainder[63]) // @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15] remainder <= {66'h0, negated_remainder}; // @[Multiplier.scala:61:22, :90:27, :94:17] if (_T_10 & divisor[63]) // @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15] divisor <= subtractor; // @[Multiplier.scala:60:20, :88:37] end neg_out <= _T_23 ? _neg_out_T_1 : ~(_T_17 & divby0 & ~isHi) & neg_out; // @[Decoupled.scala:51:35] resHi <= ~_T_23 & (_T_17 & _T_18 \| _GEN_1 ? isHi : ~_T_13 & resHi); // @[Decoupled.scala:51:35] always @(posedge) assign io_req_ready = io_req_ready_0; // @[Multiplier.scala:40:7] assign io_resp_valid = io_resp_valid_0; // @[Multiplier.scala:40:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[Multiplier.scala:40:7] assign io_resp_bits_tag = io_resp_bits_tag_0; // @[Multiplier.scala:40:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_51 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_102 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_103 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_51( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {9'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module FrontBus : output auto : { flip coupler_from_port_named_serial_tl_0_in_buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coupler_from_debug_sb_widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip fbus_clock_groups_in : { member : { fbus_0 : { clock : Clock, reset : Reset}}}, bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst fbus_clock_groups of ClockGroupAggregator_fbus inst clockGroup of ClockGroup_2 inst fixedClockNode of FixedClockBroadcast_2_1 inst broadcast of BundleBridgeNexus_NoOutput_2 inst fbus_xbar of TLXbar_fbus_i2_o1_a32d64s5k5z4u connect fbus_xbar.clock, childClock connect fbus_xbar.reset, childReset inst buffer of TLBuffer_a32d64s5k5z4u connect buffer.clock, childClock connect buffer.reset, childReset inst coupler_from_debug_sb of TLInterconnectCoupler_fbus_from_debug_sb connect coupler_from_debug_sb.clock, childClock connect coupler_from_debug_sb.reset, childReset inst coupler_from_port_named_serial_tl_0_in of TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in connect coupler_from_port_named_serial_tl_0_in.clock, childClock connect coupler_from_port_named_serial_tl_0_in.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn connect clockGroup.auto.in, fbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect buffer.auto.in, fbus_xbar.auto.anon_out connect buffer.auto.out.d, bus_xingIn.d connect bus_xingIn.a.bits, buffer.auto.out.a.bits connect bus_xingIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, bus_xingIn.a.ready connect fbus_xbar.auto.anon_in_0, coupler_from_debug_sb.auto.tl_out connect fbus_xbar.auto.anon_in_1, coupler_from_port_named_serial_tl_0_in.auto.tl_out connect auto.bus_xing_out, bus_xingOut connect fbus_clock_groups.auto.in, auto.fbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_from_debug_sb.auto.widget_anon_in, auto.coupler_from_debug_sb_widget_anon_in connect coupler_from_port_named_serial_tl_0_in.auto.buffer_in, auto.coupler_from_port_named_serial_tl_0_in_buffer_in connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset	module FrontBus( // @[ClockDomain.scala:14:9] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_debug_sb_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_debug_sb_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_fbus_clock_groups_in_member_fbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_fbus_clock_groups_in_member_fbus_0_reset, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [3:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_from_port_named_serial_tl_0_in_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _coupler_from_debug_sb_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_from_debug_sb_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [3:0] _coupler_from_debug_sb_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [31:0] _coupler_from_debug_sb_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_from_debug_sb_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_from_debug_sb_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_from_debug_sb_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [4:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire [4:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _fbus_xbar_auto_anon_in_1_a_ready; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_1_d_valid; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_in_1_d_bits_opcode; // @[BusWrapper.scala:240:32] wire [1:0] _fbus_xbar_auto_anon_in_1_d_bits_param; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_1_d_bits_size; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_1_d_bits_source; // @[BusWrapper.scala:240:32] wire [4:0] _fbus_xbar_auto_anon_in_1_d_bits_sink; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_1_d_bits_denied; // @[BusWrapper.scala:240:32] wire [63:0] _fbus_xbar_auto_anon_in_1_d_bits_data; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_1_d_bits_corrupt; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_a_ready; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_d_valid; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_in_0_d_bits_opcode; // @[BusWrapper.scala:240:32] wire [1:0] _fbus_xbar_auto_anon_in_0_d_bits_param; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_0_d_bits_size; // @[BusWrapper.scala:240:32] wire [4:0] _fbus_xbar_auto_anon_in_0_d_bits_sink; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_d_bits_denied; // @[BusWrapper.scala:240:32] wire [63:0] _fbus_xbar_auto_anon_in_0_d_bits_data; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_d_bits_corrupt; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_out_a_valid; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_out_a_bits_opcode; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_out_a_bits_param; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_out_a_bits_size; // @[BusWrapper.scala:240:32] wire [4:0] _fbus_xbar_auto_anon_out_a_bits_source; // @[BusWrapper.scala:240:32] wire [31:0] _fbus_xbar_auto_anon_out_a_bits_address; // @[BusWrapper.scala:240:32] wire [7:0] _fbus_xbar_auto_anon_out_a_bits_mask; // @[BusWrapper.scala:240:32] wire [63:0] _fbus_xbar_auto_anon_out_a_bits_data; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_out_a_bits_corrupt; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_out_d_ready; // @[BusWrapper.scala:240:32] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (auto_fbus_clock_groups_in_member_fbus_0_clock), .auto_anon_in_reset (auto_fbus_clock_groups_in_member_fbus_0_reset), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset), .auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock), .auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset) ); // @[ClockGroup.scala:115:114] TLXbar_fbus_i2_o1_a32d64s5k5z4u fbus_xbar ( // @[BusWrapper.scala:240:32] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_anon_in_1_a_ready (_fbus_xbar_auto_anon_in_1_a_ready), .auto_anon_in_1_a_valid (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_opcode (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_param (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_size (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_source (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_address (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_mask (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_data (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_corrupt (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_in_1_d_ready (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_anon_in_1_d_valid (_fbus_xbar_auto_anon_in_1_d_valid), .auto_anon_in_1_d_bits_opcode (_fbus_xbar_auto_anon_in_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (_fbus_xbar_auto_anon_in_1_d_bits_param), .auto_anon_in_1_d_bits_size (_fbus_xbar_auto_anon_in_1_d_bits_size), .auto_anon_in_1_d_bits_source (_fbus_xbar_auto_anon_in_1_d_bits_source), .auto_anon_in_1_d_bits_sink (_fbus_xbar_auto_anon_in_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (_fbus_xbar_auto_anon_in_1_d_bits_denied), .auto_anon_in_1_d_bits_data (_fbus_xbar_auto_anon_in_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (_fbus_xbar_auto_anon_in_1_d_bits_corrupt), .auto_anon_in_0_a_ready (_fbus_xbar_auto_anon_in_0_a_ready), .auto_anon_in_0_a_valid (_coupler_from_debug_sb_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_opcode (_coupler_from_debug_sb_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_size (_coupler_from_debug_sb_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_address (_coupler_from_debug_sb_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_mask (_coupler_from_debug_sb_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_data (_coupler_from_debug_sb_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_anon_in_0_d_ready (_coupler_from_debug_sb_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_anon_in_0_d_valid (_fbus_xbar_auto_anon_in_0_d_valid), .auto_anon_in_0_d_bits_opcode (_fbus_xbar_auto_anon_in_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (_fbus_xbar_auto_anon_in_0_d_bits_param), .auto_anon_in_0_d_bits_size (_fbus_xbar_auto_anon_in_0_d_bits_size), .auto_anon_in_0_d_bits_sink (_fbus_xbar_auto_anon_in_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (_fbus_xbar_auto_anon_in_0_d_bits_denied), .auto_anon_in_0_d_bits_data (_fbus_xbar_auto_anon_in_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (_fbus_xbar_auto_anon_in_0_d_bits_corrupt), .auto_anon_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_anon_out_a_valid (_fbus_xbar_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fbus_xbar_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fbus_xbar_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fbus_xbar_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fbus_xbar_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fbus_xbar_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fbus_xbar_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fbus_xbar_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fbus_xbar_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fbus_xbar_auto_anon_out_d_ready), .auto_anon_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[BusWrapper.scala:240:32] TLBuffer_a32d64s5k5z4u buffer ( // @[Buffer.scala:75:28] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_fbus_xbar_auto_anon_out_a_valid), // @[BusWrapper.scala:240:32] .auto_in_a_bits_opcode (_fbus_xbar_auto_anon_out_a_bits_opcode), // @[BusWrapper.scala:240:32] .auto_in_a_bits_param (_fbus_xbar_auto_anon_out_a_bits_param), // @[BusWrapper.scala:240:32] .auto_in_a_bits_size (_fbus_xbar_auto_anon_out_a_bits_size), // @[BusWrapper.scala:240:32] .auto_in_a_bits_source (_fbus_xbar_auto_anon_out_a_bits_source), // @[BusWrapper.scala:240:32] .auto_in_a_bits_address (_fbus_xbar_auto_anon_out_a_bits_address), // @[BusWrapper.scala:240:32] .auto_in_a_bits_mask (_fbus_xbar_auto_anon_out_a_bits_mask), // @[BusWrapper.scala:240:32] .auto_in_a_bits_data (_fbus_xbar_auto_anon_out_a_bits_data), // @[BusWrapper.scala:240:32] .auto_in_a_bits_corrupt (_fbus_xbar_auto_anon_out_a_bits_corrupt), // @[BusWrapper.scala:240:32] .auto_in_d_ready (_fbus_xbar_auto_anon_out_d_ready), // @[BusWrapper.scala:240:32] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (auto_bus_xing_out_a_ready), .auto_out_a_valid (auto_bus_xing_out_a_valid), .auto_out_a_bits_opcode (auto_bus_xing_out_a_bits_opcode), .auto_out_a_bits_param (auto_bus_xing_out_a_bits_param), .auto_out_a_bits_size (auto_bus_xing_out_a_bits_size), .auto_out_a_bits_source (auto_bus_xing_out_a_bits_source), .auto_out_a_bits_address (auto_bus_xing_out_a_bits_address), .auto_out_a_bits_mask (auto_bus_xing_out_a_bits_mask), .auto_out_a_bits_data (auto_bus_xing_out_a_bits_data), .auto_out_a_bits_corrupt (auto_bus_xing_out_a_bits_corrupt), .auto_out_d_ready (auto_bus_xing_out_d_ready), .auto_out_d_valid (auto_bus_xing_out_d_valid), .auto_out_d_bits_opcode (auto_bus_xing_out_d_bits_opcode), .auto_out_d_bits_param (auto_bus_xing_out_d_bits_param), .auto_out_d_bits_size (auto_bus_xing_out_d_bits_size), .auto_out_d_bits_source (auto_bus_xing_out_d_bits_source), .auto_out_d_bits_sink (auto_bus_xing_out_d_bits_sink), .auto_out_d_bits_denied (auto_bus_xing_out_d_bits_denied), .auto_out_d_bits_data (auto_bus_xing_out_d_bits_data), .auto_out_d_bits_corrupt (auto_bus_xing_out_d_bits_corrupt) ); // @[Buffer.scala:75:28] TLInterconnectCoupler_fbus_from_debug_sb coupler_from_debug_sb ( // @[LazyScope.scala:98:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_widget_anon_in_a_ready (auto_coupler_from_debug_sb_widget_anon_in_a_ready), .auto_widget_anon_in_a_valid (auto_coupler_from_debug_sb_widget_anon_in_a_valid), .auto_widget_anon_in_a_bits_opcode (auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode), .auto_widget_anon_in_a_bits_size (auto_coupler_from_debug_sb_widget_anon_in_a_bits_size), .auto_widget_anon_in_a_bits_address (auto_coupler_from_debug_sb_widget_anon_in_a_bits_address), .auto_widget_anon_in_a_bits_data (auto_coupler_from_debug_sb_widget_anon_in_a_bits_data), .auto_widget_anon_in_d_ready (auto_coupler_from_debug_sb_widget_anon_in_d_ready), .auto_widget_anon_in_d_valid (auto_coupler_from_debug_sb_widget_anon_in_d_valid), .auto_widget_anon_in_d_bits_opcode (auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), .auto_widget_anon_in_d_bits_param (auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), .auto_widget_anon_in_d_bits_size (auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), .auto_widget_anon_in_d_bits_sink (auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), .auto_widget_anon_in_d_bits_denied (auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), .auto_widget_anon_in_d_bits_data (auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), .auto_tl_out_a_ready (_fbus_xbar_auto_anon_in_0_a_ready), // @[BusWrapper.scala:240:32] .auto_tl_out_a_valid (_coupler_from_debug_sb_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_from_debug_sb_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_size (_coupler_from_debug_sb_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_address (_coupler_from_debug_sb_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_from_debug_sb_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_from_debug_sb_auto_tl_out_a_bits_data), .auto_tl_out_d_ready (_coupler_from_debug_sb_auto_tl_out_d_ready), .auto_tl_out_d_valid (_fbus_xbar_auto_anon_in_0_d_valid), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_opcode (_fbus_xbar_auto_anon_in_0_d_bits_opcode), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_param (_fbus_xbar_auto_anon_in_0_d_bits_param), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_size (_fbus_xbar_auto_anon_in_0_d_bits_size), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_sink (_fbus_xbar_auto_anon_in_0_d_bits_sink), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_denied (_fbus_xbar_auto_anon_in_0_d_bits_denied), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_data (_fbus_xbar_auto_anon_in_0_d_bits_data), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_corrupt (_fbus_xbar_auto_anon_in_0_d_bits_corrupt) // @[BusWrapper.scala:240:32] ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in coupler_from_port_named_serial_tl_0_in ( // @[LazyScope.scala:98:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_buffer_in_a_ready (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), .auto_buffer_in_a_valid (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid), .auto_buffer_in_a_bits_opcode (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode), .auto_buffer_in_a_bits_param (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param), .auto_buffer_in_a_bits_size (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size), .auto_buffer_in_a_bits_source (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source), .auto_buffer_in_a_bits_address (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address), .auto_buffer_in_a_bits_mask (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask), .auto_buffer_in_a_bits_data (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data), .auto_buffer_in_a_bits_corrupt (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt), .auto_buffer_in_d_ready (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready), .auto_buffer_in_d_valid (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), .auto_buffer_in_d_bits_opcode (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), .auto_buffer_in_d_bits_param (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), .auto_buffer_in_d_bits_size (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), .auto_buffer_in_d_bits_source (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), .auto_buffer_in_d_bits_sink (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), .auto_buffer_in_d_bits_denied (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), .auto_buffer_in_d_bits_data (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), .auto_buffer_in_d_bits_corrupt (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), .auto_tl_out_a_ready (_fbus_xbar_auto_anon_in_1_a_ready), // @[BusWrapper.scala:240:32] .auto_tl_out_a_valid (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_param (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_param), .auto_tl_out_a_bits_size (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_source (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_source), .auto_tl_out_a_bits_address (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_data), .auto_tl_out_a_bits_corrupt (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_corrupt), .auto_tl_out_d_ready (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_d_ready), .auto_tl_out_d_valid (_fbus_xbar_auto_anon_in_1_d_valid), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_opcode (_fbus_xbar_auto_anon_in_1_d_bits_opcode), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_param (_fbus_xbar_auto_anon_in_1_d_bits_param), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_size (_fbus_xbar_auto_anon_in_1_d_bits_size), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_source (_fbus_xbar_auto_anon_in_1_d_bits_source), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_sink (_fbus_xbar_auto_anon_in_1_d_bits_sink), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_denied (_fbus_xbar_auto_anon_in_1_d_bits_denied), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_data (_fbus_xbar_auto_anon_in_1_d_bits_data), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_corrupt (_fbus_xbar_auto_anon_in_1_d_bits_corrupt) // @[BusWrapper.scala:240:32] ); // @[LazyScope.scala:98:27] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_88 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_177 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_178 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_179 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_180 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_88( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_4 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_260 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_4( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_260 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_1 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<2>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 1, 0) node _req_clientBit_T = shr(request.source, 2) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<4>(0h8)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<2>(0h2)) node req_clientBit = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<2>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 1, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 2) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<4>(0h8)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<2>(0h2)) node probe_bit = and(_probe_bit_T_3, _probe_bit_T_4) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<2>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 1, 0) node _new_clientBit_T = shr(new_request.source, 2) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<4>(0h8)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<2>(0h2)) node new_clientBit = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_1( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire req_clientBit = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:56:48] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire probe_bit = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:56:48] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire new_clientBit = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module PE_237 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_237( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a21d64s10k1z3u_1 : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleA_a21d64s10k1z3u_1( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [20:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [20:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [9:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [20:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [9:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [20:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [9:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [20:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [9:0] saved_source; // @[Repeater.scala:21:18] reg [20:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_8 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}} inst input_buffer of InputBuffer_8 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) inst route_arbiter of Arbiter6_RouteComputerReq_8 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<6>}[6], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(UInt<2>(0h2), io.in.flit[0].bits.flow.egress_node_id) when _T_11 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_12 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_12 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_13 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_13 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_14 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_14 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_15 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_15 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_16 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_16 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_17 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_17 : connect states[5].g, UInt<3>(0h2) node _T_18 = and(io.router_req.ready, io.router_req.valid) when _T_18 : node _T_19 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_19, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_23 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_23 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_24 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_24 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_25 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_25 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_26 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_26 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_27 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_27 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_28 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_28 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<6>, clock, reset, UInt<6>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}[6] wire vcalloc_vals : UInt<1>[6] node vcalloc_filter_lo_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[3]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[3]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_16, UInt<12>(0h800), UInt<12>(0h0)) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_15, UInt<12>(0h400), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_14, UInt<12>(0h200), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_13, UInt<12>(0h100), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_12, UInt<12>(0h80), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_11, UInt<12>(0h40), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_10, UInt<12>(0h20), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_9, UInt<12>(0h10), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_8, UInt<12>(0h8), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_7, UInt<12>(0h4), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_6, UInt<12>(0h2), _vcalloc_filter_T_26) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<12>(0h1), _vcalloc_filter_T_27) node _vcalloc_sel_T = bits(vcalloc_filter, 5, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 6) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_29 = and(io.router_req.ready, io.router_req.valid) when _T_29 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_31 = or(_T_30, vcalloc_vals[2]) node _T_32 = or(_T_31, vcalloc_vals[3]) node _T_33 = or(_T_32, vcalloc_vals[4]) node _T_34 = or(_T_33, vcalloc_vals[5]) when _T_34 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = bits(vcalloc_sel, 0, 0) node _mask_T_10 = bits(vcalloc_sel, 1, 1) node _mask_T_11 = bits(vcalloc_sel, 2, 2) node _mask_T_12 = bits(vcalloc_sel, 3, 3) node _mask_T_13 = bits(vcalloc_sel, 4, 4) node _mask_T_14 = bits(vcalloc_sel, 5, 5) node _mask_T_15 = mux(_mask_T_9, _mask_T_3, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_10, _mask_T_4, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_11, _mask_T_5, UInt<1>(0h0)) node _mask_T_18 = mux(_mask_T_12, _mask_T_6, UInt<1>(0h0)) node _mask_T_19 = mux(_mask_T_13, _mask_T_7, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_14, _mask_T_8, UInt<1>(0h0)) node _mask_T_21 = or(_mask_T_15, _mask_T_16) node _mask_T_22 = or(_mask_T_21, _mask_T_17) node _mask_T_23 = or(_mask_T_22, _mask_T_18) node _mask_T_24 = or(_mask_T_23, _mask_T_19) node _mask_T_25 = or(_mask_T_24, _mask_T_20) wire _mask_WIRE : UInt<6> connect _mask_WIRE, _mask_T_25 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_4 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[6] node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_14 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_15 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_15, _io_vcalloc_req_bits_T_11) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_20) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_21) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_22) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_33) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_38 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_44) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_60 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_68 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_63) node _io_vcalloc_req_bits_T_69 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_70 = or(_io_vcalloc_req_bits_T_69, _io_vcalloc_req_bits_T_65) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_70, _io_vcalloc_req_bits_T_66) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_71 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>[1] node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_72, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_76) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_77) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_9[0], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_9 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[1] node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_90 = or(_io_vcalloc_req_bits_T_89, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_90, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_88) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_93 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[1] node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_95) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_113 = or(_io_vcalloc_req_bits_T_112, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_114 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_114, _io_vcalloc_req_bits_T_110) wire _io_vcalloc_req_bits_WIRE_15 : UInt<3> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_115 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_15 wire _io_vcalloc_req_bits_WIRE_16 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_120) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_121) wire _io_vcalloc_req_bits_WIRE_17 : UInt<2> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_126 connect _io_vcalloc_req_bits_WIRE_16.egress_node_id, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_133, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_132) wire _io_vcalloc_req_bits_WIRE_18 : UInt<4> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_137 connect _io_vcalloc_req_bits_WIRE_16.egress_node, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_138 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_139 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_139) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_144, _io_vcalloc_req_bits_T_140) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_143) wire _io_vcalloc_req_bits_WIRE_19 : UInt<2> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE_16.ingress_node_id, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_154 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_149, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_152) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_153) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_154) wire _io_vcalloc_req_bits_WIRE_20 : UInt<4> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_159 connect _io_vcalloc_req_bits_WIRE_16.ingress_node, _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_21 : UInt<2> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_170 connect _io_vcalloc_req_bits_WIRE_16.vnet_id, _io_vcalloc_req_bits_WIRE_21 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_16 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].flow, states[0].flow node _T_35 = bits(vcalloc_sel, 0, 0) node _T_36 = and(vcalloc_vals[0], _T_35) node _T_37 = and(_T_36, io.vcalloc_req.ready) when _T_37 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_38 = bits(vcalloc_sel, 1, 1) node _T_39 = and(vcalloc_vals[1], _T_38) node _T_40 = and(_T_39, io.vcalloc_req.ready) when _T_40 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].flow, states[2].flow node _T_41 = bits(vcalloc_sel, 2, 2) node _T_42 = and(vcalloc_vals[2], _T_41) node _T_43 = and(_T_42, io.vcalloc_req.ready) when _T_43 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].flow, states[3].flow node _T_44 = bits(vcalloc_sel, 3, 3) node _T_45 = and(vcalloc_vals[3], _T_44) node _T_46 = and(_T_45, io.vcalloc_req.ready) when _T_46 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].flow, states[4].flow node _T_47 = bits(vcalloc_sel, 4, 4) node _T_48 = and(vcalloc_vals[4], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].flow, states[5].flow node _T_50 = bits(vcalloc_sel, 5, 5) node _T_51 = and(vcalloc_vals[5], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[5].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[3], _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(_io_debug_va_stall_T_3, _io_debug_va_stall_T_7) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 2, 0) node _io_debug_va_stall_T_10 = sub(_io_debug_va_stall_T_9, io.vcalloc_req.ready) node _io_debug_va_stall_T_11 = tail(_io_debug_va_stall_T_10, 1) connect io.debug.va_stall, _io_debug_va_stall_T_11 node _T_53 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_53 : node _T_54 = bits(vcalloc_sel, 0, 0) when _T_54 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_55 = eq(states[0].g, UInt<3>(0h2)) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = bits(vcalloc_sel, 1, 1) when _T_59 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_60 = eq(states[1].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_60, UInt<1>(0h1), "") : assert_4 node _T_64 = bits(vcalloc_sel, 2, 2) when _T_64 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) node _T_65 = eq(states[2].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_65, UInt<1>(0h1), "") : assert_5 node _T_69 = bits(vcalloc_sel, 3, 3) when _T_69 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].g, UInt<3>(0h3) node _T_70 = eq(states[3].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_70, UInt<1>(0h1), "") : assert_6 node _T_74 = bits(vcalloc_sel, 4, 4) when _T_74 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].g, UInt<3>(0h3) node _T_75 = eq(states[4].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_75, UInt<1>(0h1), "") : assert_7 node _T_79 = bits(vcalloc_sel, 5, 5) when _T_79 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].g, UInt<3>(0h3) node _T_80 = eq(states[5].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_80, UInt<1>(0h1), "") : assert_8 inst salloc_arb of SwitchArbiter_24 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1]) node credit_available_lo = cat(credit_available_lo_hi, states[0].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4]) node credit_available_hi = cat(credit_available_hi_hi, states[0].vc_sel.`0`[3]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_1 = cat(states[0].vc_sel.`1`[0], _credit_available_T) node credit_available_hi_1 = cat(states[0].vc_sel.`3`[0], states[0].vc_sel.`2`[0]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_2 = cat(credit_available_lo_hi_1, io.out_credit_available.`0`[0]) node credit_available_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_2 = cat(credit_available_hi_hi_1, io.out_credit_available.`0`[3]) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2) node credit_available_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3) node credit_available = neq(_credit_available_T_4, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_84 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_85 = and(_T_84, input_buffer.io.deq[0].bits.tail) when _T_85 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_hi_2 = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1]) node credit_available_lo_4 = cat(credit_available_lo_hi_2, states[1].vc_sel.`0`[0]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_4 = cat(credit_available_hi_hi_2, states[1].vc_sel.`0`[3]) node _credit_available_T_5 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_5 = cat(states[1].vc_sel.`1`[0], _credit_available_T_5) node credit_available_hi_5 = cat(states[1].vc_sel.`3`[0], states[1].vc_sel.`2`[0]) node _credit_available_T_6 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_6 = cat(credit_available_lo_hi_3, io.out_credit_available.`0`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_6 = cat(credit_available_hi_hi_3, io.out_credit_available.`0`[3]) node _credit_available_T_7 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_7 = cat(io.out_credit_available.`1`[0], _credit_available_T_7) node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_8 = cat(credit_available_hi_7, credit_available_lo_7) node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8) node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_86 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_87 = and(_T_86, input_buffer.io.deq[1].bits.tail) when _T_87 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_hi_4 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) node credit_available_lo_8 = cat(credit_available_lo_hi_4, states[2].vc_sel.`0`[0]) node credit_available_hi_hi_4 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_8 = cat(credit_available_hi_hi_4, states[2].vc_sel.`0`[3]) node _credit_available_T_10 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_9 = cat(states[2].vc_sel.`1`[0], _credit_available_T_10) node credit_available_hi_9 = cat(states[2].vc_sel.`3`[0], states[2].vc_sel.`2`[0]) node _credit_available_T_11 = cat(credit_available_hi_9, credit_available_lo_9) node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_10 = cat(credit_available_lo_hi_5, io.out_credit_available.`0`[0]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_10 = cat(credit_available_hi_hi_5, io.out_credit_available.`0`[3]) node _credit_available_T_12 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_11 = cat(io.out_credit_available.`1`[0], _credit_available_T_12) node credit_available_hi_11 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_13 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13) node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_88 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_89 = and(_T_88, input_buffer.io.deq[2].bits.tail) when _T_89 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_hi_6 = cat(states[3].vc_sel.`0`[2], states[3].vc_sel.`0`[1]) node credit_available_lo_12 = cat(credit_available_lo_hi_6, states[3].vc_sel.`0`[0]) node credit_available_hi_hi_6 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_12 = cat(credit_available_hi_hi_6, states[3].vc_sel.`0`[3]) node _credit_available_T_15 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_13 = cat(states[3].vc_sel.`1`[0], _credit_available_T_15) node credit_available_hi_13 = cat(states[3].vc_sel.`3`[0], states[3].vc_sel.`2`[0]) node _credit_available_T_16 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_hi_7 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_14 = cat(credit_available_lo_hi_7, io.out_credit_available.`0`[0]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_14 = cat(credit_available_hi_hi_7, io.out_credit_available.`0`[3]) node _credit_available_T_17 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_15 = cat(io.out_credit_available.`1`[0], _credit_available_T_17) node credit_available_hi_15 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_18 = cat(credit_available_hi_15, credit_available_lo_15) node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18) node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_90 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_91 = and(_T_90, input_buffer.io.deq[3].bits.tail) when _T_91 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_hi_8 = cat(states[4].vc_sel.`0`[2], states[4].vc_sel.`0`[1]) node credit_available_lo_16 = cat(credit_available_lo_hi_8, states[4].vc_sel.`0`[0]) node credit_available_hi_hi_8 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_16 = cat(credit_available_hi_hi_8, states[4].vc_sel.`0`[3]) node _credit_available_T_20 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_17 = cat(states[4].vc_sel.`1`[0], _credit_available_T_20) node credit_available_hi_17 = cat(states[4].vc_sel.`3`[0], states[4].vc_sel.`2`[0]) node _credit_available_T_21 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_hi_9 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_18 = cat(credit_available_lo_hi_9, io.out_credit_available.`0`[0]) node credit_available_hi_hi_9 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_18 = cat(credit_available_hi_hi_9, io.out_credit_available.`0`[3]) node _credit_available_T_22 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_19 = cat(io.out_credit_available.`1`[0], _credit_available_T_22) node credit_available_hi_19 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_23 = cat(credit_available_hi_19, credit_available_lo_19) node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23) node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_92 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_93 = and(_T_92, input_buffer.io.deq[4].bits.tail) when _T_93 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_hi_10 = cat(states[5].vc_sel.`0`[2], states[5].vc_sel.`0`[1]) node credit_available_lo_20 = cat(credit_available_lo_hi_10, states[5].vc_sel.`0`[0]) node credit_available_hi_hi_10 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_20 = cat(credit_available_hi_hi_10, states[5].vc_sel.`0`[3]) node _credit_available_T_25 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_21 = cat(states[5].vc_sel.`1`[0], _credit_available_T_25) node credit_available_hi_21 = cat(states[5].vc_sel.`3`[0], states[5].vc_sel.`2`[0]) node _credit_available_T_26 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_hi_11 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_22 = cat(credit_available_lo_hi_11, io.out_credit_available.`0`[0]) node credit_available_hi_hi_11 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_22 = cat(credit_available_hi_hi_11, io.out_credit_available.`0`[3]) node _credit_available_T_27 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_23 = cat(io.out_credit_available.`1`[0], _credit_available_T_27) node credit_available_hi_23 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_28 = cat(credit_available_hi_23, credit_available_lo_23) node _credit_available_T_29 = and(_credit_available_T_26, _credit_available_T_28) node credit_available_5 = neq(_credit_available_T_29, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_94 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_95 = and(_T_94, input_buffer.io.deq[5].bits.tail) when _T_95 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_17) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_21 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_8) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_9) node _io_in_vc_free_T_15 = or(_io_in_vc_free_T_14, _io_in_vc_free_T_10) node _io_in_vc_free_T_16 = or(_io_in_vc_free_T_15, _io_in_vc_free_T_11) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_16, _io_in_vc_free_T_12) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_17 node _io_in_vc_free_T_18 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_18, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_19 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 5, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _vc_sel_WIRE : UInt<1>[6] node _vc_sel_T_6 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = or(_vc_sel_T_6, _vc_sel_T_7) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_8) node _vc_sel_T_14 = or(_vc_sel_T_13, _vc_sel_T_9) node _vc_sel_T_15 = or(_vc_sel_T_14, _vc_sel_T_10) node _vc_sel_T_16 = or(_vc_sel_T_15, _vc_sel_T_11) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_16 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_21 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_22 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_23 = or(_vc_sel_T_17, _vc_sel_T_18) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_19) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_20) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_21) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_22) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_27 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_34 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_30) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_31) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_32) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_33) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_38 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_39 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_45 = or(_vc_sel_T_39, _vc_sel_T_40) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_41) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_42) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_43) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_44) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_49 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_56 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_52) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_53) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_54) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_55) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_60 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_61 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_64 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_65 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_66 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_67 = or(_vc_sel_T_61, _vc_sel_T_62) node _vc_sel_T_68 = or(_vc_sel_T_67, _vc_sel_T_63) node _vc_sel_T_69 = or(_vc_sel_T_68, _vc_sel_T_64) node _vc_sel_T_70 = or(_vc_sel_T_69, _vc_sel_T_65) node _vc_sel_T_71 = or(_vc_sel_T_70, _vc_sel_T_66) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_71 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_7 : UInt<1>[1] node _vc_sel_T_72 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_77 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_78 = or(_vc_sel_T_72, _vc_sel_T_73) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_74) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_75) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_76) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_77) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_82 connect _vc_sel_WIRE_7[0], _vc_sel_WIRE_8 connect vc_sel.`1`, _vc_sel_WIRE_7 wire _vc_sel_WIRE_9 : UInt<1>[1] node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_89 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_90 = or(_vc_sel_T_89, _vc_sel_T_85) node _vc_sel_T_91 = or(_vc_sel_T_90, _vc_sel_T_86) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_87) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_88) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_93 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 connect vc_sel.`2`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_11 : UInt<1>[1] node _vc_sel_T_94 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_96 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_97 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_98 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_100 = or(_vc_sel_T_94, _vc_sel_T_95) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_96) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_97) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_98) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_99) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_104 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 connect vc_sel.`3`, _vc_sel_WIRE_11 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node channel_oh_0 = or(_channel_oh_T_3, vc_sel.`0`[5]) node virt_channel_lo_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node virt_channel_lo = cat(virt_channel_lo_hi, vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[3]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 5, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_9 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_10 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_11 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_12 = or(_virt_channel_T_8, _virt_channel_T_9) node _virt_channel_T_13 = or(_virt_channel_T_12, _virt_channel_T_10) node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_11) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_14 node _T_96 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_96 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_14 = or(_salloc_outs_0_flit_payload_T_13, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_15 = or(_salloc_outs_0_flit_payload_T_14, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_15, _salloc_outs_0_flit_payload_T_11) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_16 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_14 = or(_salloc_outs_0_flit_head_T_13, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_15 = or(_salloc_outs_0_flit_head_T_14, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_15, _salloc_outs_0_flit_head_T_11) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_16 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_14 = or(_salloc_outs_0_flit_tail_T_13, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_15 = or(_salloc_outs_0_flit_tail_T_14, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_15, _salloc_outs_0_flit_tail_T_11) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_16 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_14 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_15 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_15, _salloc_outs_0_flit_flow_T_11) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_22 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_20) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_21) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_22) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_33) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_38 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_44) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_57 = or(_salloc_outs_0_flit_flow_T_56, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_57, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_55) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_60 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`0`[3], UInt<1>(0h0) connect states[0].vc_sel.`0`[4], UInt<1>(0h0) connect states[0].vc_sel.`0`[5], UInt<1>(0h0) connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`0`[5], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[3], UInt<1>(0h0) connect states[2].vc_sel.`0`[4], UInt<1>(0h0) connect states[2].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) node _T_97 = asUInt(reset) when _T_97 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0)	module InputUnit_8( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [5:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [5:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [5:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [5:0] mask; // @[InputUnit.scala:250:21] wire [5:0] _vcalloc_filter_T_3 = {vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [11:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 12'h1 : _vcalloc_filter_T_3[1] ? 12'h2 : _vcalloc_filter_T_3[2] ? 12'h4 : _vcalloc_filter_T_3[3] ? 12'h8 : _vcalloc_filter_T_3[4] ? 12'h10 : _vcalloc_filter_T_3[5] ? 12'h20 : vcalloc_vals_0 ? 12'h40 : vcalloc_vals_1 ? 12'h80 : vcalloc_vals_2 ? 12'h100 : vcalloc_vals_3 ? 12'h200 : vcalloc_vals_4 ? 12'h400 : {vcalloc_vals_5, 11'h0}; // @[OneHot.scala:85:71] wire [5:0] vcalloc_sel = vcalloc_filter[5:0] \| vcalloc_filter[11:6]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 \| vcalloc_vals_1 \| vcalloc_vals_2 \| vcalloc_vals_3 \| vcalloc_vals_4 \| vcalloc_vals_5; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_33 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_33( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_12 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<8>(0h80)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}} connect _WIRE_4.bits.sink, UInt<7>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_24 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_25 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_26 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_27 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_12( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module BoomTraceGenTile_1 : input clock : Clock input reset : Reset output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, status_out : { timeout : { valid : UInt<1>, bits : UInt<4>}, error : { valid : UInt<1>, bits : UInt<4>}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>} inst tlMasterXbar of TLXbar_MasterXbar_BoomTraceGenTile_i0_o0_a1d8s1k1z1u_1 connect tlMasterXbar.clock, clock connect tlMasterXbar.reset, reset inst tlSlaveXbar of TLXbar_SlaveXbar_BoomTraceGenTile_i0_o0_a1d8s1k1z1u_1 connect tlSlaveXbar.clock, clock connect tlSlaveXbar.reset, reset inst intXbar of IntXbar_i4_o1_1 inst broadcast of BundleBridgeNexus_UInt1_1 inst broadcast_1 of BundleBridgeNexus_UInt32_1 inst nexus of BundleBridgeNexus_NoOutput_8 inst nexus_1 of BundleBridgeNexus_TraceAux_1 inst broadcast_2 of BundleBridgeNexus_NoOutput_9 inst dcache of BoomNonBlockingDCache_1 connect dcache.clock, clock connect dcache.reset, reset inst buffer of TLBuffer_a32d64s4k3z4c_2 connect buffer.clock, clock connect buffer.reset, reset inst buffer_1 of TLBuffer_5 connect buffer_1.clock, clock connect buffer_1.reset, reset wire hartIdSinkNodeIn : UInt<1> invalidate hartIdSinkNodeIn wire hartidOut : UInt<1> invalidate hartidOut wire hartidIn : UInt<1> invalidate hartidIn connect hartidOut, hartidIn wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn wire reset_vectorOut : UInt<32> invalidate reset_vectorOut wire reset_vectorIn : UInt<32> invalidate reset_vectorIn connect reset_vectorOut, reset_vectorIn wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceSourceNodeOut.time invalidate traceSourceNodeOut.insns[0].tval invalidate traceSourceNodeOut.insns[0].cause invalidate traceSourceNodeOut.insns[0].interrupt invalidate traceSourceNodeOut.insns[0].exception invalidate traceSourceNodeOut.insns[0].priv invalidate traceSourceNodeOut.insns[0].insn invalidate traceSourceNodeOut.insns[0].iaddr invalidate traceSourceNodeOut.insns[0].valid wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreSourceNodeOut.cause invalidate traceCoreSourceNodeOut.tval invalidate traceCoreSourceNodeOut.priv invalidate traceCoreSourceNodeOut.group[0].ilastsize invalidate traceCoreSourceNodeOut.group[0].itype invalidate traceCoreSourceNodeOut.group[0].iaddr invalidate traceCoreSourceNodeOut.group[0].iretire wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>} connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0) connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0) wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>} invalidate traceAuxSinkNodeIn.stall invalidate traceAuxSinkNodeIn.enable wire bpwatchSourceNodeOut : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1] invalidate bpwatchSourceNodeOut[0].action invalidate bpwatchSourceNodeOut[0].ivalid[0] invalidate bpwatchSourceNodeOut[0].wvalid[0] invalidate bpwatchSourceNodeOut[0].rvalid[0] invalidate bpwatchSourceNodeOut[0].valid[0] wire int_localOut : UInt<1>[1] invalidate int_localOut[0] wire x1_int_localOut : UInt<1>[2] invalidate x1_int_localOut[0] invalidate x1_int_localOut[1] wire x1_int_localOut_1 : UInt<1>[1] invalidate x1_int_localOut_1[0] wire x1_int_localOut_2 : UInt<1>[1] invalidate x1_int_localOut_2[0] wire int_localIn : UInt<1>[1] invalidate int_localIn[0] wire x1_int_localIn : UInt<1>[2] invalidate x1_int_localIn[0] invalidate x1_int_localIn[1] wire x1_int_localIn_1 : UInt<1>[1] invalidate x1_int_localIn_1[0] wire x1_int_localIn_2 : UInt<1>[1] invalidate x1_int_localIn_2[0] connect int_localOut, int_localIn connect x1_int_localOut, x1_int_localIn connect x1_int_localOut_1, x1_int_localIn_1 connect x1_int_localOut_2, x1_int_localIn_2 wire intSinkNodeIn : UInt<1>[5] invalidate intSinkNodeIn[0] invalidate intSinkNodeIn[1] invalidate intSinkNodeIn[2] invalidate intSinkNodeIn[3] invalidate intSinkNodeIn[4] wire haltNodeOut : UInt<1>[1] invalidate haltNodeOut[0] wire ceaseNodeOut : UInt<1>[1] invalidate ceaseNodeOut[0] wire wfiNodeOut : UInt<1>[1] invalidate wfiNodeOut[0] wire statusNodeOut : { timeout : { valid : UInt<1>, bits : UInt<4>}, error : { valid : UInt<1>, bits : UInt<4>}} invalidate statusNodeOut.error.bits invalidate statusNodeOut.error.valid invalidate statusNodeOut.timeout.bits invalidate statusNodeOut.timeout.valid wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate masterNodeOut.e.bits.sink invalidate masterNodeOut.e.valid invalidate masterNodeOut.e.ready invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.c.bits.corrupt invalidate masterNodeOut.c.bits.data invalidate masterNodeOut.c.bits.address invalidate masterNodeOut.c.bits.source invalidate masterNodeOut.c.bits.size invalidate masterNodeOut.c.bits.param invalidate masterNodeOut.c.bits.opcode invalidate masterNodeOut.c.valid invalidate masterNodeOut.c.ready invalidate masterNodeOut.b.bits.corrupt invalidate masterNodeOut.b.bits.data invalidate masterNodeOut.b.bits.mask invalidate masterNodeOut.b.bits.address invalidate masterNodeOut.b.bits.source invalidate masterNodeOut.b.bits.size invalidate masterNodeOut.b.bits.param invalidate masterNodeOut.b.bits.opcode invalidate masterNodeOut.b.valid invalidate masterNodeOut.b.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready wire masterNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate masterNodeIn.e.bits.sink invalidate masterNodeIn.e.valid invalidate masterNodeIn.e.ready invalidate masterNodeIn.d.bits.corrupt invalidate masterNodeIn.d.bits.data invalidate masterNodeIn.d.bits.denied invalidate masterNodeIn.d.bits.sink invalidate masterNodeIn.d.bits.source invalidate masterNodeIn.d.bits.size invalidate masterNodeIn.d.bits.param invalidate masterNodeIn.d.bits.opcode invalidate masterNodeIn.d.valid invalidate masterNodeIn.d.ready invalidate masterNodeIn.c.bits.corrupt invalidate masterNodeIn.c.bits.data invalidate masterNodeIn.c.bits.address invalidate masterNodeIn.c.bits.source invalidate masterNodeIn.c.bits.size invalidate masterNodeIn.c.bits.param invalidate masterNodeIn.c.bits.opcode invalidate masterNodeIn.c.valid invalidate masterNodeIn.c.ready invalidate masterNodeIn.b.bits.corrupt invalidate masterNodeIn.b.bits.data invalidate masterNodeIn.b.bits.mask invalidate masterNodeIn.b.bits.address invalidate masterNodeIn.b.bits.source invalidate masterNodeIn.b.bits.size invalidate masterNodeIn.b.bits.param invalidate masterNodeIn.b.bits.opcode invalidate masterNodeIn.b.valid invalidate masterNodeIn.b.ready invalidate masterNodeIn.a.bits.corrupt invalidate masterNodeIn.a.bits.data invalidate masterNodeIn.a.bits.mask invalidate masterNodeIn.a.bits.address invalidate masterNodeIn.a.bits.source invalidate masterNodeIn.a.bits.size invalidate masterNodeIn.a.bits.param invalidate masterNodeIn.a.bits.opcode invalidate masterNodeIn.a.valid invalidate masterNodeIn.a.ready connect masterNodeOut, masterNodeIn connect intSinkNodeIn, intXbar.auto.anon_out connect hartIdSinkNodeIn, broadcast.auto.out connect broadcast.auto.in, hartidOut connect resetVectorSinkNodeIn, broadcast_1.auto.out connect broadcast_1.auto.in, reset_vectorOut connect traceAuxSinkNodeIn, nexus_1.auto.out connect broadcast_2.auto.in[0], bpwatchSourceNodeOut[0] connect intXbar.auto.anon_in_0[0], int_localOut[0] connect intXbar.auto.anon_in_1[0], x1_int_localOut[0] connect intXbar.auto.anon_in_1[1], x1_int_localOut[1] connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0] connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0] connect masterNodeIn.e.bits, dcache.auto.out.e.bits connect masterNodeIn.e.valid, dcache.auto.out.e.valid connect dcache.auto.out.e.ready, masterNodeIn.e.ready connect dcache.auto.out.d, masterNodeIn.d connect masterNodeIn.c.bits, dcache.auto.out.c.bits connect masterNodeIn.c.valid, dcache.auto.out.c.valid connect dcache.auto.out.c.ready, masterNodeIn.c.ready connect dcache.auto.out.b, masterNodeIn.b connect masterNodeIn.a.bits, dcache.auto.out.a.bits connect masterNodeIn.a.valid, dcache.auto.out.a.valid connect dcache.auto.out.a.ready, masterNodeIn.a.ready connect buffer.auto.in, masterNodeOut connect hartidIn, auto.hartid_in connect reset_vectorIn, auto.reset_vector_in connect auto.trace_source_out, traceSourceNodeOut connect auto.trace_core_source_out, traceCoreSourceNodeOut connect int_localIn, auto.int_local_in_0 connect x1_int_localIn, auto.int_local_in_1 connect x1_int_localIn_1, auto.int_local_in_2 connect x1_int_localIn_2, auto.int_local_in_3 connect auto.halt_out, haltNodeOut connect auto.cease_out, ceaseNodeOut connect auto.wfi_out, wfiNodeOut connect auto.status_out, statusNodeOut connect auto.buffer_out.e.bits, buffer.auto.out.e.bits connect auto.buffer_out.e.valid, buffer.auto.out.e.valid connect buffer.auto.out.e.ready, auto.buffer_out.e.ready connect buffer.auto.out.d, auto.buffer_out.d connect auto.buffer_out.c.bits, buffer.auto.out.c.bits connect auto.buffer_out.c.valid, buffer.auto.out.c.valid connect buffer.auto.out.c.ready, auto.buffer_out.c.ready connect buffer.auto.out.b, auto.buffer_out.b connect auto.buffer_out.a.bits, buffer.auto.out.a.bits connect auto.buffer_out.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, auto.buffer_out.a.ready inst tracegen of TraceGenerator_1 connect tracegen.clock, clock connect tracegen.reset, reset connect tracegen.io.hartid, hartIdSinkNodeIn inst ptw of DummyPTW_1 connect ptw.clock, clock connect ptw.reset, reset invalidate ptw.io.requestors[0].customCSRs.csrs[0].sdata invalidate ptw.io.requestors[0].customCSRs.csrs[0].set invalidate ptw.io.requestors[0].customCSRs.csrs[0].stall invalidate ptw.io.requestors[0].customCSRs.csrs[0].value invalidate ptw.io.requestors[0].customCSRs.csrs[0].wdata invalidate ptw.io.requestors[0].customCSRs.csrs[0].wen invalidate ptw.io.requestors[0].customCSRs.csrs[0].ren invalidate ptw.io.requestors[0].customCSRs.csrs[1].sdata invalidate ptw.io.requestors[0].customCSRs.csrs[1].set invalidate ptw.io.requestors[0].customCSRs.csrs[1].stall invalidate ptw.io.requestors[0].customCSRs.csrs[1].value invalidate ptw.io.requestors[0].customCSRs.csrs[1].wdata invalidate ptw.io.requestors[0].customCSRs.csrs[1].wen invalidate ptw.io.requestors[0].customCSRs.csrs[1].ren invalidate ptw.io.requestors[0].customCSRs.csrs[2].sdata invalidate ptw.io.requestors[0].customCSRs.csrs[2].set invalidate ptw.io.requestors[0].customCSRs.csrs[2].stall invalidate ptw.io.requestors[0].customCSRs.csrs[2].value invalidate ptw.io.requestors[0].customCSRs.csrs[2].wdata invalidate ptw.io.requestors[0].customCSRs.csrs[2].wen invalidate ptw.io.requestors[0].customCSRs.csrs[2].ren invalidate ptw.io.requestors[0].customCSRs.csrs[3].sdata invalidate ptw.io.requestors[0].customCSRs.csrs[3].set invalidate ptw.io.requestors[0].customCSRs.csrs[3].stall invalidate ptw.io.requestors[0].customCSRs.csrs[3].value invalidate ptw.io.requestors[0].customCSRs.csrs[3].wdata invalidate ptw.io.requestors[0].customCSRs.csrs[3].wen invalidate ptw.io.requestors[0].customCSRs.csrs[3].ren invalidate ptw.io.requestors[0].gstatus.uie invalidate ptw.io.requestors[0].gstatus.sie invalidate ptw.io.requestors[0].gstatus.hie invalidate ptw.io.requestors[0].gstatus.mie invalidate ptw.io.requestors[0].gstatus.upie invalidate ptw.io.requestors[0].gstatus.spie invalidate ptw.io.requestors[0].gstatus.ube invalidate ptw.io.requestors[0].gstatus.mpie invalidate ptw.io.requestors[0].gstatus.spp invalidate ptw.io.requestors[0].gstatus.vs invalidate ptw.io.requestors[0].gstatus.mpp invalidate ptw.io.requestors[0].gstatus.fs invalidate ptw.io.requestors[0].gstatus.xs invalidate ptw.io.requestors[0].gstatus.mprv invalidate ptw.io.requestors[0].gstatus.sum invalidate ptw.io.requestors[0].gstatus.mxr invalidate ptw.io.requestors[0].gstatus.tvm invalidate ptw.io.requestors[0].gstatus.tw invalidate ptw.io.requestors[0].gstatus.tsr invalidate ptw.io.requestors[0].gstatus.zero1 invalidate ptw.io.requestors[0].gstatus.sd_rv32 invalidate ptw.io.requestors[0].gstatus.uxl invalidate ptw.io.requestors[0].gstatus.sxl invalidate ptw.io.requestors[0].gstatus.sbe invalidate ptw.io.requestors[0].gstatus.mbe invalidate ptw.io.requestors[0].gstatus.gva invalidate ptw.io.requestors[0].gstatus.mpv invalidate ptw.io.requestors[0].gstatus.zero2 invalidate ptw.io.requestors[0].gstatus.sd invalidate ptw.io.requestors[0].gstatus.v invalidate ptw.io.requestors[0].gstatus.prv invalidate ptw.io.requestors[0].gstatus.dv invalidate ptw.io.requestors[0].gstatus.dprv invalidate ptw.io.requestors[0].gstatus.isa invalidate ptw.io.requestors[0].gstatus.wfi invalidate ptw.io.requestors[0].gstatus.cease invalidate ptw.io.requestors[0].gstatus.debug invalidate ptw.io.requestors[0].hstatus.zero1 invalidate ptw.io.requestors[0].hstatus.vsbe invalidate ptw.io.requestors[0].hstatus.gva invalidate ptw.io.requestors[0].hstatus.spv invalidate ptw.io.requestors[0].hstatus.spvp invalidate ptw.io.requestors[0].hstatus.hu invalidate ptw.io.requestors[0].hstatus.zero2 invalidate ptw.io.requestors[0].hstatus.vgein invalidate ptw.io.requestors[0].hstatus.zero3 invalidate ptw.io.requestors[0].hstatus.vtvm invalidate ptw.io.requestors[0].hstatus.vtw invalidate ptw.io.requestors[0].hstatus.vtsr invalidate ptw.io.requestors[0].hstatus.zero5 invalidate ptw.io.requestors[0].hstatus.vsxl invalidate ptw.io.requestors[0].hstatus.zero6 invalidate ptw.io.requestors[0].status.uie invalidate ptw.io.requestors[0].status.sie invalidate ptw.io.requestors[0].status.hie invalidate ptw.io.requestors[0].status.mie invalidate ptw.io.requestors[0].status.upie invalidate ptw.io.requestors[0].status.spie invalidate ptw.io.requestors[0].status.ube invalidate ptw.io.requestors[0].status.mpie invalidate ptw.io.requestors[0].status.spp invalidate ptw.io.requestors[0].status.vs invalidate ptw.io.requestors[0].status.mpp invalidate ptw.io.requestors[0].status.fs invalidate ptw.io.requestors[0].status.xs invalidate ptw.io.requestors[0].status.mprv invalidate ptw.io.requestors[0].status.sum invalidate ptw.io.requestors[0].status.mxr invalidate ptw.io.requestors[0].status.tvm invalidate ptw.io.requestors[0].status.tw invalidate ptw.io.requestors[0].status.tsr invalidate ptw.io.requestors[0].status.zero1 invalidate ptw.io.requestors[0].status.sd_rv32 invalidate ptw.io.requestors[0].status.uxl invalidate ptw.io.requestors[0].status.sxl invalidate ptw.io.requestors[0].status.sbe invalidate ptw.io.requestors[0].status.mbe invalidate ptw.io.requestors[0].status.gva invalidate ptw.io.requestors[0].status.mpv invalidate ptw.io.requestors[0].status.zero2 invalidate ptw.io.requestors[0].status.sd invalidate ptw.io.requestors[0].status.v invalidate ptw.io.requestors[0].status.prv invalidate ptw.io.requestors[0].status.dv invalidate ptw.io.requestors[0].status.dprv invalidate ptw.io.requestors[0].status.isa invalidate ptw.io.requestors[0].status.wfi invalidate ptw.io.requestors[0].status.cease invalidate ptw.io.requestors[0].status.debug invalidate ptw.io.requestors[0].vsatp.ppn invalidate ptw.io.requestors[0].vsatp.asid invalidate ptw.io.requestors[0].vsatp.mode invalidate ptw.io.requestors[0].hgatp.ppn invalidate ptw.io.requestors[0].hgatp.asid invalidate ptw.io.requestors[0].hgatp.mode invalidate ptw.io.requestors[0].ptbr.ppn invalidate ptw.io.requestors[0].ptbr.asid invalidate ptw.io.requestors[0].ptbr.mode invalidate ptw.io.requestors[0].resp.bits.gpa_is_pte invalidate ptw.io.requestors[0].resp.bits.gpa.bits invalidate ptw.io.requestors[0].resp.bits.gpa.valid invalidate ptw.io.requestors[0].resp.bits.homogeneous invalidate ptw.io.requestors[0].resp.bits.fragmented_superpage invalidate ptw.io.requestors[0].resp.bits.level invalidate ptw.io.requestors[0].resp.bits.pte.v invalidate ptw.io.requestors[0].resp.bits.pte.r invalidate ptw.io.requestors[0].resp.bits.pte.w invalidate ptw.io.requestors[0].resp.bits.pte.x invalidate ptw.io.requestors[0].resp.bits.pte.u invalidate ptw.io.requestors[0].resp.bits.pte.g invalidate ptw.io.requestors[0].resp.bits.pte.a invalidate ptw.io.requestors[0].resp.bits.pte.d invalidate ptw.io.requestors[0].resp.bits.pte.reserved_for_software invalidate ptw.io.requestors[0].resp.bits.pte.ppn invalidate ptw.io.requestors[0].resp.bits.pte.reserved_for_future invalidate ptw.io.requestors[0].resp.bits.hx invalidate ptw.io.requestors[0].resp.bits.hw invalidate ptw.io.requestors[0].resp.bits.hr invalidate ptw.io.requestors[0].resp.bits.gf invalidate ptw.io.requestors[0].resp.bits.pf invalidate ptw.io.requestors[0].resp.bits.ae_final invalidate ptw.io.requestors[0].resp.bits.ae_ptw invalidate ptw.io.requestors[0].resp.valid invalidate ptw.io.requestors[0].req.bits.bits.stage2 invalidate ptw.io.requestors[0].req.bits.bits.vstage1 invalidate ptw.io.requestors[0].req.bits.bits.need_gpa invalidate ptw.io.requestors[0].req.bits.bits.addr invalidate ptw.io.requestors[0].req.bits.valid invalidate ptw.io.requestors[0].req.valid invalidate ptw.io.requestors[0].req.ready inst lsu of LSU_1 connect lsu.clock, clock connect lsu.reset, reset inst boom_shim of BoomLSUShim_1 connect boom_shim.clock, clock connect boom_shim.reset, reset invalidate lsu.io.ptw.customCSRs.csrs[0].sdata invalidate lsu.io.ptw.customCSRs.csrs[0].set invalidate lsu.io.ptw.customCSRs.csrs[0].stall invalidate lsu.io.ptw.customCSRs.csrs[0].value invalidate lsu.io.ptw.customCSRs.csrs[0].wdata invalidate lsu.io.ptw.customCSRs.csrs[0].wen invalidate lsu.io.ptw.customCSRs.csrs[0].ren invalidate lsu.io.ptw.customCSRs.csrs[1].sdata invalidate lsu.io.ptw.customCSRs.csrs[1].set invalidate lsu.io.ptw.customCSRs.csrs[1].stall invalidate lsu.io.ptw.customCSRs.csrs[1].value invalidate lsu.io.ptw.customCSRs.csrs[1].wdata invalidate lsu.io.ptw.customCSRs.csrs[1].wen invalidate lsu.io.ptw.customCSRs.csrs[1].ren invalidate lsu.io.ptw.gstatus.uie invalidate lsu.io.ptw.gstatus.sie invalidate lsu.io.ptw.gstatus.hie invalidate lsu.io.ptw.gstatus.mie invalidate lsu.io.ptw.gstatus.upie invalidate lsu.io.ptw.gstatus.spie invalidate lsu.io.ptw.gstatus.ube invalidate lsu.io.ptw.gstatus.mpie invalidate lsu.io.ptw.gstatus.spp invalidate lsu.io.ptw.gstatus.vs invalidate lsu.io.ptw.gstatus.mpp invalidate lsu.io.ptw.gstatus.fs invalidate lsu.io.ptw.gstatus.xs invalidate lsu.io.ptw.gstatus.mprv invalidate lsu.io.ptw.gstatus.sum invalidate lsu.io.ptw.gstatus.mxr invalidate lsu.io.ptw.gstatus.tvm invalidate lsu.io.ptw.gstatus.tw invalidate lsu.io.ptw.gstatus.tsr invalidate lsu.io.ptw.gstatus.zero1 invalidate lsu.io.ptw.gstatus.sd_rv32 invalidate lsu.io.ptw.gstatus.uxl invalidate lsu.io.ptw.gstatus.sxl invalidate lsu.io.ptw.gstatus.sbe invalidate lsu.io.ptw.gstatus.mbe invalidate lsu.io.ptw.gstatus.gva invalidate lsu.io.ptw.gstatus.mpv invalidate lsu.io.ptw.gstatus.zero2 invalidate lsu.io.ptw.gstatus.sd invalidate lsu.io.ptw.gstatus.v invalidate lsu.io.ptw.gstatus.prv invalidate lsu.io.ptw.gstatus.dv invalidate lsu.io.ptw.gstatus.dprv invalidate lsu.io.ptw.gstatus.isa invalidate lsu.io.ptw.gstatus.wfi invalidate lsu.io.ptw.gstatus.cease invalidate lsu.io.ptw.gstatus.debug invalidate lsu.io.ptw.hstatus.zero1 invalidate lsu.io.ptw.hstatus.vsbe invalidate lsu.io.ptw.hstatus.gva invalidate lsu.io.ptw.hstatus.spv invalidate lsu.io.ptw.hstatus.spvp invalidate lsu.io.ptw.hstatus.hu invalidate lsu.io.ptw.hstatus.zero2 invalidate lsu.io.ptw.hstatus.vgein invalidate lsu.io.ptw.hstatus.zero3 invalidate lsu.io.ptw.hstatus.vtvm invalidate lsu.io.ptw.hstatus.vtw invalidate lsu.io.ptw.hstatus.vtsr invalidate lsu.io.ptw.hstatus.zero5 invalidate lsu.io.ptw.hstatus.vsxl invalidate lsu.io.ptw.hstatus.zero6 invalidate lsu.io.ptw.status.uie invalidate lsu.io.ptw.status.sie invalidate lsu.io.ptw.status.hie invalidate lsu.io.ptw.status.mie invalidate lsu.io.ptw.status.upie invalidate lsu.io.ptw.status.spie invalidate lsu.io.ptw.status.ube invalidate lsu.io.ptw.status.mpie invalidate lsu.io.ptw.status.spp invalidate lsu.io.ptw.status.vs invalidate lsu.io.ptw.status.mpp invalidate lsu.io.ptw.status.fs invalidate lsu.io.ptw.status.xs invalidate lsu.io.ptw.status.mprv invalidate lsu.io.ptw.status.sum invalidate lsu.io.ptw.status.mxr invalidate lsu.io.ptw.status.tvm invalidate lsu.io.ptw.status.tw invalidate lsu.io.ptw.status.tsr invalidate lsu.io.ptw.status.zero1 invalidate lsu.io.ptw.status.sd_rv32 invalidate lsu.io.ptw.status.uxl invalidate lsu.io.ptw.status.sxl invalidate lsu.io.ptw.status.sbe invalidate lsu.io.ptw.status.mbe invalidate lsu.io.ptw.status.gva invalidate lsu.io.ptw.status.mpv invalidate lsu.io.ptw.status.zero2 invalidate lsu.io.ptw.status.sd invalidate lsu.io.ptw.status.v invalidate lsu.io.ptw.status.prv invalidate lsu.io.ptw.status.dv invalidate lsu.io.ptw.status.dprv invalidate lsu.io.ptw.status.isa invalidate lsu.io.ptw.status.wfi invalidate lsu.io.ptw.status.cease invalidate lsu.io.ptw.status.debug invalidate lsu.io.ptw.vsatp.ppn invalidate lsu.io.ptw.vsatp.asid invalidate lsu.io.ptw.vsatp.mode invalidate lsu.io.ptw.hgatp.ppn invalidate lsu.io.ptw.hgatp.asid invalidate lsu.io.ptw.hgatp.mode invalidate lsu.io.ptw.ptbr.ppn invalidate lsu.io.ptw.ptbr.asid invalidate lsu.io.ptw.ptbr.mode invalidate lsu.io.ptw.resp.bits.gpa_is_pte invalidate lsu.io.ptw.resp.bits.gpa.bits invalidate lsu.io.ptw.resp.bits.gpa.valid invalidate lsu.io.ptw.resp.bits.homogeneous invalidate lsu.io.ptw.resp.bits.fragmented_superpage invalidate lsu.io.ptw.resp.bits.level invalidate lsu.io.ptw.resp.bits.pte.v invalidate lsu.io.ptw.resp.bits.pte.r invalidate lsu.io.ptw.resp.bits.pte.w invalidate lsu.io.ptw.resp.bits.pte.x invalidate lsu.io.ptw.resp.bits.pte.u invalidate lsu.io.ptw.resp.bits.pte.g invalidate lsu.io.ptw.resp.bits.pte.a invalidate lsu.io.ptw.resp.bits.pte.d invalidate lsu.io.ptw.resp.bits.pte.reserved_for_software invalidate lsu.io.ptw.resp.bits.pte.ppn invalidate lsu.io.ptw.resp.bits.pte.reserved_for_future invalidate lsu.io.ptw.resp.bits.hx invalidate lsu.io.ptw.resp.bits.hw invalidate lsu.io.ptw.resp.bits.hr invalidate lsu.io.ptw.resp.bits.gf invalidate lsu.io.ptw.resp.bits.pf invalidate lsu.io.ptw.resp.bits.ae_final invalidate lsu.io.ptw.resp.bits.ae_ptw invalidate lsu.io.ptw.resp.valid invalidate lsu.io.ptw.req.bits.bits.stage2 invalidate lsu.io.ptw.req.bits.bits.vstage1 invalidate lsu.io.ptw.req.bits.bits.need_gpa invalidate lsu.io.ptw.req.bits.bits.addr invalidate lsu.io.ptw.req.bits.valid invalidate lsu.io.ptw.req.valid invalidate lsu.io.ptw.req.ready connect ptw.io.requestors[0].req, lsu.io.ptw.req connect lsu.io.ptw.resp.bits.gpa_is_pte, ptw.io.requestors[0].resp.bits.gpa_is_pte connect lsu.io.ptw.resp.bits.gpa.bits, ptw.io.requestors[0].resp.bits.gpa.bits connect lsu.io.ptw.resp.bits.gpa.valid, ptw.io.requestors[0].resp.bits.gpa.valid connect lsu.io.ptw.resp.bits.homogeneous, ptw.io.requestors[0].resp.bits.homogeneous connect lsu.io.ptw.resp.bits.fragmented_superpage, ptw.io.requestors[0].resp.bits.fragmented_superpage connect lsu.io.ptw.resp.bits.level, ptw.io.requestors[0].resp.bits.level connect lsu.io.ptw.resp.bits.pte.v, ptw.io.requestors[0].resp.bits.pte.v connect lsu.io.ptw.resp.bits.pte.r, ptw.io.requestors[0].resp.bits.pte.r connect lsu.io.ptw.resp.bits.pte.w, ptw.io.requestors[0].resp.bits.pte.w connect lsu.io.ptw.resp.bits.pte.x, ptw.io.requestors[0].resp.bits.pte.x connect lsu.io.ptw.resp.bits.pte.u, ptw.io.requestors[0].resp.bits.pte.u connect lsu.io.ptw.resp.bits.pte.g, ptw.io.requestors[0].resp.bits.pte.g connect lsu.io.ptw.resp.bits.pte.a, ptw.io.requestors[0].resp.bits.pte.a connect lsu.io.ptw.resp.bits.pte.d, ptw.io.requestors[0].resp.bits.pte.d connect lsu.io.ptw.resp.bits.pte.reserved_for_software, ptw.io.requestors[0].resp.bits.pte.reserved_for_software connect lsu.io.ptw.resp.bits.pte.ppn, ptw.io.requestors[0].resp.bits.pte.ppn connect lsu.io.ptw.resp.bits.pte.reserved_for_future, ptw.io.requestors[0].resp.bits.pte.reserved_for_future connect lsu.io.ptw.resp.bits.hx, ptw.io.requestors[0].resp.bits.hx connect lsu.io.ptw.resp.bits.hw, ptw.io.requestors[0].resp.bits.hw connect lsu.io.ptw.resp.bits.hr, ptw.io.requestors[0].resp.bits.hr connect lsu.io.ptw.resp.bits.gf, ptw.io.requestors[0].resp.bits.gf connect lsu.io.ptw.resp.bits.pf, ptw.io.requestors[0].resp.bits.pf connect lsu.io.ptw.resp.bits.ae_final, ptw.io.requestors[0].resp.bits.ae_final connect lsu.io.ptw.resp.bits.ae_ptw, ptw.io.requestors[0].resp.bits.ae_ptw connect lsu.io.ptw.resp.valid, ptw.io.requestors[0].resp.valid connect dcache.io.lsu, lsu.io.dmem connect boom_shim.io.tracegen, tracegen.io.mem connect tracegen.io.fence_rdy, boom_shim.io.tracegen.ordered connect boom_shim.io.lsu, lsu.io.core invalidate lsu.io.hellacache.clock_enabled invalidate lsu.io.hellacache.keep_clock_enabled invalidate lsu.io.hellacache.perf.storeBufferEmptyAfterStore invalidate lsu.io.hellacache.perf.storeBufferEmptyAfterLoad invalidate lsu.io.hellacache.perf.canAcceptLoadThenLoad invalidate lsu.io.hellacache.perf.canAcceptStoreThenRMW invalidate lsu.io.hellacache.perf.canAcceptStoreThenLoad invalidate lsu.io.hellacache.perf.blocked invalidate lsu.io.hellacache.perf.tlbMiss invalidate lsu.io.hellacache.perf.grant invalidate lsu.io.hellacache.perf.release invalidate lsu.io.hellacache.perf.acquire invalidate lsu.io.hellacache.store_pending invalidate lsu.io.hellacache.ordered invalidate lsu.io.hellacache.s2_gpa_is_pte invalidate lsu.io.hellacache.s2_gpa invalidate lsu.io.hellacache.s2_xcpt.ae.st invalidate lsu.io.hellacache.s2_xcpt.ae.ld invalidate lsu.io.hellacache.s2_xcpt.gf.st invalidate lsu.io.hellacache.s2_xcpt.gf.ld invalidate lsu.io.hellacache.s2_xcpt.pf.st invalidate lsu.io.hellacache.s2_xcpt.pf.ld invalidate lsu.io.hellacache.s2_xcpt.ma.st invalidate lsu.io.hellacache.s2_xcpt.ma.ld invalidate lsu.io.hellacache.replay_next invalidate lsu.io.hellacache.resp.bits.store_data invalidate lsu.io.hellacache.resp.bits.data_raw invalidate lsu.io.hellacache.resp.bits.data_word_bypass invalidate lsu.io.hellacache.resp.bits.has_data invalidate lsu.io.hellacache.resp.bits.replay invalidate lsu.io.hellacache.resp.bits.mask invalidate lsu.io.hellacache.resp.bits.data invalidate lsu.io.hellacache.resp.bits.dv invalidate lsu.io.hellacache.resp.bits.dprv invalidate lsu.io.hellacache.resp.bits.signed invalidate lsu.io.hellacache.resp.bits.size invalidate lsu.io.hellacache.resp.bits.cmd invalidate lsu.io.hellacache.resp.bits.tag invalidate lsu.io.hellacache.resp.bits.addr invalidate lsu.io.hellacache.resp.valid invalidate lsu.io.hellacache.s2_paddr invalidate lsu.io.hellacache.s2_uncached invalidate lsu.io.hellacache.s2_kill invalidate lsu.io.hellacache.s2_nack_cause_raw invalidate lsu.io.hellacache.s2_nack invalidate lsu.io.hellacache.s1_data.mask invalidate lsu.io.hellacache.s1_data.data invalidate lsu.io.hellacache.s1_kill invalidate lsu.io.hellacache.req.bits.mask invalidate lsu.io.hellacache.req.bits.data invalidate lsu.io.hellacache.req.bits.no_xcpt invalidate lsu.io.hellacache.req.bits.no_alloc invalidate lsu.io.hellacache.req.bits.no_resp invalidate lsu.io.hellacache.req.bits.phys invalidate lsu.io.hellacache.req.bits.dv invalidate lsu.io.hellacache.req.bits.dprv invalidate lsu.io.hellacache.req.bits.signed invalidate lsu.io.hellacache.req.bits.size invalidate lsu.io.hellacache.req.bits.cmd invalidate lsu.io.hellacache.req.bits.tag invalidate lsu.io.hellacache.req.bits.addr invalidate lsu.io.hellacache.req.valid invalidate lsu.io.hellacache.req.ready connect lsu.io.hellacache.req.valid, UInt<1>(0h0) regreset ceaseNodeOut_0_cease_count : UInt<4>, clock, reset, UInt<4>(0h0) node ceaseNodeOut_0_cease = geq(ceaseNodeOut_0_cease_count, UInt<4>(0h8)) node _ceaseNodeOut_0_cease_T = eq(tracegen.io.finished, UInt<1>(0h0)) when _ceaseNodeOut_0_cease_T : connect ceaseNodeOut_0_cease_count, UInt<1>(0h0) node _ceaseNodeOut_0_cease_T_1 = eq(ceaseNodeOut_0_cease, UInt<1>(0h0)) node _ceaseNodeOut_0_cease_T_2 = and(tracegen.io.finished, _ceaseNodeOut_0_cease_T_1) when _ceaseNodeOut_0_cease_T_2 : node _ceaseNodeOut_0_cease_count_T = add(ceaseNodeOut_0_cease_count, UInt<1>(0h1)) node _ceaseNodeOut_0_cease_count_T_1 = tail(_ceaseNodeOut_0_cease_count_T, 1) connect ceaseNodeOut_0_cease_count, _ceaseNodeOut_0_cease_count_T_1 regreset ceaseNodeOut_0_prev_cease : UInt<1>, clock, reset, UInt<1>(0h0) connect ceaseNodeOut_0_prev_cease, ceaseNodeOut_0_cease node _ceaseNodeOut_0_T = eq(ceaseNodeOut_0_cease, UInt<1>(0h0)) node _ceaseNodeOut_0_T_1 = and(ceaseNodeOut_0_prev_cease, _ceaseNodeOut_0_T) node _ceaseNodeOut_0_T_2 = eq(_ceaseNodeOut_0_T_1, UInt<1>(0h0)) node _ceaseNodeOut_0_T_3 = asUInt(reset) node _ceaseNodeOut_0_T_4 = eq(_ceaseNodeOut_0_T_3, UInt<1>(0h0)) when _ceaseNodeOut_0_T_4 : node _ceaseNodeOut_0_T_5 = eq(_ceaseNodeOut_0_T_2, UInt<1>(0h0)) when _ceaseNodeOut_0_T_5 : printf(clock, UInt<1>(0h1), "Assertion failed: CEASE line can not glitch once raised\n at Interrupts.scala:121 assert(!(prev_cease & !cease), \"CEASE line can not glitch once raised\")\n") : ceaseNodeOut_0_printf assert(clock, _ceaseNodeOut_0_T_2, UInt<1>(0h1), "") : ceaseNodeOut_0_assert connect ceaseNodeOut[0], ceaseNodeOut_0_cease regreset haltNodeOut_0_r : UInt<1>, clock, reset, UInt<1>(0h0) when tracegen.io.timeout : connect haltNodeOut_0_r, UInt<1>(0h1) connect haltNodeOut[0], haltNodeOut_0_r connect wfiNodeOut[0], UInt<1>(0h0) connect statusNodeOut.timeout.valid, tracegen.io.timeout connect statusNodeOut.timeout.bits, UInt<1>(0h0) connect statusNodeOut.error.valid, UInt<1>(0h0) node _T = eq(tracegen.io.timeout, UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: TraceGen tile 1: request timed out\n at tracegen.scala:262 assert(!tracegen.io.timeout, s\"TraceGen tile ${outer.tileParams.tileId}: request timed out\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert	module BoomTraceGenTile_1( // @[tracegen.scala:229:7] input clock, // @[tracegen.scala:229:7] input reset, // @[tracegen.scala:229:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_status_out_timeout_valid, // @[LazyModuleImp.scala:107:25] output auto_cease_out_0, // @[LazyModuleImp.scala:107:25] output auto_halt_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] input auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _boom_shim_io_lsu_exe_0_req_valid; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_exe_0_req_bits_uop_uopc; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_ctrl_is_load; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_ctrl_is_sta; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_ctrl_is_std; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_exe_0_req_bits_uop_rob_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_exe_0_req_bits_uop_ldq_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_exe_0_req_bits_uop_stq_idx; // @[tracegen.scala:241:25] wire [4:0] _boom_shim_io_lsu_exe_0_req_bits_uop_mem_cmd; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_is_amo; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_uses_ldq; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_uses_stq; // @[tracegen.scala:241:25] wire [63:0] _boom_shim_io_lsu_exe_0_req_bits_data; // @[tracegen.scala:241:25] wire [33:0] _boom_shim_io_lsu_exe_0_req_bits_addr; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_valid; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_dis_uops_0_bits_uopc; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_ctrl_is_load; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_ctrl_is_sta; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_ctrl_is_std; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_dis_uops_0_bits_rob_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_dis_uops_0_bits_ldq_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_dis_uops_0_bits_stq_idx; // @[tracegen.scala:241:25] wire [4:0] _boom_shim_io_lsu_dis_uops_0_bits_mem_cmd; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_is_amo; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_uses_ldq; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_uses_stq; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_valids_0; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_uopc; // @[tracegen.scala:241:25] wire [31:0] _boom_shim_io_lsu_commit_uops_0_inst; // @[tracegen.scala:241:25] wire [31:0] _boom_shim_io_lsu_commit_uops_0_debug_inst; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_rvc; // @[tracegen.scala:241:25] wire [33:0] _boom_shim_io_lsu_commit_uops_0_debug_pc; // @[tracegen.scala:241:25] wire [2:0] _boom_shim_io_lsu_commit_uops_0_iq_type; // @[tracegen.scala:241:25] wire [9:0] _boom_shim_io_lsu_commit_uops_0_fu_code; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_ctrl_br_type; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_ctrl_op1_sel; // @[tracegen.scala:241:25] wire [2:0] _boom_shim_io_lsu_commit_uops_0_ctrl_op2_sel; // @[tracegen.scala:241:25] wire [2:0] _boom_shim_io_lsu_commit_uops_0_ctrl_imm_sel; // @[tracegen.scala:241:25] wire [4:0] _boom_shim_io_lsu_commit_uops_0_ctrl_op_fcn; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ctrl_fcn_dw; // @[tracegen.scala:241:25] wire [2:0] _boom_shim_io_lsu_commit_uops_0_ctrl_csr_cmd; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ctrl_is_load; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ctrl_is_sta; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ctrl_is_std; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_iw_state; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_iw_p1_poisoned; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_iw_p2_poisoned; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_br; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_jalr; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_jal; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_sfb; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_br_mask; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_br_tag; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_ftq_idx; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_edge_inst; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_pc_lob; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_taken; // @[tracegen.scala:241:25] wire [19:0] _boom_shim_io_lsu_commit_uops_0_imm_packed; // @[tracegen.scala:241:25] wire [11:0] _boom_shim_io_lsu_commit_uops_0_csr_addr; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_rob_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_ldq_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_stq_idx; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_rxq_idx; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_pdst; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_prs1; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_prs2; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_prs3; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_ppred; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_prs1_busy; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_prs2_busy; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_prs3_busy; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ppred_busy; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_stale_pdst; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_exception; // @[tracegen.scala:241:25] wire [63:0] _boom_shim_io_lsu_commit_uops_0_exc_cause; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_bypassable; // @[tracegen.scala:241:25] wire [4:0] _boom_shim_io_lsu_commit_uops_0_mem_cmd; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_mem_size; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_mem_signed; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_fence; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_fencei; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_amo; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_uses_ldq; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_uses_stq; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_sys_pc2epc; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_unique; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_flush_on_commit; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ldst_is_rs1; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_ldst; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_lrs1; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_lrs2; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_lrs3; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ldst_val; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_dst_rtype; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_lrs1_rtype; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_lrs2_rtype; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_frs3_en; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_fp_val; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_fp_single; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_xcpt_pf_if; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_xcpt_ae_if; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_xcpt_ma_if; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_bp_debug_if; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_bp_xcpt_if; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_debug_fsrc; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_debug_tsrc; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_rob_pnr_idx; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_rob_head_idx; // @[tracegen.scala:241:25] wire _boom_shim_io_tracegen_req_ready; // @[tracegen.scala:241:25] wire _boom_shim_io_tracegen_resp_valid; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_tracegen_resp_bits_tag; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_tracegen_resp_bits_size; // @[tracegen.scala:241:25] wire [63:0] _boom_shim_io_tracegen_resp_bits_data; // @[tracegen.scala:241:25] wire _boom_shim_io_tracegen_ordered; // @[tracegen.scala:241:25] wire [20:0] _lsu_io_ptw_req_bits_bits_addr; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_valid; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_uopc; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_exe_0_iresp_bits_uop_inst; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_inst; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_rvc; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_pc; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_iq_type; // @[tracegen.scala:240:19] wire [9:0] _lsu_io_core_exe_0_iresp_bits_uop_fu_code; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_iw_state; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_br; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_jalr; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_jal; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_sfb; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_br_mask; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_br_tag; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ftq_idx; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_edge_inst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_pc_lob; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_taken; // @[tracegen.scala:240:19] wire [19:0] _lsu_io_core_exe_0_iresp_bits_uop_imm_packed; // @[tracegen.scala:240:19] wire [11:0] _lsu_io_core_exe_0_iresp_bits_uop_csr_addr; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_rob_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ldq_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_stq_idx; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_rxq_idx; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_pdst; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs1; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs2; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs3; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ppred; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_prs1_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_prs2_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_prs3_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ppred_busy; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_stale_pdst; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_exception; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_core_exe_0_iresp_bits_uop_exc_cause; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_bypassable; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_mem_cmd; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_mem_size; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_mem_signed; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_fence; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_fencei; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_amo; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_uses_ldq; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_uses_stq; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_unique; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_ldst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs2; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs3; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ldst_val; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_dst_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_frs3_en; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_fp_val; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_fp_single; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_core_exe_0_iresp_bits_data; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_valid; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_uopc; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_exe_0_fresp_bits_uop_inst; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_inst; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_rvc; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_pc; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_iq_type; // @[tracegen.scala:240:19] wire [9:0] _lsu_io_core_exe_0_fresp_bits_uop_fu_code; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_iw_state; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_br; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_jalr; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_jal; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_sfb; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_br_mask; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_br_tag; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ftq_idx; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_edge_inst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_pc_lob; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_taken; // @[tracegen.scala:240:19] wire [19:0] _lsu_io_core_exe_0_fresp_bits_uop_imm_packed; // @[tracegen.scala:240:19] wire [11:0] _lsu_io_core_exe_0_fresp_bits_uop_csr_addr; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_rob_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ldq_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_stq_idx; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_rxq_idx; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_pdst; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs1; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs2; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs3; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ppred; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_prs1_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_prs2_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_prs3_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ppred_busy; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_stale_pdst; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_exception; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_core_exe_0_fresp_bits_uop_exc_cause; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_bypassable; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_mem_cmd; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_mem_size; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_mem_signed; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_fence; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_fencei; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_amo; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_uses_ldq; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_uses_stq; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_unique; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_ldst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs2; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs3; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ldst_val; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_dst_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_frs3_en; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_fp_val; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_fp_single; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc; // @[tracegen.scala:240:19] wire [64:0] _lsu_io_core_exe_0_fresp_bits_data; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_dis_ldq_idx_0; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_dis_stq_idx_0; // @[tracegen.scala:240:19] wire _lsu_io_core_ldq_full_0; // @[tracegen.scala:240:19] wire _lsu_io_core_stq_full_0; // @[tracegen.scala:240:19] wire _lsu_io_core_fp_stdata_ready; // @[tracegen.scala:240:19] wire _lsu_io_core_clr_bsy_0_valid; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_clr_bsy_0_bits; // @[tracegen.scala:240:19] wire _lsu_io_core_clr_bsy_1_valid; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_clr_bsy_1_bits; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_clr_unsafe_0_bits; // @[tracegen.scala:240:19] wire _lsu_io_core_spec_ld_wakeup_0_valid; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_spec_ld_wakeup_0_bits; // @[tracegen.scala:240:19] wire _lsu_io_core_ld_miss; // @[tracegen.scala:240:19] wire _lsu_io_core_fencei_rdy; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_valid; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_uopc; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_lxcpt_bits_uop_inst; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_lxcpt_bits_uop_debug_inst; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_rvc; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_core_lxcpt_bits_uop_debug_pc; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_lxcpt_bits_uop_iq_type; // @[tracegen.scala:240:19] wire [9:0] _lsu_io_core_lxcpt_bits_uop_fu_code; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_ctrl_br_type; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_load; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_sta; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_std; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_iw_state; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_br; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_jalr; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_jal; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_sfb; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_br_mask; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_br_tag; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_ftq_idx; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_edge_inst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_pc_lob; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_taken; // @[tracegen.scala:240:19] wire [19:0] _lsu_io_core_lxcpt_bits_uop_imm_packed; // @[tracegen.scala:240:19] wire [11:0] _lsu_io_core_lxcpt_bits_uop_csr_addr; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_rob_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_ldq_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_stq_idx; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_rxq_idx; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_pdst; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs1; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs2; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs3; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_ppred; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_prs1_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_prs2_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_prs3_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ppred_busy; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_stale_pdst; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_exception; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_core_lxcpt_bits_uop_exc_cause; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_bypassable; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_lxcpt_bits_uop_mem_cmd; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_mem_size; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_mem_signed; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_fence; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_fencei; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_amo; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_uses_ldq; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_uses_stq; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_unique; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_flush_on_commit; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ldst_is_rs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_ldst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs2; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs3; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ldst_val; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_dst_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs1_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs2_rtype; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_frs3_en; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_fp_val; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_fp_single; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_xcpt_pf_if; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_xcpt_ae_if; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_xcpt_ma_if; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_bp_debug_if; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_bp_xcpt_if; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_debug_fsrc; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_debug_tsrc; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_lxcpt_bits_cause; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_core_lxcpt_bits_badvaddr; // @[tracegen.scala:240:19] wire _lsu_io_core_perf_acquire; // @[tracegen.scala:240:19] wire _lsu_io_core_perf_release; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_valid; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_valid; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_uopc; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_inst; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_inst; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_rvc; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_pc; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_iq_type; // @[tracegen.scala:240:19] wire [9:0] _lsu_io_dmem_req_bits_0_bits_uop_fu_code; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_iw_state; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_br; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_jalr; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_jal; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_sfb; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_br_mask; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_br_tag; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ftq_idx; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_edge_inst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_pc_lob; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_taken; // @[tracegen.scala:240:19] wire [19:0] _lsu_io_dmem_req_bits_0_bits_uop_imm_packed; // @[tracegen.scala:240:19] wire [11:0] _lsu_io_dmem_req_bits_0_bits_uop_csr_addr; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_rob_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ldq_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_stq_idx; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_rxq_idx; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_pdst; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs1; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs2; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs3; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ppred; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_prs1_busy; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_prs2_busy; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_prs3_busy; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ppred_busy; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_stale_pdst; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_exception; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_dmem_req_bits_0_bits_uop_exc_cause; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_bypassable; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_cmd; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_size; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_mem_signed; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_fence; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_fencei; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_amo; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_uses_ldq; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_uses_stq; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_unique; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_ldst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs3; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_val; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_dst_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_frs3_en; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_val; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_single; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_dmem_req_bits_0_bits_addr; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_dmem_req_bits_0_bits_data; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_is_hella; // @[tracegen.scala:240:19] wire _lsu_io_dmem_s1_kill_0; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_rob_pnr_idx; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_rob_head_idx; // @[tracegen.scala:240:19] wire _lsu_io_dmem_release_ready; // @[tracegen.scala:240:19] wire _lsu_io_dmem_force_order; // @[tracegen.scala:240:19] wire _ptw_io_requestors_0_resp_valid; // @[tracegen.scala:238:19] wire [43:0] _ptw_io_requestors_0_resp_bits_pte_ppn; // @[tracegen.scala:238:19] wire _tracegen_io_finished; // @[tracegen.scala:235:24] wire _tracegen_io_timeout; // @[tracegen.scala:235:24] wire _tracegen_io_mem_req_valid; // @[tracegen.scala:235:24] wire [39:0] _tracegen_io_mem_req_bits_addr; // @[tracegen.scala:235:24] wire [6:0] _tracegen_io_mem_req_bits_tag; // @[tracegen.scala:235:24] wire [4:0] _tracegen_io_mem_req_bits_cmd; // @[tracegen.scala:235:24] wire [63:0] _tracegen_io_mem_req_bits_data; // @[tracegen.scala:235:24] wire [63:0] _tracegen_io_mem_s1_data_data; // @[tracegen.scala:235:24] wire _dcache_io_lsu_req_ready; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_valid; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_uopc; // @[tracegen.scala:221:26] wire [31:0] _dcache_io_lsu_resp_0_bits_uop_inst; // @[tracegen.scala:221:26] wire [31:0] _dcache_io_lsu_resp_0_bits_uop_debug_inst; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_rvc; // @[tracegen.scala:221:26] wire [33:0] _dcache_io_lsu_resp_0_bits_uop_debug_pc; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_iq_type; // @[tracegen.scala:221:26] wire [9:0] _dcache_io_lsu_resp_0_bits_uop_fu_code; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_br_type; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel; // @[tracegen.scala:221:26] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_load; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_std; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_iw_state; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_br; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_jalr; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_jal; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_sfb; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_br_mask; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_br_tag; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ftq_idx; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_edge_inst; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_pc_lob; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_taken; // @[tracegen.scala:221:26] wire [19:0] _dcache_io_lsu_resp_0_bits_uop_imm_packed; // @[tracegen.scala:221:26] wire [11:0] _dcache_io_lsu_resp_0_bits_uop_csr_addr; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_rob_idx; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ldq_idx; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_stq_idx; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_rxq_idx; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_pdst; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs1; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs2; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs3; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ppred; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_prs1_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_prs2_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_prs3_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ppred_busy; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_stale_pdst; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_exception; // @[tracegen.scala:221:26] wire [63:0] _dcache_io_lsu_resp_0_bits_uop_exc_cause; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_bypassable; // @[tracegen.scala:221:26] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_mem_cmd; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_mem_size; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_mem_signed; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_fence; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_fencei; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_amo; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_uses_ldq; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_uses_stq; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_unique; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_flush_on_commit; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_ldst; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs1; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs2; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs3; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ldst_val; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_dst_rtype; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs1_rtype; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs2_rtype; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_frs3_en; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_fp_val; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_fp_single; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_bp_debug_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_debug_fsrc; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_debug_tsrc; // @[tracegen.scala:221:26] wire [63:0] _dcache_io_lsu_resp_0_bits_data; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_is_hella; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_valid; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_uopc; // @[tracegen.scala:221:26] wire [31:0] _dcache_io_lsu_nack_0_bits_uop_inst; // @[tracegen.scala:221:26] wire [31:0] _dcache_io_lsu_nack_0_bits_uop_debug_inst; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_rvc; // @[tracegen.scala:221:26] wire [33:0] _dcache_io_lsu_nack_0_bits_uop_debug_pc; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_iq_type; // @[tracegen.scala:221:26] wire [9:0] _dcache_io_lsu_nack_0_bits_uop_fu_code; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_br_type; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel; // @[tracegen.scala:221:26] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_load; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_std; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_iw_state; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_br; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_jalr; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_jal; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_sfb; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_br_mask; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_br_tag; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ftq_idx; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_edge_inst; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_pc_lob; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_taken; // @[tracegen.scala:221:26] wire [19:0] _dcache_io_lsu_nack_0_bits_uop_imm_packed; // @[tracegen.scala:221:26] wire [11:0] _dcache_io_lsu_nack_0_bits_uop_csr_addr; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_rob_idx; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ldq_idx; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_stq_idx; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_rxq_idx; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_pdst; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs1; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs2; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs3; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ppred; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_prs1_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_prs2_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_prs3_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ppred_busy; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_stale_pdst; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_exception; // @[tracegen.scala:221:26] wire [63:0] _dcache_io_lsu_nack_0_bits_uop_exc_cause; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_bypassable; // @[tracegen.scala:221:26] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_mem_cmd; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_mem_size; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_mem_signed; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_fence; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_fencei; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_amo; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_uses_ldq; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_uses_stq; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_unique; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_flush_on_commit; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_ldst; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs1; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs2; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs3; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ldst_val; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_dst_rtype; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs1_rtype; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs2_rtype; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_frs3_en; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_fp_val; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_fp_single; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_bp_debug_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_debug_fsrc; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_debug_tsrc; // @[tracegen.scala:221:26] wire [33:0] _dcache_io_lsu_nack_0_bits_addr; // @[tracegen.scala:221:26] wire [63:0] _dcache_io_lsu_nack_0_bits_data; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_is_hella; // @[tracegen.scala:221:26] wire _dcache_io_lsu_release_valid; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_release_bits_opcode; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_release_bits_param; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_release_bits_size; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_release_bits_source; // @[tracegen.scala:221:26] wire [31:0] _dcache_io_lsu_release_bits_address; // @[tracegen.scala:221:26] wire [63:0] _dcache_io_lsu_release_bits_data; // @[tracegen.scala:221:26] wire _dcache_io_lsu_ordered; // @[tracegen.scala:221:26] wire _dcache_io_lsu_perf_acquire; // @[tracegen.scala:221:26] wire _dcache_io_lsu_perf_release; // @[tracegen.scala:221:26] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[tracegen.scala:229:7] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[tracegen.scala:229:7] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[tracegen.scala:229:7] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[tracegen.scala:229:7] wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[tracegen.scala:229:7] wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[tracegen.scala:229:7] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[tracegen.scala:229:7] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[tracegen.scala:229:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[tracegen.scala:229:7] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[tracegen.scala:229:7] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[tracegen.scala:229:7] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[tracegen.scala:229:7] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[tracegen.scala:229:7] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[tracegen.scala:229:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[tracegen.scala:229:7] wire auto_hartid_in_0 = auto_hartid_in; // @[tracegen.scala:229:7] wire _ceaseNodeOut_0_T_3 = reset; // @[Interrupts.scala:121:13] wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[tracegen.scala:229:7] wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[tracegen.scala:229:7] wire auto_status_out_error_valid = 1'h0; // @[tracegen.scala:229:7] wire auto_wfi_out_0 = 1'h0; // @[tracegen.scala:229:7] wire auto_int_local_in_3_0 = 1'h0; // @[tracegen.scala:229:7] wire auto_int_local_in_2_0 = 1'h0; // @[tracegen.scala:229:7] wire auto_int_local_in_1_0 = 1'h0; // @[tracegen.scala:229:7] wire auto_int_local_in_1_1 = 1'h0; // @[tracegen.scala:229:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[tracegen.scala:229:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[tracegen.scala:229:7] wire auto_trace_source_out_insns_0_valid = 1'h0; // @[tracegen.scala:229:7] wire auto_trace_source_out_insns_0_exception = 1'h0; // @[tracegen.scala:229:7] wire auto_trace_source_out_insns_0_interrupt = 1'h0; // @[tracegen.scala:229:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_auto_in_0_valid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_2_nodeIn_0_valid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceSourceNodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire bpwatchSourceNodeOut_0_valid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1 = 1'h0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0 = 1'h0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0 = 1'h0; // @[MixedNode.scala:542:17] wire x1_int_localIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire x1_int_localIn_1 = 1'h0; // @[MixedNode.scala:551:17] wire x1_int_localIn_1_0 = 1'h0; // @[MixedNode.scala:551:17] wire x1_int_localIn_2_0 = 1'h0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1 = 1'h0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2 = 1'h0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3 = 1'h0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4 = 1'h0; // @[MixedNode.scala:551:17] wire wfiNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire statusNodeOut_error_valid = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire masterNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire [3:0] auto_status_out_timeout_bits = 4'h0; // @[tracegen.scala:229:7] wire [3:0] auto_status_out_error_bits = 4'h0; // @[tracegen.scala:229:7] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[tracegen.scala:229:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[tracegen.scala:229:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] statusNodeOut_timeout_bits = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] statusNodeOut_error_bits = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[tracegen.scala:229:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[tracegen.scala:229:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[tracegen.scala:229:7] wire [31:0] auto_trace_source_out_insns_0_insn = 32'h0; // @[tracegen.scala:229:7] wire [31:0] auto_reset_vector_in = 32'h0; // @[tracegen.scala:229:7] wire [31:0] broadcast_1_auto_in = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_1_auto_out = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_1_nodeIn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] broadcast_1_nodeOut = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] resetVectorSinkNodeIn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] reset_vectorOut = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] reset_vectorIn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceSourceNodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire [39:0] auto_trace_source_out_insns_0_iaddr = 40'h0; // @[tracegen.scala:229:7] wire [39:0] auto_trace_source_out_insns_0_tval = 40'h0; // @[tracegen.scala:229:7] wire [39:0] traceSourceNodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17] wire [2:0] auto_trace_source_out_insns_0_priv = 3'h0; // @[tracegen.scala:229:7] wire [2:0] broadcast_2_auto_in_0_action = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] broadcast_2_nodeIn_0_action = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] traceSourceNodeOut_insns_0_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] bpwatchSourceNodeOut_0_action = 3'h0; // @[MixedNode.scala:542:17] wire [63:0] auto_trace_source_out_insns_0_cause = 64'h0; // @[tracegen.scala:229:7] wire [63:0] auto_trace_source_out_time = 64'h0; // @[tracegen.scala:229:7] wire [63:0] traceSourceNodeOut_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_time = 64'h0; // @[MixedNode.scala:542:17] wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire statusNodeOut_timeout_valid; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0; // @[MixedNode.scala:542:17] wire haltNodeOut_0; // @[MixedNode.scala:542:17] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[MixedNode.scala:551:17] wire hartidIn = auto_hartid_in_0; // @[MixedNode.scala:551:17] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_a_bits_size_0; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_a_bits_source_0; // @[tracegen.scala:229:7] wire [31:0] auto_buffer_out_a_bits_address_0; // @[tracegen.scala:229:7] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[tracegen.scala:229:7] wire [63:0] auto_buffer_out_a_bits_data_0; // @[tracegen.scala:229:7] wire auto_buffer_out_a_valid_0; // @[tracegen.scala:229:7] wire auto_buffer_out_b_ready_0; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_c_bits_param_0; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_c_bits_size_0; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_c_bits_source_0; // @[tracegen.scala:229:7] wire [31:0] auto_buffer_out_c_bits_address_0; // @[tracegen.scala:229:7] wire [63:0] auto_buffer_out_c_bits_data_0; // @[tracegen.scala:229:7] wire auto_buffer_out_c_valid_0; // @[tracegen.scala:229:7] wire auto_buffer_out_d_ready_0; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_e_bits_sink_0; // @[tracegen.scala:229:7] wire auto_buffer_out_e_valid_0; // @[tracegen.scala:229:7] wire auto_status_out_timeout_valid_0; // @[tracegen.scala:229:7] wire auto_cease_out_0_0; // @[tracegen.scala:229:7] wire auto_halt_out_0_0; // @[tracegen.scala:229:7] wire hartidOut; // @[MixedNode.scala:542:17] wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire broadcast_nodeOut; // @[MixedNode.scala:542:17] wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire masterNodeOut_b_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] masterNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] masterNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] masterNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire masterNodeOut_c_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] masterNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] masterNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire masterNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire masterNodeOut_e_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] wire int_localOut_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] assign auto_halt_out_0_0 = haltNodeOut_0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0_cease; // @[Interrupts.scala:111:29] assign auto_cease_out_0_0 = ceaseNodeOut_0; // @[MixedNode.scala:542:17] assign auto_status_out_timeout_valid_0 = statusNodeOut_timeout_valid; // @[MixedNode.scala:542:17] wire masterNodeIn_a_ready = masterNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_valid = masterNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_opcode = masterNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_param = masterNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_size = masterNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] masterNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_source = masterNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_address = masterNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] masterNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_mask = masterNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] masterNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_data = masterNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire masterNodeIn_b_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_b_ready = masterNodeOut_b_ready; // @[Buffer.scala:40:9] wire masterNodeIn_b_valid = masterNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_b_bits_opcode = masterNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] masterNodeIn_b_bits_param = masterNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_b_bits_size = masterNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_b_bits_source = masterNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] masterNodeIn_b_bits_address = masterNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] masterNodeIn_b_bits_mask = masterNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] masterNodeIn_b_bits_data = masterNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_b_bits_corrupt = masterNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_c_ready = masterNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_c_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_valid = masterNodeOut_c_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_opcode = masterNodeOut_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeIn_c_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_param = masterNodeOut_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeIn_c_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_size = masterNodeOut_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] masterNodeIn_c_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_source = masterNodeOut_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeIn_c_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_address = masterNodeOut_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] masterNodeIn_c_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_data = masterNodeOut_c_bits_data; // @[Buffer.scala:40:9] wire masterNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_d_ready = masterNodeOut_d_ready; // @[Buffer.scala:40:9] wire masterNodeIn_d_valid = masterNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_d_bits_opcode = masterNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] masterNodeIn_d_bits_param = masterNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_d_bits_size = masterNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_d_bits_source = masterNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_d_bits_sink = masterNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_bits_denied = masterNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] masterNodeIn_d_bits_data = masterNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_bits_corrupt = masterNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_e_ready = masterNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_e_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_valid = masterNodeOut_e_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeIn_e_bits_sink; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_bits_sink = masterNodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign masterNodeOut_a_valid = masterNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_opcode = masterNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_param = masterNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_size = masterNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_source = masterNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_address = masterNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_mask = masterNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_data = masterNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_b_ready = masterNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_valid = masterNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_opcode = masterNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_param = masterNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_size = masterNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_source = masterNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_address = masterNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_data = masterNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_d_ready = masterNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_e_valid = masterNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_e_bits_sink = masterNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] reg [3:0] ceaseNodeOut_0_cease_count; // @[Interrupts.scala:110:26] assign ceaseNodeOut_0_cease = ceaseNodeOut_0_cease_count[3]; // @[Interrupts.scala:110:26, :111:29] assign ceaseNodeOut_0 = ceaseNodeOut_0_cease; // @[Interrupts.scala:111:29] wire _ceaseNodeOut_0_cease_T = ~_tracegen_io_finished; // @[Interrupts.scala:112:13] wire _ceaseNodeOut_0_cease_T_1 = ~ceaseNodeOut_0_cease; // @[Interrupts.scala:111:29, :113:22] wire _ceaseNodeOut_0_cease_T_2 = _tracegen_io_finished & _ceaseNodeOut_0_cease_T_1; // @[Interrupts.scala:113:{19,22}] wire [4:0] _ceaseNodeOut_0_cease_count_T = {1'h0, ceaseNodeOut_0_cease_count} + 5'h1; // @[Interrupts.scala:110:26, :113:51] wire [3:0] _ceaseNodeOut_0_cease_count_T_1 = _ceaseNodeOut_0_cease_count_T[3:0]; // @[Interrupts.scala:113:51] reg ceaseNodeOut_0_prev_cease; // @[Interrupts.scala:120:31] wire _ceaseNodeOut_0_T = ~ceaseNodeOut_0_cease; // @[Interrupts.scala:111:29, :113:22, :121:29] wire _ceaseNodeOut_0_T_1 = ceaseNodeOut_0_prev_cease & _ceaseNodeOut_0_T; // @[Interrupts.scala:120:31, :121:{27,29}] wire _ceaseNodeOut_0_T_2 = ~_ceaseNodeOut_0_T_1; // @[Interrupts.scala:121:{14,27}] wire _ceaseNodeOut_0_T_4 = ~_ceaseNodeOut_0_T_3; // @[Interrupts.scala:121:13] wire _ceaseNodeOut_0_T_5 = ~_ceaseNodeOut_0_T_2; // @[Interrupts.scala:121:{13,14}] reg haltNodeOut_0_r; // @[Interrupts.scala:97:55] assign haltNodeOut_0 = haltNodeOut_0_r; // @[Interrupts.scala:97:55]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_91 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_183 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_184 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_185 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_186 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_91( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_207 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_375 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_207( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_375 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLDebugModuleInnerAsync : output auto : { flip dmiXing_in : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, dmInner_sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip dmInner_custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip dmInner_tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip debug_clock : Clock, flip debug_reset : Reset, flip tl_clock : Clock, flip tl_reset : Reset, flip dmactive : UInt<1>, flip innerCtrl : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[4], hrmask : UInt<1>[4]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip debugUnavail : UInt<1>[4], hgDebugInt : UInt<1>[4], flip hartIsInReset : UInt<1>[4]} input rf_reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst dmInner of TLDebugModuleInner connect dmInner.clock, childClock connect dmInner.reset, childReset inst dmiXing of TLAsyncCrossingSink_a9d32s1k1z2u connect dmiXing.clock, childClock connect dmiXing.reset, childReset connect dmInner.auto.dmi_in, dmiXing.auto.out connect dmInner.auto.tl_in, auto.dmInner_tl_in connect dmInner.auto.custom_in, auto.dmInner_custom_in connect dmInner.auto.sb2tlOpt_out.d, auto.dmInner_sb2tlOpt_out.d connect auto.dmInner_sb2tlOpt_out.a.bits, dmInner.auto.sb2tlOpt_out.a.bits connect auto.dmInner_sb2tlOpt_out.a.valid, dmInner.auto.sb2tlOpt_out.a.valid connect dmInner.auto.sb2tlOpt_out.a.ready, auto.dmInner_sb2tlOpt_out.a.ready connect dmiXing.auto.in, auto.dmiXing_in connect childClock, io.debug_clock connect childReset, io.debug_reset inst dmactive_synced_dmactive_synced_dmactiveSync of AsyncResetSynchronizerShiftReg_w1_d3_i0_30 connect dmactive_synced_dmactive_synced_dmactiveSync.clock, childClock connect dmactive_synced_dmactive_synced_dmactiveSync.reset, childReset connect dmactive_synced_dmactive_synced_dmactiveSync.io.d, io.dmactive wire dmactive_synced : UInt<1> connect dmactive_synced, dmactive_synced_dmactive_synced_dmactiveSync.io.q connect dmInner.clock, io.debug_clock connect dmInner.reset, io.debug_reset connect dmInner.io.tl_clock, io.tl_clock connect dmInner.io.tl_reset, io.tl_reset connect dmInner.io.dmactive, dmactive_synced inst dmactive_synced_dmInner_io_innerCtrl_sink of AsyncQueueSink_DebugInternalBundle connect dmactive_synced_dmInner_io_innerCtrl_sink.clock, childClock connect dmactive_synced_dmInner_io_innerCtrl_sink.reset, childReset connect dmactive_synced_dmInner_io_innerCtrl_sink.io.async, io.innerCtrl connect dmInner.io.innerCtrl, dmactive_synced_dmInner_io_innerCtrl_sink.io.deq connect dmInner.io.debugUnavail[0], io.debugUnavail[0] connect dmInner.io.debugUnavail[1], io.debugUnavail[1] connect dmInner.io.debugUnavail[2], io.debugUnavail[2] connect dmInner.io.debugUnavail[3], io.debugUnavail[3] connect io.hgDebugInt, dmInner.io.hgDebugInt connect dmInner.io.hartIsInReset[0], io.hartIsInReset[0] connect dmInner.io.hartIsInReset[1], io.hartIsInReset[1] connect dmInner.io.hartIsInReset[2], io.hartIsInReset[2] connect dmInner.io.hartIsInReset[3], io.hartIsInReset[3]	module TLDebugModuleInnerAsync( // @[Debug.scala:1871:9] input [2:0] auto_dmiXing_in_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmiXing_in_a_mem_0_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmiXing_in_a_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_ridx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_widx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmiXing_in_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmiXing_in_d_mem_0_size, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_mem_0_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmiXing_in_d_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_ridx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_widx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_debug_clock, // @[Debug.scala:1877:16] input io_debug_reset, // @[Debug.scala:1877:16] input io_tl_clock, // @[Debug.scala:1877:16] input io_tl_reset, // @[Debug.scala:1877:16] input io_dmactive, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_resumereq, // @[Debug.scala:1877:16] input [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hasel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_0, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_1, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_2, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_3, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_1, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_2, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_3, // @[Debug.scala:1877:16] output io_innerCtrl_ridx, // @[Debug.scala:1877:16] input io_innerCtrl_widx, // @[Debug.scala:1877:16] output io_innerCtrl_safe_ridx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_widx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_source_reset_n, // @[Debug.scala:1877:16] output io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:1877:16] output io_hgDebugInt_0, // @[Debug.scala:1877:16] output io_hgDebugInt_1, // @[Debug.scala:1877:16] output io_hgDebugInt_2, // @[Debug.scala:1877:16] output io_hgDebugInt_3, // @[Debug.scala:1877:16] input io_hartIsInReset_0, // @[Debug.scala:1877:16] input io_hartIsInReset_1, // @[Debug.scala:1877:16] input io_hartIsInReset_2, // @[Debug.scala:1877:16] input io_hartIsInReset_3, // @[Debug.scala:1877:16] input rf_reset // @[Debug.scala:1904:22] ); wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala:211:22] wire [9:0] _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3; // @[AsyncQueue.scala:211:22] wire _dmiXing_auto_out_a_valid; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_opcode; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_param; // @[Debug.scala:1858:27] wire [1:0] _dmiXing_auto_out_a_bits_size; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_source; // @[Debug.scala:1858:27] wire [8:0] _dmiXing_auto_out_a_bits_address; // @[Debug.scala:1858:27] wire [3:0] _dmiXing_auto_out_a_bits_mask; // @[Debug.scala:1858:27] wire [31:0] _dmiXing_auto_out_a_bits_data; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_d_ready; // @[Debug.scala:1858:27] wire _dmInner_auto_dmi_in_a_ready; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_valid; // @[Debug.scala:1857:27] wire [2:0] _dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala:1857:27] wire [1:0] _dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala:1857:27] wire [31:0] _dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala:1857:27] wire [2:0] auto_dmiXing_in_a_mem_0_opcode_0 = auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala:1871:9] wire [8:0] auto_dmiXing_in_a_mem_0_address_0 = auto_dmiXing_in_a_mem_0_address; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_a_mem_0_data_0 = auto_dmiXing_in_a_mem_0_data; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_widx_0 = auto_dmiXing_in_a_widx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_widx_valid_0 = auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_source_reset_n_0 = auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_ridx_0 = auto_dmiXing_in_d_ridx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_ridx_valid_0 = auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_sink_reset_n_0 = auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_valid_0 = auto_dmInner_tl_in_a_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_param_0 = auto_dmInner_tl_in_a_bits_param; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_a_bits_size_0 = auto_dmInner_tl_in_a_bits_size; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_a_bits_source_0 = auto_dmInner_tl_in_a_bits_source; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_a_bits_address_0 = auto_dmInner_tl_in_a_bits_address; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_a_bits_data_0 = auto_dmInner_tl_in_a_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_ready_0 = auto_dmInner_tl_in_d_ready; // @[Debug.scala:1871:9] wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1871:9] wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1871:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1871:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1871:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_resumereq_0 = io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1871:9] wire [9:0] io_innerCtrl_mem_0_hartsel_0 = io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_ackhavereset_0 = io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hasel_0 = io_innerCtrl_mem_0_hasel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_0_0 = io_innerCtrl_mem_0_hamask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_1_0 = io_innerCtrl_mem_0_hamask_1; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_2_0 = io_innerCtrl_mem_0_hamask_2; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_3_0 = io_innerCtrl_mem_0_hamask_3; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_0_0 = io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_1_0 = io_innerCtrl_mem_0_hrmask_1; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_2_0 = io_innerCtrl_mem_0_hrmask_2; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_3_0 = io_innerCtrl_mem_0_hrmask_3; // @[Debug.scala:1871:9] wire io_innerCtrl_widx_0 = io_innerCtrl_widx; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_widx_valid_0 = io_innerCtrl_safe_widx_valid; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_source_reset_n_0 = io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1871:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1871:9] wire io_hartIsInReset_1_0 = io_hartIsInReset_1; // @[Debug.scala:1871:9] wire io_hartIsInReset_2_0 = io_hartIsInReset_2; // @[Debug.scala:1871:9] wire io_hartIsInReset_3_0 = io_hartIsInReset_3; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_1 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_2 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_3 = 1'h0; // @[Debug.scala:1871:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire auto_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[AsyncQueue.scala:211:22] wire [31:0] auto_dmiXing_in_b_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [31:0] auto_dmiXing_in_c_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [3:0] auto_dmiXing_in_b_mem_0_mask = 4'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_b_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_c_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_c_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1871:9] wire [3:0] auto_dmiXing_in_a_mem_0_mask = 4'hF; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_a_mem_0_size = 2'h2; // @[Debug.scala:1858:27, :1871:9] wire [2:0] auto_dmiXing_in_a_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_b_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1871:9] wire childClock = io_debug_clock_0; // @[Debug.scala:1871:9] wire childReset = io_debug_reset_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_0_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_1_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_2_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_3_0; // @[Debug.scala:1871:9] wire dmactive_synced; // @[ShiftReg.scala:48:24] TLDebugModuleInner dmInner ( // @[Debug.scala:1857:27] .clock (io_debug_clock_0), // @[Debug.scala:1871:9] .reset (io_debug_reset_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_ready (auto_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_valid (auto_dmInner_sb2tlOpt_out_a_valid_0), .auto_sb2tlOpt_out_a_bits_opcode (auto_dmInner_sb2tlOpt_out_a_bits_opcode_0), .auto_sb2tlOpt_out_a_bits_size (auto_dmInner_sb2tlOpt_out_a_bits_size_0), .auto_sb2tlOpt_out_a_bits_address (auto_dmInner_sb2tlOpt_out_a_bits_address_0), .auto_sb2tlOpt_out_a_bits_data (auto_dmInner_sb2tlOpt_out_a_bits_data_0), .auto_sb2tlOpt_out_d_ready (auto_dmInner_sb2tlOpt_out_d_ready_0), .auto_sb2tlOpt_out_d_valid (auto_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_opcode (auto_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_param (auto_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_size (auto_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_sink (auto_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_denied (auto_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_data (auto_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_a_ready (auto_dmInner_tl_in_a_ready_0), .auto_tl_in_a_valid (auto_dmInner_tl_in_a_valid_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_opcode (auto_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_param (auto_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_size (auto_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_source (auto_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_address (auto_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_mask (auto_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_data (auto_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_corrupt (auto_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_d_ready (auto_dmInner_tl_in_d_ready_0), // @[Debug.scala:1871:9] .auto_tl_in_d_valid (auto_dmInner_tl_in_d_valid_0), .auto_tl_in_d_bits_opcode (auto_dmInner_tl_in_d_bits_opcode_0), .auto_tl_in_d_bits_size (auto_dmInner_tl_in_d_bits_size_0), .auto_tl_in_d_bits_source (auto_dmInner_tl_in_d_bits_source_0), .auto_tl_in_d_bits_data (auto_dmInner_tl_in_d_bits_data_0), .auto_dmi_in_a_ready (_dmInner_auto_dmi_in_a_ready), .auto_dmi_in_a_valid (_dmiXing_auto_out_a_valid), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_param (_dmiXing_auto_out_a_bits_param), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_size (_dmiXing_auto_out_a_bits_size), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_source (_dmiXing_auto_out_a_bits_source), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_address (_dmiXing_auto_out_a_bits_address), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_mask (_dmiXing_auto_out_a_bits_mask), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_data (_dmiXing_auto_out_a_bits_data), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), // @[Debug.scala:1858:27] .auto_dmi_in_d_ready (_dmiXing_auto_out_d_ready), // @[Debug.scala:1858:27] .auto_dmi_in_d_valid (_dmInner_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), .auto_dmi_in_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), .auto_dmi_in_d_bits_data (_dmInner_auto_dmi_in_d_bits_data), .io_dmactive (dmactive_synced), // @[ShiftReg.scala:48:24] .io_innerCtrl_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3), // @[AsyncQueue.scala:211:22] .io_hgDebugInt_0 (io_hgDebugInt_0_0), .io_hgDebugInt_1 (io_hgDebugInt_1_0), .io_hgDebugInt_2 (io_hgDebugInt_2_0), .io_hgDebugInt_3 (io_hgDebugInt_3_0), .io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1871:9] .io_hartIsInReset_1 (io_hartIsInReset_1_0), // @[Debug.scala:1871:9] .io_hartIsInReset_2 (io_hartIsInReset_2_0), // @[Debug.scala:1871:9] .io_hartIsInReset_3 (io_hartIsInReset_3_0), // @[Debug.scala:1871:9] .io_tl_clock (io_tl_clock_0), // @[Debug.scala:1871:9] .io_tl_reset (io_tl_reset_0) // @[Debug.scala:1871:9] ); // @[Debug.scala:1857:27] TLAsyncCrossingSink_a9d32s1k1z2u dmiXing ( // @[Debug.scala:1858:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_mem_0_opcode (auto_dmiXing_in_a_mem_0_opcode_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_address (auto_dmiXing_in_a_mem_0_address_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_data (auto_dmiXing_in_a_mem_0_data_0), // @[Debug.scala:1871:9] .auto_in_a_ridx (auto_dmiXing_in_a_ridx_0), .auto_in_a_widx (auto_dmiXing_in_a_widx_0), // @[Debug.scala:1871:9] .auto_in_a_safe_ridx_valid (auto_dmiXing_in_a_safe_ridx_valid_0), .auto_in_a_safe_widx_valid (auto_dmiXing_in_a_safe_widx_valid_0), // @[Debug.scala:1871:9] .auto_in_a_safe_source_reset_n (auto_dmiXing_in_a_safe_source_reset_n_0), // @[Debug.scala:1871:9] .auto_in_a_safe_sink_reset_n (auto_dmiXing_in_a_safe_sink_reset_n_0), .auto_in_d_mem_0_opcode (auto_dmiXing_in_d_mem_0_opcode_0), .auto_in_d_mem_0_size (auto_dmiXing_in_d_mem_0_size_0), .auto_in_d_mem_0_source (auto_dmiXing_in_d_mem_0_source_0), .auto_in_d_mem_0_data (auto_dmiXing_in_d_mem_0_data_0), .auto_in_d_ridx (auto_dmiXing_in_d_ridx_0), // @[Debug.scala:1871:9] .auto_in_d_widx (auto_dmiXing_in_d_widx_0), .auto_in_d_safe_ridx_valid (auto_dmiXing_in_d_safe_ridx_valid_0), // @[Debug.scala:1871:9] .auto_in_d_safe_widx_valid (auto_dmiXing_in_d_safe_widx_valid_0), .auto_in_d_safe_source_reset_n (auto_dmiXing_in_d_safe_source_reset_n_0), .auto_in_d_safe_sink_reset_n (auto_dmiXing_in_d_safe_sink_reset_n_0), // @[Debug.scala:1871:9] .auto_out_a_ready (_dmInner_auto_dmi_in_a_ready), // @[Debug.scala:1857:27] .auto_out_a_valid (_dmiXing_auto_out_a_valid), .auto_out_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), .auto_out_a_bits_param (_dmiXing_auto_out_a_bits_param), .auto_out_a_bits_size (_dmiXing_auto_out_a_bits_size), .auto_out_a_bits_source (_dmiXing_auto_out_a_bits_source), .auto_out_a_bits_address (_dmiXing_auto_out_a_bits_address), .auto_out_a_bits_mask (_dmiXing_auto_out_a_bits_mask), .auto_out_a_bits_data (_dmiXing_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), .auto_out_d_ready (_dmiXing_auto_out_d_ready), .auto_out_d_valid (_dmInner_auto_dmi_in_d_valid), // @[Debug.scala:1857:27] .auto_out_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), // @[Debug.scala:1857:27] .auto_out_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), // @[Debug.scala:1857:27] .auto_out_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), // @[Debug.scala:1857:27] .auto_out_d_bits_data (_dmInner_auto_dmi_in_d_bits_data) // @[Debug.scala:1857:27] ); // @[Debug.scala:1858:27] AsyncResetSynchronizerShiftReg_w1_d3_i0_30 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala:45:23] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_d (io_dmactive_0), // @[Debug.scala:1871:9] .io_q (dmactive_synced) ); // @[ShiftReg.scala:45:23] AsyncQueueSink_DebugInternalBundle dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala:211:22] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_deq_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), .io_deq_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), .io_deq_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), .io_deq_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), .io_deq_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), .io_deq_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), .io_deq_bits_hamask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1), .io_deq_bits_hamask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2), .io_deq_bits_hamask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3), .io_deq_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), .io_deq_bits_hrmask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1), .io_deq_bits_hrmask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2), .io_deq_bits_hrmask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3), .io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), // @[Debug.scala:1871:9] .io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), // @[Debug.scala:1871:9] .io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), // @[Debug.scala:1871:9] .io_async_mem_0_hasel (io_innerCtrl_mem_0_hasel_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_0 (io_innerCtrl_mem_0_hamask_0_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_1 (io_innerCtrl_mem_0_hamask_1_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_2 (io_innerCtrl_mem_0_hamask_2_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_3 (io_innerCtrl_mem_0_hamask_3_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_1 (io_innerCtrl_mem_0_hrmask_1_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_2 (io_innerCtrl_mem_0_hrmask_2_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_3 (io_innerCtrl_mem_0_hrmask_3_0), // @[Debug.scala:1871:9] .io_async_ridx (io_innerCtrl_ridx_0), .io_async_widx (io_innerCtrl_widx_0), // @[Debug.scala:1871:9] .io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0), .io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), // @[Debug.scala:1871:9] .io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), // @[Debug.scala:1871:9] .io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0) ); // @[AsyncQueue.scala:211:22] assign auto_dmiXing_in_a_ridx = auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_ridx_valid = auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_sink_reset_n = auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_opcode = auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_size = auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_source = auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_data = auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_widx = auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_widx_valid = auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_source_reset_n = auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_a_ready = auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_valid = auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_opcode = auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_size = auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_source = auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_data = auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] assign io_innerCtrl_ridx = io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_ridx_valid = io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_0 = io_hgDebugInt_0_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_1 = io_hgDebugInt_1_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_2 = io_hgDebugInt_2_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_3 = io_hgDebugInt_3_0; // @[Debug.scala:1871:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_18 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = or(UInt<1>(0h0), _T_70) node _T_72 = and(_T_21, _T_71) node _T_73 = asUInt(reset) node _T_74 = eq(_T_73, UInt<1>(0h0)) when _T_74 : node _T_75 = eq(_T_72, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_72, UInt<1>(0h1), "") : assert_2 node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<14>(0h2000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<13>(0h1000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<17>(0h10000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<18>(0h2f000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<17>(0h10000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<13>(0h1000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<13>(0h1000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = or(_T_84, _T_89) node _T_121 = or(_T_120, _T_94) node _T_122 = or(_T_121, _T_99) node _T_123 = or(_T_122, _T_104) node _T_124 = or(_T_123, _T_109) node _T_125 = or(_T_124, _T_114) node _T_126 = or(_T_125, _T_119) node _T_127 = and(_T_79, _T_126) node _T_128 = or(UInt<1>(0h0), _T_127) node _T_129 = and(UInt<1>(0h0), _T_128) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_129, UInt<1>(0h1), "") : assert_3 node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_136 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_136, UInt<1>(0h1), "") : assert_5 node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(is_aligned, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_143 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_143, UInt<1>(0h1), "") : assert_7 node _T_147 = not(io.in.a.bits.mask) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_148, UInt<1>(0h1), "") : assert_8 node _T_152 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_T_152, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_152, UInt<1>(0h1), "") : assert_9 node _T_156 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_156 : node _T_157 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_158 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<14>(0h2000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<13>(0h1000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<17>(0h10000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<18>(0h2f000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<17>(0h10000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<13>(0h1000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<27>(0h4000000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<13>(0h1000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = or(_T_168, _T_173) node _T_205 = or(_T_204, _T_178) node _T_206 = or(_T_205, _T_183) node _T_207 = or(_T_206, _T_188) node _T_208 = or(_T_207, _T_193) node _T_209 = or(_T_208, _T_198) node _T_210 = or(_T_209, _T_203) node _T_211 = and(_T_163, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = and(_T_162, _T_212) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_213, UInt<1>(0h1), "") : assert_10 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<14>(0h2000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<17>(0h10000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<18>(0h2f000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<27>(0h4000000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = or(_T_225, _T_230) node _T_262 = or(_T_261, _T_235) node _T_263 = or(_T_262, _T_240) node _T_264 = or(_T_263, _T_245) node _T_265 = or(_T_264, _T_250) node _T_266 = or(_T_265, _T_255) node _T_267 = or(_T_266, _T_260) node _T_268 = and(_T_220, _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = and(UInt<1>(0h0), _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_270, UInt<1>(0h1), "") : assert_11 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_277 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_277, UInt<1>(0h1), "") : assert_13 node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(is_aligned, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_284 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_284, UInt<1>(0h1), "") : assert_15 node _T_288 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_288, UInt<1>(0h1), "") : assert_16 node _T_292 = not(io.in.a.bits.mask) node _T_293 = eq(_T_292, UInt<1>(0h0)) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_293, UInt<1>(0h1), "") : assert_17 node _T_297 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_297, UInt<1>(0h1), "") : assert_18 node _T_301 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_301 : node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_306 = and(_T_304, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_307, UInt<1>(0h1), "") : assert_19 node _T_311 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_312 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_313 = and(_T_311, _T_312) node _T_314 = or(UInt<1>(0h0), _T_313) node _T_315 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = and(_T_314, _T_319) node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_322 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_323 = and(_T_321, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<14>(0h2000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<27>(0h4000000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = or(_T_329, _T_334) node _T_361 = or(_T_360, _T_339) node _T_362 = or(_T_361, _T_344) node _T_363 = or(_T_362, _T_349) node _T_364 = or(_T_363, _T_354) node _T_365 = or(_T_364, _T_359) node _T_366 = and(_T_324, _T_365) node _T_367 = or(UInt<1>(0h0), _T_320) node _T_368 = or(_T_367, _T_366) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_368, UInt<1>(0h1), "") : assert_20 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_378 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_378, UInt<1>(0h1), "") : assert_23 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_382, UInt<1>(0h1), "") : assert_24 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_386, UInt<1>(0h1), "") : assert_25 node _T_390 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_390 : node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_398 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_399 = and(_T_397, _T_398) node _T_400 = or(UInt<1>(0h0), _T_399) node _T_401 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_402 = cvt(_T_401) node _T_403 = and(_T_402, asSInt(UInt<13>(0h1000))) node _T_404 = asSInt(_T_403) node _T_405 = eq(_T_404, asSInt(UInt<1>(0h0))) node _T_406 = and(_T_400, _T_405) node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_409 = and(_T_407, _T_408) node _T_410 = or(UInt<1>(0h0), _T_409) node _T_411 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<14>(0h2000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_417 = cvt(_T_416) node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000))) node _T_419 = asSInt(_T_418) node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0))) node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_422 = cvt(_T_421) node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000))) node _T_424 = asSInt(_T_423) node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0))) node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<27>(0h4000000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<13>(0h1000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = or(_T_415, _T_420) node _T_442 = or(_T_441, _T_425) node _T_443 = or(_T_442, _T_430) node _T_444 = or(_T_443, _T_435) node _T_445 = or(_T_444, _T_440) node _T_446 = and(_T_410, _T_445) node _T_447 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_448 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<17>(0h10000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = and(_T_447, _T_452) node _T_454 = or(UInt<1>(0h0), _T_406) node _T_455 = or(_T_454, _T_446) node _T_456 = or(_T_455, _T_453) node _T_457 = and(_T_396, _T_456) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_457, UInt<1>(0h1), "") : assert_26 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(is_aligned, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_467 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_467, UInt<1>(0h1), "") : assert_29 node _T_471 = eq(io.in.a.bits.mask, mask) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_471, UInt<1>(0h1), "") : assert_30 node _T_475 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_475 : node _T_476 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_477 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_480 = and(_T_478, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_483 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_484 = and(_T_482, _T_483) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_487 = cvt(_T_486) node _T_488 = and(_T_487, asSInt(UInt<13>(0h1000))) node _T_489 = asSInt(_T_488) node _T_490 = eq(_T_489, asSInt(UInt<1>(0h0))) node _T_491 = and(_T_485, _T_490) node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_493 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_494 = and(_T_492, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<14>(0h2000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_502 = cvt(_T_501) node _T_503 = and(_T_502, asSInt(UInt<18>(0h2f000))) node _T_504 = asSInt(_T_503) node _T_505 = eq(_T_504, asSInt(UInt<1>(0h0))) node _T_506 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<17>(0h10000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<13>(0h1000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<27>(0h4000000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = or(_T_500, _T_505) node _T_527 = or(_T_526, _T_510) node _T_528 = or(_T_527, _T_515) node _T_529 = or(_T_528, _T_520) node _T_530 = or(_T_529, _T_525) node _T_531 = and(_T_495, _T_530) node _T_532 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_533 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<17>(0h10000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = and(_T_532, _T_537) node _T_539 = or(UInt<1>(0h0), _T_491) node _T_540 = or(_T_539, _T_531) node _T_541 = or(_T_540, _T_538) node _T_542 = and(_T_481, _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_542, UInt<1>(0h1), "") : assert_31 node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(is_aligned, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_552 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_552, UInt<1>(0h1), "") : assert_34 node _T_556 = not(mask) node _T_557 = and(io.in.a.bits.mask, _T_556) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_558, UInt<1>(0h1), "") : assert_35 node _T_562 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_562 : node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_567 = and(_T_565, _T_566) node _T_568 = or(UInt<1>(0h0), _T_567) node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_570 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<14>(0h2000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<13>(0h1000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_584 = cvt(_T_583) node _T_585 = and(_T_584, asSInt(UInt<18>(0h2f000))) node _T_586 = asSInt(_T_585) node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0))) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_594 = cvt(_T_593) node _T_595 = and(_T_594, asSInt(UInt<13>(0h1000))) node _T_596 = asSInt(_T_595) node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0))) node _T_598 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_599 = cvt(_T_598) node _T_600 = and(_T_599, asSInt(UInt<27>(0h4000000))) node _T_601 = asSInt(_T_600) node _T_602 = eq(_T_601, asSInt(UInt<1>(0h0))) node _T_603 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = or(_T_577, _T_582) node _T_609 = or(_T_608, _T_587) node _T_610 = or(_T_609, _T_592) node _T_611 = or(_T_610, _T_597) node _T_612 = or(_T_611, _T_602) node _T_613 = or(_T_612, _T_607) node _T_614 = and(_T_572, _T_613) node _T_615 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<17>(0h10000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = and(_T_615, _T_620) node _T_622 = or(UInt<1>(0h0), _T_614) node _T_623 = or(_T_622, _T_621) node _T_624 = and(_T_568, _T_623) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_624, UInt<1>(0h1), "") : assert_36 node _T_628 = asUInt(reset) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(is_aligned, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_634 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_634, UInt<1>(0h1), "") : assert_39 node _T_638 = eq(io.in.a.bits.mask, mask) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_638, UInt<1>(0h1), "") : assert_40 node _T_642 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_642 : node _T_643 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_644 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_645 = and(_T_643, _T_644) node _T_646 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_647 = and(_T_645, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_650 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<18>(0h2f000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<17>(0h10000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<13>(0h1000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<27>(0h4000000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = or(_T_657, _T_662) node _T_689 = or(_T_688, _T_667) node _T_690 = or(_T_689, _T_672) node _T_691 = or(_T_690, _T_677) node _T_692 = or(_T_691, _T_682) node _T_693 = or(_T_692, _T_687) node _T_694 = and(_T_652, _T_693) node _T_695 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_696 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<17>(0h10000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = and(_T_695, _T_700) node _T_702 = or(UInt<1>(0h0), _T_694) node _T_703 = or(_T_702, _T_701) node _T_704 = and(_T_648, _T_703) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_704, UInt<1>(0h1), "") : assert_41 node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_711 = asUInt(reset) node _T_712 = eq(_T_711, UInt<1>(0h0)) when _T_712 : node _T_713 = eq(is_aligned, UInt<1>(0h0)) when _T_713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_714 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_714, UInt<1>(0h1), "") : assert_44 node _T_718 = eq(io.in.a.bits.mask, mask) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_718, UInt<1>(0h1), "") : assert_45 node _T_722 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_722 : node _T_723 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_724 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_725 = and(_T_723, _T_724) node _T_726 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_727 = and(_T_725, _T_726) node _T_728 = or(UInt<1>(0h0), _T_727) node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_730 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(UInt<1>(0h0), _T_731) node _T_733 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = and(_T_732, _T_737) node _T_739 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_740 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<14>(0h2000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<17>(0h10000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<18>(0h2f000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<17>(0h10000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<27>(0h4000000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<13>(0h1000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = or(_T_744, _T_749) node _T_776 = or(_T_775, _T_754) node _T_777 = or(_T_776, _T_759) node _T_778 = or(_T_777, _T_764) node _T_779 = or(_T_778, _T_769) node _T_780 = or(_T_779, _T_774) node _T_781 = and(_T_739, _T_780) node _T_782 = or(UInt<1>(0h0), _T_738) node _T_783 = or(_T_782, _T_781) node _T_784 = and(_T_728, _T_783) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_784, UInt<1>(0h1), "") : assert_46 node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(is_aligned, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_794 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_794, UInt<1>(0h1), "") : assert_49 node _T_798 = eq(io.in.a.bits.mask, mask) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_798, UInt<1>(0h1), "") : assert_50 node _T_802 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(_T_802, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_802, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_806 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(_T_806, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_806, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_810 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_810 : node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_814 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_814, UInt<1>(0h1), "") : assert_54 node _T_818 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_818, UInt<1>(0h1), "") : assert_55 node _T_822 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_822, UInt<1>(0h1), "") : assert_56 node _T_826 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_826, UInt<1>(0h1), "") : assert_57 node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(sink_ok, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_837 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_837, UInt<1>(0h1), "") : assert_60 node _T_841 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_841, UInt<1>(0h1), "") : assert_61 node _T_845 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_845, UInt<1>(0h1), "") : assert_62 node _T_849 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_849, UInt<1>(0h1), "") : assert_63 node _T_853 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_854 = or(UInt<1>(0h1), _T_853) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_854, UInt<1>(0h1), "") : assert_64 node _T_858 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_858 : node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(sink_ok, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_865, UInt<1>(0h1), "") : assert_67 node _T_869 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_869, UInt<1>(0h1), "") : assert_68 node _T_873 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_873, UInt<1>(0h1), "") : assert_69 node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_878 = or(_T_877, io.in.d.bits.corrupt) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_878, UInt<1>(0h1), "") : assert_70 node _T_882 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_883 = or(UInt<1>(0h1), _T_882) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_883, UInt<1>(0h1), "") : assert_71 node _T_887 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_887 : node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_891 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_891, UInt<1>(0h1), "") : assert_73 node _T_895 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_895, UInt<1>(0h1), "") : assert_74 node _T_899 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_900 = or(UInt<1>(0h1), _T_899) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_900, UInt<1>(0h1), "") : assert_75 node _T_904 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_904 : node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_908 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_908, UInt<1>(0h1), "") : assert_77 node _T_912 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_913 = or(_T_912, io.in.d.bits.corrupt) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_913, UInt<1>(0h1), "") : assert_78 node _T_917 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_918 = or(UInt<1>(0h1), _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_918, UInt<1>(0h1), "") : assert_79 node _T_922 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_926 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(_T_926, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_926, UInt<1>(0h1), "") : assert_81 node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_930, UInt<1>(0h1), "") : assert_82 node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_935 = or(UInt<1>(0h1), _T_934) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_935, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_939 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_939, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_943 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_943, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_947 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_947, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_951 = eq(a_first, UInt<1>(0h0)) node _T_952 = and(io.in.a.valid, _T_951) when _T_952 : node _T_953 = eq(io.in.a.bits.opcode, opcode) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_953, UInt<1>(0h1), "") : assert_87 node _T_957 = eq(io.in.a.bits.param, param) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_957, UInt<1>(0h1), "") : assert_88 node _T_961 = eq(io.in.a.bits.size, size) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_961, UInt<1>(0h1), "") : assert_89 node _T_965 = eq(io.in.a.bits.source, source) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_965, UInt<1>(0h1), "") : assert_90 node _T_969 = eq(io.in.a.bits.address, address) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_969, UInt<1>(0h1), "") : assert_91 node _T_973 = and(io.in.a.ready, io.in.a.valid) node _T_974 = and(_T_973, a_first) when _T_974 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_975 = eq(d_first, UInt<1>(0h0)) node _T_976 = and(io.in.d.valid, _T_975) when _T_976 : node _T_977 = eq(io.in.d.bits.opcode, opcode_1) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_977, UInt<1>(0h1), "") : assert_92 node _T_981 = eq(io.in.d.bits.param, param_1) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_981, UInt<1>(0h1), "") : assert_93 node _T_985 = eq(io.in.d.bits.size, size_1) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_985, UInt<1>(0h1), "") : assert_94 node _T_989 = eq(io.in.d.bits.source, source_1) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_989, UInt<1>(0h1), "") : assert_95 node _T_993 = eq(io.in.d.bits.sink, sink) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_993, UInt<1>(0h1), "") : assert_96 node _T_997 = eq(io.in.d.bits.denied, denied) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_997, UInt<1>(0h1), "") : assert_97 node _T_1001 = and(io.in.d.ready, io.in.d.valid) node _T_1002 = and(_T_1001, d_first) when _T_1002 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1003 = and(io.in.a.valid, a_first_1) node _T_1004 = and(_T_1003, UInt<1>(0h1)) when _T_1004 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1005 = and(io.in.a.ready, io.in.a.valid) node _T_1006 = and(_T_1005, a_first_1) node _T_1007 = and(_T_1006, UInt<1>(0h1)) when _T_1007 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1008 = dshr(inflight, io.in.a.bits.source) node _T_1009 = bits(_T_1008, 0, 0) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1014 = and(io.in.d.valid, d_first_1) node _T_1015 = and(_T_1014, UInt<1>(0h1)) node _T_1016 = eq(d_release_ack, UInt<1>(0h0)) node _T_1017 = and(_T_1015, _T_1016) when _T_1017 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1018 = and(io.in.d.ready, io.in.d.valid) node _T_1019 = and(_T_1018, d_first_1) node _T_1020 = and(_T_1019, UInt<1>(0h1)) node _T_1021 = eq(d_release_ack, UInt<1>(0h0)) node _T_1022 = and(_T_1020, _T_1021) when _T_1022 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1023 = and(io.in.d.valid, d_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) node _T_1025 = eq(d_release_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1027 = dshr(inflight, io.in.d.bits.source) node _T_1028 = bits(_T_1027, 0, 0) node _T_1029 = or(_T_1028, same_cycle_resp) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1033 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1034 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1035 = or(_T_1033, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_100 node _T_1039 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_101 else : node _T_1043 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1044 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1045 = or(_T_1043, _T_1044) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_102 node _T_1049 = eq(io.in.d.bits.size, a_size_lookup) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_103 node _T_1053 = and(io.in.d.valid, d_first_1) node _T_1054 = and(_T_1053, a_first_1) node _T_1055 = and(_T_1054, io.in.a.valid) node _T_1056 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = eq(d_release_ack, UInt<1>(0h0)) node _T_1059 = and(_T_1057, _T_1058) when _T_1059 : node _T_1060 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1061 = or(_T_1060, io.in.a.ready) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_104 node _T_1065 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1066 = orr(a_set_wo_ready) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = or(_T_1065, _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_36 node _T_1072 = orr(inflight) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) node _T_1074 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1075 = or(_T_1073, _T_1074) node _T_1076 = lt(watchdog, plusarg_reader.out) node _T_1077 = or(_T_1075, _T_1076) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1081 = and(io.in.a.ready, io.in.a.valid) node _T_1082 = and(io.in.d.ready, io.in.d.valid) node _T_1083 = or(_T_1081, _T_1082) when _T_1083 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1084 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1085 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1086 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1087 = and(_T_1085, _T_1086) node _T_1088 = and(_T_1084, _T_1087) when _T_1088 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1089 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1090 = and(_T_1089, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1091 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1092 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1093 = and(_T_1091, _T_1092) node _T_1094 = and(_T_1090, _T_1093) when _T_1094 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1095 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1096 = bits(_T_1095, 0, 0) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1101 = and(io.in.d.valid, d_first_2) node _T_1102 = and(_T_1101, UInt<1>(0h1)) node _T_1103 = and(_T_1102, d_release_ack_1) when _T_1103 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1104 = and(io.in.d.ready, io.in.d.valid) node _T_1105 = and(_T_1104, d_first_2) node _T_1106 = and(_T_1105, UInt<1>(0h1)) node _T_1107 = and(_T_1106, d_release_ack_1) when _T_1107 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1108 = and(io.in.d.valid, d_first_2) node _T_1109 = and(_T_1108, UInt<1>(0h1)) node _T_1110 = and(_T_1109, d_release_ack_1) when _T_1110 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1111 = dshr(inflight_1, io.in.d.bits.source) node _T_1112 = bits(_T_1111, 0, 0) node _T_1113 = or(_T_1112, same_cycle_resp_1) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1117 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_109 else : node _T_1121 = eq(io.in.d.bits.size, c_size_lookup) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_110 node _T_1125 = and(io.in.d.valid, d_first_2) node _T_1126 = and(_T_1125, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1127 = and(_T_1126, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1128 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1129 = and(_T_1127, _T_1128) node _T_1130 = and(_T_1129, d_release_ack_1) node _T_1131 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _T_1133 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1134 = or(_T_1133, _WIRE_23.ready) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_111 node _T_1138 = orr(c_set_wo_ready) when _T_1138 : node _T_1139 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_37 node _T_1143 = orr(inflight_1) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) node _T_1145 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1146 = or(_T_1144, _T_1145) node _T_1147 = lt(watchdog_1, plusarg_reader_1.out) node _T_1148 = or(_T_1146, _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1152 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1153 = and(io.in.d.ready, io.in.d.valid) node _T_1154 = or(_T_1152, _T_1153) when _T_1154 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_18( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h0; // @[Edges.scala:92:37] wire _a_first_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:92:37] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire a_first_beats1_opdata = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire a_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] a_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h2; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] io_in_a_bits_mask = 8'hF; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:657:53] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:657:61] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [4:0] _a_sizes_set_interm_T_1 = 5'h5; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'h4; // @[Monitor.scala:658:51] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [11:0] is_aligned_mask = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFFC; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC; // @[package.scala:243:71] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [28:0] _is_aligned_T = {27'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_0_1 = _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_0_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire mask_sub_1_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_1 = _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_3_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1081 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1081; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1081; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [28:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1004 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1004; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1004; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1081 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = {3'h0, a_set}; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'h5 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1053 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1053 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1125 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1125 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_166 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_166( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_122 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_122( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntToFPUnit : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<65>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip fcsr_rm : UInt<3>} connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.sfence.bits.hg invalidate io.resp.bits.sfence.bits.hv invalidate io.resp.bits.sfence.bits.asid invalidate io.resp.bits.sfence.bits.addr invalidate io.resp.bits.sfence.bits.rs2 invalidate io.resp.bits.sfence.bits.rs1 invalidate io.resp.bits.sfence.valid invalidate io.resp.bits.mxcpt.bits invalidate io.resp.bits.mxcpt.valid invalidate io.resp.bits.addr invalidate io.resp.bits.fflags.bits.flags invalidate io.resp.bits.fflags.bits.uop.debug_tsrc invalidate io.resp.bits.fflags.bits.uop.debug_fsrc invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.resp.bits.fflags.bits.uop.bp_debug_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.resp.bits.fflags.bits.uop.fp_single invalidate io.resp.bits.fflags.bits.uop.fp_val invalidate io.resp.bits.fflags.bits.uop.frs3_en invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype invalidate io.resp.bits.fflags.bits.uop.dst_rtype invalidate io.resp.bits.fflags.bits.uop.ldst_val invalidate io.resp.bits.fflags.bits.uop.lrs3 invalidate io.resp.bits.fflags.bits.uop.lrs2 invalidate io.resp.bits.fflags.bits.uop.lrs1 invalidate io.resp.bits.fflags.bits.uop.ldst invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.resp.bits.fflags.bits.uop.flush_on_commit invalidate io.resp.bits.fflags.bits.uop.is_unique invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.resp.bits.fflags.bits.uop.uses_stq invalidate io.resp.bits.fflags.bits.uop.uses_ldq invalidate io.resp.bits.fflags.bits.uop.is_amo invalidate io.resp.bits.fflags.bits.uop.is_fencei invalidate io.resp.bits.fflags.bits.uop.is_fence invalidate io.resp.bits.fflags.bits.uop.mem_signed invalidate io.resp.bits.fflags.bits.uop.mem_size invalidate io.resp.bits.fflags.bits.uop.mem_cmd invalidate io.resp.bits.fflags.bits.uop.bypassable invalidate io.resp.bits.fflags.bits.uop.exc_cause invalidate io.resp.bits.fflags.bits.uop.exception invalidate io.resp.bits.fflags.bits.uop.stale_pdst invalidate io.resp.bits.fflags.bits.uop.ppred_busy invalidate io.resp.bits.fflags.bits.uop.prs3_busy invalidate io.resp.bits.fflags.bits.uop.prs2_busy invalidate io.resp.bits.fflags.bits.uop.prs1_busy invalidate io.resp.bits.fflags.bits.uop.ppred invalidate io.resp.bits.fflags.bits.uop.prs3 invalidate io.resp.bits.fflags.bits.uop.prs2 invalidate io.resp.bits.fflags.bits.uop.prs1 invalidate io.resp.bits.fflags.bits.uop.pdst invalidate io.resp.bits.fflags.bits.uop.rxq_idx invalidate io.resp.bits.fflags.bits.uop.stq_idx invalidate io.resp.bits.fflags.bits.uop.ldq_idx invalidate io.resp.bits.fflags.bits.uop.rob_idx invalidate io.resp.bits.fflags.bits.uop.csr_addr invalidate io.resp.bits.fflags.bits.uop.imm_packed invalidate io.resp.bits.fflags.bits.uop.taken invalidate io.resp.bits.fflags.bits.uop.pc_lob invalidate io.resp.bits.fflags.bits.uop.edge_inst invalidate io.resp.bits.fflags.bits.uop.ftq_idx invalidate io.resp.bits.fflags.bits.uop.br_tag invalidate io.resp.bits.fflags.bits.uop.br_mask invalidate io.resp.bits.fflags.bits.uop.is_sfb invalidate io.resp.bits.fflags.bits.uop.is_jal invalidate io.resp.bits.fflags.bits.uop.is_jalr invalidate io.resp.bits.fflags.bits.uop.is_br invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_state invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type invalidate io.resp.bits.fflags.bits.uop.fu_code invalidate io.resp.bits.fflags.bits.uop.iq_type invalidate io.resp.bits.fflags.bits.uop.debug_pc invalidate io.resp.bits.fflags.bits.uop.is_rvc invalidate io.resp.bits.fflags.bits.uop.debug_inst invalidate io.resp.bits.fflags.bits.uop.inst invalidate io.resp.bits.fflags.bits.uop.uopc invalidate io.resp.bits.fflags.valid invalidate io.resp.bits.data invalidate io.resp.bits.predicated invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.req.ready, UInt<1>(0h1) wire _r_valids_WIRE : UInt<1>[2] connect _r_valids_WIRE[0], UInt<1>(0h0) connect _r_valids_WIRE[1], UInt<1>(0h0) regreset r_valids : UInt<1>[2], clock, reset, _r_valids_WIRE reg r_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[2], clock node _r_valids_0_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask) node _r_valids_0_T_1 = neq(_r_valids_0_T, UInt<1>(0h0)) node _r_valids_0_T_2 = eq(_r_valids_0_T_1, UInt<1>(0h0)) node _r_valids_0_T_3 = and(io.req.valid, _r_valids_0_T_2) node _r_valids_0_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_0_T_5 = and(_r_valids_0_T_3, _r_valids_0_T_4) connect r_valids[0], _r_valids_0_T_5 connect r_uops[0], io.req.bits.uop node _r_uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_0_br_mask_T_1 = and(io.req.bits.uop.br_mask, _r_uops_0_br_mask_T) connect r_uops[0].br_mask, _r_uops_0_br_mask_T_1 node _r_valids_1_T = and(io.brupdate.b1.mispredict_mask, r_uops[0].br_mask) node _r_valids_1_T_1 = neq(_r_valids_1_T, UInt<1>(0h0)) node _r_valids_1_T_2 = eq(_r_valids_1_T_1, UInt<1>(0h0)) node _r_valids_1_T_3 = and(r_valids[0], _r_valids_1_T_2) node _r_valids_1_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_1_T_5 = and(_r_valids_1_T_3, _r_valids_1_T_4) connect r_valids[1], _r_valids_1_T_5 connect r_uops[1], r_uops[0] node _r_uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_1_br_mask_T_1 = and(r_uops[0].br_mask, _r_uops_1_br_mask_T) connect r_uops[1].br_mask, _r_uops_1_br_mask_T_1 node _io_resp_valid_T = and(io.brupdate.b1.mispredict_mask, r_uops[1].br_mask) node _io_resp_valid_T_1 = neq(_io_resp_valid_T, UInt<1>(0h0)) node _io_resp_valid_T_2 = eq(_io_resp_valid_T_1, UInt<1>(0h0)) node _io_resp_valid_T_3 = and(r_valids[1], _io_resp_valid_T_2) connect io.resp.valid, _io_resp_valid_T_3 connect io.resp.bits.predicated, UInt<1>(0h0) connect io.resp.bits.uop, r_uops[1] node _io_resp_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_resp_bits_uop_br_mask_T_1 = and(r_uops[1].br_mask, _io_resp_bits_uop_br_mask_T) connect io.resp.bits.uop.br_mask, _io_resp_bits_uop_br_mask_T_1 inst fp_decoder of UOPCodeFPUDecoder connect fp_decoder.clock, clock connect fp_decoder.reset, reset connect fp_decoder.io.uopc, io.req.bits.uop.uopc node _fp_rm_T = bits(io.req.bits.uop.imm_packed, 2, 0) node _fp_rm_T_1 = eq(_fp_rm_T, UInt<3>(0h7)) node _fp_rm_T_2 = bits(io.req.bits.uop.imm_packed, 2, 0) node fp_rm = mux(_fp_rm_T_1, io.fcsr_rm, _fp_rm_T_2) wire req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect req.vec, fp_decoder.io.sigs.vec connect req.wflags, fp_decoder.io.sigs.wflags connect req.sqrt, fp_decoder.io.sigs.sqrt connect req.div, fp_decoder.io.sigs.div connect req.fma, fp_decoder.io.sigs.fma connect req.fastpipe, fp_decoder.io.sigs.fastpipe connect req.toint, fp_decoder.io.sigs.toint connect req.fromint, fp_decoder.io.sigs.fromint connect req.typeTagOut, fp_decoder.io.sigs.typeTagOut connect req.typeTagIn, fp_decoder.io.sigs.typeTagIn connect req.swap23, fp_decoder.io.sigs.swap23 connect req.swap12, fp_decoder.io.sigs.swap12 connect req.ren3, fp_decoder.io.sigs.ren3 connect req.ren2, fp_decoder.io.sigs.ren2 connect req.ren1, fp_decoder.io.sigs.ren1 connect req.wen, fp_decoder.io.sigs.wen connect req.ldst, fp_decoder.io.sigs.ldst connect req.rm, fp_rm node _req_in1_prev_unswizzled_T = bits(io.req.bits.rs1_data, 31, 31) node _req_in1_prev_unswizzled_T_1 = bits(io.req.bits.rs1_data, 52, 52) node _req_in1_prev_unswizzled_T_2 = bits(io.req.bits.rs1_data, 30, 0) node req_in1_prev_unswizzled_hi = cat(_req_in1_prev_unswizzled_T, _req_in1_prev_unswizzled_T_1) node req_in1_prev_unswizzled = cat(req_in1_prev_unswizzled_hi, _req_in1_prev_unswizzled_T_2) node req_in1_prev_prev_sign = bits(req_in1_prev_unswizzled, 32, 32) node req_in1_prev_prev_fractIn = bits(req_in1_prev_unswizzled, 22, 0) node req_in1_prev_prev_expIn = bits(req_in1_prev_unswizzled, 31, 23) node _req_in1_prev_prev_fractOut_T = shl(req_in1_prev_prev_fractIn, 53) node req_in1_prev_prev_fractOut = shr(_req_in1_prev_prev_fractOut_T, 24) node req_in1_prev_prev_expOut_expCode = bits(req_in1_prev_prev_expIn, 8, 6) node _req_in1_prev_prev_expOut_commonCase_T = add(req_in1_prev_prev_expIn, UInt<12>(0h800)) node _req_in1_prev_prev_expOut_commonCase_T_1 = tail(_req_in1_prev_prev_expOut_commonCase_T, 1) node _req_in1_prev_prev_expOut_commonCase_T_2 = sub(_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node req_in1_prev_prev_expOut_commonCase = tail(_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _req_in1_prev_prev_expOut_T = eq(req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _req_in1_prev_prev_expOut_T_1 = geq(req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _req_in1_prev_prev_expOut_T_2 = or(_req_in1_prev_prev_expOut_T, _req_in1_prev_prev_expOut_T_1) node _req_in1_prev_prev_expOut_T_3 = bits(req_in1_prev_prev_expOut_commonCase, 8, 0) node _req_in1_prev_prev_expOut_T_4 = cat(req_in1_prev_prev_expOut_expCode, _req_in1_prev_prev_expOut_T_3) node _req_in1_prev_prev_expOut_T_5 = bits(req_in1_prev_prev_expOut_commonCase, 11, 0) node req_in1_prev_prev_expOut = mux(_req_in1_prev_prev_expOut_T_2, _req_in1_prev_prev_expOut_T_4, _req_in1_prev_prev_expOut_T_5) node req_in1_prev_prev_hi = cat(req_in1_prev_prev_sign, req_in1_prev_prev_expOut) node req_in1_floats_0 = cat(req_in1_prev_prev_hi, req_in1_prev_prev_fractOut) node _req_in1_prev_isbox_T = bits(io.req.bits.rs1_data, 64, 60) node req_in1_prev_isbox = andr(_req_in1_prev_isbox_T) node req_in1_oks_0 = and(req_in1_prev_isbox, UInt<1>(0h1)) node _req_in1_truncIdx_T = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in1_truncIdx = bits(_req_in1_truncIdx_T, 0, 0) node _req_in1_T = eq(req_in1_truncIdx, UInt<1>(0h1)) node _req_in1_T_1 = mux(_req_in1_T, UInt<1>(0h1), req_in1_oks_0) node _req_in1_truncIdx_T_1 = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in1_truncIdx_1 = bits(_req_in1_truncIdx_T_1, 0, 0) node _req_in1_T_2 = eq(req_in1_truncIdx_1, UInt<1>(0h1)) node _req_in1_T_3 = mux(_req_in1_T_2, io.req.bits.rs1_data, req_in1_floats_0) node _req_in1_T_4 = mux(_req_in1_T_1, _req_in1_T_3, UInt<65>(0he008000000000000)) connect req.in1, _req_in1_T_4 node _req_in2_prev_unswizzled_T = bits(io.req.bits.rs2_data, 31, 31) node _req_in2_prev_unswizzled_T_1 = bits(io.req.bits.rs2_data, 52, 52) node _req_in2_prev_unswizzled_T_2 = bits(io.req.bits.rs2_data, 30, 0) node req_in2_prev_unswizzled_hi = cat(_req_in2_prev_unswizzled_T, _req_in2_prev_unswizzled_T_1) node req_in2_prev_unswizzled = cat(req_in2_prev_unswizzled_hi, _req_in2_prev_unswizzled_T_2) node req_in2_prev_prev_sign = bits(req_in2_prev_unswizzled, 32, 32) node req_in2_prev_prev_fractIn = bits(req_in2_prev_unswizzled, 22, 0) node req_in2_prev_prev_expIn = bits(req_in2_prev_unswizzled, 31, 23) node _req_in2_prev_prev_fractOut_T = shl(req_in2_prev_prev_fractIn, 53) node req_in2_prev_prev_fractOut = shr(_req_in2_prev_prev_fractOut_T, 24) node req_in2_prev_prev_expOut_expCode = bits(req_in2_prev_prev_expIn, 8, 6) node _req_in2_prev_prev_expOut_commonCase_T = add(req_in2_prev_prev_expIn, UInt<12>(0h800)) node _req_in2_prev_prev_expOut_commonCase_T_1 = tail(_req_in2_prev_prev_expOut_commonCase_T, 1) node _req_in2_prev_prev_expOut_commonCase_T_2 = sub(_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node req_in2_prev_prev_expOut_commonCase = tail(_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _req_in2_prev_prev_expOut_T = eq(req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _req_in2_prev_prev_expOut_T_1 = geq(req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _req_in2_prev_prev_expOut_T_2 = or(_req_in2_prev_prev_expOut_T, _req_in2_prev_prev_expOut_T_1) node _req_in2_prev_prev_expOut_T_3 = bits(req_in2_prev_prev_expOut_commonCase, 8, 0) node _req_in2_prev_prev_expOut_T_4 = cat(req_in2_prev_prev_expOut_expCode, _req_in2_prev_prev_expOut_T_3) node _req_in2_prev_prev_expOut_T_5 = bits(req_in2_prev_prev_expOut_commonCase, 11, 0) node req_in2_prev_prev_expOut = mux(_req_in2_prev_prev_expOut_T_2, _req_in2_prev_prev_expOut_T_4, _req_in2_prev_prev_expOut_T_5) node req_in2_prev_prev_hi = cat(req_in2_prev_prev_sign, req_in2_prev_prev_expOut) node req_in2_floats_0 = cat(req_in2_prev_prev_hi, req_in2_prev_prev_fractOut) node _req_in2_prev_isbox_T = bits(io.req.bits.rs2_data, 64, 60) node req_in2_prev_isbox = andr(_req_in2_prev_isbox_T) node req_in2_oks_0 = and(req_in2_prev_isbox, UInt<1>(0h1)) node _req_in2_truncIdx_T = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in2_truncIdx = bits(_req_in2_truncIdx_T, 0, 0) node _req_in2_T = eq(req_in2_truncIdx, UInt<1>(0h1)) node _req_in2_T_1 = mux(_req_in2_T, UInt<1>(0h1), req_in2_oks_0) node _req_in2_truncIdx_T_1 = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in2_truncIdx_1 = bits(_req_in2_truncIdx_T_1, 0, 0) node _req_in2_T_2 = eq(req_in2_truncIdx_1, UInt<1>(0h1)) node _req_in2_T_3 = mux(_req_in2_T_2, io.req.bits.rs2_data, req_in2_floats_0) node _req_in2_T_4 = mux(_req_in2_T_1, _req_in2_T_3, UInt<65>(0he008000000000000)) connect req.in2, _req_in2_T_4 invalidate req.in3 node _req_typ_T = bits(io.req.bits.uop.imm_packed, 9, 8) connect req.typ, _req_typ_T invalidate req.fmt invalidate req.fmaCmd node _T = and(io.req.valid, fp_decoder.io.sigs.fromint) node _T_1 = bits(req.in1, 64, 64) node _T_2 = and(_T, _T_1) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed: [func] IntToFP integer input has 65th high-order bit set!\n at functional-unit.scala:618 assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _T_7 = eq(fp_decoder.io.sigs.fromint, UInt<1>(0h0)) node _T_8 = and(io.req.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: [func] Only support fromInt micro-ops.\n at functional-unit.scala:621 assert (!(io.req.valid && !fp_ctrl.fromint),\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 inst ifpu of IntToFP connect ifpu.clock, clock connect ifpu.reset, reset connect ifpu.io.in.valid, io.req.valid connect ifpu.io.in.bits.in1, req.in1 connect ifpu.io.in.bits.typ, req.typ connect ifpu.io.in.bits.rm, req.rm connect ifpu.io.in.bits.vec, req.vec connect ifpu.io.in.bits.wflags, req.wflags connect ifpu.io.in.bits.sqrt, req.sqrt connect ifpu.io.in.bits.div, req.div connect ifpu.io.in.bits.fma, req.fma connect ifpu.io.in.bits.fastpipe, req.fastpipe connect ifpu.io.in.bits.toint, req.toint connect ifpu.io.in.bits.fromint, req.fromint connect ifpu.io.in.bits.typeTagOut, req.typeTagOut connect ifpu.io.in.bits.typeTagIn, req.typeTagIn connect ifpu.io.in.bits.swap23, req.swap23 connect ifpu.io.in.bits.swap12, req.swap12 connect ifpu.io.in.bits.ren3, req.ren3 connect ifpu.io.in.bits.ren2, req.ren2 connect ifpu.io.in.bits.ren1, req.ren1 connect ifpu.io.in.bits.wen, req.wen connect ifpu.io.in.bits.ldst, req.ldst connect ifpu.io.in.bits.in1, io.req.bits.rs1_data node _out_double_T = eq(fp_decoder.io.sigs.typeTagOut, UInt<1>(0h1)) regreset out_double_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect out_double_pipe_v, io.req.valid reg out_double_pipe_b : UInt<1>, clock when io.req.valid : connect out_double_pipe_b, _out_double_T regreset out_double_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect out_double_pipe_pipe_v, out_double_pipe_v reg out_double_pipe_pipe_b : UInt<1>, clock when out_double_pipe_v : connect out_double_pipe_pipe_b, out_double_pipe_b wire out_double_pipe_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect out_double_pipe_pipe_out.valid, out_double_pipe_pipe_v connect out_double_pipe_pipe_out.bits, out_double_pipe_pipe_b node _io_resp_bits_data_opts_bigger_swizzledNaN_T = andr(UInt<20>(0hfffff)) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_1 = bits(ifpu.io.out.bits.data, 31, 31) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_2 = bits(ifpu.io.out.bits.data, 32, 32) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_3 = bits(ifpu.io.out.bits.data, 30, 0) node io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi = cat(UInt<20>(0hfffff), _io_resp_bits_data_opts_bigger_swizzledNaN_T_2) node io_resp_bits_data_opts_bigger_swizzledNaN_lo = cat(io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi, _io_resp_bits_data_opts_bigger_swizzledNaN_T_3) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo = cat(UInt<7>(0h7f), _io_resp_bits_data_opts_bigger_swizzledNaN_T_1) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _io_resp_bits_data_opts_bigger_swizzledNaN_T) node io_resp_bits_data_opts_bigger_swizzledNaN_hi = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi, io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo) node io_resp_bits_data_opts_bigger_swizzledNaN = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi, io_resp_bits_data_opts_bigger_swizzledNaN_lo) node _io_resp_bits_data_opts_bigger_T = andr(UInt<3>(0h7)) node io_resp_bits_data_opts_bigger = mux(_io_resp_bits_data_opts_bigger_T, io_resp_bits_data_opts_bigger_swizzledNaN, UInt<65>(0h1ffffffffffffffff)) node io_resp_bits_data_opts_0 = or(io_resp_bits_data_opts_bigger, UInt<1>(0h0)) node _io_resp_bits_data_T = eq(out_double_pipe_pipe_out.bits, UInt<1>(0h1)) node _io_resp_bits_data_T_1 = mux(_io_resp_bits_data_T, ifpu.io.out.bits.data, io_resp_bits_data_opts_0) connect io.resp.bits.data, _io_resp_bits_data_T_1 connect io.resp.bits.fflags.valid, ifpu.io.out.valid connect io.resp.bits.fflags.bits.uop.debug_tsrc, io.resp.bits.uop.debug_tsrc connect io.resp.bits.fflags.bits.uop.debug_fsrc, io.resp.bits.uop.debug_fsrc connect io.resp.bits.fflags.bits.uop.bp_xcpt_if, io.resp.bits.uop.bp_xcpt_if connect io.resp.bits.fflags.bits.uop.bp_debug_if, io.resp.bits.uop.bp_debug_if connect io.resp.bits.fflags.bits.uop.xcpt_ma_if, io.resp.bits.uop.xcpt_ma_if connect io.resp.bits.fflags.bits.uop.xcpt_ae_if, io.resp.bits.uop.xcpt_ae_if connect io.resp.bits.fflags.bits.uop.xcpt_pf_if, io.resp.bits.uop.xcpt_pf_if connect io.resp.bits.fflags.bits.uop.fp_single, io.resp.bits.uop.fp_single connect io.resp.bits.fflags.bits.uop.fp_val, io.resp.bits.uop.fp_val connect io.resp.bits.fflags.bits.uop.frs3_en, io.resp.bits.uop.frs3_en connect io.resp.bits.fflags.bits.uop.lrs2_rtype, io.resp.bits.uop.lrs2_rtype connect io.resp.bits.fflags.bits.uop.lrs1_rtype, io.resp.bits.uop.lrs1_rtype connect io.resp.bits.fflags.bits.uop.dst_rtype, io.resp.bits.uop.dst_rtype connect io.resp.bits.fflags.bits.uop.ldst_val, io.resp.bits.uop.ldst_val connect io.resp.bits.fflags.bits.uop.lrs3, io.resp.bits.uop.lrs3 connect io.resp.bits.fflags.bits.uop.lrs2, io.resp.bits.uop.lrs2 connect io.resp.bits.fflags.bits.uop.lrs1, io.resp.bits.uop.lrs1 connect io.resp.bits.fflags.bits.uop.ldst, io.resp.bits.uop.ldst connect io.resp.bits.fflags.bits.uop.ldst_is_rs1, io.resp.bits.uop.ldst_is_rs1 connect io.resp.bits.fflags.bits.uop.flush_on_commit, io.resp.bits.uop.flush_on_commit connect io.resp.bits.fflags.bits.uop.is_unique, io.resp.bits.uop.is_unique connect io.resp.bits.fflags.bits.uop.is_sys_pc2epc, io.resp.bits.uop.is_sys_pc2epc connect io.resp.bits.fflags.bits.uop.uses_stq, io.resp.bits.uop.uses_stq connect io.resp.bits.fflags.bits.uop.uses_ldq, io.resp.bits.uop.uses_ldq connect io.resp.bits.fflags.bits.uop.is_amo, io.resp.bits.uop.is_amo connect io.resp.bits.fflags.bits.uop.is_fencei, io.resp.bits.uop.is_fencei connect io.resp.bits.fflags.bits.uop.is_fence, io.resp.bits.uop.is_fence connect io.resp.bits.fflags.bits.uop.mem_signed, io.resp.bits.uop.mem_signed connect io.resp.bits.fflags.bits.uop.mem_size, io.resp.bits.uop.mem_size connect io.resp.bits.fflags.bits.uop.mem_cmd, io.resp.bits.uop.mem_cmd connect io.resp.bits.fflags.bits.uop.bypassable, io.resp.bits.uop.bypassable connect io.resp.bits.fflags.bits.uop.exc_cause, io.resp.bits.uop.exc_cause connect io.resp.bits.fflags.bits.uop.exception, io.resp.bits.uop.exception connect io.resp.bits.fflags.bits.uop.stale_pdst, io.resp.bits.uop.stale_pdst connect io.resp.bits.fflags.bits.uop.ppred_busy, io.resp.bits.uop.ppred_busy connect io.resp.bits.fflags.bits.uop.prs3_busy, io.resp.bits.uop.prs3_busy connect io.resp.bits.fflags.bits.uop.prs2_busy, io.resp.bits.uop.prs2_busy connect io.resp.bits.fflags.bits.uop.prs1_busy, io.resp.bits.uop.prs1_busy connect io.resp.bits.fflags.bits.uop.ppred, io.resp.bits.uop.ppred connect io.resp.bits.fflags.bits.uop.prs3, io.resp.bits.uop.prs3 connect io.resp.bits.fflags.bits.uop.prs2, io.resp.bits.uop.prs2 connect io.resp.bits.fflags.bits.uop.prs1, io.resp.bits.uop.prs1 connect io.resp.bits.fflags.bits.uop.pdst, io.resp.bits.uop.pdst connect io.resp.bits.fflags.bits.uop.rxq_idx, io.resp.bits.uop.rxq_idx connect io.resp.bits.fflags.bits.uop.stq_idx, io.resp.bits.uop.stq_idx connect io.resp.bits.fflags.bits.uop.ldq_idx, io.resp.bits.uop.ldq_idx connect io.resp.bits.fflags.bits.uop.rob_idx, io.resp.bits.uop.rob_idx connect io.resp.bits.fflags.bits.uop.csr_addr, io.resp.bits.uop.csr_addr connect io.resp.bits.fflags.bits.uop.imm_packed, io.resp.bits.uop.imm_packed connect io.resp.bits.fflags.bits.uop.taken, io.resp.bits.uop.taken connect io.resp.bits.fflags.bits.uop.pc_lob, io.resp.bits.uop.pc_lob connect io.resp.bits.fflags.bits.uop.edge_inst, io.resp.bits.uop.edge_inst connect io.resp.bits.fflags.bits.uop.ftq_idx, io.resp.bits.uop.ftq_idx connect io.resp.bits.fflags.bits.uop.br_tag, io.resp.bits.uop.br_tag connect io.resp.bits.fflags.bits.uop.br_mask, io.resp.bits.uop.br_mask connect io.resp.bits.fflags.bits.uop.is_sfb, io.resp.bits.uop.is_sfb connect io.resp.bits.fflags.bits.uop.is_jal, io.resp.bits.uop.is_jal connect io.resp.bits.fflags.bits.uop.is_jalr, io.resp.bits.uop.is_jalr connect io.resp.bits.fflags.bits.uop.is_br, io.resp.bits.uop.is_br connect io.resp.bits.fflags.bits.uop.iw_p2_poisoned, io.resp.bits.uop.iw_p2_poisoned connect io.resp.bits.fflags.bits.uop.iw_p1_poisoned, io.resp.bits.uop.iw_p1_poisoned connect io.resp.bits.fflags.bits.uop.iw_state, io.resp.bits.uop.iw_state connect io.resp.bits.fflags.bits.uop.ctrl.is_std, io.resp.bits.uop.ctrl.is_std connect io.resp.bits.fflags.bits.uop.ctrl.is_sta, io.resp.bits.uop.ctrl.is_sta connect io.resp.bits.fflags.bits.uop.ctrl.is_load, io.resp.bits.uop.ctrl.is_load connect io.resp.bits.fflags.bits.uop.ctrl.csr_cmd, io.resp.bits.uop.ctrl.csr_cmd connect io.resp.bits.fflags.bits.uop.ctrl.fcn_dw, io.resp.bits.uop.ctrl.fcn_dw connect io.resp.bits.fflags.bits.uop.ctrl.op_fcn, io.resp.bits.uop.ctrl.op_fcn connect io.resp.bits.fflags.bits.uop.ctrl.imm_sel, io.resp.bits.uop.ctrl.imm_sel connect io.resp.bits.fflags.bits.uop.ctrl.op2_sel, io.resp.bits.uop.ctrl.op2_sel connect io.resp.bits.fflags.bits.uop.ctrl.op1_sel, io.resp.bits.uop.ctrl.op1_sel connect io.resp.bits.fflags.bits.uop.ctrl.br_type, io.resp.bits.uop.ctrl.br_type connect io.resp.bits.fflags.bits.uop.fu_code, io.resp.bits.uop.fu_code connect io.resp.bits.fflags.bits.uop.iq_type, io.resp.bits.uop.iq_type connect io.resp.bits.fflags.bits.uop.debug_pc, io.resp.bits.uop.debug_pc connect io.resp.bits.fflags.bits.uop.is_rvc, io.resp.bits.uop.is_rvc connect io.resp.bits.fflags.bits.uop.debug_inst, io.resp.bits.uop.debug_inst connect io.resp.bits.fflags.bits.uop.inst, io.resp.bits.uop.inst connect io.resp.bits.fflags.bits.uop.uopc, io.resp.bits.uop.uopc connect io.resp.bits.fflags.bits.flags, ifpu.io.out.bits.exc	module IntToFPUnit( // @[functional-unit.scala:591:7] input clock, // @[functional-unit.scala:591:7] input reset, // @[functional-unit.scala:591:7] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14] ); wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [64:0] _ifpu_io_out_bits_data; // @[functional-unit.scala:624:20] wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[functional-unit.scala:600:26] wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[functional-unit.scala:600:26] wire _fp_decoder_io_sigs_fromint; // @[functional-unit.scala:600:26] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:591:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:591:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:591:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:591:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:591:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:591:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:591:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:591:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:591:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:591:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:591:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[functional-unit.scala:591:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:591:7] wire _io_resp_bits_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _io_resp_bits_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[functional-unit.scala:591:7] wire [64:0] req_in3 = 65'h0; // @[functional-unit.scala:605:17] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_ready = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:591:7] wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35] wire req_vec = 1'h0; // @[functional-unit.scala:605:17] wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:591:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:591:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [1:0] req_fmaCmd = 2'h0; // @[functional-unit.scala:605:17] wire [1:0] req_fmt = 2'h0; // @[functional-unit.scala:605:17] wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47] wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0 = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst_0 = io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0 = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_rvc_0 = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0 = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0 = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_br_0 = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jalr_0 = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jal_0 = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sfb_0 = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire [15:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [15:0] io_resp_bits_fflags_bits_uop_br_mask_0 = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_br_tag_0 = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx_0 = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_edge_inst_0 = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0 = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_taken_0 = io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0 = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0 = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx_0 = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx_0 = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx_0 = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0 = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_pdst_0 = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs1_0 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs2_0 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs3_0 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ppred_0 = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs1_busy_0 = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs2_busy_0 = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs3_busy_0 = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ppred_busy_0 = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst_0 = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_exception_0 = io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0 = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bypassable_0 = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0 = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0 = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_mem_signed_0 = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fence_0 = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fencei_0 = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_amo_0 = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_ldq_0 = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_stq_0 = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_unique_0 = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit_0 = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0 = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_val_0 = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0 = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_frs3_en_0 = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_val_0 = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_single_0 = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if_0 = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0 = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0 = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [64:0] _io_resp_bits_data_T_1; // @[package.scala:39:76] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_valid_0; // @[functional-unit.scala:591:7] wire [64:0] io_resp_bits_data_0; // @[functional-unit.scala:591:7] wire io_resp_valid_0; // @[functional-unit.scala:591:7] reg r_valids_0; // @[functional-unit.scala:236:27] reg r_valids_1; // @[functional-unit.scala:236:27] reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_is_br; // @[functional-unit.scala:237:23] reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_0_is_jal; // @[functional-unit.scala:237:23] reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23] reg [15:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_0_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_pdst; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs1; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs2; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs3; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ppred; // @[functional-unit.scala:237:23] reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_0_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_0_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23] reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_0_is_fence; // @[functional-unit.scala:237:23] reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_0_is_amo; // @[functional-unit.scala:237:23] reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_0_is_unique; // @[functional-unit.scala:237:23] reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_0_fp_val; // @[functional-unit.scala:237:23] reg r_uops_0_fp_single; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uopc_0 = r_uops_1_uopc; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_inst_0 = r_uops_1_inst; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_inst_0 = r_uops_1_debug_inst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_rvc_0 = r_uops_1_is_rvc; // @[functional-unit.scala:237:23, :591:7] reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_pc_0 = r_uops_1_debug_pc; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iq_type_0 = r_uops_1_iq_type; // @[functional-unit.scala:237:23, :591:7] reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fu_code_0 = r_uops_1_fu_code; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_state_0 = r_uops_1_iw_state; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_br; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_br_0 = r_uops_1_is_br; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jalr_0 = r_uops_1_is_jalr; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jal; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jal_0 = r_uops_1_is_jal; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sfb_0 = r_uops_1_is_sfb; // @[functional-unit.scala:237:23, :591:7] reg [15:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_br_tag_0 = r_uops_1_br_tag; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ftq_idx_0 = r_uops_1_ftq_idx; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_edge_inst_0 = r_uops_1_edge_inst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pc_lob_0 = r_uops_1_pc_lob; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_taken; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_taken_0 = r_uops_1_taken; // @[functional-unit.scala:237:23, :591:7] reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_imm_packed_0 = r_uops_1_imm_packed; // @[functional-unit.scala:237:23, :591:7] reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_csr_addr_0 = r_uops_1_csr_addr; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rob_idx_0 = r_uops_1_rob_idx; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldq_idx_0 = r_uops_1_ldq_idx; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stq_idx_0 = r_uops_1_stq_idx; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rxq_idx_0 = r_uops_1_rxq_idx; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pdst_0 = r_uops_1_pdst; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_prs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_0 = r_uops_1_prs1; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_prs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_0 = r_uops_1_prs2; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_prs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_0 = r_uops_1_prs3; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ppred; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_0 = r_uops_1_ppred; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_busy_0 = r_uops_1_prs1_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_busy_0 = r_uops_1_prs2_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_busy_0 = r_uops_1_prs3_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_busy_0 = r_uops_1_ppred_busy; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stale_pdst_0 = r_uops_1_stale_pdst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_exception; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exception_0 = r_uops_1_exception; // @[functional-unit.scala:237:23, :591:7] reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exc_cause_0 = r_uops_1_exc_cause; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bypassable; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bypassable_0 = r_uops_1_bypassable; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_cmd_0 = r_uops_1_mem_cmd; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_size_0 = r_uops_1_mem_size; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_signed_0 = r_uops_1_mem_signed; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fence; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fence_0 = r_uops_1_is_fence; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fencei_0 = r_uops_1_is_fencei; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_amo; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_amo_0 = r_uops_1_is_amo; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_ldq_0 = r_uops_1_uses_ldq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_stq_0 = r_uops_1_uses_stq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_unique; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_unique_0 = r_uops_1_is_unique; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_flush_on_commit_0 = r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_0 = r_uops_1_ldst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_0 = r_uops_1_lrs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_0 = r_uops_1_lrs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs3_0 = r_uops_1_lrs3; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_val_0 = r_uops_1_ldst_val; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_dst_rtype_0 = r_uops_1_dst_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_frs3_en_0 = r_uops_1_frs3_en; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_val_0 = r_uops_1_fp_val; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_single; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_single_0 = r_uops_1_fp_single; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_debug_if_0 = r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_fsrc_0 = r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_tsrc_0 = r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23, :591:7] wire [15:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _r_valids_0_T_1 = \|_r_valids_0_T; // @[util.scala:118:{51,59}] wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59] wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :591:7] wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :591:7] wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}] wire [15:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51] wire _r_valids_1_T_1 = \|_r_valids_1_T; // @[util.scala:118:{51,59}] wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59] wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :591:7] wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51] wire _io_resp_valid_T_1 = \|_io_resp_valid_T; // @[util.scala:118:{51,59}] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59] assign _io_resp_valid_T_3 = r_valids_1 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :591:7] wire [15:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _io_resp_bits_uop_br_mask_T_1 = r_uops_1_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}] assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [2:0] _fp_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire [2:0] _fp_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire _fp_rm_T_1 = &_fp_rm_T; // @[util.scala:289:58] wire [2:0] fp_rm = _fp_rm_T_1 ? io_fcsr_rm_0 : _fp_rm_T_2; // @[util.scala:289:58] wire [2:0] req_rm = fp_rm; // @[functional-unit.scala:604:18, :605:17] wire [1:0] _req_typ_T; // @[util.scala:295:59] wire [64:0] _req_in1_T_4; // @[FPU.scala:369:10] wire [64:0] _req_in2_T_4; // @[FPU.scala:369:10] wire req_ldst; // @[functional-unit.scala:605:17] wire req_wen; // @[functional-unit.scala:605:17] wire req_ren1; // @[functional-unit.scala:605:17] wire req_ren2; // @[functional-unit.scala:605:17] wire req_ren3; // @[functional-unit.scala:605:17] wire req_swap12; // @[functional-unit.scala:605:17] wire req_swap23; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagIn; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagOut; // @[functional-unit.scala:605:17] wire req_fromint; // @[functional-unit.scala:605:17] wire req_toint; // @[functional-unit.scala:605:17] wire req_fastpipe; // @[functional-unit.scala:605:17] wire req_fma; // @[functional-unit.scala:605:17] wire req_div; // @[functional-unit.scala:605:17] wire req_sqrt; // @[functional-unit.scala:605:17] wire req_wflags; // @[functional-unit.scala:605:17] wire [1:0] req_typ; // @[functional-unit.scala:605:17] wire [64:0] req_in1; // @[functional-unit.scala:605:17] wire [64:0] req_in2; // @[functional-unit.scala:605:17] wire _req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in1_prev_unswizzled_hi = {_req_in1_prev_unswizzled_T, _req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in1_prev_unswizzled = {req_in1_prev_unswizzled_hi, _req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in1_prev_prev_sign = req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in1_prev_prev_fractIn = req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in1_prev_prev_expIn = req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in1_prev_prev_fractOut_T = {req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in1_prev_prev_fractOut = _req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in1_prev_prev_expOut_expCode = req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T = {4'h0, req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in1_prev_prev_expOut_commonCase_T_1 = _req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in1_prev_prev_expOut_commonCase = _req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in1_prev_prev_expOut_T_5 = req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in1_prev_prev_expOut_T = req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in1_prev_prev_expOut_T_1 = req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in1_prev_prev_expOut_T_2 = _req_in1_prev_prev_expOut_T \| _req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in1_prev_prev_expOut_T_3 = req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in1_prev_prev_expOut_T_4 = {req_in1_prev_prev_expOut_expCode, _req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in1_prev_prev_expOut = _req_in1_prev_prev_expOut_T_2 ? _req_in1_prev_prev_expOut_T_4 : _req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in1_prev_prev_hi = {req_in1_prev_prev_sign, req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in1_floats_0 = {req_in1_prev_prev_hi, req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire req_in1_prev_isbox = &_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in1_oks_0 = req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in1_truncIdx_T; // @[package.scala:38:21] wire req_in1_truncIdx = _req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in1_T = req_in1_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in1_T_1 = _req_in1_T \| req_in1_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in1_truncIdx_T_1; // @[package.scala:38:21] wire req_in1_truncIdx_1 = _req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in1_T_2 = req_in1_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in1_T_3 = _req_in1_T_2 ? io_req_bits_rs1_data_0 : req_in1_floats_0; // @[package.scala:39:{76,86}] assign _req_in1_T_4 = _req_in1_T_1 ? _req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in1 = _req_in1_T_4; // @[FPU.scala:369:10] wire _req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in2_prev_unswizzled_hi = {_req_in2_prev_unswizzled_T, _req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in2_prev_unswizzled = {req_in2_prev_unswizzled_hi, _req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in2_prev_prev_sign = req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in2_prev_prev_fractIn = req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in2_prev_prev_expIn = req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in2_prev_prev_fractOut_T = {req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in2_prev_prev_fractOut = _req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in2_prev_prev_expOut_expCode = req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T = {4'h0, req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in2_prev_prev_expOut_commonCase_T_1 = _req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in2_prev_prev_expOut_commonCase = _req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in2_prev_prev_expOut_T_5 = req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in2_prev_prev_expOut_T = req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in2_prev_prev_expOut_T_1 = req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in2_prev_prev_expOut_T_2 = _req_in2_prev_prev_expOut_T \| _req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in2_prev_prev_expOut_T_3 = req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in2_prev_prev_expOut_T_4 = {req_in2_prev_prev_expOut_expCode, _req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in2_prev_prev_expOut = _req_in2_prev_prev_expOut_T_2 ? _req_in2_prev_prev_expOut_T_4 : _req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in2_prev_prev_hi = {req_in2_prev_prev_sign, req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in2_floats_0 = {req_in2_prev_prev_hi, req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire req_in2_prev_isbox = &_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in2_oks_0 = req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in2_truncIdx_T; // @[package.scala:38:21] wire req_in2_truncIdx = _req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in2_T = req_in2_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in2_T_1 = _req_in2_T \| req_in2_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in2_truncIdx_T_1; // @[package.scala:38:21] wire req_in2_truncIdx_1 = _req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in2_T_2 = req_in2_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in2_T_3 = _req_in2_T_2 ? io_req_bits_rs2_data_0 : req_in2_floats_0; // @[package.scala:39:{76,86}] assign _req_in2_T_4 = _req_in2_T_1 ? _req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in2 = _req_in2_T_4; // @[FPU.scala:369:10] assign _req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] assign req_typ = _req_typ_T; // @[util.scala:295:59]

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_95 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_95( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OutputUnit_121 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[10], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[10], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[10], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[10], out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} reg states : { `9` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `8` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `7` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `6` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `5` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `4` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `3` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `2` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `1` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}, `0` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, clock connect io.channel_status[0].occupied, states.`0`.occupied connect io.channel_status[0].flow, states.`0`.flow connect io.channel_status[1].occupied, states.`1`.occupied connect io.channel_status[1].flow, states.`1`.flow connect io.channel_status[2].occupied, states.`2`.occupied connect io.channel_status[2].flow, states.`2`.flow connect io.channel_status[3].occupied, states.`3`.occupied connect io.channel_status[3].flow, states.`3`.flow connect io.channel_status[4].occupied, states.`4`.occupied connect io.channel_status[4].flow, states.`4`.flow connect io.channel_status[5].occupied, states.`5`.occupied connect io.channel_status[5].flow, states.`5`.flow connect io.channel_status[6].occupied, states.`6`.occupied connect io.channel_status[6].flow, states.`6`.flow connect io.channel_status[7].occupied, states.`7`.occupied connect io.channel_status[7].flow, states.`7`.flow connect io.channel_status[8].occupied, states.`8`.occupied connect io.channel_status[8].flow, states.`8`.flow connect io.channel_status[9].occupied, states.`9`.occupied connect io.channel_status[9].flow, states.`9`.flow connect io.out.flit, io.in node _T = bits(io.out.vc_free, 9, 9) when _T : node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(states.`9`.occupied, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf assert(clock, states.`9`.occupied, UInt<1>(0h1), "") : assert connect states.`9`.occupied, UInt<1>(0h0) when io.allocs[9].alloc : connect states.`9`.occupied, UInt<1>(0h1) connect states.`9`.flow, io.allocs[9].flow node _io_credit_available_0_T = neq(states.`0`.c, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_credit_available_1_T = neq(states.`1`.c, UInt<1>(0h0)) connect io.credit_available[1], _io_credit_available_1_T node _io_credit_available_2_T = neq(states.`2`.c, UInt<1>(0h0)) connect io.credit_available[2], _io_credit_available_2_T node _io_credit_available_3_T = neq(states.`3`.c, UInt<1>(0h0)) connect io.credit_available[3], _io_credit_available_3_T node _io_credit_available_4_T = neq(states.`4`.c, UInt<1>(0h0)) connect io.credit_available[4], _io_credit_available_4_T node _io_credit_available_5_T = neq(states.`5`.c, UInt<1>(0h0)) connect io.credit_available[5], _io_credit_available_5_T node _io_credit_available_6_T = neq(states.`6`.c, UInt<1>(0h0)) connect io.credit_available[6], _io_credit_available_6_T node _io_credit_available_7_T = neq(states.`7`.c, UInt<1>(0h0)) connect io.credit_available[7], _io_credit_available_7_T node _io_credit_available_8_T = neq(states.`8`.c, UInt<1>(0h0)) connect io.credit_available[8], _io_credit_available_8_T node _io_credit_available_9_T = neq(states.`9`.c, UInt<1>(0h0)) connect io.credit_available[9], _io_credit_available_9_T node free = bits(io.out.credit_return, 0, 0) node free_1 = bits(io.out.credit_return, 1, 1) node free_2 = bits(io.out.credit_return, 2, 2) node free_3 = bits(io.out.credit_return, 3, 3) node free_4 = bits(io.out.credit_return, 4, 4) node free_5 = bits(io.out.credit_return, 5, 5) node free_6 = bits(io.out.credit_return, 6, 6) node free_7 = bits(io.out.credit_return, 7, 7) node free_8 = bits(io.out.credit_return, 8, 8) node free_9 = bits(io.out.credit_return, 9, 9) node _states_9_c_T = add(states.`9`.c, free_9) node _states_9_c_T_1 = sub(_states_9_c_T, io.credit_alloc[9].alloc) node _states_9_c_T_2 = tail(_states_9_c_T_1, 1) connect states.`9`.c, _states_9_c_T_2 node _T_4 = asUInt(reset) when _T_4 : connect states.`0`.occupied, UInt<1>(0h0) connect states.`1`.occupied, UInt<1>(0h0) connect states.`2`.occupied, UInt<1>(0h0) connect states.`3`.occupied, UInt<1>(0h0) connect states.`4`.occupied, UInt<1>(0h0) connect states.`5`.occupied, UInt<1>(0h0) connect states.`6`.occupied, UInt<1>(0h0) connect states.`7`.occupied, UInt<1>(0h0) connect states.`8`.occupied, UInt<1>(0h0) connect states.`9`.occupied, UInt<1>(0h0) connect states.`0`.c, UInt<3>(0h4) connect states.`1`.c, UInt<3>(0h4) connect states.`2`.c, UInt<3>(0h4) connect states.`3`.c, UInt<3>(0h4) connect states.`4`.c, UInt<3>(0h4) connect states.`5`.c, UInt<3>(0h4) connect states.`6`.c, UInt<3>(0h4) connect states.`7`.c, UInt<3>(0h4) connect states.`8`.c, UInt<3>(0h4) connect states.`9`.c, UInt<3>(0h4)

module OutputUnit_121( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_9, // @[OutputUnit.scala:58:14] output io_channel_status_9_occupied, // @[OutputUnit.scala:58:14] input io_allocs_9_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_9_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [9:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [9:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_9_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_9_c; // @[OutputUnit.scala:66:19]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_24 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<27>(0h4000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<27>(0h4000000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<27>(0h4000000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<27>(0h4000000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<27>(0h4000000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<27>(0h4000000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<27>(0h4000000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<27>(0h4000000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<27>(0h4000000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<28>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _T_1085 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1086 = orr(a_set_wo_ready) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) node _T_1088 = or(_T_1085, _T_1087) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_48 node _T_1092 = orr(inflight) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) node _T_1094 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1095 = or(_T_1093, _T_1094) node _T_1096 = lt(watchdog, plusarg_reader.out) node _T_1097 = or(_T_1095, _T_1096) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1101 = and(io.in.a.ready, io.in.a.valid) node _T_1102 = and(io.in.d.ready, io.in.d.valid) node _T_1103 = or(_T_1101, _T_1102) when _T_1103 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1104 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1105 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1106 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = and(_T_1104, _T_1107) when _T_1108 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1109 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1110 = and(_T_1109, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1111 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1112 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1113 = and(_T_1111, _T_1112) node _T_1114 = and(_T_1110, _T_1113) when _T_1114 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1115 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1116 = bits(_T_1115, 0, 0) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1124 = and(io.in.d.ready, io.in.d.valid) node _T_1125 = and(_T_1124, d_first_2) node _T_1126 = and(_T_1125, UInt<1>(0h1)) node _T_1127 = and(_T_1126, d_release_ack_1) when _T_1127 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1128 = and(io.in.d.valid, d_first_2) node _T_1129 = and(_T_1128, UInt<1>(0h1)) node _T_1130 = and(_T_1129, d_release_ack_1) when _T_1130 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1131 = dshr(inflight_1, io.in.d.bits.source) node _T_1132 = bits(_T_1131, 0, 0) node _T_1133 = or(_T_1132, same_cycle_resp_1) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1137 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_109 else : node _T_1141 = eq(io.in.d.bits.size, c_size_lookup) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_110 node _T_1145 = and(io.in.d.valid, d_first_2) node _T_1146 = and(_T_1145, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1147 = and(_T_1146, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1148 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1149 = and(_T_1147, _T_1148) node _T_1150 = and(_T_1149, d_release_ack_1) node _T_1151 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1152 = and(_T_1150, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<28>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1154 = or(_T_1153, _WIRE_27.ready) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_111 node _T_1158 = orr(c_set_wo_ready) when _T_1158 : node _T_1159 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_49 node _T_1163 = orr(inflight_1) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) node _T_1165 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = lt(watchdog_1, plusarg_reader_1.out) node _T_1168 = or(_T_1166, _T_1167) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<28>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1172 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1173 = and(io.in.d.ready, io.in.d.valid) node _T_1174 = or(_T_1172, _T_1173) when _T_1174 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_24( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1101 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1101; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1101; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1174 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1174; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1174; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1174; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1027 = _T_1101 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1042 = _T_1174 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1145 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1145 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1127 = _T_1174 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1127 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1127 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1127 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module MSHR_7 : input clock : Clock input reset : Reset output io : { flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>}, idx_match : UInt<1>, tag : UInt<20>, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, refill : { way_en : UInt<8>, addr : UInt<12>}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, sdq_id : UInt<5>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<2>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, probe_rdy : UInt<1>} regreset state : UInt<4>, clock, reset, UInt<4>(0h0) reg req : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>}, clock node req_idx = bits(req.addr, 11, 6) node req_tag = shr(req.addr, 12) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) node _idx_match_T = bits(io.req_bits.addr, 11, 6) node idx_match = eq(req_idx, _idx_match_T) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req_bits.cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req_bits.cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req_bits.cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req_bits.cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req_bits.cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req_bits.cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req_bits.cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req_bits.cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req_bits.cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req_bits.cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req_bits.cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req_bits.cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req_bits.cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req_bits.cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req_bits.cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req_bits.cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req_bits.cmd, req.cmd) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, io.mem_grant.valid) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when io.mem_grant.valid : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 3) node _sec_rdy_T = eq(state, UInt<4>(0h1)) node _sec_rdy_T_1 = eq(state, UInt<4>(0h2)) node _sec_rdy_T_2 = eq(state, UInt<4>(0h3)) node _sec_rdy_T_3 = or(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_4 = or(_sec_rdy_T_3, _sec_rdy_T_2) node _sec_rdy_T_5 = eq(state, UInt<4>(0h4)) node _sec_rdy_T_6 = eq(state, UInt<4>(0h5)) node _sec_rdy_T_7 = or(_sec_rdy_T_5, _sec_rdy_T_6) node _sec_rdy_T_8 = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_9 = and(_sec_rdy_T_7, _sec_rdy_T_8) node _sec_rdy_T_10 = eq(refill_done, UInt<1>(0h0)) node _sec_rdy_T_11 = and(_sec_rdy_T_9, _sec_rdy_T_10) node _sec_rdy_T_12 = or(_sec_rdy_T_4, _sec_rdy_T_11) node sec_rdy = and(idx_match, _sec_rdy_T_12) inst rpq of Queue16_ReplayInternal connect rpq.clock, clock connect rpq.reset, reset node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req_bits.cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req_bits.cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req_bits.sdq_id connect rpq.io.enq.bits.no_xcpt, io.req_bits.no_xcpt connect rpq.io.enq.bits.no_alloc, io.req_bits.no_alloc connect rpq.io.enq.bits.no_resp, io.req_bits.no_resp connect rpq.io.enq.bits.phys, io.req_bits.phys connect rpq.io.enq.bits.dv, io.req_bits.dv connect rpq.io.enq.bits.dprv, io.req_bits.dprv connect rpq.io.enq.bits.signed, io.req_bits.signed connect rpq.io.enq.bits.size, io.req_bits.size connect rpq.io.enq.bits.cmd, io.req_bits.cmd connect rpq.io.enq.bits.tag, io.req_bits.tag connect rpq.io.enq.bits.addr, io.req_bits.addr node _rpq_io_deq_ready_T = eq(state, UInt<4>(0h8)) node _rpq_io_deq_ready_T_1 = and(io.replay.ready, _rpq_io_deq_ready_T) node _rpq_io_deq_ready_T_2 = eq(state, UInt<4>(0h0)) node _rpq_io_deq_ready_T_3 = or(_rpq_io_deq_ready_T_1, _rpq_io_deq_ready_T_2) connect rpq.io.deq.ready, _rpq_io_deq_ready_T_3 reg acked : UInt<1>, clock when io.mem_grant.valid : connect acked, UInt<1>(0h1) node _T = eq(state, UInt<4>(0h8)) node _T_1 = eq(rpq.io.deq.valid, UInt<1>(0h0)) node _T_2 = and(_T, _T_1) when _T_2 : connect state, UInt<4>(0h0) node _T_3 = eq(state, UInt<4>(0h7)) when _T_3 : connect state, UInt<4>(0h8) node _T_4 = eq(state, UInt<4>(0h6)) node _T_5 = and(_T_4, io.meta_write.ready) when _T_5 : connect state, UInt<4>(0h7) node _T_6 = eq(state, UInt<4>(0h5)) node _T_7 = and(_T_6, refill_done) when _T_7 : connect new_coh, coh_on_grant connect state, UInt<4>(0h6) node _T_8 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_8 : connect state, UInt<4>(0h5) node _T_9 = eq(state, UInt<4>(0h3)) node _T_10 = and(_T_9, io.meta_write.ready) when _T_10 : connect state, UInt<4>(0h4) node _T_11 = eq(state, UInt<4>(0h2)) node _T_12 = and(_T_11, io.wb_req.ready) node _T_13 = and(_T_12, acked) when _T_13 : connect state, UInt<4>(0h3) node _T_14 = and(io.wb_req.ready, io.wb_req.valid) when _T_14 : connect state, UInt<4>(0h2) node _T_15 = and(io.req_sec_val, io.req_sec_rdy) when _T_15 : connect req.cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_16 = and(io.req_pri_val, io.req_pri_rdy) when _T_16 : connect req, io.req_bits connect acked, UInt<1>(0h0) node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.req_bits.old_meta.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _r_c_cat_T = eq(io.req_bits.cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(io.req_bits.cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(io.req_bits.cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(io.req_bits.cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(io.req_bits.cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(io.req_bits.cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(io.req_bits.cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(io.req_bits.cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(io.req_bits.cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(io.req_bits.cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(io.req_bits.cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(io.req_bits.cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(io.req_bits.cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(io.req_bits.cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(io.req_bits.cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(io.req_bits.cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, io.req_bits.old_meta.coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 when io.req_bits.tag_match : when is_hit : connect new_coh, coh_on_hit connect state, UInt<4>(0h6) else : connect new_coh, io.req_bits.old_meta.coh connect state, UInt<4>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 node _state_T = mux(needs_wb, UInt<4>(0h1), UInt<4>(0h3)) connect state, _state_T inst grantackq of Queue1_TLBundleE_a32d64s2k3z4c connect grantackq.clock, clock connect grantackq.reset, reset node _can_finish_T = eq(state, UInt<4>(0h0)) node _can_finish_T_1 = eq(state, UInt<4>(0h4)) node can_finish = or(_can_finish_T, _can_finish_T_1) node _grantackq_io_enq_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantackq_io_enq_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantackq_io_enq_valid_T_2 = eq(_grantackq_io_enq_valid_T_1, UInt<1>(0h0)) node _grantackq_io_enq_valid_T_3 = and(_grantackq_io_enq_valid_T, _grantackq_io_enq_valid_T_2) node _grantackq_io_enq_valid_T_4 = and(refill_done, _grantackq_io_enq_valid_T_3) connect grantackq.io.enq.valid, _grantackq_io_enq_valid_T_4 wire grantackq_io_enq_bits_e : { sink : UInt<3>} connect grantackq_io_enq_bits_e.sink, io.mem_grant.bits.sink connect grantackq.io.enq.bits.sink, grantackq_io_enq_bits_e.sink node _io_mem_finish_valid_T = and(grantackq.io.deq.valid, can_finish) connect io.mem_finish.valid, _io_mem_finish_valid_T connect io.mem_finish.bits, grantackq.io.deq.bits node _grantackq_io_deq_ready_T = and(io.mem_finish.ready, can_finish) connect grantackq.io.deq.ready, _grantackq_io_deq_ready_T node _io_idx_match_T = neq(state, UInt<4>(0h0)) node _io_idx_match_T_1 = and(_io_idx_match_T, idx_match) connect io.idx_match, _io_idx_match_T_1 connect io.refill.way_en, req.way_en node _io_refill_addr_T = or(req_block_addr, refill_address_inc) connect io.refill.addr, _io_refill_addr_T connect io.tag, req_tag node _io_req_pri_rdy_T = eq(state, UInt<4>(0h0)) connect io.req_pri_rdy, _io_req_pri_rdy_T node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_17 = neq(meta_hazard, UInt<1>(0h0)) when _T_17 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_18 = and(io.meta_write.ready, io.meta_write.valid) when _T_18 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(idx_match, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<4>(0h1)) node _io_probe_rdy_T_2 = eq(state, UInt<4>(0h2)) node _io_probe_rdy_T_3 = eq(state, UInt<4>(0h3)) node _io_probe_rdy_T_4 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_4, _io_probe_rdy_T_3) node _io_probe_rdy_T_6 = eq(_io_probe_rdy_T_5, UInt<1>(0h0)) node _io_probe_rdy_T_7 = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_8 = and(_io_probe_rdy_T_6, _io_probe_rdy_T_7) node _io_probe_rdy_T_9 = or(_io_probe_rdy_T, _io_probe_rdy_T_8) connect io.probe_rdy, _io_probe_rdy_T_9 node _io_meta_write_valid_T = eq(state, UInt<4>(0h6)) node _io_meta_write_valid_T_1 = eq(state, UInt<4>(0h3)) node _io_meta_write_valid_T_2 = or(_io_meta_write_valid_T, _io_meta_write_valid_T_1) connect io.meta_write.valid, _io_meta_write_valid_T_2 connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.tag, io.tag node _io_meta_write_bits_data_coh_T = eq(state, UInt<4>(0h3)) node _io_meta_write_bits_data_coh_T_1 = mux(_io_meta_write_bits_data_coh_T, coh_on_clear, new_coh) connect io.meta_write.bits.data.coh, _io_meta_write_bits_data_coh_T_1 connect io.meta_write.bits.data.tag, io.tag connect io.meta_write.bits.way_en, req.way_en node _io_wb_req_valid_T = eq(state, UInt<4>(0h1)) connect io.wb_req.valid, _io_wb_req_valid_T connect io.wb_req.bits.source, UInt<1>(0h0) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.voluntary, UInt<1>(0h1) node _io_mem_acquire_valid_T = eq(state, UInt<4>(0h4)) node _io_mem_acquire_valid_T_1 = and(_io_mem_acquire_valid_T, grantackq.io.enq.ready) connect io.mem_acquire.valid, _io_mem_acquire_valid_T_1 node _io_mem_acquire_bits_T = cat(io.tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = xor(_io_mem_acquire_bits_T_1, UInt<17>(0h10000)) node _io_mem_acquire_bits_legal_T_7 = cvt(_io_mem_acquire_bits_legal_T_6) node _io_mem_acquire_bits_legal_T_8 = and(_io_mem_acquire_bits_legal_T_7, asSInt(UInt<33>(0h8c011000))) node _io_mem_acquire_bits_legal_T_9 = asSInt(_io_mem_acquire_bits_legal_T_8) node _io_mem_acquire_bits_legal_T_10 = eq(_io_mem_acquire_bits_legal_T_9, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_11 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0hc000000)) node _io_mem_acquire_bits_legal_T_12 = cvt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = and(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_14 = asSInt(_io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = eq(_io_mem_acquire_bits_legal_T_14, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_16 = or(_io_mem_acquire_bits_legal_T_5, _io_mem_acquire_bits_legal_T_10) node _io_mem_acquire_bits_legal_T_17 = or(_io_mem_acquire_bits_legal_T_16, _io_mem_acquire_bits_legal_T_15) node _io_mem_acquire_bits_legal_T_18 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_17) node _io_mem_acquire_bits_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_20 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_19) node _io_mem_acquire_bits_legal_T_21 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0h8000000)) node _io_mem_acquire_bits_legal_T_22 = cvt(_io_mem_acquire_bits_legal_T_21) node _io_mem_acquire_bits_legal_T_23 = and(_io_mem_acquire_bits_legal_T_22, asSInt(UInt<33>(0h8c010000))) node _io_mem_acquire_bits_legal_T_24 = asSInt(_io_mem_acquire_bits_legal_T_23) node _io_mem_acquire_bits_legal_T_25 = eq(_io_mem_acquire_bits_legal_T_24, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_26 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_27 = cvt(_io_mem_acquire_bits_legal_T_26) node _io_mem_acquire_bits_legal_T_28 = and(_io_mem_acquire_bits_legal_T_27, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_29 = asSInt(_io_mem_acquire_bits_legal_T_28) node _io_mem_acquire_bits_legal_T_30 = eq(_io_mem_acquire_bits_legal_T_29, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_31 = or(_io_mem_acquire_bits_legal_T_25, _io_mem_acquire_bits_legal_T_30) node _io_mem_acquire_bits_legal_T_32 = and(_io_mem_acquire_bits_legal_T_20, _io_mem_acquire_bits_legal_T_31) node _io_mem_acquire_bits_legal_T_33 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_18) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_33, _io_mem_acquire_bits_legal_T_32) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, UInt<1>(0h0) connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a node _io_meta_read_valid_T = eq(state, UInt<4>(0h8)) connect io.meta_read.valid, _io_meta_read_valid_T connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, io.tag node _io_meta_read_bits_way_en_T = not(UInt<8>(0h0)) connect io.meta_read.bits.way_en, _io_meta_read_bits_way_en_T node _io_replay_valid_T = eq(state, UInt<4>(0h8)) node _io_replay_valid_T_1 = and(_io_replay_valid_T, rpq.io.deq.valid) connect io.replay.valid, _io_replay_valid_T_1 connect io.replay.bits, rpq.io.deq.bits connect io.replay.bits.phys, UInt<1>(0h1) node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(io.tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_19 = eq(io.meta_read.ready, UInt<1>(0h0)) when _T_19 : connect rpq.io.deq.ready, UInt<1>(0h0) connect io.replay.bits.cmd, UInt<3>(0h5)

module MSHR_7( // @[NBDcache.scala:150:7] input clock, // @[NBDcache.scala:150:7] input reset, // @[NBDcache.scala:150:7] input io_req_pri_val, // @[NBDcache.scala:151:14] output io_req_pri_rdy, // @[NBDcache.scala:151:14] input io_req_sec_val, // @[NBDcache.scala:151:14] output io_req_sec_rdy, // @[NBDcache.scala:151:14] input [39:0] io_req_bits_addr, // @[NBDcache.scala:151:14] input [6:0] io_req_bits_tag, // @[NBDcache.scala:151:14] input [4:0] io_req_bits_cmd, // @[NBDcache.scala:151:14] input [1:0] io_req_bits_size, // @[NBDcache.scala:151:14] input io_req_bits_signed, // @[NBDcache.scala:151:14] input [1:0] io_req_bits_dprv, // @[NBDcache.scala:151:14] input io_req_bits_dv, // @[NBDcache.scala:151:14] input io_req_bits_phys, // @[NBDcache.scala:151:14] input io_req_bits_no_resp, // @[NBDcache.scala:151:14] input io_req_bits_no_alloc, // @[NBDcache.scala:151:14] input io_req_bits_no_xcpt, // @[NBDcache.scala:151:14] input [4:0] io_req_bits_sdq_id, // @[NBDcache.scala:151:14] input io_req_bits_tag_match, // @[NBDcache.scala:151:14] input [1:0] io_req_bits_old_meta_coh_state, // @[NBDcache.scala:151:14] input [19:0] io_req_bits_old_meta_tag, // @[NBDcache.scala:151:14] input [7:0] io_req_bits_way_en, // @[NBDcache.scala:151:14] output io_idx_match, // @[NBDcache.scala:151:14] output [19:0] io_tag, // @[NBDcache.scala:151:14] input io_mem_acquire_ready, // @[NBDcache.scala:151:14] output io_mem_acquire_valid, // @[NBDcache.scala:151:14] output [2:0] io_mem_acquire_bits_param, // @[NBDcache.scala:151:14] output [31:0] io_mem_acquire_bits_address, // @[NBDcache.scala:151:14] input io_mem_grant_valid, // @[NBDcache.scala:151:14] input [2:0] io_mem_grant_bits_opcode, // @[NBDcache.scala:151:14] input [1:0] io_mem_grant_bits_param, // @[NBDcache.scala:151:14] input [3:0] io_mem_grant_bits_size, // @[NBDcache.scala:151:14] input [1:0] io_mem_grant_bits_source, // @[NBDcache.scala:151:14] input [2:0] io_mem_grant_bits_sink, // @[NBDcache.scala:151:14] input io_mem_grant_bits_denied, // @[NBDcache.scala:151:14] input [63:0] io_mem_grant_bits_data, // @[NBDcache.scala:151:14] input io_mem_grant_bits_corrupt, // @[NBDcache.scala:151:14] input io_mem_finish_ready, // @[NBDcache.scala:151:14] output io_mem_finish_valid, // @[NBDcache.scala:151:14] output [2:0] io_mem_finish_bits_sink, // @[NBDcache.scala:151:14] output [7:0] io_refill_way_en, // @[NBDcache.scala:151:14] output [11:0] io_refill_addr, // @[NBDcache.scala:151:14] input io_meta_read_ready, // @[NBDcache.scala:151:14] output io_meta_read_valid, // @[NBDcache.scala:151:14] output [5:0] io_meta_read_bits_idx, // @[NBDcache.scala:151:14] output [19:0] io_meta_read_bits_tag, // @[NBDcache.scala:151:14] input io_meta_write_ready, // @[NBDcache.scala:151:14] output io_meta_write_valid, // @[NBDcache.scala:151:14] output [5:0] io_meta_write_bits_idx, // @[NBDcache.scala:151:14] output [7:0] io_meta_write_bits_way_en, // @[NBDcache.scala:151:14] output [19:0] io_meta_write_bits_tag, // @[NBDcache.scala:151:14] output [1:0] io_meta_write_bits_data_coh_state, // @[NBDcache.scala:151:14] output [19:0] io_meta_write_bits_data_tag, // @[NBDcache.scala:151:14] input io_replay_ready, // @[NBDcache.scala:151:14] output io_replay_valid, // @[NBDcache.scala:151:14] output [39:0] io_replay_bits_addr, // @[NBDcache.scala:151:14] output [6:0] io_replay_bits_tag, // @[NBDcache.scala:151:14] output [4:0] io_replay_bits_cmd, // @[NBDcache.scala:151:14] output [1:0] io_replay_bits_size, // @[NBDcache.scala:151:14] output io_replay_bits_signed, // @[NBDcache.scala:151:14] output [1:0] io_replay_bits_dprv, // @[NBDcache.scala:151:14] output io_replay_bits_dv, // @[NBDcache.scala:151:14] output io_replay_bits_no_resp, // @[NBDcache.scala:151:14] output io_replay_bits_no_alloc, // @[NBDcache.scala:151:14] output io_replay_bits_no_xcpt, // @[NBDcache.scala:151:14] output [4:0] io_replay_bits_sdq_id, // @[NBDcache.scala:151:14] input io_wb_req_ready, // @[NBDcache.scala:151:14] output io_wb_req_valid, // @[NBDcache.scala:151:14] output [19:0] io_wb_req_bits_tag, // @[NBDcache.scala:151:14] output [5:0] io_wb_req_bits_idx, // @[NBDcache.scala:151:14] output [2:0] io_wb_req_bits_param, // @[NBDcache.scala:151:14] output [7:0] io_wb_req_bits_way_en, // @[NBDcache.scala:151:14] output io_probe_rdy // @[NBDcache.scala:151:14] ); wire [19:0] io_tag_0; // @[NBDcache.scala:150:7] wire _grantackq_io_enq_ready; // @[NBDcache.scala:263:25] wire _grantackq_io_deq_valid; // @[NBDcache.scala:263:25] wire _rpq_io_enq_ready; // @[NBDcache.scala:200:19] wire _rpq_io_deq_valid; // @[NBDcache.scala:200:19] wire [39:0] _rpq_io_deq_bits_addr; // @[NBDcache.scala:200:19] wire [4:0] _rpq_io_deq_bits_cmd; // @[NBDcache.scala:200:19] wire io_req_pri_val_0 = io_req_pri_val; // @[NBDcache.scala:150:7] wire io_req_sec_val_0 = io_req_sec_val; // @[NBDcache.scala:150:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[NBDcache.scala:150:7] wire [6:0] io_req_bits_tag_0 = io_req_bits_tag; // @[NBDcache.scala:150:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[NBDcache.scala:150:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[NBDcache.scala:150:7] wire io_req_bits_signed_0 = io_req_bits_signed; // @[NBDcache.scala:150:7] wire [1:0] io_req_bits_dprv_0 = io_req_bits_dprv; // @[NBDcache.scala:150:7] wire io_req_bits_dv_0 = io_req_bits_dv; // @[NBDcache.scala:150:7] wire io_req_bits_phys_0 = io_req_bits_phys; // @[NBDcache.scala:150:7] wire io_req_bits_no_resp_0 = io_req_bits_no_resp; // @[NBDcache.scala:150:7] wire io_req_bits_no_alloc_0 = io_req_bits_no_alloc; // @[NBDcache.scala:150:7] wire io_req_bits_no_xcpt_0 = io_req_bits_no_xcpt; // @[NBDcache.scala:150:7] wire [4:0] io_req_bits_sdq_id_0 = io_req_bits_sdq_id; // @[NBDcache.scala:150:7] wire io_req_bits_tag_match_0 = io_req_bits_tag_match; // @[NBDcache.scala:150:7] wire [1:0] io_req_bits_old_meta_coh_state_0 = io_req_bits_old_meta_coh_state; // @[NBDcache.scala:150:7] wire [19:0] io_req_bits_old_meta_tag_0 = io_req_bits_old_meta_tag; // @[NBDcache.scala:150:7] wire [7:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[NBDcache.scala:150:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[NBDcache.scala:150:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[NBDcache.scala:150:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[NBDcache.scala:150:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[NBDcache.scala:150:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[NBDcache.scala:150:7] wire [1:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[NBDcache.scala:150:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[NBDcache.scala:150:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[NBDcache.scala:150:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[NBDcache.scala:150:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[NBDcache.scala:150:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[NBDcache.scala:150:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[NBDcache.scala:150:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[NBDcache.scala:150:7] wire io_replay_ready_0 = io_replay_ready; // @[NBDcache.scala:150:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[NBDcache.scala:150:7] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire io_replay_bits_phys = 1'h1; // @[NBDcache.scala:150:7] wire io_wb_req_bits_voluntary = 1'h1; // @[NBDcache.scala:150:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_corrupt = 1'h0; // @[NBDcache.scala:150:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[NBDcache.scala:150:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[NBDcache.scala:150:7] wire [7:0] io_meta_read_bits_way_en = 8'hFF; // @[NBDcache.scala:150:7] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire [7:0] _io_meta_read_bits_way_en_T = 8'hFF; // @[NBDcache.scala:308:31] wire [1:0] io_mem_acquire_bits_source = 2'h0; // @[NBDcache.scala:150:7] wire [1:0] io_wb_req_bits_source = 2'h0; // @[NBDcache.scala:150:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] io_mem_acquire_bits_a_source = 2'h0; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[NBDcache.scala:150:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[NBDcache.scala:150:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire _io_req_pri_rdy_T; // @[NBDcache.scala:275:27] wire _io_req_sec_rdy_T; // @[NBDcache.scala:276:29] wire _io_idx_match_T_1; // @[NBDcache.scala:271:41] wire [19:0] io_meta_read_bits_tag_0 = io_tag_0; // @[NBDcache.scala:150:7] wire [19:0] io_meta_write_bits_tag_0 = io_tag_0; // @[NBDcache.scala:150:7] wire [19:0] io_meta_write_bits_data_tag_0 = io_tag_0; // @[NBDcache.scala:150:7] wire _io_mem_acquire_valid_T_1; // @[NBDcache.scala:298:50] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantackq_io_enq_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire _io_mem_finish_valid_T; // @[NBDcache.scala:267:49] wire _io_meta_read_valid_T; // @[NBDcache.scala:305:31] wire [5:0] req_idx; // @[NBDcache.scala:177:25] wire _io_meta_write_valid_T_2; // @[package.scala:81:59] wire [1:0] _io_meta_write_bits_data_coh_T_1_state; // @[NBDcache.scala:286:37] wire _io_replay_valid_T_1; // @[NBDcache.scala:310:44] wire _io_wb_req_valid_T; // @[NBDcache.scala:290:28] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire _io_probe_rdy_T_9; // @[NBDcache.scala:281:30] wire [2:0] io_mem_acquire_bits_param_0; // @[NBDcache.scala:150:7] wire [31:0] io_mem_acquire_bits_address_0; // @[NBDcache.scala:150:7] wire io_mem_acquire_valid_0; // @[NBDcache.scala:150:7] wire [2:0] io_mem_finish_bits_sink_0; // @[NBDcache.scala:150:7] wire io_mem_finish_valid_0; // @[NBDcache.scala:150:7] wire [7:0] io_refill_way_en_0; // @[NBDcache.scala:150:7] wire [11:0] io_refill_addr_0; // @[NBDcache.scala:150:7] wire [5:0] io_meta_read_bits_idx_0; // @[NBDcache.scala:150:7] wire io_meta_read_valid_0; // @[NBDcache.scala:150:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[NBDcache.scala:150:7] wire [5:0] io_meta_write_bits_idx_0; // @[NBDcache.scala:150:7] wire [7:0] io_meta_write_bits_way_en_0; // @[NBDcache.scala:150:7] wire io_meta_write_valid_0; // @[NBDcache.scala:150:7] wire [39:0] io_replay_bits_addr_0; // @[NBDcache.scala:150:7] wire [6:0] io_replay_bits_tag_0; // @[NBDcache.scala:150:7] wire [4:0] io_replay_bits_cmd_0; // @[NBDcache.scala:150:7] wire [1:0] io_replay_bits_size_0; // @[NBDcache.scala:150:7] wire io_replay_bits_signed_0; // @[NBDcache.scala:150:7] wire [1:0] io_replay_bits_dprv_0; // @[NBDcache.scala:150:7] wire io_replay_bits_dv_0; // @[NBDcache.scala:150:7] wire io_replay_bits_no_resp_0; // @[NBDcache.scala:150:7] wire io_replay_bits_no_alloc_0; // @[NBDcache.scala:150:7] wire io_replay_bits_no_xcpt_0; // @[NBDcache.scala:150:7] wire [4:0] io_replay_bits_sdq_id_0; // @[NBDcache.scala:150:7] wire io_replay_valid_0; // @[NBDcache.scala:150:7] wire [19:0] io_wb_req_bits_tag_0; // @[NBDcache.scala:150:7] wire [5:0] io_wb_req_bits_idx_0; // @[NBDcache.scala:150:7] wire [2:0] io_wb_req_bits_param_0; // @[NBDcache.scala:150:7] wire [7:0] io_wb_req_bits_way_en_0; // @[NBDcache.scala:150:7] wire io_wb_req_valid_0; // @[NBDcache.scala:150:7] wire io_req_pri_rdy_0; // @[NBDcache.scala:150:7] wire io_req_sec_rdy_0; // @[NBDcache.scala:150:7] wire io_idx_match_0; // @[NBDcache.scala:150:7] wire io_probe_rdy_0; // @[NBDcache.scala:150:7] reg [3:0] state; // @[NBDcache.scala:174:22] reg [39:0] req_addr; // @[NBDcache.scala:176:16] reg [6:0] req_tag; // @[NBDcache.scala:176:16] reg [4:0] req_cmd; // @[NBDcache.scala:176:16] reg [1:0] req_size; // @[NBDcache.scala:176:16] reg req_signed; // @[NBDcache.scala:176:16] reg [1:0] req_dprv; // @[NBDcache.scala:176:16] reg req_dv; // @[NBDcache.scala:176:16] reg req_phys; // @[NBDcache.scala:176:16] reg req_no_resp; // @[NBDcache.scala:176:16] reg req_no_alloc; // @[NBDcache.scala:176:16] reg req_no_xcpt; // @[NBDcache.scala:176:16] reg [4:0] req_sdq_id; // @[NBDcache.scala:176:16] reg req_tag_match; // @[NBDcache.scala:176:16] reg [1:0] req_old_meta_coh_state; // @[NBDcache.scala:176:16] reg [19:0] req_old_meta_tag; // @[NBDcache.scala:176:16] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[NBDcache.scala:150:7, :176:16] reg [7:0] req_way_en; // @[NBDcache.scala:176:16] assign io_refill_way_en_0 = req_way_en; // @[NBDcache.scala:150:7, :176:16] assign io_meta_write_bits_way_en_0 = req_way_en; // @[NBDcache.scala:150:7, :176:16] assign io_wb_req_bits_way_en_0 = req_way_en; // @[NBDcache.scala:150:7, :176:16] assign req_idx = req_addr[11:6]; // @[NBDcache.scala:176:16, :177:25] assign io_meta_read_bits_idx_0 = req_idx; // @[NBDcache.scala:150:7, :177:25] assign io_meta_write_bits_idx_0 = req_idx; // @[NBDcache.scala:150:7, :177:25] assign io_wb_req_bits_idx_0 = req_idx; // @[NBDcache.scala:150:7, :177:25] wire [27:0] req_tag_0 = req_addr[39:12]; // @[NBDcache.scala:176:16, :178:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[NBDcache.scala:176:16, :179:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[NBDcache.scala:179:{34,51}] wire [5:0] _idx_match_T = io_req_bits_addr_0[11:6]; // @[NBDcache.scala:150:7, :180:47] wire idx_match = req_idx == _idx_match_T; // @[NBDcache.scala:177:25, :180:{27,47}] reg [1:0] new_coh_state; // @[NBDcache.scala:182:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_cmd == 5'h1; // @[NBDcache.scala:176:16] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_cmd == 5'h11; // @[NBDcache.scala:176:16] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_cmd == 5'h7; // @[NBDcache.scala:176:16] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_cmd == 5'h3; // @[NBDcache.scala:176:16] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_cmd == 5'h6; // @[NBDcache.scala:176:16] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] wire [1:0] coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_bits_cmd_0 == 5'h1; // @[NBDcache.scala:150:7] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_bits_cmd_0 == 5'h11; // @[NBDcache.scala:150:7] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_bits_cmd_0 == 5'h7; // @[NBDcache.scala:150:7] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_bits_cmd_0 == 5'h3; // @[NBDcache.scala:150:7] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_bits_cmd_0 == 5'h6; // @[NBDcache.scala:150:7] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_bits_cmd_0 : req_cmd; // @[Metadata.scala:106:42, :109:27] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & io_mem_grant_valid_0; // @[Edges.scala:232:33, :233:22] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _GEN_27 = state == 4'h1; // @[package.scala:16:47] wire _sec_rdy_T; // @[package.scala:16:47] assign _sec_rdy_T = _GEN_27; // @[package.scala:16:47] wire _io_probe_rdy_T_1; // @[package.scala:16:47] assign _io_probe_rdy_T_1 = _GEN_27; // @[package.scala:16:47] assign _io_wb_req_valid_T = _GEN_27; // @[package.scala:16:47] wire _T_11 = state == 4'h2; // @[package.scala:16:47] wire _sec_rdy_T_1; // @[package.scala:16:47] assign _sec_rdy_T_1 = _T_11; // @[package.scala:16:47] wire _io_probe_rdy_T_2; // @[package.scala:16:47] assign _io_probe_rdy_T_2 = _T_11; // @[package.scala:16:47] wire _T_9 = state == 4'h3; // @[package.scala:16:47] wire _sec_rdy_T_2; // @[package.scala:16:47] assign _sec_rdy_T_2 = _T_9; // @[package.scala:16:47] wire _io_probe_rdy_T_3; // @[package.scala:16:47] assign _io_probe_rdy_T_3 = _T_9; // @[package.scala:16:47] wire _io_meta_write_valid_T_1; // @[package.scala:16:47] assign _io_meta_write_valid_T_1 = _T_9; // @[package.scala:16:47] wire _io_meta_write_bits_data_coh_T; // @[NBDcache.scala:286:44] assign _io_meta_write_bits_data_coh_T = _T_9; // @[package.scala:16:47] wire _sec_rdy_T_3 = _sec_rdy_T | _sec_rdy_T_1; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_4 = _sec_rdy_T_3 | _sec_rdy_T_2; // @[package.scala:16:47, :81:59] wire _GEN_28 = state == 4'h4; // @[package.scala:16:47] wire _sec_rdy_T_5; // @[package.scala:16:47] assign _sec_rdy_T_5 = _GEN_28; // @[package.scala:16:47] wire _can_finish_T_1; // @[package.scala:16:47] assign _can_finish_T_1 = _GEN_28; // @[package.scala:16:47] wire _io_mem_acquire_valid_T; // @[NBDcache.scala:298:33] assign _io_mem_acquire_valid_T = _GEN_28; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 4'h5; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_9 = _sec_rdy_T_7 & _sec_rdy_T_8; // @[package.scala:81:59] wire _sec_rdy_T_10 = ~refill_done; // @[Edges.scala:233:22] wire _sec_rdy_T_11 = _sec_rdy_T_9 & _sec_rdy_T_10; // @[NBDcache.scala:197:65, :198:{52,55}] wire _sec_rdy_T_12 = _sec_rdy_T_4 | _sec_rdy_T_11; // @[package.scala:81:59] wire sec_rdy = idx_match & _sec_rdy_T_12; // @[NBDcache.scala:180:27, :195:27, :196:56] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[NBDcache.scala:150:7, :201:39] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & sec_rdy; // @[NBDcache.scala:150:7, :195:27, :201:75] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[NBDcache.scala:201:{39,57,75}] wire _rpq_io_enq_valid_T_3 = io_req_bits_cmd_0 == 5'h2; // @[NBDcache.scala:150:7] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[NBDcache.scala:201:90] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[NBDcache.scala:201:{57,87,90}] wire _T = state == 4'h8; // @[NBDcache.scala:174:22, :203:49] wire _rpq_io_deq_ready_T; // @[NBDcache.scala:203:49] assign _rpq_io_deq_ready_T = _T; // @[NBDcache.scala:203:49] assign _io_meta_read_valid_T = _T; // @[NBDcache.scala:203:49, :305:31] wire _io_replay_valid_T; // @[NBDcache.scala:310:28] assign _io_replay_valid_T = _T; // @[NBDcache.scala:203:49, :310:28] wire _rpq_io_deq_ready_T_1 = io_replay_ready_0 & _rpq_io_deq_ready_T; // @[NBDcache.scala:150:7, :203:{40,49}] wire _rpq_io_deq_ready_T_2 = ~(|state); // @[NBDcache.scala:174:22, :203:75] wire _rpq_io_deq_ready_T_3 = _rpq_io_deq_ready_T_1 | _rpq_io_deq_ready_T_2; // @[NBDcache.scala:203:{40,66,75}] reg acked; // @[NBDcache.scala:205:18] wire _io_meta_write_valid_T = state == 4'h6; // @[package.scala:16:47] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_req_bits_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, io_req_bits_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire [3:0] _state_T = {2'h0, ~needs_wb, 1'h1}; // @[Misc.scala:38:9] wire _can_finish_T = ~(|state); // @[package.scala:16:47] wire can_finish = _can_finish_T | _can_finish_T_1; // @[package.scala:16:47, :81:59] wire _grantackq_io_enq_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantackq_io_enq_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantackq_io_enq_valid_T_2 = ~_grantackq_io_enq_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantackq_io_enq_valid_T_3 = _grantackq_io_enq_valid_T & _grantackq_io_enq_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire _grantackq_io_enq_valid_T_4 = refill_done & _grantackq_io_enq_valid_T_3; // @[Edges.scala:71:40, :233:22] assign _io_mem_finish_valid_T = _grantackq_io_deq_valid & can_finish; // @[package.scala:81:59] assign io_mem_finish_valid_0 = _io_mem_finish_valid_T; // @[NBDcache.scala:150:7, :267:49] wire _grantackq_io_deq_ready_T = io_mem_finish_ready_0 & can_finish; // @[package.scala:81:59] wire _io_idx_match_T = |state; // @[NBDcache.scala:174:22, :203:75, :271:26] assign _io_idx_match_T_1 = _io_idx_match_T & idx_match; // @[NBDcache.scala:180:27, :271:{26,41}] assign io_idx_match_0 = _io_idx_match_T_1; // @[NBDcache.scala:150:7, :271:41] wire [39:0] _io_refill_addr_T = {req_block_addr[39:12], req_block_addr[11:0] | refill_address_inc}; // @[Edges.scala:269:29] assign io_refill_addr_0 = _io_refill_addr_T[11:0]; // @[NBDcache.scala:150:7, :273:{18,36}] assign io_tag_0 = req_tag_0[19:0]; // @[NBDcache.scala:150:7, :178:26, :274:10] assign _io_req_pri_rdy_T = ~(|state); // @[NBDcache.scala:174:22, :203:75, :275:27] assign io_req_pri_rdy_0 = _io_req_pri_rdy_T; // @[NBDcache.scala:150:7, :275:27] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[NBDcache.scala:195:27, :200:19, :276:29] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[NBDcache.scala:150:7, :276:29] reg [1:0] meta_hazard; // @[NBDcache.scala:278:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[NBDcache.scala:278:28, :279:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[NBDcache.scala:279:59] wire _io_probe_rdy_T = ~idx_match; // @[NBDcache.scala:180:27, :281:19] wire _io_probe_rdy_T_4 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_4 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = ~_io_probe_rdy_T_5; // @[package.scala:81:59] wire _io_probe_rdy_T_7 = meta_hazard == 2'h0; // @[NBDcache.scala:278:28, :281:86] wire _io_probe_rdy_T_8 = _io_probe_rdy_T_6 & _io_probe_rdy_T_7; // @[NBDcache.scala:281:{34,71,86}] assign _io_probe_rdy_T_9 = _io_probe_rdy_T | _io_probe_rdy_T_8; // @[NBDcache.scala:281:{19,30,71}] assign io_probe_rdy_0 = _io_probe_rdy_T_9; // @[NBDcache.scala:150:7, :281:30] assign _io_meta_write_valid_T_2 = _io_meta_write_valid_T | _io_meta_write_valid_T_1; // @[package.scala:16:47, :81:59] assign io_meta_write_valid_0 = _io_meta_write_valid_T_2; // @[package.scala:81:59] assign _io_meta_write_bits_data_coh_T_1_state = _io_meta_write_bits_data_coh_T ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] assign io_meta_write_bits_data_coh_state_0 = _io_meta_write_bits_data_coh_T_1_state; // @[NBDcache.scala:150:7, :286:37] assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[NBDcache.scala:150:7, :290:28] assign _io_mem_acquire_valid_T_1 = _io_mem_acquire_valid_T & _grantackq_io_enq_ready; // @[NBDcache.scala:263:25, :298:{33,50}] assign io_mem_acquire_valid_0 = _io_mem_acquire_valid_T_1; // @[NBDcache.scala:150:7, :298:50] wire [25:0] _GEN_29 = {io_tag_0, req_idx}; // @[NBDcache.scala:150:7, :177:25, :301:48] wire [25:0] _io_mem_acquire_bits_T; // @[NBDcache.scala:301:48] assign _io_mem_acquire_bits_T = _GEN_29; // @[NBDcache.scala:301:48] wire [25:0] io_replay_bits_addr_hi; // @[NBDcache.scala:313:29] assign io_replay_bits_addr_hi = _GEN_29; // @[NBDcache.scala:301:48, :313:29] wire [31:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[NBDcache.scala:179:51, :301:{48,66}] wire [31:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[NBDcache.scala:301:66] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1; // @[Edges.scala:346:17] wire [32:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[31:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[NBDcache.scala:301:66] wire [32:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[NBDcache.scala:301:66] wire [32:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 | _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 | _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [31:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[NBDcache.scala:301:66] wire [32:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_26 = _io_mem_acquire_bits_T_1 ^ 32'h80000000; // @[NBDcache.scala:301:66] wire [32:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 | _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] assign io_meta_read_valid_0 = _io_meta_read_valid_T; // @[NBDcache.scala:150:7, :305:31] assign _io_replay_valid_T_1 = _io_replay_valid_T & _rpq_io_deq_valid; // @[NBDcache.scala:200:19, :310:{28,44}] assign io_replay_valid_0 = _io_replay_valid_T_1; // @[NBDcache.scala:150:7, :310:44] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[NBDcache.scala:200:19, :313:67] wire [31:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[NBDcache.scala:313:{29,67}] assign io_replay_bits_addr_0 = {8'h0, _io_replay_bits_addr_T_1}; // @[Edges.scala:232:25] assign io_replay_bits_cmd_0 = io_meta_read_ready_0 ? _rpq_io_deq_bits_cmd : 5'h5; // @[NBDcache.scala:150:7, :200:19, :311:18, :315:30, :317:24] wire _T_7 = _sec_rdy_T_6 & refill_done; // @[package.scala:16:47] wire _T_15 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[NBDcache.scala:150:7, :234:24] always @(posedge clock) begin // @[NBDcache.scala:150:7] if (reset) begin // @[NBDcache.scala:150:7] state <= 4'h0; // @[NBDcache.scala:174:22] new_coh_state <= 2'h0; // @[NBDcache.scala:182:24] r_counter <= 9'h0; // @[Edges.scala:229:27] meta_hazard <= 2'h0; // @[NBDcache.scala:278:28] end else begin // @[NBDcache.scala:150:7] if (_rpq_io_enq_valid_T) begin // @[NBDcache.scala:201:39] state <= io_req_bits_tag_match_0 ? {2'h1, is_hit, 1'h0} : _state_T; // @[Misc.scala:35:9] new_coh_state <= io_req_bits_tag_match_0 ? (is_hit ? coh_on_hit_state : io_req_bits_old_meta_coh_state_0) : 2'h0; // @[Misc.scala:35:9] end else begin // @[NBDcache.scala:201:39] if (io_wb_req_ready_0 & io_wb_req_valid_0) // @[Decoupled.scala:51:35] state <= 4'h2; // @[NBDcache.scala:174:22] else if (_T_11 & io_wb_req_ready_0 & acked) // @[package.scala:16:47] state <= 4'h3; // @[NBDcache.scala:174:22] else if (_T_9 & io_meta_write_ready_0) // @[package.scala:16:47] state <= 4'h4; // @[NBDcache.scala:174:22] else if (io_mem_acquire_ready_0 & io_mem_acquire_valid_0) // @[Decoupled.scala:51:35] state <= 4'h5; // @[NBDcache.scala:174:22] else if (_T_7) // @[NBDcache.scala:218:33] state <= 4'h6; // @[NBDcache.scala:174:22] else if (_io_meta_write_valid_T & io_meta_write_ready_0) // @[package.scala:16:47] state <= 4'h7; // @[NBDcache.scala:174:22] else if (state == 4'h7) // @[NBDcache.scala:174:22, :211:15] state <= 4'h8; // @[NBDcache.scala:174:22] else if (_T & ~_rpq_io_deq_valid) // @[NBDcache.scala:200:19, :203:49, :208:{31,34}] state <= 4'h0; // @[NBDcache.scala:174:22] if (_T_15 & is_hit_again) // @[Metadata.scala:105:27] new_coh_state <= dirtier_coh_state; // @[Metadata.scala:160:20] else if (_T_7) // @[NBDcache.scala:218:33] new_coh_state <= coh_on_grant_state; // @[Metadata.scala:160:20] end if (io_mem_grant_valid_0) // @[NBDcache.scala:150:7] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (io_meta_write_ready_0 & io_meta_write_valid_0) // @[Decoupled.scala:51:35] meta_hazard <= 2'h1; // @[NBDcache.scala:278:28] else if (|meta_hazard) // @[NBDcache.scala:278:28, :279:21] meta_hazard <= _meta_hazard_T_1; // @[NBDcache.scala:278:28, :279:59] end if (_rpq_io_enq_valid_T) begin // @[NBDcache.scala:201:39] req_addr <= io_req_bits_addr_0; // @[NBDcache.scala:150:7, :176:16] req_tag <= io_req_bits_tag_0; // @[NBDcache.scala:150:7, :176:16] req_cmd <= io_req_bits_cmd_0; // @[NBDcache.scala:150:7, :176:16] req_size <= io_req_bits_size_0; // @[NBDcache.scala:150:7, :176:16] req_signed <= io_req_bits_signed_0; // @[NBDcache.scala:150:7, :176:16] req_dprv <= io_req_bits_dprv_0; // @[NBDcache.scala:150:7, :176:16] req_dv <= io_req_bits_dv_0; // @[NBDcache.scala:150:7, :176:16] req_phys <= io_req_bits_phys_0; // @[NBDcache.scala:150:7, :176:16] req_no_resp <= io_req_bits_no_resp_0; // @[NBDcache.scala:150:7, :176:16] req_no_alloc <= io_req_bits_no_alloc_0; // @[NBDcache.scala:150:7, :176:16] req_no_xcpt <= io_req_bits_no_xcpt_0; // @[NBDcache.scala:150:7, :176:16] req_sdq_id <= io_req_bits_sdq_id_0; // @[NBDcache.scala:150:7, :176:16] req_tag_match <= io_req_bits_tag_match_0; // @[NBDcache.scala:150:7, :176:16] req_old_meta_coh_state <= io_req_bits_old_meta_coh_state_0; // @[NBDcache.scala:150:7, :176:16] req_old_meta_tag <= io_req_bits_old_meta_tag_0; // @[NBDcache.scala:150:7, :176:16] req_way_en <= io_req_bits_way_en_0; // @[NBDcache.scala:150:7, :176:16] end else if (_T_15) // @[NBDcache.scala:234:24] req_cmd <= dirtier_cmd; // @[Metadata.scala:109:27] acked <= ~_rpq_io_enq_valid_T & (io_mem_grant_valid_0 | acked); // @[NBDcache.scala:150:7, :201:39, :205:18, :206:{29,37}, :243:43, :245:11] always @(posedge) Queue16_ReplayInternal rpq ( // @[NBDcache.scala:200:19] .clock (clock), .reset (reset), .io_enq_ready (_rpq_io_enq_ready), .io_enq_valid (_rpq_io_enq_valid_T_7), // @[NBDcache.scala:201:87] .io_enq_bits_addr (io_req_bits_addr_0), // @[NBDcache.scala:150:7] .io_enq_bits_tag (io_req_bits_tag_0), // @[NBDcache.scala:150:7] .io_enq_bits_cmd (io_req_bits_cmd_0), // @[NBDcache.scala:150:7] .io_enq_bits_size (io_req_bits_size_0), // @[NBDcache.scala:150:7] .io_enq_bits_signed (io_req_bits_signed_0), // @[NBDcache.scala:150:7] .io_enq_bits_dprv (io_req_bits_dprv_0), // @[NBDcache.scala:150:7] .io_enq_bits_dv (io_req_bits_dv_0), // @[NBDcache.scala:150:7] .io_enq_bits_phys (io_req_bits_phys_0), // @[NBDcache.scala:150:7] .io_enq_bits_no_resp (io_req_bits_no_resp_0), // @[NBDcache.scala:150:7] .io_enq_bits_no_alloc (io_req_bits_no_alloc_0), // @[NBDcache.scala:150:7] .io_enq_bits_no_xcpt (io_req_bits_no_xcpt_0), // @[NBDcache.scala:150:7] .io_enq_bits_sdq_id (io_req_bits_sdq_id_0), // @[NBDcache.scala:150:7] .io_deq_ready (io_meta_read_ready_0 & _rpq_io_deq_ready_T_3), // @[NBDcache.scala:150:7, :203:{20,66}, :315:30, :316:22] .io_deq_valid (_rpq_io_deq_valid), .io_deq_bits_addr (_rpq_io_deq_bits_addr), .io_deq_bits_tag (io_replay_bits_tag_0), .io_deq_bits_cmd (_rpq_io_deq_bits_cmd), .io_deq_bits_size (io_replay_bits_size_0), .io_deq_bits_signed (io_replay_bits_signed_0), .io_deq_bits_dprv (io_replay_bits_dprv_0), .io_deq_bits_dv (io_replay_bits_dv_0), .io_deq_bits_no_resp (io_replay_bits_no_resp_0), .io_deq_bits_no_alloc (io_replay_bits_no_alloc_0), .io_deq_bits_no_xcpt (io_replay_bits_no_xcpt_0), .io_deq_bits_sdq_id (io_replay_bits_sdq_id_0) ); // @[NBDcache.scala:200:19] Queue1_TLBundleE_a32d64s2k3z4c grantackq ( // @[NBDcache.scala:263:25] .clock (clock), .reset (reset), .io_enq_ready (_grantackq_io_enq_ready), .io_enq_valid (_grantackq_io_enq_valid_T_4), // @[NBDcache.scala:265:41] .io_enq_bits_sink (grantackq_io_enq_bits_e_sink), // @[Edges.scala:451:17] .io_deq_ready (_grantackq_io_deq_ready_T), // @[NBDcache.scala:269:49] .io_deq_valid (_grantackq_io_deq_valid), .io_deq_bits_sink (io_mem_finish_bits_sink_0) ); // @[NBDcache.scala:263:25] assign io_req_pri_rdy = io_req_pri_rdy_0; // @[NBDcache.scala:150:7] assign io_req_sec_rdy = io_req_sec_rdy_0; // @[NBDcache.scala:150:7] assign io_idx_match = io_idx_match_0; // @[NBDcache.scala:150:7] assign io_tag = io_tag_0; // @[NBDcache.scala:150:7] assign io_mem_acquire_valid = io_mem_acquire_valid_0; // @[NBDcache.scala:150:7] assign io_mem_acquire_bits_param = io_mem_acquire_bits_param_0; // @[NBDcache.scala:150:7] assign io_mem_acquire_bits_address = io_mem_acquire_bits_address_0; // @[NBDcache.scala:150:7] assign io_mem_finish_valid = io_mem_finish_valid_0; // @[NBDcache.scala:150:7] assign io_mem_finish_bits_sink = io_mem_finish_bits_sink_0; // @[NBDcache.scala:150:7] assign io_refill_way_en = io_refill_way_en_0; // @[NBDcache.scala:150:7] assign io_refill_addr = io_refill_addr_0; // @[NBDcache.scala:150:7] assign io_meta_read_valid = io_meta_read_valid_0; // @[NBDcache.scala:150:7] assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[NBDcache.scala:150:7] assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[NBDcache.scala:150:7] assign io_meta_write_valid = io_meta_write_valid_0; // @[NBDcache.scala:150:7] assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[NBDcache.scala:150:7] assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[NBDcache.scala:150:7] assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[NBDcache.scala:150:7] assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[NBDcache.scala:150:7] assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[NBDcache.scala:150:7] assign io_replay_valid = io_replay_valid_0; // @[NBDcache.scala:150:7] assign io_replay_bits_addr = io_replay_bits_addr_0; // @[NBDcache.scala:150:7] assign io_replay_bits_tag = io_replay_bits_tag_0; // @[NBDcache.scala:150:7] assign io_replay_bits_cmd = io_replay_bits_cmd_0; // @[NBDcache.scala:150:7] assign io_replay_bits_size = io_replay_bits_size_0; // @[NBDcache.scala:150:7] assign io_replay_bits_signed = io_replay_bits_signed_0; // @[NBDcache.scala:150:7] assign io_replay_bits_dprv = io_replay_bits_dprv_0; // @[NBDcache.scala:150:7] assign io_replay_bits_dv = io_replay_bits_dv_0; // @[NBDcache.scala:150:7] assign io_replay_bits_no_resp = io_replay_bits_no_resp_0; // @[NBDcache.scala:150:7] assign io_replay_bits_no_alloc = io_replay_bits_no_alloc_0; // @[NBDcache.scala:150:7] assign io_replay_bits_no_xcpt = io_replay_bits_no_xcpt_0; // @[NBDcache.scala:150:7] assign io_replay_bits_sdq_id = io_replay_bits_sdq_id_0; // @[NBDcache.scala:150:7] assign io_wb_req_valid = io_wb_req_valid_0; // @[NBDcache.scala:150:7] assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[NBDcache.scala:150:7] assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[NBDcache.scala:150:7] assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[NBDcache.scala:150:7] assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[NBDcache.scala:150:7] assign io_probe_rdy = io_probe_rdy_0; // @[NBDcache.scala:150:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_23 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], _T_191, UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], _T_331, UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<17>(0h10000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<17>(0h10000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<17>(0h10000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<26>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_46 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<26>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_47 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<26>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1094 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1094; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1094; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_1162 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1162; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1027 = _T_1094 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1042 = _T_1162 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1138 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1138 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1120 = _T_1162 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1120 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1120 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1120 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a21d64s8k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)

module Repeater_TLBundleA_a21d64s8k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [20:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [20:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [7:0] saved_source; // @[Repeater.scala:21:18] reg [20:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18] saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_4 : input clock : Clock input reset : Reset output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<4>(0hf)) when _T : connect doing_reset, UInt<1>(0h0) reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0)) node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0) wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect f2_entry, entries[_f2_entry_T_1] node _T_1 = eq(io.update_idx, io.f2_req_idx) node _T_2 = and(io.update_repair, _T_1) when _T_2 : connect f2_entry.s_cnt, io.update_meta.s_cnt else : node _T_3 = eq(io.update_idx, io.f2_req_idx) node _T_4 = and(io.update_mispredict, _T_3) when _T_4 : connect f2_entry.s_cnt, UInt<1>(0h0) reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f3_entry, f2_entry reg f3_scnt_REG : UInt, clock connect f3_scnt_REG, io.f2_req_idx node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG) node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T) node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt) node _f3_tag_T = bits(io.f2_req_idx, 13, 4) reg f3_tag : UInt, clock connect f3_tag, _f3_tag_T connect io.f3_pred, io.f3_pred_in connect io.f3_meta.s_cnt, f3_scnt node _T_5 = eq(f3_entry.tag, f3_tag) when _T_5 : node _T_6 = eq(f3_scnt, f3_entry.p_cnt) node _T_7 = eq(f3_entry.conf, UInt<3>(0h7)) node _T_8 = and(_T_6, _T_7) when _T_8 : node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0)) connect io.f3_pred, _io_f3_pred_T reg f4_fire : UInt<1>, clock connect f4_fire, io.f3_req_fire reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f4_entry, f3_entry reg f4_tag : UInt, clock connect f4_tag, f3_tag reg f4_scnt : UInt, clock connect f4_scnt, f3_scnt reg f4_idx_REG : UInt, clock connect f4_idx_REG, io.f2_req_idx reg f4_idx : UInt, clock connect f4_idx, f4_idx_REG when f4_fire : node _T_9 = eq(f4_entry.tag, f4_tag) when _T_9 : node _T_10 = eq(f4_scnt, f4_entry.p_cnt) node _T_11 = eq(f4_entry.conf, UInt<3>(0h7)) node _T_12 = and(_T_10, _T_11) when _T_12 : node _T_13 = or(f4_idx, UInt<4>(0h0)) node _T_14 = bits(_T_13, 3, 0) connect entries[_T_14].age, UInt<3>(0h7) node _T_15 = or(f4_idx, UInt<4>(0h0)) node _T_16 = bits(_T_15, 3, 0) connect entries[_T_16].s_cnt, UInt<1>(0h0) else : node _T_17 = or(f4_idx, UInt<4>(0h0)) node _T_18 = bits(_T_17, 3, 0) node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1)) node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1) connect entries[_T_18].s_cnt, _entries_s_cnt_T_1 node _T_19 = or(f4_idx, UInt<4>(0h0)) node _T_20 = bits(_T_19, 3, 0) node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7)) node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1)) node _entries_age_T_2 = tail(_entries_age_T_1, 1) node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2) connect entries[_T_20].age, _entries_age_T_3 node _entry_T = or(io.update_idx, UInt<4>(0h0)) node _entry_T_1 = bits(_entry_T, 3, 0) node tag = bits(io.update_idx, 13, 4) node tag_match = eq(entries[_entry_T_1].tag, tag) node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt) wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect wentry, entries[_entry_T_1] node _T_21 = eq(doing_reset, UInt<1>(0h0)) node _T_22 = and(io.update_mispredict, _T_21) when _T_22 : node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_24 = and(_T_23, tag_match) when _T_24 : connect wentry.s_cnt, UInt<1>(0h0) node _wentry_conf_T = sub(entries[_entry_T_1].conf, UInt<1>(0h1)) node _wentry_conf_T_1 = tail(_wentry_conf_T, 1) connect wentry.conf, _wentry_conf_T_1 else : node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_26 = eq(tag_match, UInt<1>(0h0)) node _T_27 = and(_T_25, _T_26) when _T_27 : skip else : node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_29 = and(_T_28, tag_match) node _T_30 = and(_T_29, ctr_match) when _T_30 : node _wentry_conf_T_2 = add(entries[_entry_T_1].conf, UInt<1>(0h1)) node _wentry_conf_T_3 = tail(_wentry_conf_T_2, 1) connect wentry.conf, _wentry_conf_T_3 connect wentry.s_cnt, UInt<1>(0h0) else : node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_32 = and(_T_31, tag_match) node _T_33 = eq(ctr_match, UInt<1>(0h0)) node _T_34 = and(_T_32, _T_33) when _T_34 : connect wentry.conf, UInt<1>(0h0) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_36 = eq(tag_match, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) when _T_39 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_41 = eq(tag_match, UInt<1>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) when _T_44 : node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1)) node _wentry_age_T_1 = tail(_wentry_age_T, 1) connect wentry.age, _wentry_age_T_1 else : node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_46 = and(_T_45, tag_match) node _T_47 = and(_T_46, ctr_match) when _T_47 : connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_49 = and(_T_48, tag_match) node _T_50 = eq(ctr_match, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) when _T_51 : connect wentry.p_cnt, io.update_meta.s_cnt connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_53 = eq(tag_match, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) when _T_54 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt node _T_55 = or(io.update_idx, UInt<4>(0h0)) node _T_56 = bits(_T_55, 3, 0) connect entries[_T_56], wentry else : node _T_57 = eq(doing_reset, UInt<1>(0h0)) node _T_58 = and(io.update_repair, _T_57) when _T_58 : node _T_59 = eq(io.update_idx, f4_idx) node _T_60 = and(f4_fire, _T_59) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = and(tag_match, _T_61) when _T_62 : connect wentry.s_cnt, io.update_meta.s_cnt node _T_63 = or(io.update_idx, UInt<4>(0h0)) node _T_64 = bits(_T_63, 3, 0) connect entries[_T_64], wentry when doing_reset : wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect _entries_WIRE.s_cnt, UInt<10>(0h0) connect _entries_WIRE.p_cnt, UInt<10>(0h0) connect _entries_WIRE.age, UInt<3>(0h0) connect _entries_WIRE.conf, UInt<3>(0h0) connect _entries_WIRE.tag, UInt<10>(0h0) connect entries[reset_idx], _entries_WIRE

module LoopBranchPredictorColumn_4( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [35:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [35:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [35:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [35:0] f4_idx_REG; // @[loop.scala:92:35] reg [35:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire [3:0] _GEN_4 = {1'h0, _GEN_0[_entry_T_1]}; // @[loop.scala:66:28, :110:31, :119:36] wire [3:0] _wentry_conf_T = _GEN_4 - 4'h1; // @[loop.scala:119:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:119:36] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T_2 = _GEN_4 + 4'h1; // @[loop.scala:102:80, :119:36, :126:36] wire [2:0] _wentry_conf_T_3 = _wentry_conf_T_2[2:0]; // @[loop.scala:126:36] wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_5 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_6 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_6 | ~(_T_39 | ~(_T_44 | _GEN_5 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? _wentry_conf_T_1 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_3 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:{22,36}, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_7 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_8 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_8 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_7 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_8 | ~(_T_44 | _T_47 | ~_GEN_7)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_6 | _T_39 | ~(_T_44 | ~(_GEN_5 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_9 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_15 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[3]}, tail : UInt<1>}}[1]}, credit_alloc : { `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[3]}, switch_sel : { `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}} inst arbs_0 of SwitchArbiter_113 connect arbs_0.clock, clock connect arbs_0.reset, reset inst arbs_1 of SwitchArbiter_114 connect arbs_1.clock, clock connect arbs_1.reset, reset connect arbs_0.io.out[0].ready, UInt<1>(0h1) connect arbs_1.io.out[0].ready, UInt<1>(0h1) wire fires : UInt<1>[2] node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_0_valid_T_2 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_1) connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_2 connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid) connect fires[0], _fires_0_T node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid) connect fires[1], _fires_1_T node _io_req_0_0_ready_T = or(fires[0], fires[1]) connect io.req.`0`[0].ready, _io_req_0_0_ready_T wire fires_1 : UInt<1>[2] node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_1_valid_T_2 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_1) connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_2 connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid) connect fires_1[0], _fires_0_T_1 node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid) connect fires_1[1], _fires_1_T_1 node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1]) connect io.req.`1`[0].ready, _io_req_1_0_ready_T wire fires_2 : UInt<1>[2] node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_2_valid_T_2 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_1) connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_2 connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid) connect fires_2[0], _fires_0_T_2 node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid) connect fires_2[1], _fires_1_T_2 node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1]) connect io.req.`2`[0].ready, _io_req_2_0_ready_T node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0) node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T) node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2 node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1) node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T) node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2 node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2) node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T) node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2 node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0) node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T) node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2 node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1) node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T) node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2 node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2) node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T) node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2 connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0) connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0) connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0) node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0]) when _T : connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1]) when _T_1 : connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2]) when _T_2 : connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail node _T_3 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0]) when _T_3 : connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail

module SwitchAllocator_15( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_2_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_2_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_1_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_2_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_0_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [2:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:83:45] wire [2:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_0_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_0_0 | io_req_0_0_bits_vc_sel_0_1 | io_req_0_0_bits_vc_sel_0_2); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_0 | io_req_1_0_bits_vc_sel_0_1 | io_req_1_0_bits_vc_sel_0_2); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_0_0 | io_req_2_0_bits_vc_sel_0_1 | io_req_2_0_bits_vc_sel_0_2); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33] SwitchArbiter_112 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_0_io_in_0_ready), .io_in_0_valid (arbs_0_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_0_io_in_1_ready), .io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_in_2_ready (_arbs_0_io_in_2_ready), .io_in_2_valid (arbs_0_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_ready (1'h1), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_0 (/* unused */), .io_out_0_bits_vc_sel_0_1 (_arbs_0_io_out_0_bits_vc_sel_0_1), .io_out_0_bits_vc_sel_0_2 (_arbs_0_io_out_0_bits_vc_sel_0_2), .io_out_0_bits_tail (/* unused */), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_112 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_1_io_in_1_ready), .io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_in_2_ready (_arbs_1_io_in_2_ready), .io_in_2_valid (arbs_1_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_ready (1'h1), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0), .io_out_0_bits_vc_sel_0_0 (/* unused */), .io_out_0_bits_vc_sel_0_1 (/* unused */), .io_out_0_bits_vc_sel_0_2 (/* unused */), .io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_2_0_ready = _arbs_0_io_in_2_ready & arbs_0_io_in_2_valid | _arbs_1_io_in_2_ready & arbs_1_io_in_2_valid; // @[Decoupled.scala:51:35] assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid | _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_0_io_in_0_ready & arbs_0_io_in_0_valid | _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_0_1_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_2_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_1_0_2_0 = arbs_1_io_in_2_valid & _arbs_1_io_chosen_oh_0[2] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_2_0 = arbs_0_io_in_2_valid & _arbs_0_io_chosen_oh_0[2] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_0_0 = arbs_0_io_in_0_valid & _arbs_0_io_chosen_oh_0[0] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_72 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}} wire _in_flight_WIRE : UInt<1>[2] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_40 = and(_T_38, _T_39) node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_47 = and(_T_45, _T_46) node _T_48 = or(_T_12, _T_19) node _T_49 = or(_T_48, _T_26) node _T_50 = or(_T_49, _T_33) node _T_51 = or(_T_50, _T_40) node _T_52 = or(_T_51, _T_47) node _T_53 = or(_T_5, _T_52) node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : node _T_56 = eq(_T_53, UInt<1>(0h0)) when _T_56 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_53, UInt<1>(0h1), "") : assert_1 node _T_57 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_71 = and(_T_69, _T_70) node _T_72 = or(_T_64, _T_71) node _T_73 = or(_T_57, _T_72) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_73, UInt<1>(0h1), "") : assert_2

module NoCMonitor_72( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_91 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_179 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_91( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_179 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_34 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} inst input_buffer of InputBuffer_34 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) inst route_arbiter of Arbiter8_RouteComputerReq_34 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h15)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_9 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_9 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_10 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_11 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_12 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_13 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_14 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_15 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_16 : connect states[7].g, UInt<3>(0h2) node _T_17 = and(io.router_req.ready, io.router_req.valid) when _T_17 : node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_18, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_22 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_23 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_24 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_25 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_26 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_27 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_28 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_29 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.router_resp.vc_sel.`4` regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] wire vcalloc_vals : UInt<1>[8] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_30 = and(io.router_req.ready, io.router_req.valid) when _T_30 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_31 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_32 = or(_T_31, vcalloc_vals[2]) node _T_33 = or(_T_32, vcalloc_vals[3]) node _T_34 = or(_T_33, vcalloc_vals[4]) node _T_35 = or(_T_34, vcalloc_vals[5]) node _T_36 = or(_T_35, vcalloc_vals[6]) node _T_37 = or(_T_36, vcalloc_vals[7]) when _T_37 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = bits(vcalloc_sel, 0, 0) node _mask_T_12 = bits(vcalloc_sel, 1, 1) node _mask_T_13 = bits(vcalloc_sel, 2, 2) node _mask_T_14 = bits(vcalloc_sel, 3, 3) node _mask_T_15 = bits(vcalloc_sel, 4, 4) node _mask_T_16 = bits(vcalloc_sel, 5, 5) node _mask_T_17 = bits(vcalloc_sel, 6, 6) node _mask_T_18 = bits(vcalloc_sel, 7, 7) node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) node _mask_T_27 = or(_mask_T_19, _mask_T_20) node _mask_T_28 = or(_mask_T_27, _mask_T_21) node _mask_T_29 = or(_mask_T_28, _mask_T_22) node _mask_T_30 = or(_mask_T_29, _mask_T_23) node _mask_T_31 = or(_mask_T_30, _mask_T_24) node _mask_T_32 = or(_mask_T_31, _mask_T_25) node _mask_T_33 = or(_mask_T_32, _mask_T_26) wire _mask_WIRE : UInt<8> connect _mask_WIRE, _mask_T_33 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} wire _io_vcalloc_req_bits_WIRE_1 : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8] node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382 connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34 node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) wire _io_vcalloc_req_bits_WIRE_35 : UInt<1> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35 node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459) node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460) node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461) node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462) node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463) node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464) node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465) wire _io_vcalloc_req_bits_WIRE_36 : UInt<1> connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472 connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36 node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477) node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478) node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479) node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480) wire _io_vcalloc_req_bits_WIRE_37 : UInt<1> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487 connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29 wire _io_vcalloc_req_bits_WIRE_38 : UInt<1>[8] node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495) wire _io_vcalloc_req_bits_WIRE_39 : UInt<1> connect _io_vcalloc_req_bits_WIRE_39, _io_vcalloc_req_bits_T_502 connect _io_vcalloc_req_bits_WIRE_38[0], _io_vcalloc_req_bits_WIRE_39 node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504) node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510) wire _io_vcalloc_req_bits_WIRE_40 : UInt<1> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517 connect _io_vcalloc_req_bits_WIRE_38[1], _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519) node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520) node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521) node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522) node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523) node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525) wire _io_vcalloc_req_bits_WIRE_41 : UInt<1> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532 connect _io_vcalloc_req_bits_WIRE_38[2], _io_vcalloc_req_bits_WIRE_41 node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534) node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535) node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536) node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537) node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538) node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539) node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540) wire _io_vcalloc_req_bits_WIRE_42 : UInt<1> connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547 connect _io_vcalloc_req_bits_WIRE_38[3], _io_vcalloc_req_bits_WIRE_42 node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553) node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554) node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555) wire _io_vcalloc_req_bits_WIRE_43 : UInt<1> connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562 connect _io_vcalloc_req_bits_WIRE_38[4], _io_vcalloc_req_bits_WIRE_43 node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_44 : UInt<1> connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577 connect _io_vcalloc_req_bits_WIRE_38[5], _io_vcalloc_req_bits_WIRE_44 node _io_vcalloc_req_bits_T_578 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_579 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_580 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_581 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_582 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_583 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_584 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_585 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_586 = or(_io_vcalloc_req_bits_T_578, _io_vcalloc_req_bits_T_579) node _io_vcalloc_req_bits_T_587 = or(_io_vcalloc_req_bits_T_586, _io_vcalloc_req_bits_T_580) node _io_vcalloc_req_bits_T_588 = or(_io_vcalloc_req_bits_T_587, _io_vcalloc_req_bits_T_581) node _io_vcalloc_req_bits_T_589 = or(_io_vcalloc_req_bits_T_588, _io_vcalloc_req_bits_T_582) node _io_vcalloc_req_bits_T_590 = or(_io_vcalloc_req_bits_T_589, _io_vcalloc_req_bits_T_583) node _io_vcalloc_req_bits_T_591 = or(_io_vcalloc_req_bits_T_590, _io_vcalloc_req_bits_T_584) node _io_vcalloc_req_bits_T_592 = or(_io_vcalloc_req_bits_T_591, _io_vcalloc_req_bits_T_585) wire _io_vcalloc_req_bits_WIRE_45 : UInt<1> connect _io_vcalloc_req_bits_WIRE_45, _io_vcalloc_req_bits_T_592 connect _io_vcalloc_req_bits_WIRE_38[6], _io_vcalloc_req_bits_WIRE_45 node _io_vcalloc_req_bits_T_593 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_594 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_595 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_596 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_597 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_598 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_599 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_600 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_601 = or(_io_vcalloc_req_bits_T_593, _io_vcalloc_req_bits_T_594) node _io_vcalloc_req_bits_T_602 = or(_io_vcalloc_req_bits_T_601, _io_vcalloc_req_bits_T_595) node _io_vcalloc_req_bits_T_603 = or(_io_vcalloc_req_bits_T_602, _io_vcalloc_req_bits_T_596) node _io_vcalloc_req_bits_T_604 = or(_io_vcalloc_req_bits_T_603, _io_vcalloc_req_bits_T_597) node _io_vcalloc_req_bits_T_605 = or(_io_vcalloc_req_bits_T_604, _io_vcalloc_req_bits_T_598) node _io_vcalloc_req_bits_T_606 = or(_io_vcalloc_req_bits_T_605, _io_vcalloc_req_bits_T_599) node _io_vcalloc_req_bits_T_607 = or(_io_vcalloc_req_bits_T_606, _io_vcalloc_req_bits_T_600) wire _io_vcalloc_req_bits_WIRE_46 : UInt<1> connect _io_vcalloc_req_bits_WIRE_46, _io_vcalloc_req_bits_T_607 connect _io_vcalloc_req_bits_WIRE_38[7], _io_vcalloc_req_bits_WIRE_46 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_38 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_608 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_609 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_610 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_611 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_612 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_613 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_614 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_615 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_616 = or(_io_vcalloc_req_bits_T_608, _io_vcalloc_req_bits_T_609) node _io_vcalloc_req_bits_T_617 = or(_io_vcalloc_req_bits_T_616, _io_vcalloc_req_bits_T_610) node _io_vcalloc_req_bits_T_618 = or(_io_vcalloc_req_bits_T_617, _io_vcalloc_req_bits_T_611) node _io_vcalloc_req_bits_T_619 = or(_io_vcalloc_req_bits_T_618, _io_vcalloc_req_bits_T_612) node _io_vcalloc_req_bits_T_620 = or(_io_vcalloc_req_bits_T_619, _io_vcalloc_req_bits_T_613) node _io_vcalloc_req_bits_T_621 = or(_io_vcalloc_req_bits_T_620, _io_vcalloc_req_bits_T_614) node _io_vcalloc_req_bits_T_622 = or(_io_vcalloc_req_bits_T_621, _io_vcalloc_req_bits_T_615) wire _io_vcalloc_req_bits_WIRE_47 : UInt<3> connect _io_vcalloc_req_bits_WIRE_47, _io_vcalloc_req_bits_T_622 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_47 wire _io_vcalloc_req_bits_WIRE_48 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_623 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_624 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_625 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_626 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_627 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_628 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_629 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_630 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_631 = or(_io_vcalloc_req_bits_T_623, _io_vcalloc_req_bits_T_624) node _io_vcalloc_req_bits_T_632 = or(_io_vcalloc_req_bits_T_631, _io_vcalloc_req_bits_T_625) node _io_vcalloc_req_bits_T_633 = or(_io_vcalloc_req_bits_T_632, _io_vcalloc_req_bits_T_626) node _io_vcalloc_req_bits_T_634 = or(_io_vcalloc_req_bits_T_633, _io_vcalloc_req_bits_T_627) node _io_vcalloc_req_bits_T_635 = or(_io_vcalloc_req_bits_T_634, _io_vcalloc_req_bits_T_628) node _io_vcalloc_req_bits_T_636 = or(_io_vcalloc_req_bits_T_635, _io_vcalloc_req_bits_T_629) node _io_vcalloc_req_bits_T_637 = or(_io_vcalloc_req_bits_T_636, _io_vcalloc_req_bits_T_630) wire _io_vcalloc_req_bits_WIRE_49 : UInt<2> connect _io_vcalloc_req_bits_WIRE_49, _io_vcalloc_req_bits_T_637 connect _io_vcalloc_req_bits_WIRE_48.egress_node_id, _io_vcalloc_req_bits_WIRE_49 node _io_vcalloc_req_bits_T_638 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_639 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_640 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_641 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_642 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_643 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_644 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_645 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_646 = or(_io_vcalloc_req_bits_T_638, _io_vcalloc_req_bits_T_639) node _io_vcalloc_req_bits_T_647 = or(_io_vcalloc_req_bits_T_646, _io_vcalloc_req_bits_T_640) node _io_vcalloc_req_bits_T_648 = or(_io_vcalloc_req_bits_T_647, _io_vcalloc_req_bits_T_641) node _io_vcalloc_req_bits_T_649 = or(_io_vcalloc_req_bits_T_648, _io_vcalloc_req_bits_T_642) node _io_vcalloc_req_bits_T_650 = or(_io_vcalloc_req_bits_T_649, _io_vcalloc_req_bits_T_643) node _io_vcalloc_req_bits_T_651 = or(_io_vcalloc_req_bits_T_650, _io_vcalloc_req_bits_T_644) node _io_vcalloc_req_bits_T_652 = or(_io_vcalloc_req_bits_T_651, _io_vcalloc_req_bits_T_645) wire _io_vcalloc_req_bits_WIRE_50 : UInt<5> connect _io_vcalloc_req_bits_WIRE_50, _io_vcalloc_req_bits_T_652 connect _io_vcalloc_req_bits_WIRE_48.egress_node, _io_vcalloc_req_bits_WIRE_50 node _io_vcalloc_req_bits_T_653 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_654 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_655 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_656 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_657 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_658 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_659 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_660 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_661 = or(_io_vcalloc_req_bits_T_653, _io_vcalloc_req_bits_T_654) node _io_vcalloc_req_bits_T_662 = or(_io_vcalloc_req_bits_T_661, _io_vcalloc_req_bits_T_655) node _io_vcalloc_req_bits_T_663 = or(_io_vcalloc_req_bits_T_662, _io_vcalloc_req_bits_T_656) node _io_vcalloc_req_bits_T_664 = or(_io_vcalloc_req_bits_T_663, _io_vcalloc_req_bits_T_657) node _io_vcalloc_req_bits_T_665 = or(_io_vcalloc_req_bits_T_664, _io_vcalloc_req_bits_T_658) node _io_vcalloc_req_bits_T_666 = or(_io_vcalloc_req_bits_T_665, _io_vcalloc_req_bits_T_659) node _io_vcalloc_req_bits_T_667 = or(_io_vcalloc_req_bits_T_666, _io_vcalloc_req_bits_T_660) wire _io_vcalloc_req_bits_WIRE_51 : UInt<2> connect _io_vcalloc_req_bits_WIRE_51, _io_vcalloc_req_bits_T_667 connect _io_vcalloc_req_bits_WIRE_48.ingress_node_id, _io_vcalloc_req_bits_WIRE_51 node _io_vcalloc_req_bits_T_668 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_669 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_670 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_671 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_672 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_673 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_674 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_675 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_676 = or(_io_vcalloc_req_bits_T_668, _io_vcalloc_req_bits_T_669) node _io_vcalloc_req_bits_T_677 = or(_io_vcalloc_req_bits_T_676, _io_vcalloc_req_bits_T_670) node _io_vcalloc_req_bits_T_678 = or(_io_vcalloc_req_bits_T_677, _io_vcalloc_req_bits_T_671) node _io_vcalloc_req_bits_T_679 = or(_io_vcalloc_req_bits_T_678, _io_vcalloc_req_bits_T_672) node _io_vcalloc_req_bits_T_680 = or(_io_vcalloc_req_bits_T_679, _io_vcalloc_req_bits_T_673) node _io_vcalloc_req_bits_T_681 = or(_io_vcalloc_req_bits_T_680, _io_vcalloc_req_bits_T_674) node _io_vcalloc_req_bits_T_682 = or(_io_vcalloc_req_bits_T_681, _io_vcalloc_req_bits_T_675) wire _io_vcalloc_req_bits_WIRE_52 : UInt<5> connect _io_vcalloc_req_bits_WIRE_52, _io_vcalloc_req_bits_T_682 connect _io_vcalloc_req_bits_WIRE_48.ingress_node, _io_vcalloc_req_bits_WIRE_52 node _io_vcalloc_req_bits_T_683 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_684 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_685 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_686 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_687 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_688 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_689 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_690 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_691 = or(_io_vcalloc_req_bits_T_683, _io_vcalloc_req_bits_T_684) node _io_vcalloc_req_bits_T_692 = or(_io_vcalloc_req_bits_T_691, _io_vcalloc_req_bits_T_685) node _io_vcalloc_req_bits_T_693 = or(_io_vcalloc_req_bits_T_692, _io_vcalloc_req_bits_T_686) node _io_vcalloc_req_bits_T_694 = or(_io_vcalloc_req_bits_T_693, _io_vcalloc_req_bits_T_687) node _io_vcalloc_req_bits_T_695 = or(_io_vcalloc_req_bits_T_694, _io_vcalloc_req_bits_T_688) node _io_vcalloc_req_bits_T_696 = or(_io_vcalloc_req_bits_T_695, _io_vcalloc_req_bits_T_689) node _io_vcalloc_req_bits_T_697 = or(_io_vcalloc_req_bits_T_696, _io_vcalloc_req_bits_T_690) wire _io_vcalloc_req_bits_WIRE_53 : UInt<3> connect _io_vcalloc_req_bits_WIRE_53, _io_vcalloc_req_bits_T_697 connect _io_vcalloc_req_bits_WIRE_48.vnet_id, _io_vcalloc_req_bits_WIRE_53 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_48 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4` connect vcalloc_reqs[0].flow, states[0].flow node _T_38 = bits(vcalloc_sel, 0, 0) node _T_39 = and(vcalloc_vals[0], _T_38) node _T_40 = and(_T_39, io.vcalloc_req.ready) when _T_40 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].flow, states[1].flow node _T_41 = bits(vcalloc_sel, 1, 1) node _T_42 = and(vcalloc_vals[1], _T_41) node _T_43 = and(_T_42, io.vcalloc_req.ready) when _T_43 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].flow, states[2].flow node _T_44 = bits(vcalloc_sel, 2, 2) node _T_45 = and(vcalloc_vals[2], _T_44) node _T_46 = and(_T_45, io.vcalloc_req.ready) when _T_46 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].vc_sel.`4`, states[3].vc_sel.`4` connect vcalloc_reqs[3].flow, states[3].flow node _T_47 = bits(vcalloc_sel, 3, 3) node _T_48 = and(vcalloc_vals[3], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].vc_sel.`4`, states[4].vc_sel.`4` connect vcalloc_reqs[4].flow, states[4].flow node _T_50 = bits(vcalloc_sel, 4, 4) node _T_51 = and(vcalloc_vals[4], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].vc_sel.`4`, states[5].vc_sel.`4` connect vcalloc_reqs[5].flow, states[5].flow node _T_53 = bits(vcalloc_sel, 5, 5) node _T_54 = and(vcalloc_vals[5], _T_53) node _T_55 = and(_T_54, io.vcalloc_req.ready) when _T_55 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3` connect vcalloc_reqs[6].vc_sel.`4`, states[6].vc_sel.`4` connect vcalloc_reqs[6].flow, states[6].flow node _T_56 = bits(vcalloc_sel, 6, 6) node _T_57 = and(vcalloc_vals[6], _T_56) node _T_58 = and(_T_57, io.vcalloc_req.ready) when _T_58 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` connect vcalloc_reqs[7].vc_sel.`4`, states[7].vc_sel.`4` connect vcalloc_reqs[7].flow, states[7].flow node _T_59 = bits(vcalloc_sel, 7, 7) node _T_60 = and(vcalloc_vals[7], _T_59) node _T_61 = and(_T_60, io.vcalloc_req.ready) when _T_61 : connect states[7].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) connect io.debug.va_stall, _io_debug_va_stall_T_15 node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_62 : node _T_63 = bits(vcalloc_sel, 0, 0) when _T_63 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].g, UInt<3>(0h3) node _T_64 = eq(states[0].g, UInt<3>(0h2)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_64, UInt<1>(0h1), "") : assert_3 node _T_68 = bits(vcalloc_sel, 1, 1) when _T_68 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].g, UInt<3>(0h3) node _T_69 = eq(states[1].g, UInt<3>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_69, UInt<1>(0h1), "") : assert_4 node _T_73 = bits(vcalloc_sel, 2, 2) when _T_73 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].g, UInt<3>(0h3) node _T_74 = eq(states[2].g, UInt<3>(0h2)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_74, UInt<1>(0h1), "") : assert_5 node _T_78 = bits(vcalloc_sel, 3, 3) when _T_78 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[3].g, UInt<3>(0h3) node _T_79 = eq(states[3].g, UInt<3>(0h2)) node _T_80 = asUInt(reset) node _T_81 = eq(_T_80, UInt<1>(0h0)) when _T_81 : node _T_82 = eq(_T_79, UInt<1>(0h0)) when _T_82 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_79, UInt<1>(0h1), "") : assert_6 node _T_83 = bits(vcalloc_sel, 4, 4) when _T_83 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[4].g, UInt<3>(0h3) node _T_84 = eq(states[4].g, UInt<3>(0h2)) node _T_85 = asUInt(reset) node _T_86 = eq(_T_85, UInt<1>(0h0)) when _T_86 : node _T_87 = eq(_T_84, UInt<1>(0h0)) when _T_87 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_84, UInt<1>(0h1), "") : assert_7 node _T_88 = bits(vcalloc_sel, 5, 5) when _T_88 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[5].g, UInt<3>(0h3) node _T_89 = eq(states[5].g, UInt<3>(0h2)) node _T_90 = asUInt(reset) node _T_91 = eq(_T_90, UInt<1>(0h0)) when _T_91 : node _T_92 = eq(_T_89, UInt<1>(0h0)) when _T_92 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_89, UInt<1>(0h1), "") : assert_8 node _T_93 = bits(vcalloc_sel, 6, 6) when _T_93 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[6].g, UInt<3>(0h3) node _T_94 = eq(states[6].g, UInt<3>(0h2)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = bits(vcalloc_sel, 7, 7) when _T_98 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[7].g, UInt<3>(0h3) node _T_99 = eq(states[7].g, UInt<3>(0h2)) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 inst salloc_arb of SwitchArbiter_99 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0]) node credit_available_lo_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4]) node credit_available_hi_hi = cat(states[0].vc_sel.`0`[7], states[0].vc_sel.`0`[6]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0]) node credit_available_lo_hi_1 = cat(states[0].vc_sel.`1`[3], states[0].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[0].vc_sel.`1`[5], states[0].vc_sel.`1`[4]) node credit_available_hi_hi_1 = cat(states[0].vc_sel.`1`[7], states[0].vc_sel.`1`[6]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0]) node credit_available_lo_hi_2 = cat(states[0].vc_sel.`2`[3], states[0].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[0].vc_sel.`2`[5], states[0].vc_sel.`2`[4]) node credit_available_hi_hi_2 = cat(states[0].vc_sel.`2`[7], states[0].vc_sel.`2`[6]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_lo_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0]) node credit_available_lo_hi_3 = cat(states[0].vc_sel.`3`[3], states[0].vc_sel.`3`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(states[0].vc_sel.`3`[5], states[0].vc_sel.`3`[4]) node credit_available_hi_hi_3 = cat(states[0].vc_sel.`3`[7], states[0].vc_sel.`3`[6]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node credit_available_lo_lo_4 = cat(states[0].vc_sel.`4`[1], states[0].vc_sel.`4`[0]) node credit_available_lo_hi_4 = cat(states[0].vc_sel.`4`[3], states[0].vc_sel.`4`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(states[0].vc_sel.`4`[5], states[0].vc_sel.`4`[4]) node credit_available_hi_hi_4 = cat(states[0].vc_sel.`4`[7], states[0].vc_sel.`4`[6]) node credit_available_hi_4 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_5 = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_hi_5 = cat(_credit_available_T_4, _credit_available_T_3) node credit_available_hi_5 = cat(credit_available_hi_hi_5, _credit_available_T_2) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_6 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_6 = cat(credit_available_hi_hi_6, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_lo_6 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_6 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_7 = cat(credit_available_hi_hi_7, credit_available_hi_lo_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7) node credit_available_lo_lo_7 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_7 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_8 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_8 = cat(credit_available_hi_hi_8, credit_available_hi_lo_7) node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_lo_8 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_8 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_9 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_9 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_9 = cat(credit_available_hi_hi_9, credit_available_hi_lo_8) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9) node credit_available_lo_lo_9 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_9 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_10 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_10 = cat(credit_available_hi_hi_10, credit_available_hi_lo_9) node _credit_available_T_10 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_11 = cat(_credit_available_T_7, _credit_available_T_6) node credit_available_hi_hi_11 = cat(_credit_available_T_10, _credit_available_T_9) node credit_available_hi_11 = cat(credit_available_hi_hi_11, _credit_available_T_8) node _credit_available_T_11 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_12 = and(_credit_available_T_5, _credit_available_T_11) node credit_available = neq(_credit_available_T_12, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6] connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] connect salloc_arb.io.in[0].bits.vc_sel.`1`[3], states[0].vc_sel.`1`[3] connect salloc_arb.io.in[0].bits.vc_sel.`1`[4], states[0].vc_sel.`1`[4] connect salloc_arb.io.in[0].bits.vc_sel.`1`[5], states[0].vc_sel.`1`[5] connect salloc_arb.io.in[0].bits.vc_sel.`1`[6], states[0].vc_sel.`1`[6] connect salloc_arb.io.in[0].bits.vc_sel.`1`[7], states[0].vc_sel.`1`[7] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2] connect salloc_arb.io.in[0].bits.vc_sel.`2`[3], states[0].vc_sel.`2`[3] connect salloc_arb.io.in[0].bits.vc_sel.`2`[4], states[0].vc_sel.`2`[4] connect salloc_arb.io.in[0].bits.vc_sel.`2`[5], states[0].vc_sel.`2`[5] connect salloc_arb.io.in[0].bits.vc_sel.`2`[6], states[0].vc_sel.`2`[6] connect salloc_arb.io.in[0].bits.vc_sel.`2`[7], states[0].vc_sel.`2`[7] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1] connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2] connect salloc_arb.io.in[0].bits.vc_sel.`3`[3], states[0].vc_sel.`3`[3] connect salloc_arb.io.in[0].bits.vc_sel.`3`[4], states[0].vc_sel.`3`[4] connect salloc_arb.io.in[0].bits.vc_sel.`3`[5], states[0].vc_sel.`3`[5] connect salloc_arb.io.in[0].bits.vc_sel.`3`[6], states[0].vc_sel.`3`[6] connect salloc_arb.io.in[0].bits.vc_sel.`3`[7], states[0].vc_sel.`3`[7] connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0] connect salloc_arb.io.in[0].bits.vc_sel.`4`[1], states[0].vc_sel.`4`[1] connect salloc_arb.io.in[0].bits.vc_sel.`4`[2], states[0].vc_sel.`4`[2] connect salloc_arb.io.in[0].bits.vc_sel.`4`[3], states[0].vc_sel.`4`[3] connect salloc_arb.io.in[0].bits.vc_sel.`4`[4], states[0].vc_sel.`4`[4] connect salloc_arb.io.in[0].bits.vc_sel.`4`[5], states[0].vc_sel.`4`[5] connect salloc_arb.io.in[0].bits.vc_sel.`4`[6], states[0].vc_sel.`4`[6] connect salloc_arb.io.in[0].bits.vc_sel.`4`[7], states[0].vc_sel.`4`[7] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_103 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_104 = and(_T_103, input_buffer.io.deq[0].bits.tail) when _T_104 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_lo_10 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi_10 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_hi_12 = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) node credit_available_hi_12 = cat(credit_available_hi_hi_12, credit_available_hi_lo_10) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_lo_11 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_lo_hi_11 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) node credit_available_hi_hi_13 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) node credit_available_hi_13 = cat(credit_available_hi_hi_13, credit_available_hi_lo_11) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_lo_12 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo_hi_12 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) node credit_available_hi_hi_14 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) node credit_available_hi_14 = cat(credit_available_hi_hi_14, credit_available_hi_lo_12) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_lo_13 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) node credit_available_lo_hi_13 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4]) node credit_available_hi_hi_15 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6]) node credit_available_hi_15 = cat(credit_available_hi_hi_15, credit_available_hi_lo_13) node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15) node credit_available_lo_lo_14 = cat(states[1].vc_sel.`4`[1], states[1].vc_sel.`4`[0]) node credit_available_lo_hi_14 = cat(states[1].vc_sel.`4`[3], states[1].vc_sel.`4`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[1].vc_sel.`4`[5], states[1].vc_sel.`4`[4]) node credit_available_hi_hi_16 = cat(states[1].vc_sel.`4`[7], states[1].vc_sel.`4`[6]) node credit_available_hi_16 = cat(credit_available_hi_hi_16, credit_available_hi_lo_14) node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_17 = cat(_credit_available_T_14, _credit_available_T_13) node credit_available_hi_hi_17 = cat(_credit_available_T_17, _credit_available_T_16) node credit_available_hi_17 = cat(credit_available_hi_hi_17, _credit_available_T_15) node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_15 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_18 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_18 = cat(credit_available_hi_hi_18, credit_available_hi_lo_15) node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_16 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_19 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_19 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_19 = cat(credit_available_hi_hi_19, credit_available_hi_lo_16) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19) node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_17 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_20 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_20 = cat(credit_available_hi_hi_20, credit_available_hi_lo_17) node _credit_available_T_21 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_lo_18 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_18 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_21 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_21 = cat(credit_available_hi_hi_21, credit_available_hi_lo_18) node _credit_available_T_22 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_19 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_19 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_22 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_22 = cat(credit_available_hi_hi_22, credit_available_hi_lo_19) node _credit_available_T_23 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_23 = cat(_credit_available_T_20, _credit_available_T_19) node credit_available_hi_hi_23 = cat(_credit_available_T_23, _credit_available_T_22) node credit_available_hi_23 = cat(credit_available_hi_hi_23, _credit_available_T_21) node _credit_available_T_24 = cat(credit_available_hi_23, credit_available_lo_23) node _credit_available_T_25 = and(_credit_available_T_18, _credit_available_T_24) node credit_available_1 = neq(_credit_available_T_25, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3] connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4] connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5] connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6] connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.vc_sel.`4`[1], states[1].vc_sel.`4`[1] connect salloc_arb.io.in[1].bits.vc_sel.`4`[2], states[1].vc_sel.`4`[2] connect salloc_arb.io.in[1].bits.vc_sel.`4`[3], states[1].vc_sel.`4`[3] connect salloc_arb.io.in[1].bits.vc_sel.`4`[4], states[1].vc_sel.`4`[4] connect salloc_arb.io.in[1].bits.vc_sel.`4`[5], states[1].vc_sel.`4`[5] connect salloc_arb.io.in[1].bits.vc_sel.`4`[6], states[1].vc_sel.`4`[6] connect salloc_arb.io.in[1].bits.vc_sel.`4`[7], states[1].vc_sel.`4`[7] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_105 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_106 = and(_T_105, input_buffer.io.deq[1].bits.tail) when _T_106 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_20 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_20 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_hi_24 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) node credit_available_hi_24 = cat(credit_available_hi_hi_24, credit_available_hi_lo_20) node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_lo_21 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_21 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) node credit_available_hi_hi_25 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) node credit_available_hi_25 = cat(credit_available_hi_hi_25, credit_available_hi_lo_21) node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_22 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_22 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) node credit_available_hi_hi_26 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) node credit_available_hi_26 = cat(credit_available_hi_hi_26, credit_available_hi_lo_22) node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_lo_23 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0]) node credit_available_lo_hi_23 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4]) node credit_available_hi_hi_27 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6]) node credit_available_hi_27 = cat(credit_available_hi_hi_27, credit_available_hi_lo_23) node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27) node credit_available_lo_lo_24 = cat(states[2].vc_sel.`4`[1], states[2].vc_sel.`4`[0]) node credit_available_lo_hi_24 = cat(states[2].vc_sel.`4`[3], states[2].vc_sel.`4`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[2].vc_sel.`4`[5], states[2].vc_sel.`4`[4]) node credit_available_hi_hi_28 = cat(states[2].vc_sel.`4`[7], states[2].vc_sel.`4`[6]) node credit_available_hi_28 = cat(credit_available_hi_hi_28, credit_available_hi_lo_24) node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_29 = cat(_credit_available_T_27, _credit_available_T_26) node credit_available_hi_hi_29 = cat(_credit_available_T_30, _credit_available_T_29) node credit_available_hi_29 = cat(credit_available_hi_hi_29, _credit_available_T_28) node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29) node credit_available_lo_lo_25 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_25 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_30 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_30 = cat(credit_available_hi_hi_30, credit_available_hi_lo_25) node _credit_available_T_32 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_lo_26 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_26 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_31 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_31 = cat(credit_available_hi_hi_31, credit_available_hi_lo_26) node _credit_available_T_33 = cat(credit_available_hi_31, credit_available_lo_31) node credit_available_lo_lo_27 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_27 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_32 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_32 = cat(credit_available_hi_hi_32, credit_available_hi_lo_27) node _credit_available_T_34 = cat(credit_available_hi_32, credit_available_lo_32) node credit_available_lo_lo_28 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_28 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_33 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_33 = cat(credit_available_hi_hi_33, credit_available_hi_lo_28) node _credit_available_T_35 = cat(credit_available_hi_33, credit_available_lo_33) node credit_available_lo_lo_29 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_29 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_34 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_34 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_34 = cat(credit_available_hi_hi_34, credit_available_hi_lo_29) node _credit_available_T_36 = cat(credit_available_hi_34, credit_available_lo_34) node credit_available_lo_35 = cat(_credit_available_T_33, _credit_available_T_32) node credit_available_hi_hi_35 = cat(_credit_available_T_36, _credit_available_T_35) node credit_available_hi_35 = cat(credit_available_hi_hi_35, _credit_available_T_34) node _credit_available_T_37 = cat(credit_available_hi_35, credit_available_lo_35) node _credit_available_T_38 = and(_credit_available_T_31, _credit_available_T_37) node credit_available_2 = neq(_credit_available_T_38, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3] connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4] connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5] connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6] connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`4`[1], states[2].vc_sel.`4`[1] connect salloc_arb.io.in[2].bits.vc_sel.`4`[2], states[2].vc_sel.`4`[2] connect salloc_arb.io.in[2].bits.vc_sel.`4`[3], states[2].vc_sel.`4`[3] connect salloc_arb.io.in[2].bits.vc_sel.`4`[4], states[2].vc_sel.`4`[4] connect salloc_arb.io.in[2].bits.vc_sel.`4`[5], states[2].vc_sel.`4`[5] connect salloc_arb.io.in[2].bits.vc_sel.`4`[6], states[2].vc_sel.`4`[6] connect salloc_arb.io.in[2].bits.vc_sel.`4`[7], states[2].vc_sel.`4`[7] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_107 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_108 = and(_T_107, input_buffer.io.deq[2].bits.tail) when _T_108 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_30 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_30 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_hi_36 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) node credit_available_hi_36 = cat(credit_available_hi_hi_36, credit_available_hi_lo_30) node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36) node credit_available_lo_lo_31 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_31 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) node credit_available_hi_hi_37 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) node credit_available_hi_37 = cat(credit_available_hi_hi_37, credit_available_hi_lo_31) node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37) node credit_available_lo_lo_32 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_32 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) node credit_available_hi_hi_38 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) node credit_available_hi_38 = cat(credit_available_hi_hi_38, credit_available_hi_lo_32) node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38) node credit_available_lo_lo_33 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0]) node credit_available_lo_hi_33 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2]) node credit_available_lo_39 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4]) node credit_available_hi_hi_39 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6]) node credit_available_hi_39 = cat(credit_available_hi_hi_39, credit_available_hi_lo_33) node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39) node credit_available_lo_lo_34 = cat(states[3].vc_sel.`4`[1], states[3].vc_sel.`4`[0]) node credit_available_lo_hi_34 = cat(states[3].vc_sel.`4`[3], states[3].vc_sel.`4`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(states[3].vc_sel.`4`[5], states[3].vc_sel.`4`[4]) node credit_available_hi_hi_40 = cat(states[3].vc_sel.`4`[7], states[3].vc_sel.`4`[6]) node credit_available_hi_40 = cat(credit_available_hi_hi_40, credit_available_hi_lo_34) node _credit_available_T_43 = cat(credit_available_hi_40, credit_available_lo_40) node credit_available_lo_41 = cat(_credit_available_T_40, _credit_available_T_39) node credit_available_hi_hi_41 = cat(_credit_available_T_43, _credit_available_T_42) node credit_available_hi_41 = cat(credit_available_hi_hi_41, _credit_available_T_41) node _credit_available_T_44 = cat(credit_available_hi_41, credit_available_lo_41) node credit_available_lo_lo_35 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_35 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_42 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_42 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_42 = cat(credit_available_hi_hi_42, credit_available_hi_lo_35) node _credit_available_T_45 = cat(credit_available_hi_42, credit_available_lo_42) node credit_available_lo_lo_36 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_36 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_43 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_43 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_43 = cat(credit_available_hi_hi_43, credit_available_hi_lo_36) node _credit_available_T_46 = cat(credit_available_hi_43, credit_available_lo_43) node credit_available_lo_lo_37 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_37 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_44 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_44 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_44 = cat(credit_available_hi_hi_44, credit_available_hi_lo_37) node _credit_available_T_47 = cat(credit_available_hi_44, credit_available_lo_44) node credit_available_lo_lo_38 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_38 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_45 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_45 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_45 = cat(credit_available_hi_hi_45, credit_available_hi_lo_38) node _credit_available_T_48 = cat(credit_available_hi_45, credit_available_lo_45) node credit_available_lo_lo_39 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_39 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_46 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_46 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_46 = cat(credit_available_hi_hi_46, credit_available_hi_lo_39) node _credit_available_T_49 = cat(credit_available_hi_46, credit_available_lo_46) node credit_available_lo_47 = cat(_credit_available_T_46, _credit_available_T_45) node credit_available_hi_hi_47 = cat(_credit_available_T_49, _credit_available_T_48) node credit_available_hi_47 = cat(credit_available_hi_hi_47, _credit_available_T_47) node _credit_available_T_50 = cat(credit_available_hi_47, credit_available_lo_47) node _credit_available_T_51 = and(_credit_available_T_44, _credit_available_T_50) node credit_available_3 = neq(_credit_available_T_51, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1] connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2] connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3] connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4] connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5] connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6] connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7] connect salloc_arb.io.in[3].bits.vc_sel.`4`[0], states[3].vc_sel.`4`[0] connect salloc_arb.io.in[3].bits.vc_sel.`4`[1], states[3].vc_sel.`4`[1] connect salloc_arb.io.in[3].bits.vc_sel.`4`[2], states[3].vc_sel.`4`[2] connect salloc_arb.io.in[3].bits.vc_sel.`4`[3], states[3].vc_sel.`4`[3] connect salloc_arb.io.in[3].bits.vc_sel.`4`[4], states[3].vc_sel.`4`[4] connect salloc_arb.io.in[3].bits.vc_sel.`4`[5], states[3].vc_sel.`4`[5] connect salloc_arb.io.in[3].bits.vc_sel.`4`[6], states[3].vc_sel.`4`[6] connect salloc_arb.io.in[3].bits.vc_sel.`4`[7], states[3].vc_sel.`4`[7] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_109 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_110 = and(_T_109, input_buffer.io.deq[3].bits.tail) when _T_110 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_40 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_40 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) node credit_available_lo_48 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_hi_48 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) node credit_available_hi_48 = cat(credit_available_hi_hi_48, credit_available_hi_lo_40) node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48) node credit_available_lo_lo_41 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_41 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) node credit_available_lo_49 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) node credit_available_hi_hi_49 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) node credit_available_hi_49 = cat(credit_available_hi_hi_49, credit_available_hi_lo_41) node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49) node credit_available_lo_lo_42 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_42 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) node credit_available_lo_50 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) node credit_available_hi_lo_42 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) node credit_available_hi_hi_50 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) node credit_available_hi_50 = cat(credit_available_hi_hi_50, credit_available_hi_lo_42) node _credit_available_T_54 = cat(credit_available_hi_50, credit_available_lo_50) node credit_available_lo_lo_43 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0]) node credit_available_lo_hi_43 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2]) node credit_available_lo_51 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) node credit_available_hi_lo_43 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4]) node credit_available_hi_hi_51 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6]) node credit_available_hi_51 = cat(credit_available_hi_hi_51, credit_available_hi_lo_43) node _credit_available_T_55 = cat(credit_available_hi_51, credit_available_lo_51) node credit_available_lo_lo_44 = cat(states[4].vc_sel.`4`[1], states[4].vc_sel.`4`[0]) node credit_available_lo_hi_44 = cat(states[4].vc_sel.`4`[3], states[4].vc_sel.`4`[2]) node credit_available_lo_52 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) node credit_available_hi_lo_44 = cat(states[4].vc_sel.`4`[5], states[4].vc_sel.`4`[4]) node credit_available_hi_hi_52 = cat(states[4].vc_sel.`4`[7], states[4].vc_sel.`4`[6]) node credit_available_hi_52 = cat(credit_available_hi_hi_52, credit_available_hi_lo_44) node _credit_available_T_56 = cat(credit_available_hi_52, credit_available_lo_52) node credit_available_lo_53 = cat(_credit_available_T_53, _credit_available_T_52) node credit_available_hi_hi_53 = cat(_credit_available_T_56, _credit_available_T_55) node credit_available_hi_53 = cat(credit_available_hi_hi_53, _credit_available_T_54) node _credit_available_T_57 = cat(credit_available_hi_53, credit_available_lo_53) node credit_available_lo_lo_45 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_45 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_54 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) node credit_available_hi_lo_45 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_54 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_54 = cat(credit_available_hi_hi_54, credit_available_hi_lo_45) node _credit_available_T_58 = cat(credit_available_hi_54, credit_available_lo_54) node credit_available_lo_lo_46 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_46 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_55 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) node credit_available_hi_lo_46 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_55 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_55 = cat(credit_available_hi_hi_55, credit_available_hi_lo_46) node _credit_available_T_59 = cat(credit_available_hi_55, credit_available_lo_55) node credit_available_lo_lo_47 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_47 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_56 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) node credit_available_hi_lo_47 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_56 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_56 = cat(credit_available_hi_hi_56, credit_available_hi_lo_47) node _credit_available_T_60 = cat(credit_available_hi_56, credit_available_lo_56) node credit_available_lo_lo_48 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_48 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_57 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48) node credit_available_hi_lo_48 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_57 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_57 = cat(credit_available_hi_hi_57, credit_available_hi_lo_48) node _credit_available_T_61 = cat(credit_available_hi_57, credit_available_lo_57) node credit_available_lo_lo_49 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_49 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_58 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49) node credit_available_hi_lo_49 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_58 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_58 = cat(credit_available_hi_hi_58, credit_available_hi_lo_49) node _credit_available_T_62 = cat(credit_available_hi_58, credit_available_lo_58) node credit_available_lo_59 = cat(_credit_available_T_59, _credit_available_T_58) node credit_available_hi_hi_59 = cat(_credit_available_T_62, _credit_available_T_61) node credit_available_hi_59 = cat(credit_available_hi_hi_59, _credit_available_T_60) node _credit_available_T_63 = cat(credit_available_hi_59, credit_available_lo_59) node _credit_available_T_64 = and(_credit_available_T_57, _credit_available_T_63) node credit_available_4 = neq(_credit_available_T_64, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1] connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2] connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3] connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4] connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5] connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6] connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7] connect salloc_arb.io.in[4].bits.vc_sel.`4`[0], states[4].vc_sel.`4`[0] connect salloc_arb.io.in[4].bits.vc_sel.`4`[1], states[4].vc_sel.`4`[1] connect salloc_arb.io.in[4].bits.vc_sel.`4`[2], states[4].vc_sel.`4`[2] connect salloc_arb.io.in[4].bits.vc_sel.`4`[3], states[4].vc_sel.`4`[3] connect salloc_arb.io.in[4].bits.vc_sel.`4`[4], states[4].vc_sel.`4`[4] connect salloc_arb.io.in[4].bits.vc_sel.`4`[5], states[4].vc_sel.`4`[5] connect salloc_arb.io.in[4].bits.vc_sel.`4`[6], states[4].vc_sel.`4`[6] connect salloc_arb.io.in[4].bits.vc_sel.`4`[7], states[4].vc_sel.`4`[7] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_111 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_112 = and(_T_111, input_buffer.io.deq[4].bits.tail) when _T_112 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_50 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_50 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) node credit_available_lo_60 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50) node credit_available_hi_lo_50 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_hi_60 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) node credit_available_hi_60 = cat(credit_available_hi_hi_60, credit_available_hi_lo_50) node _credit_available_T_65 = cat(credit_available_hi_60, credit_available_lo_60) node credit_available_lo_lo_51 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_51 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) node credit_available_lo_61 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51) node credit_available_hi_lo_51 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) node credit_available_hi_hi_61 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) node credit_available_hi_61 = cat(credit_available_hi_hi_61, credit_available_hi_lo_51) node _credit_available_T_66 = cat(credit_available_hi_61, credit_available_lo_61) node credit_available_lo_lo_52 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_52 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) node credit_available_lo_62 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52) node credit_available_hi_lo_52 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) node credit_available_hi_hi_62 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) node credit_available_hi_62 = cat(credit_available_hi_hi_62, credit_available_hi_lo_52) node _credit_available_T_67 = cat(credit_available_hi_62, credit_available_lo_62) node credit_available_lo_lo_53 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0]) node credit_available_lo_hi_53 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2]) node credit_available_lo_63 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53) node credit_available_hi_lo_53 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4]) node credit_available_hi_hi_63 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6]) node credit_available_hi_63 = cat(credit_available_hi_hi_63, credit_available_hi_lo_53) node _credit_available_T_68 = cat(credit_available_hi_63, credit_available_lo_63) node credit_available_lo_lo_54 = cat(states[5].vc_sel.`4`[1], states[5].vc_sel.`4`[0]) node credit_available_lo_hi_54 = cat(states[5].vc_sel.`4`[3], states[5].vc_sel.`4`[2]) node credit_available_lo_64 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54) node credit_available_hi_lo_54 = cat(states[5].vc_sel.`4`[5], states[5].vc_sel.`4`[4]) node credit_available_hi_hi_64 = cat(states[5].vc_sel.`4`[7], states[5].vc_sel.`4`[6]) node credit_available_hi_64 = cat(credit_available_hi_hi_64, credit_available_hi_lo_54) node _credit_available_T_69 = cat(credit_available_hi_64, credit_available_lo_64) node credit_available_lo_65 = cat(_credit_available_T_66, _credit_available_T_65) node credit_available_hi_hi_65 = cat(_credit_available_T_69, _credit_available_T_68) node credit_available_hi_65 = cat(credit_available_hi_hi_65, _credit_available_T_67) node _credit_available_T_70 = cat(credit_available_hi_65, credit_available_lo_65) node credit_available_lo_lo_55 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_55 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_66 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55) node credit_available_hi_lo_55 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_66 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_66 = cat(credit_available_hi_hi_66, credit_available_hi_lo_55) node _credit_available_T_71 = cat(credit_available_hi_66, credit_available_lo_66) node credit_available_lo_lo_56 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_56 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_67 = cat(credit_available_lo_hi_56, credit_available_lo_lo_56) node credit_available_hi_lo_56 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_67 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_67 = cat(credit_available_hi_hi_67, credit_available_hi_lo_56) node _credit_available_T_72 = cat(credit_available_hi_67, credit_available_lo_67) node credit_available_lo_lo_57 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_57 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_68 = cat(credit_available_lo_hi_57, credit_available_lo_lo_57) node credit_available_hi_lo_57 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_68 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_68 = cat(credit_available_hi_hi_68, credit_available_hi_lo_57) node _credit_available_T_73 = cat(credit_available_hi_68, credit_available_lo_68) node credit_available_lo_lo_58 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_58 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_69 = cat(credit_available_lo_hi_58, credit_available_lo_lo_58) node credit_available_hi_lo_58 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_69 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_69 = cat(credit_available_hi_hi_69, credit_available_hi_lo_58) node _credit_available_T_74 = cat(credit_available_hi_69, credit_available_lo_69) node credit_available_lo_lo_59 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_59 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_70 = cat(credit_available_lo_hi_59, credit_available_lo_lo_59) node credit_available_hi_lo_59 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_70 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_70 = cat(credit_available_hi_hi_70, credit_available_hi_lo_59) node _credit_available_T_75 = cat(credit_available_hi_70, credit_available_lo_70) node credit_available_lo_71 = cat(_credit_available_T_72, _credit_available_T_71) node credit_available_hi_hi_71 = cat(_credit_available_T_75, _credit_available_T_74) node credit_available_hi_71 = cat(credit_available_hi_hi_71, _credit_available_T_73) node _credit_available_T_76 = cat(credit_available_hi_71, credit_available_lo_71) node _credit_available_T_77 = and(_credit_available_T_70, _credit_available_T_76) node credit_available_5 = neq(_credit_available_T_77, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1] connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2] connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3] connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4] connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5] connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6] connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7] connect salloc_arb.io.in[5].bits.vc_sel.`4`[0], states[5].vc_sel.`4`[0] connect salloc_arb.io.in[5].bits.vc_sel.`4`[1], states[5].vc_sel.`4`[1] connect salloc_arb.io.in[5].bits.vc_sel.`4`[2], states[5].vc_sel.`4`[2] connect salloc_arb.io.in[5].bits.vc_sel.`4`[3], states[5].vc_sel.`4`[3] connect salloc_arb.io.in[5].bits.vc_sel.`4`[4], states[5].vc_sel.`4`[4] connect salloc_arb.io.in[5].bits.vc_sel.`4`[5], states[5].vc_sel.`4`[5] connect salloc_arb.io.in[5].bits.vc_sel.`4`[6], states[5].vc_sel.`4`[6] connect salloc_arb.io.in[5].bits.vc_sel.`4`[7], states[5].vc_sel.`4`[7] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_113 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_114 = and(_T_113, input_buffer.io.deq[5].bits.tail) when _T_114 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_60 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_60 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) node credit_available_lo_72 = cat(credit_available_lo_hi_60, credit_available_lo_lo_60) node credit_available_hi_lo_60 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) node credit_available_hi_hi_72 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) node credit_available_hi_72 = cat(credit_available_hi_hi_72, credit_available_hi_lo_60) node _credit_available_T_78 = cat(credit_available_hi_72, credit_available_lo_72) node credit_available_lo_lo_61 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_61 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) node credit_available_lo_73 = cat(credit_available_lo_hi_61, credit_available_lo_lo_61) node credit_available_hi_lo_61 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) node credit_available_hi_hi_73 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) node credit_available_hi_73 = cat(credit_available_hi_hi_73, credit_available_hi_lo_61) node _credit_available_T_79 = cat(credit_available_hi_73, credit_available_lo_73) node credit_available_lo_lo_62 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_62 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) node credit_available_lo_74 = cat(credit_available_lo_hi_62, credit_available_lo_lo_62) node credit_available_hi_lo_62 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) node credit_available_hi_hi_74 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) node credit_available_hi_74 = cat(credit_available_hi_hi_74, credit_available_hi_lo_62) node _credit_available_T_80 = cat(credit_available_hi_74, credit_available_lo_74) node credit_available_lo_lo_63 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0]) node credit_available_lo_hi_63 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2]) node credit_available_lo_75 = cat(credit_available_lo_hi_63, credit_available_lo_lo_63) node credit_available_hi_lo_63 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4]) node credit_available_hi_hi_75 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6]) node credit_available_hi_75 = cat(credit_available_hi_hi_75, credit_available_hi_lo_63) node _credit_available_T_81 = cat(credit_available_hi_75, credit_available_lo_75) node credit_available_lo_lo_64 = cat(states[6].vc_sel.`4`[1], states[6].vc_sel.`4`[0]) node credit_available_lo_hi_64 = cat(states[6].vc_sel.`4`[3], states[6].vc_sel.`4`[2]) node credit_available_lo_76 = cat(credit_available_lo_hi_64, credit_available_lo_lo_64) node credit_available_hi_lo_64 = cat(states[6].vc_sel.`4`[5], states[6].vc_sel.`4`[4]) node credit_available_hi_hi_76 = cat(states[6].vc_sel.`4`[7], states[6].vc_sel.`4`[6]) node credit_available_hi_76 = cat(credit_available_hi_hi_76, credit_available_hi_lo_64) node _credit_available_T_82 = cat(credit_available_hi_76, credit_available_lo_76) node credit_available_lo_77 = cat(_credit_available_T_79, _credit_available_T_78) node credit_available_hi_hi_77 = cat(_credit_available_T_82, _credit_available_T_81) node credit_available_hi_77 = cat(credit_available_hi_hi_77, _credit_available_T_80) node _credit_available_T_83 = cat(credit_available_hi_77, credit_available_lo_77) node credit_available_lo_lo_65 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_65 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_78 = cat(credit_available_lo_hi_65, credit_available_lo_lo_65) node credit_available_hi_lo_65 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_78 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_78 = cat(credit_available_hi_hi_78, credit_available_hi_lo_65) node _credit_available_T_84 = cat(credit_available_hi_78, credit_available_lo_78) node credit_available_lo_lo_66 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_66 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_79 = cat(credit_available_lo_hi_66, credit_available_lo_lo_66) node credit_available_hi_lo_66 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_79 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_79 = cat(credit_available_hi_hi_79, credit_available_hi_lo_66) node _credit_available_T_85 = cat(credit_available_hi_79, credit_available_lo_79) node credit_available_lo_lo_67 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_67 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_80 = cat(credit_available_lo_hi_67, credit_available_lo_lo_67) node credit_available_hi_lo_67 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_80 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_80 = cat(credit_available_hi_hi_80, credit_available_hi_lo_67) node _credit_available_T_86 = cat(credit_available_hi_80, credit_available_lo_80) node credit_available_lo_lo_68 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_68 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_81 = cat(credit_available_lo_hi_68, credit_available_lo_lo_68) node credit_available_hi_lo_68 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_81 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_81 = cat(credit_available_hi_hi_81, credit_available_hi_lo_68) node _credit_available_T_87 = cat(credit_available_hi_81, credit_available_lo_81) node credit_available_lo_lo_69 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_69 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_82 = cat(credit_available_lo_hi_69, credit_available_lo_lo_69) node credit_available_hi_lo_69 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_82 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_82 = cat(credit_available_hi_hi_82, credit_available_hi_lo_69) node _credit_available_T_88 = cat(credit_available_hi_82, credit_available_lo_82) node credit_available_lo_83 = cat(_credit_available_T_85, _credit_available_T_84) node credit_available_hi_hi_83 = cat(_credit_available_T_88, _credit_available_T_87) node credit_available_hi_83 = cat(credit_available_hi_hi_83, _credit_available_T_86) node _credit_available_T_89 = cat(credit_available_hi_83, credit_available_lo_83) node _credit_available_T_90 = and(_credit_available_T_83, _credit_available_T_89) node credit_available_6 = neq(_credit_available_T_90, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_6) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0] connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1] connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2] connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3] connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4] connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5] connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6] connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7] connect salloc_arb.io.in[6].bits.vc_sel.`4`[0], states[6].vc_sel.`4`[0] connect salloc_arb.io.in[6].bits.vc_sel.`4`[1], states[6].vc_sel.`4`[1] connect salloc_arb.io.in[6].bits.vc_sel.`4`[2], states[6].vc_sel.`4`[2] connect salloc_arb.io.in[6].bits.vc_sel.`4`[3], states[6].vc_sel.`4`[3] connect salloc_arb.io.in[6].bits.vc_sel.`4`[4], states[6].vc_sel.`4`[4] connect salloc_arb.io.in[6].bits.vc_sel.`4`[5], states[6].vc_sel.`4`[5] connect salloc_arb.io.in[6].bits.vc_sel.`4`[6], states[6].vc_sel.`4`[6] connect salloc_arb.io.in[6].bits.vc_sel.`4`[7], states[6].vc_sel.`4`[7] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_115 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_116 = and(_T_115, input_buffer.io.deq[6].bits.tail) when _T_116 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_70 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_70 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) node credit_available_lo_84 = cat(credit_available_lo_hi_70, credit_available_lo_lo_70) node credit_available_hi_lo_70 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) node credit_available_hi_hi_84 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) node credit_available_hi_84 = cat(credit_available_hi_hi_84, credit_available_hi_lo_70) node _credit_available_T_91 = cat(credit_available_hi_84, credit_available_lo_84) node credit_available_lo_lo_71 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_71 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) node credit_available_lo_85 = cat(credit_available_lo_hi_71, credit_available_lo_lo_71) node credit_available_hi_lo_71 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) node credit_available_hi_hi_85 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) node credit_available_hi_85 = cat(credit_available_hi_hi_85, credit_available_hi_lo_71) node _credit_available_T_92 = cat(credit_available_hi_85, credit_available_lo_85) node credit_available_lo_lo_72 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_72 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) node credit_available_lo_86 = cat(credit_available_lo_hi_72, credit_available_lo_lo_72) node credit_available_hi_lo_72 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) node credit_available_hi_hi_86 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) node credit_available_hi_86 = cat(credit_available_hi_hi_86, credit_available_hi_lo_72) node _credit_available_T_93 = cat(credit_available_hi_86, credit_available_lo_86) node credit_available_lo_lo_73 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0]) node credit_available_lo_hi_73 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2]) node credit_available_lo_87 = cat(credit_available_lo_hi_73, credit_available_lo_lo_73) node credit_available_hi_lo_73 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4]) node credit_available_hi_hi_87 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6]) node credit_available_hi_87 = cat(credit_available_hi_hi_87, credit_available_hi_lo_73) node _credit_available_T_94 = cat(credit_available_hi_87, credit_available_lo_87) node credit_available_lo_lo_74 = cat(states[7].vc_sel.`4`[1], states[7].vc_sel.`4`[0]) node credit_available_lo_hi_74 = cat(states[7].vc_sel.`4`[3], states[7].vc_sel.`4`[2]) node credit_available_lo_88 = cat(credit_available_lo_hi_74, credit_available_lo_lo_74) node credit_available_hi_lo_74 = cat(states[7].vc_sel.`4`[5], states[7].vc_sel.`4`[4]) node credit_available_hi_hi_88 = cat(states[7].vc_sel.`4`[7], states[7].vc_sel.`4`[6]) node credit_available_hi_88 = cat(credit_available_hi_hi_88, credit_available_hi_lo_74) node _credit_available_T_95 = cat(credit_available_hi_88, credit_available_lo_88) node credit_available_lo_89 = cat(_credit_available_T_92, _credit_available_T_91) node credit_available_hi_hi_89 = cat(_credit_available_T_95, _credit_available_T_94) node credit_available_hi_89 = cat(credit_available_hi_hi_89, _credit_available_T_93) node _credit_available_T_96 = cat(credit_available_hi_89, credit_available_lo_89) node credit_available_lo_lo_75 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_75 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_90 = cat(credit_available_lo_hi_75, credit_available_lo_lo_75) node credit_available_hi_lo_75 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_90 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_90 = cat(credit_available_hi_hi_90, credit_available_hi_lo_75) node _credit_available_T_97 = cat(credit_available_hi_90, credit_available_lo_90) node credit_available_lo_lo_76 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_76 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_91 = cat(credit_available_lo_hi_76, credit_available_lo_lo_76) node credit_available_hi_lo_76 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_91 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_91 = cat(credit_available_hi_hi_91, credit_available_hi_lo_76) node _credit_available_T_98 = cat(credit_available_hi_91, credit_available_lo_91) node credit_available_lo_lo_77 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_77 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_92 = cat(credit_available_lo_hi_77, credit_available_lo_lo_77) node credit_available_hi_lo_77 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_92 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_92 = cat(credit_available_hi_hi_92, credit_available_hi_lo_77) node _credit_available_T_99 = cat(credit_available_hi_92, credit_available_lo_92) node credit_available_lo_lo_78 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_78 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_93 = cat(credit_available_lo_hi_78, credit_available_lo_lo_78) node credit_available_hi_lo_78 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_93 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_93 = cat(credit_available_hi_hi_93, credit_available_hi_lo_78) node _credit_available_T_100 = cat(credit_available_hi_93, credit_available_lo_93) node credit_available_lo_lo_79 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_79 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_94 = cat(credit_available_lo_hi_79, credit_available_lo_lo_79) node credit_available_hi_lo_79 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_94 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_94 = cat(credit_available_hi_hi_94, credit_available_hi_lo_79) node _credit_available_T_101 = cat(credit_available_hi_94, credit_available_lo_94) node credit_available_lo_95 = cat(_credit_available_T_98, _credit_available_T_97) node credit_available_hi_hi_95 = cat(_credit_available_T_101, _credit_available_T_100) node credit_available_hi_95 = cat(credit_available_hi_hi_95, _credit_available_T_99) node _credit_available_T_102 = cat(credit_available_hi_95, credit_available_lo_95) node _credit_available_T_103 = and(_credit_available_T_96, _credit_available_T_102) node credit_available_7 = neq(_credit_available_T_103, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_7) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1] connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2] connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3] connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4] connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5] connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6] connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7] connect salloc_arb.io.in[7].bits.vc_sel.`4`[0], states[7].vc_sel.`4`[0] connect salloc_arb.io.in[7].bits.vc_sel.`4`[1], states[7].vc_sel.`4`[1] connect salloc_arb.io.in[7].bits.vc_sel.`4`[2], states[7].vc_sel.`4`[2] connect salloc_arb.io.in[7].bits.vc_sel.`4`[3], states[7].vc_sel.`4`[3] connect salloc_arb.io.in[7].bits.vc_sel.`4`[4], states[7].vc_sel.`4`[4] connect salloc_arb.io.in[7].bits.vc_sel.`4`[5], states[7].vc_sel.`4`[5] connect salloc_arb.io.in[7].bits.vc_sel.`4`[6], states[7].vc_sel.`4`[6] connect salloc_arb.io.in[7].bits.vc_sel.`4`[7], states[7].vc_sel.`4`[7] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_117 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_118 = and(_T_117, input_buffer.io.deq[7].bits.tail) when _T_118 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_29 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_25 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _vc_sel_WIRE : UInt<1>[8] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_22 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_37 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_52 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_67 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_82 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_97 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_112 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_127 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_9 : UInt<1>[8] node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_142 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_157 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_172 connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_187 connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_202 connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_217 connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_232 connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_247 connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 connect vc_sel.`1`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_18 : UInt<1>[8] node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_262 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_277 connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_292 connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) wire _vc_sel_WIRE_22 : UInt<1> connect _vc_sel_WIRE_22, _vc_sel_T_307 connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_322 connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_337 connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_352 connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_367 connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 connect vc_sel.`2`, _vc_sel_WIRE_18 wire _vc_sel_WIRE_27 : UInt<1>[8] node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369) node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370) node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371) node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372) node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373) node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_382 connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28 node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384) node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385) node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386) node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387) node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388) node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389) node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_397 connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29 node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401) node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402) node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403) node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404) node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_412 connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30 node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_427 connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430) node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_442 connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32 node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444) node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445) node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446) node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447) node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448) node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449) node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450) wire _vc_sel_WIRE_33 : UInt<1> connect _vc_sel_WIRE_33, _vc_sel_T_457 connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33 node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459) node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460) node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461) node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462) node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463) node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464) node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465) wire _vc_sel_WIRE_34 : UInt<1> connect _vc_sel_WIRE_34, _vc_sel_T_472 connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34 node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477) node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478) node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479) node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480) wire _vc_sel_WIRE_35 : UInt<1> connect _vc_sel_WIRE_35, _vc_sel_T_487 connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35 connect vc_sel.`3`, _vc_sel_WIRE_27 wire _vc_sel_WIRE_36 : UInt<1>[8] node _vc_sel_T_488 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_489 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_490 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_491 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_492 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_493 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_494 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_495 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_496 = or(_vc_sel_T_488, _vc_sel_T_489) node _vc_sel_T_497 = or(_vc_sel_T_496, _vc_sel_T_490) node _vc_sel_T_498 = or(_vc_sel_T_497, _vc_sel_T_491) node _vc_sel_T_499 = or(_vc_sel_T_498, _vc_sel_T_492) node _vc_sel_T_500 = or(_vc_sel_T_499, _vc_sel_T_493) node _vc_sel_T_501 = or(_vc_sel_T_500, _vc_sel_T_494) node _vc_sel_T_502 = or(_vc_sel_T_501, _vc_sel_T_495) wire _vc_sel_WIRE_37 : UInt<1> connect _vc_sel_WIRE_37, _vc_sel_T_502 connect _vc_sel_WIRE_36[0], _vc_sel_WIRE_37 node _vc_sel_T_503 = mux(_vc_sel_T, states[0].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_504 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_505 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_506 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_507 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_508 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_509 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_510 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_511 = or(_vc_sel_T_503, _vc_sel_T_504) node _vc_sel_T_512 = or(_vc_sel_T_511, _vc_sel_T_505) node _vc_sel_T_513 = or(_vc_sel_T_512, _vc_sel_T_506) node _vc_sel_T_514 = or(_vc_sel_T_513, _vc_sel_T_507) node _vc_sel_T_515 = or(_vc_sel_T_514, _vc_sel_T_508) node _vc_sel_T_516 = or(_vc_sel_T_515, _vc_sel_T_509) node _vc_sel_T_517 = or(_vc_sel_T_516, _vc_sel_T_510) wire _vc_sel_WIRE_38 : UInt<1> connect _vc_sel_WIRE_38, _vc_sel_T_517 connect _vc_sel_WIRE_36[1], _vc_sel_WIRE_38 node _vc_sel_T_518 = mux(_vc_sel_T, states[0].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_519 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_520 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_521 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_522 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_523 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_524 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_525 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_526 = or(_vc_sel_T_518, _vc_sel_T_519) node _vc_sel_T_527 = or(_vc_sel_T_526, _vc_sel_T_520) node _vc_sel_T_528 = or(_vc_sel_T_527, _vc_sel_T_521) node _vc_sel_T_529 = or(_vc_sel_T_528, _vc_sel_T_522) node _vc_sel_T_530 = or(_vc_sel_T_529, _vc_sel_T_523) node _vc_sel_T_531 = or(_vc_sel_T_530, _vc_sel_T_524) node _vc_sel_T_532 = or(_vc_sel_T_531, _vc_sel_T_525) wire _vc_sel_WIRE_39 : UInt<1> connect _vc_sel_WIRE_39, _vc_sel_T_532 connect _vc_sel_WIRE_36[2], _vc_sel_WIRE_39 node _vc_sel_T_533 = mux(_vc_sel_T, states[0].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_534 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_535 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_536 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_537 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_538 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_539 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_540 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_541 = or(_vc_sel_T_533, _vc_sel_T_534) node _vc_sel_T_542 = or(_vc_sel_T_541, _vc_sel_T_535) node _vc_sel_T_543 = or(_vc_sel_T_542, _vc_sel_T_536) node _vc_sel_T_544 = or(_vc_sel_T_543, _vc_sel_T_537) node _vc_sel_T_545 = or(_vc_sel_T_544, _vc_sel_T_538) node _vc_sel_T_546 = or(_vc_sel_T_545, _vc_sel_T_539) node _vc_sel_T_547 = or(_vc_sel_T_546, _vc_sel_T_540) wire _vc_sel_WIRE_40 : UInt<1> connect _vc_sel_WIRE_40, _vc_sel_T_547 connect _vc_sel_WIRE_36[3], _vc_sel_WIRE_40 node _vc_sel_T_548 = mux(_vc_sel_T, states[0].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_549 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_550 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_551 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_552 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_553 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_554 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_555 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_556 = or(_vc_sel_T_548, _vc_sel_T_549) node _vc_sel_T_557 = or(_vc_sel_T_556, _vc_sel_T_550) node _vc_sel_T_558 = or(_vc_sel_T_557, _vc_sel_T_551) node _vc_sel_T_559 = or(_vc_sel_T_558, _vc_sel_T_552) node _vc_sel_T_560 = or(_vc_sel_T_559, _vc_sel_T_553) node _vc_sel_T_561 = or(_vc_sel_T_560, _vc_sel_T_554) node _vc_sel_T_562 = or(_vc_sel_T_561, _vc_sel_T_555) wire _vc_sel_WIRE_41 : UInt<1> connect _vc_sel_WIRE_41, _vc_sel_T_562 connect _vc_sel_WIRE_36[4], _vc_sel_WIRE_41 node _vc_sel_T_563 = mux(_vc_sel_T, states[0].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_564 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_565 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_566 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_567 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_568 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_569 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_570 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_571 = or(_vc_sel_T_563, _vc_sel_T_564) node _vc_sel_T_572 = or(_vc_sel_T_571, _vc_sel_T_565) node _vc_sel_T_573 = or(_vc_sel_T_572, _vc_sel_T_566) node _vc_sel_T_574 = or(_vc_sel_T_573, _vc_sel_T_567) node _vc_sel_T_575 = or(_vc_sel_T_574, _vc_sel_T_568) node _vc_sel_T_576 = or(_vc_sel_T_575, _vc_sel_T_569) node _vc_sel_T_577 = or(_vc_sel_T_576, _vc_sel_T_570) wire _vc_sel_WIRE_42 : UInt<1> connect _vc_sel_WIRE_42, _vc_sel_T_577 connect _vc_sel_WIRE_36[5], _vc_sel_WIRE_42 node _vc_sel_T_578 = mux(_vc_sel_T, states[0].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_579 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_580 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_581 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_582 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_583 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_584 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_585 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_586 = or(_vc_sel_T_578, _vc_sel_T_579) node _vc_sel_T_587 = or(_vc_sel_T_586, _vc_sel_T_580) node _vc_sel_T_588 = or(_vc_sel_T_587, _vc_sel_T_581) node _vc_sel_T_589 = or(_vc_sel_T_588, _vc_sel_T_582) node _vc_sel_T_590 = or(_vc_sel_T_589, _vc_sel_T_583) node _vc_sel_T_591 = or(_vc_sel_T_590, _vc_sel_T_584) node _vc_sel_T_592 = or(_vc_sel_T_591, _vc_sel_T_585) wire _vc_sel_WIRE_43 : UInt<1> connect _vc_sel_WIRE_43, _vc_sel_T_592 connect _vc_sel_WIRE_36[6], _vc_sel_WIRE_43 node _vc_sel_T_593 = mux(_vc_sel_T, states[0].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_594 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_595 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_596 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_597 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_598 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_599 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_600 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_601 = or(_vc_sel_T_593, _vc_sel_T_594) node _vc_sel_T_602 = or(_vc_sel_T_601, _vc_sel_T_595) node _vc_sel_T_603 = or(_vc_sel_T_602, _vc_sel_T_596) node _vc_sel_T_604 = or(_vc_sel_T_603, _vc_sel_T_597) node _vc_sel_T_605 = or(_vc_sel_T_604, _vc_sel_T_598) node _vc_sel_T_606 = or(_vc_sel_T_605, _vc_sel_T_599) node _vc_sel_T_607 = or(_vc_sel_T_606, _vc_sel_T_600) wire _vc_sel_WIRE_44 : UInt<1> connect _vc_sel_WIRE_44, _vc_sel_T_607 connect _vc_sel_WIRE_36[7], _vc_sel_WIRE_44 connect vc_sel.`4`, _vc_sel_WIRE_36 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6]) node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7]) node _channel_oh_T_24 = or(vc_sel.`4`[0], vc_sel.`4`[1]) node _channel_oh_T_25 = or(_channel_oh_T_24, vc_sel.`4`[2]) node _channel_oh_T_26 = or(_channel_oh_T_25, vc_sel.`4`[3]) node _channel_oh_T_27 = or(_channel_oh_T_26, vc_sel.`4`[4]) node _channel_oh_T_28 = or(_channel_oh_T_27, vc_sel.`4`[5]) node _channel_oh_T_29 = or(_channel_oh_T_28, vc_sel.`4`[6]) node channel_oh_4 = or(_channel_oh_T_29, vc_sel.`4`[7]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2]) node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3) node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4]) node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6]) node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3) node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node virt_channel_lo_lo_4 = cat(vc_sel.`4`[1], vc_sel.`4`[0]) node virt_channel_lo_hi_4 = cat(vc_sel.`4`[3], vc_sel.`4`[2]) node virt_channel_lo_12 = cat(virt_channel_lo_hi_4, virt_channel_lo_lo_4) node virt_channel_hi_lo_4 = cat(vc_sel.`4`[5], vc_sel.`4`[4]) node virt_channel_hi_hi_4 = cat(vc_sel.`4`[7], vc_sel.`4`[6]) node virt_channel_hi_12 = cat(virt_channel_hi_hi_4, virt_channel_hi_lo_4) node _virt_channel_T_32 = cat(virt_channel_hi_12, virt_channel_lo_12) node virt_channel_hi_13 = bits(_virt_channel_T_32, 7, 4) node virt_channel_lo_13 = bits(_virt_channel_T_32, 3, 0) node _virt_channel_T_33 = orr(virt_channel_hi_13) node _virt_channel_T_34 = or(virt_channel_hi_13, virt_channel_lo_13) node virt_channel_hi_14 = bits(_virt_channel_T_34, 3, 2) node virt_channel_lo_14 = bits(_virt_channel_T_34, 1, 0) node _virt_channel_T_35 = orr(virt_channel_hi_14) node _virt_channel_T_36 = or(virt_channel_hi_14, virt_channel_lo_14) node _virt_channel_T_37 = bits(_virt_channel_T_36, 1, 1) node _virt_channel_T_38 = cat(_virt_channel_T_35, _virt_channel_T_37) node _virt_channel_T_39 = cat(_virt_channel_T_33, _virt_channel_T_38) node _virt_channel_T_40 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_41 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_42 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_43 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0)) node _virt_channel_T_44 = mux(channel_oh_4, _virt_channel_T_39, UInt<1>(0h0)) node _virt_channel_T_45 = or(_virt_channel_T_40, _virt_channel_T_41) node _virt_channel_T_46 = or(_virt_channel_T_45, _virt_channel_T_42) node _virt_channel_T_47 = or(_virt_channel_T_46, _virt_channel_T_43) node _virt_channel_T_48 = or(_virt_channel_T_47, _virt_channel_T_44) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_48 node _T_119 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_119 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`1`[0], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[2], UInt<1>(0h0) connect states[0].vc_sel.`1`[3], UInt<1>(0h0) connect states[0].vc_sel.`1`[4], UInt<1>(0h0) connect states[0].vc_sel.`1`[5], UInt<1>(0h0) connect states[0].vc_sel.`1`[6], UInt<1>(0h0) connect states[0].vc_sel.`1`[7], UInt<1>(0h0) connect states[0].vc_sel.`2`[0], UInt<1>(0h0) connect states[0].vc_sel.`2`[1], UInt<1>(0h0) connect states[0].vc_sel.`2`[2], UInt<1>(0h0) connect states[0].vc_sel.`2`[3], UInt<1>(0h0) connect states[0].vc_sel.`2`[4], UInt<1>(0h0) connect states[0].vc_sel.`2`[5], UInt<1>(0h0) connect states[0].vc_sel.`2`[6], UInt<1>(0h0) connect states[0].vc_sel.`2`[7], UInt<1>(0h0) connect states[0].vc_sel.`3`[1], UInt<1>(0h0) connect states[0].vc_sel.`3`[2], UInt<1>(0h0) connect states[0].vc_sel.`3`[3], UInt<1>(0h0) connect states[0].vc_sel.`3`[4], UInt<1>(0h0) connect states[0].vc_sel.`3`[5], UInt<1>(0h0) connect states[0].vc_sel.`3`[6], UInt<1>(0h0) connect states[0].vc_sel.`3`[7], UInt<1>(0h0) connect states[0].vc_sel.`4`[1], UInt<1>(0h0) connect states[0].vc_sel.`4`[2], UInt<1>(0h0) connect states[0].vc_sel.`4`[3], UInt<1>(0h0) connect states[0].vc_sel.`4`[4], UInt<1>(0h0) connect states[0].vc_sel.`4`[5], UInt<1>(0h0) connect states[0].vc_sel.`4`[6], UInt<1>(0h0) connect states[0].vc_sel.`4`[7], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[5], UInt<1>(0h0) connect states[1].vc_sel.`1`[6], UInt<1>(0h0) connect states[1].vc_sel.`1`[7], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[3], UInt<1>(0h0) connect states[1].vc_sel.`2`[4], UInt<1>(0h0) connect states[1].vc_sel.`2`[5], UInt<1>(0h0) connect states[1].vc_sel.`2`[6], UInt<1>(0h0) connect states[1].vc_sel.`2`[7], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[2], UInt<1>(0h0) connect states[2].vc_sel.`1`[3], UInt<1>(0h0) connect states[2].vc_sel.`1`[4], UInt<1>(0h0) connect states[2].vc_sel.`1`[5], UInt<1>(0h0) connect states[2].vc_sel.`1`[6], UInt<1>(0h0) connect states[2].vc_sel.`1`[7], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[1], UInt<1>(0h0) connect states[2].vc_sel.`2`[2], UInt<1>(0h0) connect states[2].vc_sel.`2`[3], UInt<1>(0h0) connect states[2].vc_sel.`2`[4], UInt<1>(0h0) connect states[2].vc_sel.`2`[5], UInt<1>(0h0) connect states[2].vc_sel.`2`[6], UInt<1>(0h0) connect states[2].vc_sel.`2`[7], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[1], UInt<1>(0h0) connect states[3].vc_sel.`1`[2], UInt<1>(0h0) connect states[3].vc_sel.`1`[3], UInt<1>(0h0) connect states[3].vc_sel.`1`[4], UInt<1>(0h0) connect states[3].vc_sel.`1`[5], UInt<1>(0h0) connect states[3].vc_sel.`1`[6], UInt<1>(0h0) connect states[3].vc_sel.`1`[7], UInt<1>(0h0) connect states[3].vc_sel.`2`[0], UInt<1>(0h0) connect states[3].vc_sel.`2`[1], UInt<1>(0h0) connect states[3].vc_sel.`2`[2], UInt<1>(0h0) connect states[3].vc_sel.`2`[3], UInt<1>(0h0) connect states[3].vc_sel.`2`[4], UInt<1>(0h0) connect states[3].vc_sel.`2`[5], UInt<1>(0h0) connect states[3].vc_sel.`2`[6], UInt<1>(0h0) connect states[3].vc_sel.`2`[7], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[2], UInt<1>(0h0) connect states[4].vc_sel.`1`[3], UInt<1>(0h0) connect states[4].vc_sel.`1`[4], UInt<1>(0h0) connect states[4].vc_sel.`1`[5], UInt<1>(0h0) connect states[4].vc_sel.`1`[6], UInt<1>(0h0) connect states[4].vc_sel.`1`[7], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[1], UInt<1>(0h0) connect states[4].vc_sel.`2`[2], UInt<1>(0h0) connect states[4].vc_sel.`2`[3], UInt<1>(0h0) connect states[4].vc_sel.`2`[4], UInt<1>(0h0) connect states[4].vc_sel.`2`[5], UInt<1>(0h0) connect states[4].vc_sel.`2`[6], UInt<1>(0h0) connect states[4].vc_sel.`2`[7], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[1], UInt<1>(0h0) connect states[5].vc_sel.`1`[2], UInt<1>(0h0) connect states[5].vc_sel.`1`[3], UInt<1>(0h0) connect states[5].vc_sel.`1`[4], UInt<1>(0h0) connect states[5].vc_sel.`2`[0], UInt<1>(0h0) connect states[5].vc_sel.`2`[1], UInt<1>(0h0) connect states[5].vc_sel.`2`[2], UInt<1>(0h0) connect states[5].vc_sel.`2`[3], UInt<1>(0h0) connect states[5].vc_sel.`2`[4], UInt<1>(0h0) connect states[5].vc_sel.`2`[5], UInt<1>(0h0) connect states[5].vc_sel.`2`[6], UInt<1>(0h0) connect states[5].vc_sel.`2`[7], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[1], UInt<1>(0h0) connect states[6].vc_sel.`1`[2], UInt<1>(0h0) connect states[6].vc_sel.`1`[3], UInt<1>(0h0) connect states[6].vc_sel.`1`[4], UInt<1>(0h0) connect states[6].vc_sel.`2`[0], UInt<1>(0h0) connect states[6].vc_sel.`2`[1], UInt<1>(0h0) connect states[6].vc_sel.`2`[2], UInt<1>(0h0) connect states[6].vc_sel.`2`[3], UInt<1>(0h0) connect states[6].vc_sel.`2`[4], UInt<1>(0h0) connect states[6].vc_sel.`2`[5], UInt<1>(0h0) connect states[6].vc_sel.`2`[6], UInt<1>(0h0) connect states[6].vc_sel.`2`[7], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[1], UInt<1>(0h0) connect states[7].vc_sel.`1`[2], UInt<1>(0h0) connect states[7].vc_sel.`1`[3], UInt<1>(0h0) connect states[7].vc_sel.`1`[4], UInt<1>(0h0) connect states[7].vc_sel.`2`[0], UInt<1>(0h0) connect states[7].vc_sel.`2`[1], UInt<1>(0h0) connect states[7].vc_sel.`2`[2], UInt<1>(0h0) connect states[7].vc_sel.`2`[3], UInt<1>(0h0) connect states[7].vc_sel.`2`[4], UInt<1>(0h0) connect states[7].vc_sel.`2`[5], UInt<1>(0h0) connect states[7].vc_sel.`2`[6], UInt<1>(0h0) connect states[7].vc_sel.`2`[7], UInt<1>(0h0) node _T_120 = asUInt(reset) when _T_120 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0)

module InputUnit_34( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_1, // @[InputUnit.scala:170:14] input io_out_credit_available_4_2, // @[InputUnit.scala:170:14] input io_out_credit_available_4_3, // @[InputUnit.scala:170:14] input io_out_credit_available_4_4, // @[InputUnit.scala:170:14] input io_out_credit_available_4_5, // @[InputUnit.scala:170:14] input io_out_credit_available_4_6, // @[InputUnit.scala:170:14] input io_out_credit_available_4_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_3_3, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_17 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_27 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_17( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_27 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<4>(0h8)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<4>(0h9)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<4>(0ha)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<4>(0hb)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h1)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 3) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h7)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 node _source_ok_T_43 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[2]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[3]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[4]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[5]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_48, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<4>(0h8)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<4>(0h9)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<4>(0ha)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<4>(0hb)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<2>(0h2)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_77 = shr(io.in.a.bits.source, 3) node _T_78 = eq(_T_77, UInt<1>(0h1)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_90 = shr(io.in.a.bits.source, 3) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<3>(0h7)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _T_103 = and(_T_11, _T_24) node _T_104 = and(_T_103, _T_37) node _T_105 = and(_T_104, _T_50) node _T_106 = and(_T_105, _T_63) node _T_107 = and(_T_106, _T_76) node _T_108 = and(_T_107, _T_89) node _T_109 = and(_T_108, _T_102) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_109, UInt<1>(0h1), "") : assert_1 node _T_113 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_113 : node _T_114 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_115 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_116 = and(_T_114, _T_115) node _T_117 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<4>(0h8)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_7) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<4>(0h9)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_8) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<4>(0ha)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_9) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_136 = shr(io.in.a.bits.source, 2) node _T_137 = eq(_T_136, UInt<4>(0hb)) node _T_138 = leq(UInt<1>(0h0), uncommonBits_10) node _T_139 = and(_T_137, _T_138) node _T_140 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_141 = and(_T_139, _T_140) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_142 = shr(io.in.a.bits.source, 3) node _T_143 = eq(_T_142, UInt<2>(0h2)) node _T_144 = leq(UInt<1>(0h0), uncommonBits_11) node _T_145 = and(_T_143, _T_144) node _T_146 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_147 = and(_T_145, _T_146) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_148 = shr(io.in.a.bits.source, 3) node _T_149 = eq(_T_148, UInt<1>(0h1)) node _T_150 = leq(UInt<1>(0h0), uncommonBits_12) node _T_151 = and(_T_149, _T_150) node _T_152 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_153 = and(_T_151, _T_152) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_154 = shr(io.in.a.bits.source, 3) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = leq(UInt<1>(0h0), uncommonBits_13) node _T_157 = and(_T_155, _T_156) node _T_158 = leq(uncommonBits_13, UInt<3>(0h7)) node _T_159 = and(_T_157, _T_158) node _T_160 = or(_T_117, _T_123) node _T_161 = or(_T_160, _T_129) node _T_162 = or(_T_161, _T_135) node _T_163 = or(_T_162, _T_141) node _T_164 = or(_T_163, _T_147) node _T_165 = or(_T_164, _T_153) node _T_166 = or(_T_165, _T_159) node _T_167 = and(_T_116, _T_166) node _T_168 = or(UInt<1>(0h0), _T_167) node _T_169 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<14>(0h2000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<13>(0h1000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<17>(0h10000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_186 = cvt(_T_185) node _T_187 = and(_T_186, asSInt(UInt<18>(0h2f000))) node _T_188 = asSInt(_T_187) node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0))) node _T_190 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_191 = cvt(_T_190) node _T_192 = and(_T_191, asSInt(UInt<17>(0h10000))) node _T_193 = asSInt(_T_192) node _T_194 = eq(_T_193, asSInt(UInt<1>(0h0))) node _T_195 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_196 = cvt(_T_195) node _T_197 = and(_T_196, asSInt(UInt<13>(0h1000))) node _T_198 = asSInt(_T_197) node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0))) node _T_200 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_201 = cvt(_T_200) node _T_202 = and(_T_201, asSInt(UInt<27>(0h4000000))) node _T_203 = asSInt(_T_202) node _T_204 = eq(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_206 = cvt(_T_205) node _T_207 = and(_T_206, asSInt(UInt<13>(0h1000))) node _T_208 = asSInt(_T_207) node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0))) node _T_210 = or(_T_174, _T_179) node _T_211 = or(_T_210, _T_184) node _T_212 = or(_T_211, _T_189) node _T_213 = or(_T_212, _T_194) node _T_214 = or(_T_213, _T_199) node _T_215 = or(_T_214, _T_204) node _T_216 = or(_T_215, _T_209) node _T_217 = and(_T_169, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = and(_T_168, _T_218) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_219, UInt<1>(0h1), "") : assert_2 node _T_223 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<4>(0h8)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_14) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_230 = shr(io.in.a.bits.source, 2) node _T_231 = eq(_T_230, UInt<4>(0h9)) node _T_232 = leq(UInt<1>(0h0), uncommonBits_15) node _T_233 = and(_T_231, _T_232) node _T_234 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<4>(0ha)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_16) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<4>(0hb)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_17) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_248 = shr(io.in.a.bits.source, 3) node _T_249 = eq(_T_248, UInt<2>(0h2)) node _T_250 = leq(UInt<1>(0h0), uncommonBits_18) node _T_251 = and(_T_249, _T_250) node _T_252 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_253 = and(_T_251, _T_252) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_254 = shr(io.in.a.bits.source, 3) node _T_255 = eq(_T_254, UInt<1>(0h1)) node _T_256 = leq(UInt<1>(0h0), uncommonBits_19) node _T_257 = and(_T_255, _T_256) node _T_258 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_259 = and(_T_257, _T_258) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_260 = shr(io.in.a.bits.source, 3) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = leq(UInt<1>(0h0), uncommonBits_20) node _T_263 = and(_T_261, _T_262) node _T_264 = leq(uncommonBits_20, UInt<3>(0h7)) node _T_265 = and(_T_263, _T_264) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_223 connect _WIRE[1], _T_229 connect _WIRE[2], _T_235 connect _WIRE[3], _T_241 connect _WIRE[4], _T_247 connect _WIRE[5], _T_253 connect _WIRE[6], _T_259 connect _WIRE[7], _T_265 node _T_266 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_267 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_268 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_269 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_270 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_271 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_272 = mux(_WIRE[5], _T_266, UInt<1>(0h0)) node _T_273 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_274 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_275 = or(_T_267, _T_268) node _T_276 = or(_T_275, _T_269) node _T_277 = or(_T_276, _T_270) node _T_278 = or(_T_277, _T_271) node _T_279 = or(_T_278, _T_272) node _T_280 = or(_T_279, _T_273) node _T_281 = or(_T_280, _T_274) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_281 node _T_282 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_283 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_284 = and(_T_282, _T_283) node _T_285 = or(UInt<1>(0h0), _T_284) node _T_286 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<14>(0h2000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<18>(0h2f000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<17>(0h10000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<27>(0h4000000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<13>(0h1000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = or(_T_290, _T_295) node _T_327 = or(_T_326, _T_300) node _T_328 = or(_T_327, _T_305) node _T_329 = or(_T_328, _T_310) node _T_330 = or(_T_329, _T_315) node _T_331 = or(_T_330, _T_320) node _T_332 = or(_T_331, _T_325) node _T_333 = and(_T_285, _T_332) node _T_334 = or(UInt<1>(0h0), _T_333) node _T_335 = and(_WIRE_1, _T_334) node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_T_335, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_335, UInt<1>(0h1), "") : assert_3 node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(source_ok, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_342 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_342, UInt<1>(0h1), "") : assert_5 node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(is_aligned, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_349 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_349, UInt<1>(0h1), "") : assert_7 node _T_353 = not(io.in.a.bits.mask) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_354, UInt<1>(0h1), "") : assert_8 node _T_358 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_T_358, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_358, UInt<1>(0h1), "") : assert_9 node _T_362 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_362 : node _T_363 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_364 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_367 = shr(io.in.a.bits.source, 2) node _T_368 = eq(_T_367, UInt<4>(0h8)) node _T_369 = leq(UInt<1>(0h0), uncommonBits_21) node _T_370 = and(_T_368, _T_369) node _T_371 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_372 = and(_T_370, _T_371) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_373 = shr(io.in.a.bits.source, 2) node _T_374 = eq(_T_373, UInt<4>(0h9)) node _T_375 = leq(UInt<1>(0h0), uncommonBits_22) node _T_376 = and(_T_374, _T_375) node _T_377 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_378 = and(_T_376, _T_377) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_379 = shr(io.in.a.bits.source, 2) node _T_380 = eq(_T_379, UInt<4>(0ha)) node _T_381 = leq(UInt<1>(0h0), uncommonBits_23) node _T_382 = and(_T_380, _T_381) node _T_383 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_384 = and(_T_382, _T_383) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_385 = shr(io.in.a.bits.source, 2) node _T_386 = eq(_T_385, UInt<4>(0hb)) node _T_387 = leq(UInt<1>(0h0), uncommonBits_24) node _T_388 = and(_T_386, _T_387) node _T_389 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_390 = and(_T_388, _T_389) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_391 = shr(io.in.a.bits.source, 3) node _T_392 = eq(_T_391, UInt<2>(0h2)) node _T_393 = leq(UInt<1>(0h0), uncommonBits_25) node _T_394 = and(_T_392, _T_393) node _T_395 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_396 = and(_T_394, _T_395) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_397 = shr(io.in.a.bits.source, 3) node _T_398 = eq(_T_397, UInt<1>(0h1)) node _T_399 = leq(UInt<1>(0h0), uncommonBits_26) node _T_400 = and(_T_398, _T_399) node _T_401 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_402 = and(_T_400, _T_401) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_403 = shr(io.in.a.bits.source, 3) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = leq(UInt<1>(0h0), uncommonBits_27) node _T_406 = and(_T_404, _T_405) node _T_407 = leq(uncommonBits_27, UInt<3>(0h7)) node _T_408 = and(_T_406, _T_407) node _T_409 = or(_T_366, _T_372) node _T_410 = or(_T_409, _T_378) node _T_411 = or(_T_410, _T_384) node _T_412 = or(_T_411, _T_390) node _T_413 = or(_T_412, _T_396) node _T_414 = or(_T_413, _T_402) node _T_415 = or(_T_414, _T_408) node _T_416 = and(_T_365, _T_415) node _T_417 = or(UInt<1>(0h0), _T_416) node _T_418 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_419 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<14>(0h2000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<13>(0h1000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<17>(0h10000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<18>(0h2f000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<17>(0h10000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<13>(0h1000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_450 = cvt(_T_449) node _T_451 = and(_T_450, asSInt(UInt<27>(0h4000000))) node _T_452 = asSInt(_T_451) node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) node _T_454 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<13>(0h1000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = or(_T_423, _T_428) node _T_460 = or(_T_459, _T_433) node _T_461 = or(_T_460, _T_438) node _T_462 = or(_T_461, _T_443) node _T_463 = or(_T_462, _T_448) node _T_464 = or(_T_463, _T_453) node _T_465 = or(_T_464, _T_458) node _T_466 = and(_T_418, _T_465) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = and(_T_417, _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_468, UInt<1>(0h1), "") : assert_10 node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_473 = shr(io.in.a.bits.source, 2) node _T_474 = eq(_T_473, UInt<4>(0h8)) node _T_475 = leq(UInt<1>(0h0), uncommonBits_28) node _T_476 = and(_T_474, _T_475) node _T_477 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_478 = and(_T_476, _T_477) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_479 = shr(io.in.a.bits.source, 2) node _T_480 = eq(_T_479, UInt<4>(0h9)) node _T_481 = leq(UInt<1>(0h0), uncommonBits_29) node _T_482 = and(_T_480, _T_481) node _T_483 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_484 = and(_T_482, _T_483) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_485 = shr(io.in.a.bits.source, 2) node _T_486 = eq(_T_485, UInt<4>(0ha)) node _T_487 = leq(UInt<1>(0h0), uncommonBits_30) node _T_488 = and(_T_486, _T_487) node _T_489 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_490 = and(_T_488, _T_489) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_491 = shr(io.in.a.bits.source, 2) node _T_492 = eq(_T_491, UInt<4>(0hb)) node _T_493 = leq(UInt<1>(0h0), uncommonBits_31) node _T_494 = and(_T_492, _T_493) node _T_495 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_496 = and(_T_494, _T_495) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_497 = shr(io.in.a.bits.source, 3) node _T_498 = eq(_T_497, UInt<2>(0h2)) node _T_499 = leq(UInt<1>(0h0), uncommonBits_32) node _T_500 = and(_T_498, _T_499) node _T_501 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_502 = and(_T_500, _T_501) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_503 = shr(io.in.a.bits.source, 3) node _T_504 = eq(_T_503, UInt<1>(0h1)) node _T_505 = leq(UInt<1>(0h0), uncommonBits_33) node _T_506 = and(_T_504, _T_505) node _T_507 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_508 = and(_T_506, _T_507) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_509 = shr(io.in.a.bits.source, 3) node _T_510 = eq(_T_509, UInt<1>(0h0)) node _T_511 = leq(UInt<1>(0h0), uncommonBits_34) node _T_512 = and(_T_510, _T_511) node _T_513 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_514 = and(_T_512, _T_513) wire _WIRE_2 : UInt<1>[8] connect _WIRE_2[0], _T_472 connect _WIRE_2[1], _T_478 connect _WIRE_2[2], _T_484 connect _WIRE_2[3], _T_490 connect _WIRE_2[4], _T_496 connect _WIRE_2[5], _T_502 connect _WIRE_2[6], _T_508 connect _WIRE_2[7], _T_514 node _T_515 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_516 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_517 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_518 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_520 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_521 = mux(_WIRE_2[5], _T_515, UInt<1>(0h0)) node _T_522 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_524 = or(_T_516, _T_517) node _T_525 = or(_T_524, _T_518) node _T_526 = or(_T_525, _T_519) node _T_527 = or(_T_526, _T_520) node _T_528 = or(_T_527, _T_521) node _T_529 = or(_T_528, _T_522) node _T_530 = or(_T_529, _T_523) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_530 node _T_531 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_532 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_533 = and(_T_531, _T_532) node _T_534 = or(UInt<1>(0h0), _T_533) node _T_535 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_536 = cvt(_T_535) node _T_537 = and(_T_536, asSInt(UInt<14>(0h2000))) node _T_538 = asSInt(_T_537) node _T_539 = eq(_T_538, asSInt(UInt<1>(0h0))) node _T_540 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_541 = cvt(_T_540) node _T_542 = and(_T_541, asSInt(UInt<13>(0h1000))) node _T_543 = asSInt(_T_542) node _T_544 = eq(_T_543, asSInt(UInt<1>(0h0))) node _T_545 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_546 = cvt(_T_545) node _T_547 = and(_T_546, asSInt(UInt<17>(0h10000))) node _T_548 = asSInt(_T_547) node _T_549 = eq(_T_548, asSInt(UInt<1>(0h0))) node _T_550 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_551 = cvt(_T_550) node _T_552 = and(_T_551, asSInt(UInt<18>(0h2f000))) node _T_553 = asSInt(_T_552) node _T_554 = eq(_T_553, asSInt(UInt<1>(0h0))) node _T_555 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_556 = cvt(_T_555) node _T_557 = and(_T_556, asSInt(UInt<17>(0h10000))) node _T_558 = asSInt(_T_557) node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0))) node _T_560 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_561 = cvt(_T_560) node _T_562 = and(_T_561, asSInt(UInt<13>(0h1000))) node _T_563 = asSInt(_T_562) node _T_564 = eq(_T_563, asSInt(UInt<1>(0h0))) node _T_565 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_566 = cvt(_T_565) node _T_567 = and(_T_566, asSInt(UInt<27>(0h4000000))) node _T_568 = asSInt(_T_567) node _T_569 = eq(_T_568, asSInt(UInt<1>(0h0))) node _T_570 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_571 = cvt(_T_570) node _T_572 = and(_T_571, asSInt(UInt<13>(0h1000))) node _T_573 = asSInt(_T_572) node _T_574 = eq(_T_573, asSInt(UInt<1>(0h0))) node _T_575 = or(_T_539, _T_544) node _T_576 = or(_T_575, _T_549) node _T_577 = or(_T_576, _T_554) node _T_578 = or(_T_577, _T_559) node _T_579 = or(_T_578, _T_564) node _T_580 = or(_T_579, _T_569) node _T_581 = or(_T_580, _T_574) node _T_582 = and(_T_534, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = and(_WIRE_3, _T_583) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_584, UInt<1>(0h1), "") : assert_11 node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(source_ok, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_591 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(_T_591, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_591, UInt<1>(0h1), "") : assert_13 node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(is_aligned, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_598 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_598, UInt<1>(0h1), "") : assert_15 node _T_602 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_602, UInt<1>(0h1), "") : assert_16 node _T_606 = not(io.in.a.bits.mask) node _T_607 = eq(_T_606, UInt<1>(0h0)) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(_T_607, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_607, UInt<1>(0h1), "") : assert_17 node _T_611 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_611, UInt<1>(0h1), "") : assert_18 node _T_615 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<4>(0h8)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_35) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<4>(0h9)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_36) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<4>(0ha)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_37) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<4>(0hb)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_38) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_644 = shr(io.in.a.bits.source, 3) node _T_645 = eq(_T_644, UInt<2>(0h2)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_39) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_649 = and(_T_647, _T_648) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_650 = shr(io.in.a.bits.source, 3) node _T_651 = eq(_T_650, UInt<1>(0h1)) node _T_652 = leq(UInt<1>(0h0), uncommonBits_40) node _T_653 = and(_T_651, _T_652) node _T_654 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_655 = and(_T_653, _T_654) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_656 = shr(io.in.a.bits.source, 3) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = leq(UInt<1>(0h0), uncommonBits_41) node _T_659 = and(_T_657, _T_658) node _T_660 = leq(uncommonBits_41, UInt<3>(0h7)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(_T_619, _T_625) node _T_663 = or(_T_662, _T_631) node _T_664 = or(_T_663, _T_637) node _T_665 = or(_T_664, _T_643) node _T_666 = or(_T_665, _T_649) node _T_667 = or(_T_666, _T_655) node _T_668 = or(_T_667, _T_661) node _T_669 = and(_T_618, _T_668) node _T_670 = or(UInt<1>(0h0), _T_669) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_670, UInt<1>(0h1), "") : assert_19 node _T_674 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_675 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_676 = and(_T_674, _T_675) node _T_677 = or(UInt<1>(0h0), _T_676) node _T_678 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<13>(0h1000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = and(_T_677, _T_682) node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_685 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_686 = and(_T_684, _T_685) node _T_687 = or(UInt<1>(0h0), _T_686) node _T_688 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<14>(0h2000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<17>(0h10000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<18>(0h2f000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<17>(0h10000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<13>(0h1000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<27>(0h4000000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = or(_T_692, _T_697) node _T_724 = or(_T_723, _T_702) node _T_725 = or(_T_724, _T_707) node _T_726 = or(_T_725, _T_712) node _T_727 = or(_T_726, _T_717) node _T_728 = or(_T_727, _T_722) node _T_729 = and(_T_687, _T_728) node _T_730 = or(UInt<1>(0h0), _T_683) node _T_731 = or(_T_730, _T_729) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_731, UInt<1>(0h1), "") : assert_20 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(source_ok, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_741 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_741, UInt<1>(0h1), "") : assert_23 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_745, UInt<1>(0h1), "") : assert_24 node _T_749 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_749, UInt<1>(0h1), "") : assert_25 node _T_753 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<4>(0h8)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_42) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<4>(0h9)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_43) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<4>(0ha)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_44) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<4>(0hb)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_45) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_782 = shr(io.in.a.bits.source, 3) node _T_783 = eq(_T_782, UInt<2>(0h2)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_46) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_788 = shr(io.in.a.bits.source, 3) node _T_789 = eq(_T_788, UInt<1>(0h1)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_47) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_793 = and(_T_791, _T_792) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_794 = shr(io.in.a.bits.source, 3) node _T_795 = eq(_T_794, UInt<1>(0h0)) node _T_796 = leq(UInt<1>(0h0), uncommonBits_48) node _T_797 = and(_T_795, _T_796) node _T_798 = leq(uncommonBits_48, UInt<3>(0h7)) node _T_799 = and(_T_797, _T_798) node _T_800 = or(_T_757, _T_763) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_775) node _T_803 = or(_T_802, _T_781) node _T_804 = or(_T_803, _T_787) node _T_805 = or(_T_804, _T_793) node _T_806 = or(_T_805, _T_799) node _T_807 = and(_T_756, _T_806) node _T_808 = or(UInt<1>(0h0), _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<13>(0h1000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = and(_T_812, _T_817) node _T_819 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_820 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_821 = and(_T_819, _T_820) node _T_822 = or(UInt<1>(0h0), _T_821) node _T_823 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_824 = cvt(_T_823) node _T_825 = and(_T_824, asSInt(UInt<14>(0h2000))) node _T_826 = asSInt(_T_825) node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) node _T_828 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_829 = cvt(_T_828) node _T_830 = and(_T_829, asSInt(UInt<18>(0h2f000))) node _T_831 = asSInt(_T_830) node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) node _T_833 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_834 = cvt(_T_833) node _T_835 = and(_T_834, asSInt(UInt<17>(0h10000))) node _T_836 = asSInt(_T_835) node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0))) node _T_838 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_839 = cvt(_T_838) node _T_840 = and(_T_839, asSInt(UInt<13>(0h1000))) node _T_841 = asSInt(_T_840) node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) node _T_843 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<27>(0h4000000))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_849 = cvt(_T_848) node _T_850 = and(_T_849, asSInt(UInt<13>(0h1000))) node _T_851 = asSInt(_T_850) node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0))) node _T_853 = or(_T_827, _T_832) node _T_854 = or(_T_853, _T_837) node _T_855 = or(_T_854, _T_842) node _T_856 = or(_T_855, _T_847) node _T_857 = or(_T_856, _T_852) node _T_858 = and(_T_822, _T_857) node _T_859 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_860 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<17>(0h10000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = and(_T_859, _T_864) node _T_866 = or(UInt<1>(0h0), _T_818) node _T_867 = or(_T_866, _T_858) node _T_868 = or(_T_867, _T_865) node _T_869 = and(_T_808, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_869, UInt<1>(0h1), "") : assert_26 node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(source_ok, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(is_aligned, UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_879 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_880 = asUInt(reset) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(_T_879, UInt<1>(0h0)) when _T_882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_879, UInt<1>(0h1), "") : assert_29 node _T_883 = eq(io.in.a.bits.mask, mask) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_883, UInt<1>(0h1), "") : assert_30 node _T_887 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_887 : node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_892 = shr(io.in.a.bits.source, 2) node _T_893 = eq(_T_892, UInt<4>(0h8)) node _T_894 = leq(UInt<1>(0h0), uncommonBits_49) node _T_895 = and(_T_893, _T_894) node _T_896 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_897 = and(_T_895, _T_896) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_898 = shr(io.in.a.bits.source, 2) node _T_899 = eq(_T_898, UInt<4>(0h9)) node _T_900 = leq(UInt<1>(0h0), uncommonBits_50) node _T_901 = and(_T_899, _T_900) node _T_902 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_903 = and(_T_901, _T_902) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_904 = shr(io.in.a.bits.source, 2) node _T_905 = eq(_T_904, UInt<4>(0ha)) node _T_906 = leq(UInt<1>(0h0), uncommonBits_51) node _T_907 = and(_T_905, _T_906) node _T_908 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_909 = and(_T_907, _T_908) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_910 = shr(io.in.a.bits.source, 2) node _T_911 = eq(_T_910, UInt<4>(0hb)) node _T_912 = leq(UInt<1>(0h0), uncommonBits_52) node _T_913 = and(_T_911, _T_912) node _T_914 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_915 = and(_T_913, _T_914) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_916 = shr(io.in.a.bits.source, 3) node _T_917 = eq(_T_916, UInt<2>(0h2)) node _T_918 = leq(UInt<1>(0h0), uncommonBits_53) node _T_919 = and(_T_917, _T_918) node _T_920 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_921 = and(_T_919, _T_920) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_922 = shr(io.in.a.bits.source, 3) node _T_923 = eq(_T_922, UInt<1>(0h1)) node _T_924 = leq(UInt<1>(0h0), uncommonBits_54) node _T_925 = and(_T_923, _T_924) node _T_926 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_927 = and(_T_925, _T_926) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0) node _T_928 = shr(io.in.a.bits.source, 3) node _T_929 = eq(_T_928, UInt<1>(0h0)) node _T_930 = leq(UInt<1>(0h0), uncommonBits_55) node _T_931 = and(_T_929, _T_930) node _T_932 = leq(uncommonBits_55, UInt<3>(0h7)) node _T_933 = and(_T_931, _T_932) node _T_934 = or(_T_891, _T_897) node _T_935 = or(_T_934, _T_903) node _T_936 = or(_T_935, _T_909) node _T_937 = or(_T_936, _T_915) node _T_938 = or(_T_937, _T_921) node _T_939 = or(_T_938, _T_927) node _T_940 = or(_T_939, _T_933) node _T_941 = and(_T_890, _T_940) node _T_942 = or(UInt<1>(0h0), _T_941) node _T_943 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_944 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_945 = and(_T_943, _T_944) node _T_946 = or(UInt<1>(0h0), _T_945) node _T_947 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<13>(0h1000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = and(_T_946, _T_951) node _T_953 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_954 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_955 = and(_T_953, _T_954) node _T_956 = or(UInt<1>(0h0), _T_955) node _T_957 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_958 = cvt(_T_957) node _T_959 = and(_T_958, asSInt(UInt<14>(0h2000))) node _T_960 = asSInt(_T_959) node _T_961 = eq(_T_960, asSInt(UInt<1>(0h0))) node _T_962 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_963 = cvt(_T_962) node _T_964 = and(_T_963, asSInt(UInt<18>(0h2f000))) node _T_965 = asSInt(_T_964) node _T_966 = eq(_T_965, asSInt(UInt<1>(0h0))) node _T_967 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_968 = cvt(_T_967) node _T_969 = and(_T_968, asSInt(UInt<17>(0h10000))) node _T_970 = asSInt(_T_969) node _T_971 = eq(_T_970, asSInt(UInt<1>(0h0))) node _T_972 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_973 = cvt(_T_972) node _T_974 = and(_T_973, asSInt(UInt<13>(0h1000))) node _T_975 = asSInt(_T_974) node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0))) node _T_977 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<27>(0h4000000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = or(_T_961, _T_966) node _T_988 = or(_T_987, _T_971) node _T_989 = or(_T_988, _T_976) node _T_990 = or(_T_989, _T_981) node _T_991 = or(_T_990, _T_986) node _T_992 = and(_T_956, _T_991) node _T_993 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_994 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = and(_T_993, _T_998) node _T_1000 = or(UInt<1>(0h0), _T_952) node _T_1001 = or(_T_1000, _T_992) node _T_1002 = or(_T_1001, _T_999) node _T_1003 = and(_T_942, _T_1002) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_31 node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(source_ok, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(is_aligned, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1013 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_34 node _T_1017 = not(mask) node _T_1018 = and(io.in.a.bits.mask, _T_1017) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_35 node _T_1023 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1023 : node _T_1024 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1025 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1026 = and(_T_1024, _T_1025) node _T_1027 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1028 = shr(io.in.a.bits.source, 2) node _T_1029 = eq(_T_1028, UInt<4>(0h8)) node _T_1030 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1033 = and(_T_1031, _T_1032) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1034 = shr(io.in.a.bits.source, 2) node _T_1035 = eq(_T_1034, UInt<4>(0h9)) node _T_1036 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1037 = and(_T_1035, _T_1036) node _T_1038 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1039 = and(_T_1037, _T_1038) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1040 = shr(io.in.a.bits.source, 2) node _T_1041 = eq(_T_1040, UInt<4>(0ha)) node _T_1042 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1045 = and(_T_1043, _T_1044) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1046 = shr(io.in.a.bits.source, 2) node _T_1047 = eq(_T_1046, UInt<4>(0hb)) node _T_1048 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1051 = and(_T_1049, _T_1050) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0) node _T_1052 = shr(io.in.a.bits.source, 3) node _T_1053 = eq(_T_1052, UInt<2>(0h2)) node _T_1054 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1055 = and(_T_1053, _T_1054) node _T_1056 = leq(uncommonBits_60, UInt<3>(0h7)) node _T_1057 = and(_T_1055, _T_1056) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0) node _T_1058 = shr(io.in.a.bits.source, 3) node _T_1059 = eq(_T_1058, UInt<1>(0h1)) node _T_1060 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1061 = and(_T_1059, _T_1060) node _T_1062 = leq(uncommonBits_61, UInt<3>(0h7)) node _T_1063 = and(_T_1061, _T_1062) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0) node _T_1064 = shr(io.in.a.bits.source, 3) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) node _T_1066 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1067 = and(_T_1065, _T_1066) node _T_1068 = leq(uncommonBits_62, UInt<3>(0h7)) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = or(_T_1027, _T_1033) node _T_1071 = or(_T_1070, _T_1039) node _T_1072 = or(_T_1071, _T_1045) node _T_1073 = or(_T_1072, _T_1051) node _T_1074 = or(_T_1073, _T_1057) node _T_1075 = or(_T_1074, _T_1063) node _T_1076 = or(_T_1075, _T_1069) node _T_1077 = and(_T_1026, _T_1076) node _T_1078 = or(UInt<1>(0h0), _T_1077) node _T_1079 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1080 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1081 = and(_T_1079, _T_1080) node _T_1082 = or(UInt<1>(0h0), _T_1081) node _T_1083 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1084 = cvt(_T_1083) node _T_1085 = and(_T_1084, asSInt(UInt<14>(0h2000))) node _T_1086 = asSInt(_T_1085) node _T_1087 = eq(_T_1086, asSInt(UInt<1>(0h0))) node _T_1088 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1089 = cvt(_T_1088) node _T_1090 = and(_T_1089, asSInt(UInt<13>(0h1000))) node _T_1091 = asSInt(_T_1090) node _T_1092 = eq(_T_1091, asSInt(UInt<1>(0h0))) node _T_1093 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1094 = cvt(_T_1093) node _T_1095 = and(_T_1094, asSInt(UInt<18>(0h2f000))) node _T_1096 = asSInt(_T_1095) node _T_1097 = eq(_T_1096, asSInt(UInt<1>(0h0))) node _T_1098 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1099 = cvt(_T_1098) node _T_1100 = and(_T_1099, asSInt(UInt<17>(0h10000))) node _T_1101 = asSInt(_T_1100) node _T_1102 = eq(_T_1101, asSInt(UInt<1>(0h0))) node _T_1103 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1104 = cvt(_T_1103) node _T_1105 = and(_T_1104, asSInt(UInt<13>(0h1000))) node _T_1106 = asSInt(_T_1105) node _T_1107 = eq(_T_1106, asSInt(UInt<1>(0h0))) node _T_1108 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1109 = cvt(_T_1108) node _T_1110 = and(_T_1109, asSInt(UInt<27>(0h4000000))) node _T_1111 = asSInt(_T_1110) node _T_1112 = eq(_T_1111, asSInt(UInt<1>(0h0))) node _T_1113 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1114 = cvt(_T_1113) node _T_1115 = and(_T_1114, asSInt(UInt<13>(0h1000))) node _T_1116 = asSInt(_T_1115) node _T_1117 = eq(_T_1116, asSInt(UInt<1>(0h0))) node _T_1118 = or(_T_1087, _T_1092) node _T_1119 = or(_T_1118, _T_1097) node _T_1120 = or(_T_1119, _T_1102) node _T_1121 = or(_T_1120, _T_1107) node _T_1122 = or(_T_1121, _T_1112) node _T_1123 = or(_T_1122, _T_1117) node _T_1124 = and(_T_1082, _T_1123) node _T_1125 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1126 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1127 = cvt(_T_1126) node _T_1128 = and(_T_1127, asSInt(UInt<17>(0h10000))) node _T_1129 = asSInt(_T_1128) node _T_1130 = eq(_T_1129, asSInt(UInt<1>(0h0))) node _T_1131 = and(_T_1125, _T_1130) node _T_1132 = or(UInt<1>(0h0), _T_1124) node _T_1133 = or(_T_1132, _T_1131) node _T_1134 = and(_T_1078, _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_36 node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(source_ok, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(is_aligned, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1144 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_39 node _T_1148 = eq(io.in.a.bits.mask, mask) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_40 node _T_1152 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1152 : node _T_1153 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1154 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1157 = shr(io.in.a.bits.source, 2) node _T_1158 = eq(_T_1157, UInt<4>(0h8)) node _T_1159 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1160 = and(_T_1158, _T_1159) node _T_1161 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1162 = and(_T_1160, _T_1161) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_1163 = shr(io.in.a.bits.source, 2) node _T_1164 = eq(_T_1163, UInt<4>(0h9)) node _T_1165 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1166 = and(_T_1164, _T_1165) node _T_1167 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_1168 = and(_T_1166, _T_1167) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1169 = shr(io.in.a.bits.source, 2) node _T_1170 = eq(_T_1169, UInt<4>(0ha)) node _T_1171 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1172 = and(_T_1170, _T_1171) node _T_1173 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1174 = and(_T_1172, _T_1173) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1175 = shr(io.in.a.bits.source, 2) node _T_1176 = eq(_T_1175, UInt<4>(0hb)) node _T_1177 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1178 = and(_T_1176, _T_1177) node _T_1179 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1180 = and(_T_1178, _T_1179) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0) node _T_1181 = shr(io.in.a.bits.source, 3) node _T_1182 = eq(_T_1181, UInt<2>(0h2)) node _T_1183 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1184 = and(_T_1182, _T_1183) node _T_1185 = leq(uncommonBits_67, UInt<3>(0h7)) node _T_1186 = and(_T_1184, _T_1185) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0) node _T_1187 = shr(io.in.a.bits.source, 3) node _T_1188 = eq(_T_1187, UInt<1>(0h1)) node _T_1189 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1190 = and(_T_1188, _T_1189) node _T_1191 = leq(uncommonBits_68, UInt<3>(0h7)) node _T_1192 = and(_T_1190, _T_1191) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1193 = shr(io.in.a.bits.source, 3) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) node _T_1195 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1196 = and(_T_1194, _T_1195) node _T_1197 = leq(uncommonBits_69, UInt<3>(0h7)) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = or(_T_1156, _T_1162) node _T_1200 = or(_T_1199, _T_1168) node _T_1201 = or(_T_1200, _T_1174) node _T_1202 = or(_T_1201, _T_1180) node _T_1203 = or(_T_1202, _T_1186) node _T_1204 = or(_T_1203, _T_1192) node _T_1205 = or(_T_1204, _T_1198) node _T_1206 = and(_T_1155, _T_1205) node _T_1207 = or(UInt<1>(0h0), _T_1206) node _T_1208 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1209 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = or(UInt<1>(0h0), _T_1210) node _T_1212 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<14>(0h2000))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1218 = cvt(_T_1217) node _T_1219 = and(_T_1218, asSInt(UInt<13>(0h1000))) node _T_1220 = asSInt(_T_1219) node _T_1221 = eq(_T_1220, asSInt(UInt<1>(0h0))) node _T_1222 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<18>(0h2f000))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1228 = cvt(_T_1227) node _T_1229 = and(_T_1228, asSInt(UInt<17>(0h10000))) node _T_1230 = asSInt(_T_1229) node _T_1231 = eq(_T_1230, asSInt(UInt<1>(0h0))) node _T_1232 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1233 = cvt(_T_1232) node _T_1234 = and(_T_1233, asSInt(UInt<13>(0h1000))) node _T_1235 = asSInt(_T_1234) node _T_1236 = eq(_T_1235, asSInt(UInt<1>(0h0))) node _T_1237 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1238 = cvt(_T_1237) node _T_1239 = and(_T_1238, asSInt(UInt<27>(0h4000000))) node _T_1240 = asSInt(_T_1239) node _T_1241 = eq(_T_1240, asSInt(UInt<1>(0h0))) node _T_1242 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1243 = cvt(_T_1242) node _T_1244 = and(_T_1243, asSInt(UInt<13>(0h1000))) node _T_1245 = asSInt(_T_1244) node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0))) node _T_1247 = or(_T_1216, _T_1221) node _T_1248 = or(_T_1247, _T_1226) node _T_1249 = or(_T_1248, _T_1231) node _T_1250 = or(_T_1249, _T_1236) node _T_1251 = or(_T_1250, _T_1241) node _T_1252 = or(_T_1251, _T_1246) node _T_1253 = and(_T_1211, _T_1252) node _T_1254 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1255 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1256 = cvt(_T_1255) node _T_1257 = and(_T_1256, asSInt(UInt<17>(0h10000))) node _T_1258 = asSInt(_T_1257) node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0))) node _T_1260 = and(_T_1254, _T_1259) node _T_1261 = or(UInt<1>(0h0), _T_1253) node _T_1262 = or(_T_1261, _T_1260) node _T_1263 = and(_T_1207, _T_1262) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_41 node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(source_ok, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(is_aligned, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1273 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_44 node _T_1277 = eq(io.in.a.bits.mask, mask) node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(_T_1277, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1277, UInt<1>(0h1), "") : assert_45 node _T_1281 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1281 : node _T_1282 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1283 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1284 = and(_T_1282, _T_1283) node _T_1285 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1286 = shr(io.in.a.bits.source, 2) node _T_1287 = eq(_T_1286, UInt<4>(0h8)) node _T_1288 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1289 = and(_T_1287, _T_1288) node _T_1290 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1291 = and(_T_1289, _T_1290) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1292 = shr(io.in.a.bits.source, 2) node _T_1293 = eq(_T_1292, UInt<4>(0h9)) node _T_1294 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1297 = and(_T_1295, _T_1296) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1298 = shr(io.in.a.bits.source, 2) node _T_1299 = eq(_T_1298, UInt<4>(0ha)) node _T_1300 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1301 = and(_T_1299, _T_1300) node _T_1302 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1303 = and(_T_1301, _T_1302) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1304 = shr(io.in.a.bits.source, 2) node _T_1305 = eq(_T_1304, UInt<4>(0hb)) node _T_1306 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1307 = and(_T_1305, _T_1306) node _T_1308 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1309 = and(_T_1307, _T_1308) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1310 = shr(io.in.a.bits.source, 3) node _T_1311 = eq(_T_1310, UInt<2>(0h2)) node _T_1312 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1313 = and(_T_1311, _T_1312) node _T_1314 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1315 = and(_T_1313, _T_1314) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0) node _T_1316 = shr(io.in.a.bits.source, 3) node _T_1317 = eq(_T_1316, UInt<1>(0h1)) node _T_1318 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = leq(uncommonBits_75, UInt<3>(0h7)) node _T_1321 = and(_T_1319, _T_1320) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0) node _T_1322 = shr(io.in.a.bits.source, 3) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) node _T_1324 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = leq(uncommonBits_76, UInt<3>(0h7)) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = or(_T_1285, _T_1291) node _T_1329 = or(_T_1328, _T_1297) node _T_1330 = or(_T_1329, _T_1303) node _T_1331 = or(_T_1330, _T_1309) node _T_1332 = or(_T_1331, _T_1315) node _T_1333 = or(_T_1332, _T_1321) node _T_1334 = or(_T_1333, _T_1327) node _T_1335 = and(_T_1284, _T_1334) node _T_1336 = or(UInt<1>(0h0), _T_1335) node _T_1337 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1338 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1339 = and(_T_1337, _T_1338) node _T_1340 = or(UInt<1>(0h0), _T_1339) node _T_1341 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1342 = cvt(_T_1341) node _T_1343 = and(_T_1342, asSInt(UInt<13>(0h1000))) node _T_1344 = asSInt(_T_1343) node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) node _T_1346 = and(_T_1340, _T_1345) node _T_1347 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1348 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1349 = cvt(_T_1348) node _T_1350 = and(_T_1349, asSInt(UInt<14>(0h2000))) node _T_1351 = asSInt(_T_1350) node _T_1352 = eq(_T_1351, asSInt(UInt<1>(0h0))) node _T_1353 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1354 = cvt(_T_1353) node _T_1355 = and(_T_1354, asSInt(UInt<17>(0h10000))) node _T_1356 = asSInt(_T_1355) node _T_1357 = eq(_T_1356, asSInt(UInt<1>(0h0))) node _T_1358 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1359 = cvt(_T_1358) node _T_1360 = and(_T_1359, asSInt(UInt<18>(0h2f000))) node _T_1361 = asSInt(_T_1360) node _T_1362 = eq(_T_1361, asSInt(UInt<1>(0h0))) node _T_1363 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1364 = cvt(_T_1363) node _T_1365 = and(_T_1364, asSInt(UInt<17>(0h10000))) node _T_1366 = asSInt(_T_1365) node _T_1367 = eq(_T_1366, asSInt(UInt<1>(0h0))) node _T_1368 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1369 = cvt(_T_1368) node _T_1370 = and(_T_1369, asSInt(UInt<13>(0h1000))) node _T_1371 = asSInt(_T_1370) node _T_1372 = eq(_T_1371, asSInt(UInt<1>(0h0))) node _T_1373 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1374 = cvt(_T_1373) node _T_1375 = and(_T_1374, asSInt(UInt<27>(0h4000000))) node _T_1376 = asSInt(_T_1375) node _T_1377 = eq(_T_1376, asSInt(UInt<1>(0h0))) node _T_1378 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1379 = cvt(_T_1378) node _T_1380 = and(_T_1379, asSInt(UInt<13>(0h1000))) node _T_1381 = asSInt(_T_1380) node _T_1382 = eq(_T_1381, asSInt(UInt<1>(0h0))) node _T_1383 = or(_T_1352, _T_1357) node _T_1384 = or(_T_1383, _T_1362) node _T_1385 = or(_T_1384, _T_1367) node _T_1386 = or(_T_1385, _T_1372) node _T_1387 = or(_T_1386, _T_1377) node _T_1388 = or(_T_1387, _T_1382) node _T_1389 = and(_T_1347, _T_1388) node _T_1390 = or(UInt<1>(0h0), _T_1346) node _T_1391 = or(_T_1390, _T_1389) node _T_1392 = and(_T_1336, _T_1391) node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(_T_1392, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1392, UInt<1>(0h1), "") : assert_46 node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(source_ok, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(is_aligned, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1402 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_49 node _T_1406 = eq(io.in.a.bits.mask, mask) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_50 node _T_1410 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1414 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1415 = asUInt(reset) node _T_1416 = eq(_T_1415, UInt<1>(0h0)) when _T_1416 : node _T_1417 = eq(_T_1414, UInt<1>(0h0)) when _T_1417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1414, UInt<1>(0h1), "") : assert_52 node _source_ok_T_49 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_50 = shr(io.in.d.bits.source, 2) node _source_ok_T_51 = eq(_source_ok_T_50, UInt<4>(0h8)) node _source_ok_T_52 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_T_54 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_56 = shr(io.in.d.bits.source, 2) node _source_ok_T_57 = eq(_source_ok_T_56, UInt<4>(0h9)) node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_T_60 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_62 = shr(io.in.d.bits.source, 2) node _source_ok_T_63 = eq(_source_ok_T_62, UInt<4>(0ha)) node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_T_66 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_68 = shr(io.in.d.bits.source, 2) node _source_ok_T_69 = eq(_source_ok_T_68, UInt<4>(0hb)) node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_74 = shr(io.in.d.bits.source, 3) node _source_ok_T_75 = eq(_source_ok_T_74, UInt<2>(0h2)) node _source_ok_T_76 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_T_78 = leq(source_ok_uncommonBits_11, UInt<3>(0h7)) node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0) node _source_ok_T_80 = shr(io.in.d.bits.source, 3) node _source_ok_T_81 = eq(_source_ok_T_80, UInt<1>(0h1)) node _source_ok_T_82 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_T_84 = leq(source_ok_uncommonBits_12, UInt<3>(0h7)) node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0) node _source_ok_T_86 = shr(io.in.d.bits.source, 3) node _source_ok_T_87 = eq(_source_ok_T_86, UInt<1>(0h0)) node _source_ok_T_88 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_T_90 = leq(source_ok_uncommonBits_13, UInt<3>(0h7)) node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_49 connect _source_ok_WIRE_1[1], _source_ok_T_55 connect _source_ok_WIRE_1[2], _source_ok_T_61 connect _source_ok_WIRE_1[3], _source_ok_T_67 connect _source_ok_WIRE_1[4], _source_ok_T_73 connect _source_ok_WIRE_1[5], _source_ok_T_79 connect _source_ok_WIRE_1[6], _source_ok_T_85 connect _source_ok_WIRE_1[7], _source_ok_T_91 node _source_ok_T_92 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[2]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[3]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[4]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[5]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_97, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1418 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1418 : node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(source_ok_1, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1422 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1423 = asUInt(reset) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) when _T_1424 : node _T_1425 = eq(_T_1422, UInt<1>(0h0)) when _T_1425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1422, UInt<1>(0h1), "") : assert_54 node _T_1426 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1427 = asUInt(reset) node _T_1428 = eq(_T_1427, UInt<1>(0h0)) when _T_1428 : node _T_1429 = eq(_T_1426, UInt<1>(0h0)) when _T_1429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1426, UInt<1>(0h1), "") : assert_55 node _T_1430 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1431 = asUInt(reset) node _T_1432 = eq(_T_1431, UInt<1>(0h0)) when _T_1432 : node _T_1433 = eq(_T_1430, UInt<1>(0h0)) when _T_1433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1430, UInt<1>(0h1), "") : assert_56 node _T_1434 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(_T_1434, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1434, UInt<1>(0h1), "") : assert_57 node _T_1438 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1438 : node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(source_ok_1, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(sink_ok, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1445 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_60 node _T_1449 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1450 = asUInt(reset) node _T_1451 = eq(_T_1450, UInt<1>(0h0)) when _T_1451 : node _T_1452 = eq(_T_1449, UInt<1>(0h0)) when _T_1452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1449, UInt<1>(0h1), "") : assert_61 node _T_1453 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(_T_1453, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1453, UInt<1>(0h1), "") : assert_62 node _T_1457 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1458 = asUInt(reset) node _T_1459 = eq(_T_1458, UInt<1>(0h0)) when _T_1459 : node _T_1460 = eq(_T_1457, UInt<1>(0h0)) when _T_1460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1457, UInt<1>(0h1), "") : assert_63 node _T_1461 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1462 = or(UInt<1>(0h1), _T_1461) node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(_T_1462, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1462, UInt<1>(0h1), "") : assert_64 node _T_1466 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1466 : node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(source_ok_1, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(sink_ok, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1473 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(_T_1473, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1473, UInt<1>(0h1), "") : assert_67 node _T_1477 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1478 = asUInt(reset) node _T_1479 = eq(_T_1478, UInt<1>(0h0)) when _T_1479 : node _T_1480 = eq(_T_1477, UInt<1>(0h0)) when _T_1480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1477, UInt<1>(0h1), "") : assert_68 node _T_1481 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(_T_1481, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1481, UInt<1>(0h1), "") : assert_69 node _T_1485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1486 = or(_T_1485, io.in.d.bits.corrupt) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_70 node _T_1490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1491 = or(UInt<1>(0h1), _T_1490) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_71 node _T_1495 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1495 : node _T_1496 = asUInt(reset) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) when _T_1497 : node _T_1498 = eq(source_ok_1, UInt<1>(0h0)) when _T_1498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1500 = asUInt(reset) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) when _T_1501 : node _T_1502 = eq(_T_1499, UInt<1>(0h0)) when _T_1502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1499, UInt<1>(0h1), "") : assert_73 node _T_1503 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_74 node _T_1507 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1508 = or(UInt<1>(0h1), _T_1507) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_75 node _T_1512 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1512 : node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(source_ok_1, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1516 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_77 node _T_1520 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1521 = or(_T_1520, io.in.d.bits.corrupt) node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(_T_1521, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1521, UInt<1>(0h1), "") : assert_78 node _T_1525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1526 = or(UInt<1>(0h1), _T_1525) node _T_1527 = asUInt(reset) node _T_1528 = eq(_T_1527, UInt<1>(0h0)) when _T_1528 : node _T_1529 = eq(_T_1526, UInt<1>(0h0)) when _T_1529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1526, UInt<1>(0h1), "") : assert_79 node _T_1530 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1530 : node _T_1531 = asUInt(reset) node _T_1532 = eq(_T_1531, UInt<1>(0h0)) when _T_1532 : node _T_1533 = eq(source_ok_1, UInt<1>(0h0)) when _T_1533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1534 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_81 node _T_1538 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_82 node _T_1542 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1543 = or(UInt<1>(0h1), _T_1542) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<6>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1547 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(_T_1547, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1547, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1551 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(_T_1551, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1551, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1555 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1559 = eq(a_first, UInt<1>(0h0)) node _T_1560 = and(io.in.a.valid, _T_1559) when _T_1560 : node _T_1561 = eq(io.in.a.bits.opcode, opcode) node _T_1562 = asUInt(reset) node _T_1563 = eq(_T_1562, UInt<1>(0h0)) when _T_1563 : node _T_1564 = eq(_T_1561, UInt<1>(0h0)) when _T_1564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1561, UInt<1>(0h1), "") : assert_87 node _T_1565 = eq(io.in.a.bits.param, param) node _T_1566 = asUInt(reset) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) when _T_1567 : node _T_1568 = eq(_T_1565, UInt<1>(0h0)) when _T_1568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1565, UInt<1>(0h1), "") : assert_88 node _T_1569 = eq(io.in.a.bits.size, size) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_89 node _T_1573 = eq(io.in.a.bits.source, source) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_90 node _T_1577 = eq(io.in.a.bits.address, address) node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(_T_1577, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1577, UInt<1>(0h1), "") : assert_91 node _T_1581 = and(io.in.a.ready, io.in.a.valid) node _T_1582 = and(_T_1581, a_first) when _T_1582 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1583 = eq(d_first, UInt<1>(0h0)) node _T_1584 = and(io.in.d.valid, _T_1583) when _T_1584 : node _T_1585 = eq(io.in.d.bits.opcode, opcode_1) node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(_T_1585, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1585, UInt<1>(0h1), "") : assert_92 node _T_1589 = eq(io.in.d.bits.param, param_1) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_93 node _T_1593 = eq(io.in.d.bits.size, size_1) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_94 node _T_1597 = eq(io.in.d.bits.source, source_1) node _T_1598 = asUInt(reset) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) when _T_1599 : node _T_1600 = eq(_T_1597, UInt<1>(0h0)) when _T_1600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1597, UInt<1>(0h1), "") : assert_95 node _T_1601 = eq(io.in.d.bits.sink, sink) node _T_1602 = asUInt(reset) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) when _T_1603 : node _T_1604 = eq(_T_1601, UInt<1>(0h0)) when _T_1604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1601, UInt<1>(0h1), "") : assert_96 node _T_1605 = eq(io.in.d.bits.denied, denied) node _T_1606 = asUInt(reset) node _T_1607 = eq(_T_1606, UInt<1>(0h0)) when _T_1607 : node _T_1608 = eq(_T_1605, UInt<1>(0h0)) when _T_1608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1605, UInt<1>(0h1), "") : assert_97 node _T_1609 = and(io.in.d.ready, io.in.d.valid) node _T_1610 = and(_T_1609, d_first) when _T_1610 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<49>, clock, reset, UInt<49>(0h0) regreset inflight_opcodes : UInt<196>, clock, reset, UInt<196>(0h0) regreset inflight_sizes : UInt<392>, clock, reset, UInt<392>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<49> connect a_set, UInt<49>(0h0) wire a_set_wo_ready : UInt<49> connect a_set_wo_ready, UInt<49>(0h0) wire a_opcodes_set : UInt<196> connect a_opcodes_set, UInt<196>(0h0) wire a_sizes_set : UInt<392> connect a_sizes_set, UInt<392>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1611 = and(io.in.a.valid, a_first_1) node _T_1612 = and(_T_1611, UInt<1>(0h1)) when _T_1612 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1613 = and(io.in.a.ready, io.in.a.valid) node _T_1614 = and(_T_1613, a_first_1) node _T_1615 = and(_T_1614, UInt<1>(0h1)) when _T_1615 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1616 = dshr(inflight, io.in.a.bits.source) node _T_1617 = bits(_T_1616, 0, 0) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) node _T_1619 = asUInt(reset) node _T_1620 = eq(_T_1619, UInt<1>(0h0)) when _T_1620 : node _T_1621 = eq(_T_1618, UInt<1>(0h0)) when _T_1621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1618, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<49> connect d_clr, UInt<49>(0h0) wire d_clr_wo_ready : UInt<49> connect d_clr_wo_ready, UInt<49>(0h0) wire d_opcodes_clr : UInt<196> connect d_opcodes_clr, UInt<196>(0h0) wire d_sizes_clr : UInt<392> connect d_sizes_clr, UInt<392>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1622 = and(io.in.d.valid, d_first_1) node _T_1623 = and(_T_1622, UInt<1>(0h1)) node _T_1624 = eq(d_release_ack, UInt<1>(0h0)) node _T_1625 = and(_T_1623, _T_1624) when _T_1625 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1626 = and(io.in.d.ready, io.in.d.valid) node _T_1627 = and(_T_1626, d_first_1) node _T_1628 = and(_T_1627, UInt<1>(0h1)) node _T_1629 = eq(d_release_ack, UInt<1>(0h0)) node _T_1630 = and(_T_1628, _T_1629) when _T_1630 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1631 = and(io.in.d.valid, d_first_1) node _T_1632 = and(_T_1631, UInt<1>(0h1)) node _T_1633 = eq(d_release_ack, UInt<1>(0h0)) node _T_1634 = and(_T_1632, _T_1633) when _T_1634 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1635 = dshr(inflight, io.in.d.bits.source) node _T_1636 = bits(_T_1635, 0, 0) node _T_1637 = or(_T_1636, same_cycle_resp) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1641 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1642 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1643 = or(_T_1641, _T_1642) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_100 node _T_1647 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1648 = asUInt(reset) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(_T_1647, UInt<1>(0h0)) when _T_1650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1647, UInt<1>(0h1), "") : assert_101 else : node _T_1651 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1652 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1653 = or(_T_1651, _T_1652) node _T_1654 = asUInt(reset) node _T_1655 = eq(_T_1654, UInt<1>(0h0)) when _T_1655 : node _T_1656 = eq(_T_1653, UInt<1>(0h0)) when _T_1656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1653, UInt<1>(0h1), "") : assert_102 node _T_1657 = eq(io.in.d.bits.size, a_size_lookup) node _T_1658 = asUInt(reset) node _T_1659 = eq(_T_1658, UInt<1>(0h0)) when _T_1659 : node _T_1660 = eq(_T_1657, UInt<1>(0h0)) when _T_1660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1657, UInt<1>(0h1), "") : assert_103 node _T_1661 = and(io.in.d.valid, d_first_1) node _T_1662 = and(_T_1661, a_first_1) node _T_1663 = and(_T_1662, io.in.a.valid) node _T_1664 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1665 = and(_T_1663, _T_1664) node _T_1666 = eq(d_release_ack, UInt<1>(0h0)) node _T_1667 = and(_T_1665, _T_1666) when _T_1667 : node _T_1668 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1669 = or(_T_1668, io.in.a.ready) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_104 node _T_1673 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1674 = orr(a_set_wo_ready) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) node _T_1676 = or(_T_1673, _T_1675) node _T_1677 = asUInt(reset) node _T_1678 = eq(_T_1677, UInt<1>(0h0)) when _T_1678 : node _T_1679 = eq(_T_1676, UInt<1>(0h0)) when _T_1679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1676, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_38 node _T_1680 = orr(inflight) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) node _T_1682 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1683 = or(_T_1681, _T_1682) node _T_1684 = lt(watchdog, plusarg_reader.out) node _T_1685 = or(_T_1683, _T_1684) node _T_1686 = asUInt(reset) node _T_1687 = eq(_T_1686, UInt<1>(0h0)) when _T_1687 : node _T_1688 = eq(_T_1685, UInt<1>(0h0)) when _T_1688 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1685, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1689 = and(io.in.a.ready, io.in.a.valid) node _T_1690 = and(io.in.d.ready, io.in.d.valid) node _T_1691 = or(_T_1689, _T_1690) when _T_1691 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<49>, clock, reset, UInt<49>(0h0) regreset inflight_opcodes_1 : UInt<196>, clock, reset, UInt<196>(0h0) regreset inflight_sizes_1 : UInt<392>, clock, reset, UInt<392>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<49> connect c_set, UInt<49>(0h0) wire c_set_wo_ready : UInt<49> connect c_set_wo_ready, UInt<49>(0h0) wire c_opcodes_set : UInt<196> connect c_opcodes_set, UInt<196>(0h0) wire c_sizes_set : UInt<392> connect c_sizes_set, UInt<392>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1692 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1693 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1694 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = and(_T_1692, _T_1695) when _T_1696 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1697 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1698 = and(_T_1697, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1699 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1700 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = and(_T_1698, _T_1701) when _T_1702 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1703 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1704 = bits(_T_1703, 0, 0) node _T_1705 = eq(_T_1704, UInt<1>(0h0)) node _T_1706 = asUInt(reset) node _T_1707 = eq(_T_1706, UInt<1>(0h0)) when _T_1707 : node _T_1708 = eq(_T_1705, UInt<1>(0h0)) when _T_1708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1705, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<49> connect d_clr_1, UInt<49>(0h0) wire d_clr_wo_ready_1 : UInt<49> connect d_clr_wo_ready_1, UInt<49>(0h0) wire d_opcodes_clr_1 : UInt<196> connect d_opcodes_clr_1, UInt<196>(0h0) wire d_sizes_clr_1 : UInt<392> connect d_sizes_clr_1, UInt<392>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1709 = and(io.in.d.valid, d_first_2) node _T_1710 = and(_T_1709, UInt<1>(0h1)) node _T_1711 = and(_T_1710, d_release_ack_1) when _T_1711 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1712 = and(io.in.d.ready, io.in.d.valid) node _T_1713 = and(_T_1712, d_first_2) node _T_1714 = and(_T_1713, UInt<1>(0h1)) node _T_1715 = and(_T_1714, d_release_ack_1) when _T_1715 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1716 = and(io.in.d.valid, d_first_2) node _T_1717 = and(_T_1716, UInt<1>(0h1)) node _T_1718 = and(_T_1717, d_release_ack_1) when _T_1718 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1719 = dshr(inflight_1, io.in.d.bits.source) node _T_1720 = bits(_T_1719, 0, 0) node _T_1721 = or(_T_1720, same_cycle_resp_1) node _T_1722 = asUInt(reset) node _T_1723 = eq(_T_1722, UInt<1>(0h0)) when _T_1723 : node _T_1724 = eq(_T_1721, UInt<1>(0h0)) when _T_1724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1721, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1725 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1726 = asUInt(reset) node _T_1727 = eq(_T_1726, UInt<1>(0h0)) when _T_1727 : node _T_1728 = eq(_T_1725, UInt<1>(0h0)) when _T_1728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1725, UInt<1>(0h1), "") : assert_109 else : node _T_1729 = eq(io.in.d.bits.size, c_size_lookup) node _T_1730 = asUInt(reset) node _T_1731 = eq(_T_1730, UInt<1>(0h0)) when _T_1731 : node _T_1732 = eq(_T_1729, UInt<1>(0h0)) when _T_1732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1729, UInt<1>(0h1), "") : assert_110 node _T_1733 = and(io.in.d.valid, d_first_2) node _T_1734 = and(_T_1733, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1735 = and(_T_1734, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1736 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1737 = and(_T_1735, _T_1736) node _T_1738 = and(_T_1737, d_release_ack_1) node _T_1739 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1740 = and(_T_1738, _T_1739) when _T_1740 : node _T_1741 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<6>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1742 = or(_T_1741, _WIRE_27.ready) node _T_1743 = asUInt(reset) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) when _T_1744 : node _T_1745 = eq(_T_1742, UInt<1>(0h0)) when _T_1745 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1742, UInt<1>(0h1), "") : assert_111 node _T_1746 = orr(c_set_wo_ready) when _T_1746 : node _T_1747 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1748 = asUInt(reset) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) when _T_1749 : node _T_1750 = eq(_T_1747, UInt<1>(0h0)) when _T_1750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1747, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_39 node _T_1751 = orr(inflight_1) node _T_1752 = eq(_T_1751, UInt<1>(0h0)) node _T_1753 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1754 = or(_T_1752, _T_1753) node _T_1755 = lt(watchdog_1, plusarg_reader_1.out) node _T_1756 = or(_T_1754, _T_1755) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<6>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1760 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1761 = and(io.in.d.ready, io.in.d.valid) node _T_1762 = or(_T_1760, _T_1761) when _T_1762 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_40 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_41 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [391:0] c_sizes_set = 392'h0; // @[Monitor.scala:741:34] wire [195:0] c_opcodes_set = 196'h0; // @[Monitor.scala:740:34] wire [48:0] c_set = 49'h0; // @[Monitor.scala:738:34] wire [48:0] c_set_wo_ready = 49'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_37 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_48 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = io_in_d_bits_source_0 == 6'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_50 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_56 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_62 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_68 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_51 = _source_ok_T_50 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_57 = _source_ok_T_56 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_69 = _source_ok_T_68 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_74 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_80 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_86 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_75 = _source_ok_T_74 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_79; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_81 = _source_ok_T_80 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_87 = _source_ok_T_86 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_97 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1689 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1689; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1689; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1762 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1762; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1762; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1762; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [48:0] inflight; // @[Monitor.scala:614:27] reg [195:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [391:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [48:0] a_set; // @[Monitor.scala:626:34] wire [48:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [195:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [391:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [195:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [195:0] _a_opcode_lookup_T_6 = {192'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [195:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[195:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [391:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [391:0] _a_size_lookup_T_6 = {384'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [391:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[391:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire _T_1615 = _T_1689 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1615 ? _a_set_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1615 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1615 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1615 ? _a_opcodes_set_T_1[195:0] : 196'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1615 ? _a_sizes_set_T_1[391:0] : 392'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [48:0] d_clr; // @[Monitor.scala:664:34] wire [48:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [195:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [391:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1661 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1661 & ~d_release_ack ? _d_clr_wo_ready_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire _T_1630 = _T_1762 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1630 ? _d_clr_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1630 ? _d_opcodes_clr_T_5[195:0] : 196'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1630 ? _d_sizes_clr_T_5[391:0] : 392'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [48:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [48:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [48:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [195:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [195:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [195:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [391:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [391:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [391:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [48:0] inflight_1; // @[Monitor.scala:726:35] wire [48:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [195:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [195:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [391:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [391:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [195:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [195:0] _c_opcode_lookup_T_6 = {192'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [195:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[195:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [391:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [391:0] _c_size_lookup_T_6 = {384'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [391:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[391:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [48:0] d_clr_1; // @[Monitor.scala:774:34] wire [48:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [195:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [391:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1733 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1733 & d_release_ack_1 ? _d_clr_wo_ready_T_1[48:0] : 49'h0; // @[OneHot.scala:58:35] wire _T_1715 = _T_1762 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1715 ? _d_clr_T_1[48:0] : 49'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1715 ? _d_opcodes_clr_T_11[195:0] : 196'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1715 ? _d_sizes_clr_T_11[391:0] : 392'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [48:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [48:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [195:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [195:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [391:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [391:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_25 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut

module MulFullRawFN_25( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _T_889 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_890 = orr(a_set_wo_ready) node _T_891 = eq(_T_890, UInt<1>(0h0)) node _T_892 = or(_T_889, _T_891) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_892, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_97 node _T_896 = orr(inflight) node _T_897 = eq(_T_896, UInt<1>(0h0)) node _T_898 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_899 = or(_T_897, _T_898) node _T_900 = lt(watchdog, plusarg_reader.out) node _T_901 = or(_T_899, _T_900) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_901, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_905 = and(io.in.a.ready, io.in.a.valid) node _T_906 = and(io.in.d.ready, io.in.d.valid) node _T_907 = or(_T_905, _T_906) when _T_907 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_908 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_909 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_910 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_911 = and(_T_909, _T_910) node _T_912 = and(_T_908, _T_911) when _T_912 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_913 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_914 = and(_T_913, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_915 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_916 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_917 = and(_T_915, _T_916) node _T_918 = and(_T_914, _T_917) when _T_918 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_919 = dshr(inflight_1, _WIRE_15.bits.source) node _T_920 = bits(_T_919, 0, 0) node _T_921 = eq(_T_920, UInt<1>(0h0)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_921, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_928 = and(io.in.d.ready, io.in.d.valid) node _T_929 = and(_T_928, d_first_2) node _T_930 = and(_T_929, UInt<1>(0h1)) node _T_931 = and(_T_930, d_release_ack_1) when _T_931 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_932 = and(io.in.d.valid, d_first_2) node _T_933 = and(_T_932, UInt<1>(0h1)) node _T_934 = and(_T_933, d_release_ack_1) when _T_934 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_935 = dshr(inflight_1, io.in.d.bits.source) node _T_936 = bits(_T_935, 0, 0) node _T_937 = or(_T_936, same_cycle_resp_1) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_937, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_941 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_941, UInt<1>(0h1), "") : assert_109 else : node _T_945 = eq(io.in.d.bits.size, c_size_lookup) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_945, UInt<1>(0h1), "") : assert_110 node _T_949 = and(io.in.d.valid, d_first_2) node _T_950 = and(_T_949, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_951 = and(_T_950, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_952 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_953 = and(_T_951, _T_952) node _T_954 = and(_T_953, d_release_ack_1) node _T_955 = eq(c_probe_ack, UInt<1>(0h0)) node _T_956 = and(_T_954, _T_955) when _T_956 : node _T_957 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_958 = or(_T_957, _WIRE_23.ready) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_958, UInt<1>(0h1), "") : assert_111 node _T_962 = orr(c_set_wo_ready) when _T_962 : node _T_963 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_963, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_98 node _T_967 = orr(inflight_1) node _T_968 = eq(_T_967, UInt<1>(0h0)) node _T_969 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_970 = or(_T_968, _T_969) node _T_971 = lt(watchdog_1, plusarg_reader_1.out) node _T_972 = or(_T_970, _T_971) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_972, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_976 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_977 = and(io.in.d.ready, io.in.d.valid) node _T_978 = or(_T_976, _T_977) when _T_978 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_30 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}}, resp : { `2` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, `1` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, `0` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, channel_status : { flip `3` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5]}, out_allocs : { `3` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5]}} regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire in_arb_reqs : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}[3] wire in_arb_vals : UInt<1>[3] node in_arb_filter_hi = cat(in_arb_vals[2], in_arb_vals[1]) node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_vals[0]) node in_arb_filter_hi_1 = cat(in_arb_vals[2], in_arb_vals[1]) node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_vals[0]) node _in_arb_filter_T_2 = not(mask) node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2) node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3) node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0) node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1) node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2) node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3) node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4) node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5) node _in_arb_filter_T_11 = mux(_in_arb_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _in_arb_filter_T_12 = mux(_in_arb_filter_T_9, UInt<6>(0h10), _in_arb_filter_T_11) node _in_arb_filter_T_13 = mux(_in_arb_filter_T_8, UInt<6>(0h8), _in_arb_filter_T_12) node _in_arb_filter_T_14 = mux(_in_arb_filter_T_7, UInt<6>(0h4), _in_arb_filter_T_13) node _in_arb_filter_T_15 = mux(_in_arb_filter_T_6, UInt<6>(0h2), _in_arb_filter_T_14) node in_arb_filter = mux(_in_arb_filter_T_5, UInt<6>(0h1), _in_arb_filter_T_15) node _in_arb_sel_T = bits(in_arb_filter, 2, 0) node _in_arb_sel_T_1 = shr(in_arb_filter, 3) node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1) node _T = or(in_arb_vals[0], in_arb_vals[1]) node _T_1 = or(_T, in_arb_vals[2]) when _T_1 : node _mask_T = not(UInt<1>(0h0)) node _mask_T_1 = not(UInt<2>(0h0)) node _mask_T_2 = not(UInt<3>(0h0)) node _mask_T_3 = bits(in_arb_sel, 0, 0) node _mask_T_4 = bits(in_arb_sel, 1, 1) node _mask_T_5 = bits(in_arb_sel, 2, 2) node _mask_T_6 = mux(_mask_T_3, _mask_T, UInt<1>(0h0)) node _mask_T_7 = mux(_mask_T_4, _mask_T_1, UInt<1>(0h0)) node _mask_T_8 = mux(_mask_T_5, _mask_T_2, UInt<1>(0h0)) node _mask_T_9 = or(_mask_T_6, _mask_T_7) node _mask_T_10 = or(_mask_T_9, _mask_T_8) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_10 connect mask, _mask_WIRE node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T) connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1 node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T) connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1 node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T) connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1 node _in_arb_reqs_0_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_3_T_1 = and(io.req.`0`.bits.vc_sel.`0`[3], _in_arb_reqs_0_0_3_T) connect in_arb_reqs[0].`0`[3], _in_arb_reqs_0_0_3_T_1 node _in_arb_reqs_0_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_4_T_1 = and(io.req.`0`.bits.vc_sel.`0`[4], _in_arb_reqs_0_0_4_T) connect in_arb_reqs[0].`0`[4], _in_arb_reqs_0_0_4_T_1 node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T) connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1 node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T) connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1 node _in_arb_reqs_0_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_3_0_T_1 = and(io.req.`0`.bits.vc_sel.`3`[0], _in_arb_reqs_0_3_0_T) connect in_arb_reqs[0].`3`[0], _in_arb_reqs_0_3_0_T_1 node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1]) node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2]) node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T_1, in_arb_reqs[0].`0`[3]) node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`0`[4]) node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T_3, in_arb_reqs[0].`1`[0]) node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`2`[0]) node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`3`[0]) node _in_arb_vals_0_T_7 = and(io.req.`0`.valid, _in_arb_vals_0_T_6) connect in_arb_vals[0], _in_arb_vals_0_T_7 node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T) connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1 node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T) connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1 node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T) connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1 node _in_arb_reqs_1_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_3_T_1 = and(io.req.`1`.bits.vc_sel.`0`[3], _in_arb_reqs_1_0_3_T) connect in_arb_reqs[1].`0`[3], _in_arb_reqs_1_0_3_T_1 node _in_arb_reqs_1_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_4_T_1 = and(io.req.`1`.bits.vc_sel.`0`[4], _in_arb_reqs_1_0_4_T) connect in_arb_reqs[1].`0`[4], _in_arb_reqs_1_0_4_T_1 node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T) connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1 node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T) connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1 node _in_arb_reqs_1_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_3_0_T_1 = and(io.req.`1`.bits.vc_sel.`3`[0], _in_arb_reqs_1_3_0_T) connect in_arb_reqs[1].`3`[0], _in_arb_reqs_1_3_0_T_1 node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1]) node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2]) node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T_1, in_arb_reqs[1].`0`[3]) node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`0`[4]) node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T_3, in_arb_reqs[1].`1`[0]) node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`2`[0]) node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`3`[0]) node _in_arb_vals_1_T_7 = and(io.req.`1`.valid, _in_arb_vals_1_T_6) connect in_arb_vals[1], _in_arb_vals_1_T_7 node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T) connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1 node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T) connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1 node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T) connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1 node _in_arb_reqs_2_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_3_T_1 = and(io.req.`2`.bits.vc_sel.`0`[3], _in_arb_reqs_2_0_3_T) connect in_arb_reqs[2].`0`[3], _in_arb_reqs_2_0_3_T_1 node _in_arb_reqs_2_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_4_T_1 = and(io.req.`2`.bits.vc_sel.`0`[4], _in_arb_reqs_2_0_4_T) connect in_arb_reqs[2].`0`[4], _in_arb_reqs_2_0_4_T_1 node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T) connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1 node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T) connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1 node _in_arb_reqs_2_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_3_0_T_1 = and(io.req.`2`.bits.vc_sel.`3`[0], _in_arb_reqs_2_3_0_T) connect in_arb_reqs[2].`3`[0], _in_arb_reqs_2_3_0_T_1 node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1]) node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2]) node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T_1, in_arb_reqs[2].`0`[3]) node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`0`[4]) node _in_arb_vals_2_T_4 = or(_in_arb_vals_2_T_3, in_arb_reqs[2].`1`[0]) node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`2`[0]) node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, in_arb_reqs[2].`3`[0]) node _in_arb_vals_2_T_7 = and(io.req.`2`.valid, _in_arb_vals_2_T_6) connect in_arb_vals[2], _in_arb_vals_2_T_7 connect io.req.`0`.ready, UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h0) wire in_alloc : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]} node _in_flow_T = bits(in_arb_sel, 0, 0) node _in_flow_T_1 = bits(in_arb_sel, 1, 1) node _in_flow_T_2 = bits(in_arb_sel, 2, 2) wire in_flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _in_flow_T_3 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_4 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_5 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_6 = or(_in_flow_T_3, _in_flow_T_4) node _in_flow_T_7 = or(_in_flow_T_6, _in_flow_T_5) wire _in_flow_WIRE : UInt<2> connect _in_flow_WIRE, _in_flow_T_7 connect in_flow.egress_node_id, _in_flow_WIRE node _in_flow_T_8 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_9 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_10 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_11 = or(_in_flow_T_8, _in_flow_T_9) node _in_flow_T_12 = or(_in_flow_T_11, _in_flow_T_10) wire _in_flow_WIRE_1 : UInt<5> connect _in_flow_WIRE_1, _in_flow_T_12 connect in_flow.egress_node, _in_flow_WIRE_1 node _in_flow_T_13 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_14 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_15 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_16 = or(_in_flow_T_13, _in_flow_T_14) node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_15) wire _in_flow_WIRE_2 : UInt<2> connect _in_flow_WIRE_2, _in_flow_T_17 connect in_flow.ingress_node_id, _in_flow_WIRE_2 node _in_flow_T_18 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_19 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_20 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_21 = or(_in_flow_T_18, _in_flow_T_19) node _in_flow_T_22 = or(_in_flow_T_21, _in_flow_T_20) wire _in_flow_WIRE_3 : UInt<5> connect _in_flow_WIRE_3, _in_flow_T_22 connect in_flow.ingress_node, _in_flow_WIRE_3 node _in_flow_T_23 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_24 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_25 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_26 = or(_in_flow_T_23, _in_flow_T_24) node _in_flow_T_27 = or(_in_flow_T_26, _in_flow_T_25) wire _in_flow_WIRE_4 : UInt<3> connect _in_flow_WIRE_4, _in_flow_T_27 connect in_flow.vnet_id, _in_flow_WIRE_4 node _in_vc_T = bits(in_arb_sel, 0, 0) node _in_vc_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_T_3 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_4 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_5 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_6 = or(_in_vc_T_3, _in_vc_T_4) node _in_vc_T_7 = or(_in_vc_T_6, _in_vc_T_5) wire in_vc : UInt<3> connect in_vc, _in_vc_T_7 node _in_vc_sel_T = bits(in_arb_sel, 0, 0) node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2) wire in_vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]} wire _in_vc_sel_WIRE : UInt<1>[5] node _in_vc_sel_T_3 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_4 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_5 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_6 = or(_in_vc_sel_T_3, _in_vc_sel_T_4) node _in_vc_sel_T_7 = or(_in_vc_sel_T_6, _in_vc_sel_T_5) wire _in_vc_sel_WIRE_1 : UInt<1> connect _in_vc_sel_WIRE_1, _in_vc_sel_T_7 connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1 node _in_vc_sel_T_8 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_9 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_10 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_11 = or(_in_vc_sel_T_8, _in_vc_sel_T_9) node _in_vc_sel_T_12 = or(_in_vc_sel_T_11, _in_vc_sel_T_10) wire _in_vc_sel_WIRE_2 : UInt<1> connect _in_vc_sel_WIRE_2, _in_vc_sel_T_12 connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2 node _in_vc_sel_T_13 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_14 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_15 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_16 = or(_in_vc_sel_T_13, _in_vc_sel_T_14) node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_15) wire _in_vc_sel_WIRE_3 : UInt<1> connect _in_vc_sel_WIRE_3, _in_vc_sel_T_17 connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3 node _in_vc_sel_T_18 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_19 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_20 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_21 = or(_in_vc_sel_T_18, _in_vc_sel_T_19) node _in_vc_sel_T_22 = or(_in_vc_sel_T_21, _in_vc_sel_T_20) wire _in_vc_sel_WIRE_4 : UInt<1> connect _in_vc_sel_WIRE_4, _in_vc_sel_T_22 connect _in_vc_sel_WIRE[3], _in_vc_sel_WIRE_4 node _in_vc_sel_T_23 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_24 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_25 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_26 = or(_in_vc_sel_T_23, _in_vc_sel_T_24) node _in_vc_sel_T_27 = or(_in_vc_sel_T_26, _in_vc_sel_T_25) wire _in_vc_sel_WIRE_5 : UInt<1> connect _in_vc_sel_WIRE_5, _in_vc_sel_T_27 connect _in_vc_sel_WIRE[4], _in_vc_sel_WIRE_5 connect in_vc_sel.`0`, _in_vc_sel_WIRE wire _in_vc_sel_WIRE_6 : UInt<1>[1] node _in_vc_sel_T_28 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_29 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_30 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_31 = or(_in_vc_sel_T_28, _in_vc_sel_T_29) node _in_vc_sel_T_32 = or(_in_vc_sel_T_31, _in_vc_sel_T_30) wire _in_vc_sel_WIRE_7 : UInt<1> connect _in_vc_sel_WIRE_7, _in_vc_sel_T_32 connect _in_vc_sel_WIRE_6[0], _in_vc_sel_WIRE_7 connect in_vc_sel.`1`, _in_vc_sel_WIRE_6 wire _in_vc_sel_WIRE_8 : UInt<1>[1] node _in_vc_sel_T_33 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_34 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_35 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_36 = or(_in_vc_sel_T_33, _in_vc_sel_T_34) node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_35) wire _in_vc_sel_WIRE_9 : UInt<1> connect _in_vc_sel_WIRE_9, _in_vc_sel_T_37 connect _in_vc_sel_WIRE_8[0], _in_vc_sel_WIRE_9 connect in_vc_sel.`2`, _in_vc_sel_WIRE_8 wire _in_vc_sel_WIRE_10 : UInt<1>[1] node _in_vc_sel_T_38 = mux(_in_vc_sel_T, in_arb_reqs[0].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_39 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_40 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_41 = or(_in_vc_sel_T_38, _in_vc_sel_T_39) node _in_vc_sel_T_42 = or(_in_vc_sel_T_41, _in_vc_sel_T_40) wire _in_vc_sel_WIRE_11 : UInt<1> connect _in_vc_sel_WIRE_11, _in_vc_sel_T_42 connect _in_vc_sel_WIRE_10[0], _in_vc_sel_WIRE_11 connect in_vc_sel.`3`, _in_vc_sel_WIRE_10 node _T_2 = or(in_arb_vals[0], in_arb_vals[1]) node _T_3 = or(_T_2, in_arb_vals[2]) node hi = bits(in_arb_sel, 2, 2) node lo = bits(in_arb_sel, 1, 0) node _T_4 = orr(hi) node _T_5 = or(hi, lo) node _T_6 = bits(_T_5, 1, 1) node _T_7 = cat(_T_4, _T_6) node _T_8 = and(io.req.`0`.ready, io.req.`0`.valid) node _T_9 = and(io.req.`1`.ready, io.req.`1`.valid) node _T_10 = and(io.req.`2`.ready, io.req.`2`.valid) node _T_11 = or(_T_8, _T_9) node _T_12 = or(_T_11, _T_10) node lo_1 = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0]) node hi_hi = cat(in_vc_sel.`0`[4], in_vc_sel.`0`[3]) node hi_1 = cat(hi_hi, in_vc_sel.`0`[2]) node _T_13 = cat(hi_1, lo_1) node lo_2 = cat(in_vc_sel.`1`[0], _T_13) node hi_2 = cat(in_vc_sel.`3`[0], in_vc_sel.`2`[0]) node _T_14 = cat(hi_2, lo_2) regreset mask_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _full_T = not(mask_1) node _full_T_1 = and(_T_14, _full_T) node full = cat(_T_14, _full_T_1) node _oh_T = bits(full, 0, 0) node _oh_T_1 = bits(full, 1, 1) node _oh_T_2 = bits(full, 2, 2) node _oh_T_3 = bits(full, 3, 3) node _oh_T_4 = bits(full, 4, 4) node _oh_T_5 = bits(full, 5, 5) node _oh_T_6 = bits(full, 6, 6) node _oh_T_7 = bits(full, 7, 7) node _oh_T_8 = bits(full, 8, 8) node _oh_T_9 = bits(full, 9, 9) node _oh_T_10 = bits(full, 10, 10) node _oh_T_11 = bits(full, 11, 11) node _oh_T_12 = bits(full, 12, 12) node _oh_T_13 = bits(full, 13, 13) node _oh_T_14 = bits(full, 14, 14) node _oh_T_15 = bits(full, 15, 15) node _oh_T_16 = mux(_oh_T_15, UInt<16>(0h8000), UInt<16>(0h0)) node _oh_T_17 = mux(_oh_T_14, UInt<16>(0h4000), _oh_T_16) node _oh_T_18 = mux(_oh_T_13, UInt<16>(0h2000), _oh_T_17) node _oh_T_19 = mux(_oh_T_12, UInt<16>(0h1000), _oh_T_18) node _oh_T_20 = mux(_oh_T_11, UInt<16>(0h800), _oh_T_19) node _oh_T_21 = mux(_oh_T_10, UInt<16>(0h400), _oh_T_20) node _oh_T_22 = mux(_oh_T_9, UInt<16>(0h200), _oh_T_21) node _oh_T_23 = mux(_oh_T_8, UInt<16>(0h100), _oh_T_22) node _oh_T_24 = mux(_oh_T_7, UInt<16>(0h80), _oh_T_23) node _oh_T_25 = mux(_oh_T_6, UInt<16>(0h40), _oh_T_24) node _oh_T_26 = mux(_oh_T_5, UInt<16>(0h20), _oh_T_25) node _oh_T_27 = mux(_oh_T_4, UInt<16>(0h10), _oh_T_26) node _oh_T_28 = mux(_oh_T_3, UInt<16>(0h8), _oh_T_27) node _oh_T_29 = mux(_oh_T_2, UInt<16>(0h4), _oh_T_28) node _oh_T_30 = mux(_oh_T_1, UInt<16>(0h2), _oh_T_29) node oh = mux(_oh_T, UInt<16>(0h1), _oh_T_30) node _sel_T = bits(oh, 7, 0) node _sel_T_1 = shr(oh, 8) node sel = or(_sel_T, _sel_T_1) when _T_12 : node _mask_T_11 = bits(sel, 0, 0) node _mask_T_12 = not(UInt<1>(0h0)) node _mask_T_13 = bits(sel, 1, 1) node _mask_T_14 = not(UInt<2>(0h0)) node _mask_T_15 = bits(sel, 2, 2) node _mask_T_16 = not(UInt<3>(0h0)) node _mask_T_17 = bits(sel, 3, 3) node _mask_T_18 = not(UInt<4>(0h0)) node _mask_T_19 = bits(sel, 4, 4) node _mask_T_20 = not(UInt<5>(0h0)) node _mask_T_21 = bits(sel, 5, 5) node _mask_T_22 = not(UInt<6>(0h0)) node _mask_T_23 = bits(sel, 6, 6) node _mask_T_24 = not(UInt<7>(0h0)) node _mask_T_25 = bits(sel, 7, 7) node _mask_T_26 = not(UInt<8>(0h0)) node _mask_T_27 = mux(_mask_T_25, _mask_T_26, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_23, _mask_T_24, _mask_T_27) node _mask_T_29 = mux(_mask_T_21, _mask_T_22, _mask_T_28) node _mask_T_30 = mux(_mask_T_19, _mask_T_20, _mask_T_29) node _mask_T_31 = mux(_mask_T_17, _mask_T_18, _mask_T_30) node _mask_T_32 = mux(_mask_T_15, _mask_T_16, _mask_T_31) node _mask_T_33 = mux(_mask_T_13, _mask_T_14, _mask_T_32) node _mask_T_34 = mux(_mask_T_11, _mask_T_12, _mask_T_33) connect mask_1, _mask_T_34 wire _WIRE : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]} wire _WIRE_1 : UInt<8> connect _WIRE_1, sel node _T_15 = bits(_WIRE_1, 0, 0) connect _WIRE.`0`[0], _T_15 node _T_16 = bits(_WIRE_1, 1, 1) connect _WIRE.`0`[1], _T_16 node _T_17 = bits(_WIRE_1, 2, 2) connect _WIRE.`0`[2], _T_17 node _T_18 = bits(_WIRE_1, 3, 3) connect _WIRE.`0`[3], _T_18 node _T_19 = bits(_WIRE_1, 4, 4) connect _WIRE.`0`[4], _T_19 node _T_20 = bits(_WIRE_1, 5, 5) connect _WIRE.`1`[0], _T_20 node _T_21 = bits(_WIRE_1, 6, 6) connect _WIRE.`2`[0], _T_21 node _T_22 = bits(_WIRE_1, 7, 7) connect _WIRE.`3`[0], _T_22 wire _WIRE_2 : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]} connect _WIRE_2.`0`[0], UInt<1>(0h0) connect _WIRE_2.`0`[1], UInt<1>(0h0) connect _WIRE_2.`0`[2], UInt<1>(0h0) connect _WIRE_2.`0`[3], UInt<1>(0h0) connect _WIRE_2.`0`[4], UInt<1>(0h0) connect _WIRE_2.`1`[0], UInt<1>(0h0) connect _WIRE_2.`2`[0], UInt<1>(0h0) connect _WIRE_2.`3`[0], UInt<1>(0h0) node _T_23 = mux(_T_3, _WIRE, _WIRE_2) connect in_alloc.`0`, _T_23.`0` connect in_alloc.`1`, _T_23.`1` connect in_alloc.`2`, _T_23.`2` connect in_alloc.`3`, _T_23.`3` node _io_req_0_ready_T = bits(in_arb_sel, 0, 0) connect io.req.`0`.ready, _io_req_0_ready_T connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`0`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`0`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`0`.vc_sel.`3`[0], in_alloc.`3`[0] node lo_3 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0]) node hi_hi_1 = cat(io.resp.`0`.vc_sel.`0`[4], io.resp.`0`.vc_sel.`0`[3]) node hi_3 = cat(hi_hi_1, io.resp.`0`.vc_sel.`0`[2]) node _T_24 = cat(hi_3, lo_3) node lo_4 = cat(io.resp.`0`.vc_sel.`1`[0], _T_24) node hi_4 = cat(io.resp.`0`.vc_sel.`3`[0], io.resp.`0`.vc_sel.`2`[0]) node _T_25 = cat(hi_4, lo_4) node _T_26 = bits(_T_25, 0, 0) node _T_27 = bits(_T_25, 1, 1) node _T_28 = bits(_T_25, 2, 2) node _T_29 = bits(_T_25, 3, 3) node _T_30 = bits(_T_25, 4, 4) node _T_31 = bits(_T_25, 5, 5) node _T_32 = bits(_T_25, 6, 6) node _T_33 = bits(_T_25, 7, 7) node _T_34 = add(_T_26, _T_27) node _T_35 = bits(_T_34, 1, 0) node _T_36 = add(_T_28, _T_29) node _T_37 = bits(_T_36, 1, 0) node _T_38 = add(_T_35, _T_37) node _T_39 = bits(_T_38, 2, 0) node _T_40 = add(_T_30, _T_31) node _T_41 = bits(_T_40, 1, 0) node _T_42 = add(_T_32, _T_33) node _T_43 = bits(_T_42, 1, 0) node _T_44 = add(_T_41, _T_43) node _T_45 = bits(_T_44, 2, 0) node _T_46 = add(_T_39, _T_45) node _T_47 = bits(_T_46, 3, 0) node _T_48 = leq(_T_47, UInt<1>(0h1)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf assert(clock, _T_48, UInt<1>(0h1), "") : assert node _io_req_1_ready_T = bits(in_arb_sel, 1, 1) connect io.req.`1`.ready, _io_req_1_ready_T connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`1`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`1`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`1`.vc_sel.`3`[0], in_alloc.`3`[0] node lo_5 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0]) node hi_hi_2 = cat(io.resp.`1`.vc_sel.`0`[4], io.resp.`1`.vc_sel.`0`[3]) node hi_5 = cat(hi_hi_2, io.resp.`1`.vc_sel.`0`[2]) node _T_52 = cat(hi_5, lo_5) node lo_6 = cat(io.resp.`1`.vc_sel.`1`[0], _T_52) node hi_6 = cat(io.resp.`1`.vc_sel.`3`[0], io.resp.`1`.vc_sel.`2`[0]) node _T_53 = cat(hi_6, lo_6) node _T_54 = bits(_T_53, 0, 0) node _T_55 = bits(_T_53, 1, 1) node _T_56 = bits(_T_53, 2, 2) node _T_57 = bits(_T_53, 3, 3) node _T_58 = bits(_T_53, 4, 4) node _T_59 = bits(_T_53, 5, 5) node _T_60 = bits(_T_53, 6, 6) node _T_61 = bits(_T_53, 7, 7) node _T_62 = add(_T_54, _T_55) node _T_63 = bits(_T_62, 1, 0) node _T_64 = add(_T_56, _T_57) node _T_65 = bits(_T_64, 1, 0) node _T_66 = add(_T_63, _T_65) node _T_67 = bits(_T_66, 2, 0) node _T_68 = add(_T_58, _T_59) node _T_69 = bits(_T_68, 1, 0) node _T_70 = add(_T_60, _T_61) node _T_71 = bits(_T_70, 1, 0) node _T_72 = add(_T_69, _T_71) node _T_73 = bits(_T_72, 2, 0) node _T_74 = add(_T_67, _T_73) node _T_75 = bits(_T_74, 3, 0) node _T_76 = leq(_T_75, UInt<1>(0h1)) node _T_77 = asUInt(reset) node _T_78 = eq(_T_77, UInt<1>(0h0)) when _T_78 : node _T_79 = eq(_T_76, UInt<1>(0h0)) when _T_79 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1 assert(clock, _T_76, UInt<1>(0h1), "") : assert_1 node _io_req_2_ready_T = bits(in_arb_sel, 2, 2) connect io.req.`2`.ready, _io_req_2_ready_T connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`2`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`2`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`2`.vc_sel.`3`[0], in_alloc.`3`[0] node lo_7 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0]) node hi_hi_3 = cat(io.resp.`2`.vc_sel.`0`[4], io.resp.`2`.vc_sel.`0`[3]) node hi_7 = cat(hi_hi_3, io.resp.`2`.vc_sel.`0`[2]) node _T_80 = cat(hi_7, lo_7) node lo_8 = cat(io.resp.`2`.vc_sel.`1`[0], _T_80) node hi_8 = cat(io.resp.`2`.vc_sel.`3`[0], io.resp.`2`.vc_sel.`2`[0]) node _T_81 = cat(hi_8, lo_8) node _T_82 = bits(_T_81, 0, 0) node _T_83 = bits(_T_81, 1, 1) node _T_84 = bits(_T_81, 2, 2) node _T_85 = bits(_T_81, 3, 3) node _T_86 = bits(_T_81, 4, 4) node _T_87 = bits(_T_81, 5, 5) node _T_88 = bits(_T_81, 6, 6) node _T_89 = bits(_T_81, 7, 7) node _T_90 = add(_T_82, _T_83) node _T_91 = bits(_T_90, 1, 0) node _T_92 = add(_T_84, _T_85) node _T_93 = bits(_T_92, 1, 0) node _T_94 = add(_T_91, _T_93) node _T_95 = bits(_T_94, 2, 0) node _T_96 = add(_T_86, _T_87) node _T_97 = bits(_T_96, 1, 0) node _T_98 = add(_T_88, _T_89) node _T_99 = bits(_T_98, 1, 0) node _T_100 = add(_T_97, _T_99) node _T_101 = bits(_T_100, 2, 0) node _T_102 = add(_T_95, _T_101) node _T_103 = bits(_T_102, 3, 0) node _T_104 = leq(_T_103, UInt<1>(0h1)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2 assert(clock, _T_104, UInt<1>(0h1), "") : assert_2 connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0] connect io.out_allocs.`0`[0].flow, in_flow connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1] connect io.out_allocs.`0`[1].flow, in_flow connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2] connect io.out_allocs.`0`[2].flow, in_flow connect io.out_allocs.`0`[3].alloc, in_alloc.`0`[3] connect io.out_allocs.`0`[3].flow, in_flow connect io.out_allocs.`0`[4].alloc, in_alloc.`0`[4] connect io.out_allocs.`0`[4].flow, in_flow connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0] connect io.out_allocs.`1`[0].flow, in_flow connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0] connect io.out_allocs.`2`[0].flow, in_flow connect io.out_allocs.`3`[0].alloc, in_alloc.`3`[0] connect io.out_allocs.`3`[0].flow, in_flow

module RotatingSingleVCAllocator_30( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_1_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [2:0] mask; // @[SingleVCAllocator.scala:16:21] wire [2:0] _in_arb_filter_T_3 = {in_arb_vals_2, 1'h0, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [5:0] in_arb_filter = _in_arb_filter_T_3[0] ? 6'h1 : _in_arb_filter_T_3[1] ? 6'h2 : _in_arb_filter_T_3[2] ? 6'h4 : in_arb_vals_0 ? 6'h8 : {in_arb_vals_2, 5'h0}; // @[OneHot.scala:85:71] wire [2:0] in_arb_sel = in_arb_filter[2:0] | in_arb_filter[5:3]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 | in_arb_vals_2; // @[package.scala:81:59] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_1_0 | in_arb_reqs_0_2_0 | in_arb_reqs_0_3_0); // @[package.scala:81:59] wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_3_0 = io_req_2_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (io_req_2_bits_vc_sel_0_0 | in_arb_reqs_2_0_1 | io_req_2_bits_vc_sel_0_2 | io_req_2_bits_vc_sel_0_3 | io_req_2_bits_vc_sel_0_4 | in_arb_reqs_2_1_0 | in_arb_reqs_2_2_0 | in_arb_reqs_2_3_0); // @[package.scala:81:59] wire _in_vc_sel_T_5 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_10 = in_arb_sel[2] & in_arb_reqs_2_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_15 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_20 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_25 = in_arb_sel[2] & io_req_2_bits_vc_sel_0_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_32 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[2] & in_arb_reqs_2_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_37 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[2] & in_arb_reqs_2_2_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_42 = in_arb_sel[0] & in_arb_reqs_0_3_0 | in_arb_sel[2] & in_arb_reqs_2_3_0; // @[Mux.scala:30:73, :32:36] reg [7:0] mask_1; // @[ISLIP.scala:17:25] wire [7:0] _full_T_1 = {_in_vc_sel_T_42, _in_vc_sel_T_37, _in_vc_sel_T_32, _in_vc_sel_T_25, _in_vc_sel_T_20, _in_vc_sel_T_15, _in_vc_sel_T_10, _in_vc_sel_T_5} & ~mask_1; // @[Mux.scala:30:73] wire [15:0] oh = _full_T_1[0] ? 16'h1 : _full_T_1[1] ? 16'h2 : _full_T_1[2] ? 16'h4 : _full_T_1[3] ? 16'h8 : _full_T_1[4] ? 16'h10 : _full_T_1[5] ? 16'h20 : _full_T_1[6] ? 16'h40 : _full_T_1[7] ? 16'h80 : _in_vc_sel_T_5 ? 16'h100 : _in_vc_sel_T_10 ? 16'h200 : _in_vc_sel_T_15 ? 16'h400 : _in_vc_sel_T_20 ? 16'h800 : _in_vc_sel_T_25 ? 16'h1000 : _in_vc_sel_T_32 ? 16'h2000 : _in_vc_sel_T_37 ? 16'h4000 : {_in_vc_sel_T_42, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] sel = oh[7:0] | oh[15:8]; // @[Mux.scala:50:70] wire in_alloc_3_0 = _GEN & sel[7]; // @[package.scala:81:59] wire in_alloc_2_0 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59] wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59]

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_4 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}} wire _in_flight_WIRE : UInt<1>[8] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_41 = and(_T_39, _T_40) node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_45 = and(_T_43, _T_44) node _T_46 = or(_T_17, _T_24) node _T_47 = or(_T_46, _T_31) node _T_48 = or(_T_47, _T_38) node _T_49 = or(_T_48, _T_45) node _T_50 = or(_T_10, _T_49) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_50, UInt<1>(0h1), "") : assert_2 node _T_54 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_71 = and(_T_69, _T_70) node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_75 = and(_T_73, _T_74) node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_61, _T_68) node _T_91 = or(_T_90, _T_75) node _T_92 = or(_T_91, _T_82) node _T_93 = or(_T_92, _T_89) node _T_94 = or(_T_54, _T_93) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_94, UInt<1>(0h1), "") : assert_3 node _T_98 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_100 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_105 = and(_T_103, _T_104) node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_112 = and(_T_110, _T_111) node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_121 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_128 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_135 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_136 = and(_T_134, _T_135) node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_142 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_149 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_156 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(_T_105, _T_112) node _T_163 = or(_T_162, _T_119) node _T_164 = or(_T_163, _T_126) node _T_165 = or(_T_164, _T_133) node _T_166 = or(_T_165, _T_140) node _T_167 = or(_T_166, _T_147) node _T_168 = or(_T_167, _T_154) node _T_169 = or(_T_168, _T_161) node _T_170 = or(_T_98, _T_169) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_170, UInt<1>(0h1), "") : assert_4 node _T_174 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_176 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_179 = and(_T_177, _T_178) node _T_180 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_181 = and(_T_179, _T_180) node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_183 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_190 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_191 = and(_T_189, _T_190) node _T_192 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_193 = and(_T_191, _T_192) node _T_194 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_195 = and(_T_193, _T_194) node _T_196 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_197 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_204 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_205 = and(_T_203, _T_204) node _T_206 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_207 = and(_T_205, _T_206) node _T_208 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_211 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_212 = and(_T_210, _T_211) node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_214 = and(_T_212, _T_213) node _T_215 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_218 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_219 = and(_T_217, _T_218) node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_221 = and(_T_219, _T_220) node _T_222 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_225 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_226 = and(_T_224, _T_225) node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_232 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_233 = and(_T_231, _T_232) node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_235 = and(_T_233, _T_234) node _T_236 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_237 = and(_T_235, _T_236) node _T_238 = or(_T_181, _T_188) node _T_239 = or(_T_238, _T_195) node _T_240 = or(_T_239, _T_202) node _T_241 = or(_T_240, _T_209) node _T_242 = or(_T_241, _T_216) node _T_243 = or(_T_242, _T_223) node _T_244 = or(_T_243, _T_230) node _T_245 = or(_T_244, _T_237) node _T_246 = or(_T_174, _T_245) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_246, UInt<1>(0h1), "") : assert_5 node _T_250 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_255 = and(_T_253, _T_254) node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_257 = and(_T_255, _T_256) node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_269 = and(_T_267, _T_268) node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_273 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_278 = and(_T_276, _T_277) node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_280 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_285 = and(_T_283, _T_284) node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_287 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_292 = and(_T_290, _T_291) node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_294 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_297 = and(_T_295, _T_296) node _T_298 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_301 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_306 = and(_T_304, _T_305) node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_308 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_309 = and(_T_307, _T_308) node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_311 = and(_T_309, _T_310) node _T_312 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_313 = and(_T_311, _T_312) node _T_314 = or(_T_257, _T_264) node _T_315 = or(_T_314, _T_271) node _T_316 = or(_T_315, _T_278) node _T_317 = or(_T_316, _T_285) node _T_318 = or(_T_317, _T_292) node _T_319 = or(_T_318, _T_299) node _T_320 = or(_T_319, _T_306) node _T_321 = or(_T_320, _T_313) node _T_322 = or(_T_250, _T_321) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_322, UInt<1>(0h1), "") : assert_6 node _T_326 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_327 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_328 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_329 = and(_T_327, _T_328) node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_331 = and(_T_329, _T_330) node _T_332 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_335 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_338 = and(_T_336, _T_337) node _T_339 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_340 = and(_T_338, _T_339) node _T_341 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_342 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_345 = and(_T_343, _T_344) node _T_346 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_349 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_350 = and(_T_348, _T_349) node _T_351 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_356 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_357 = and(_T_355, _T_356) node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_359 = and(_T_357, _T_358) node _T_360 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_361 = and(_T_359, _T_360) node _T_362 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_363 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_364 = and(_T_362, _T_363) node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_370 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_371 = and(_T_369, _T_370) node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_373 = and(_T_371, _T_372) node _T_374 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) node _T_376 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_377 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_378 = and(_T_376, _T_377) node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_380 = and(_T_378, _T_379) node _T_381 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_384 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_385 = and(_T_383, _T_384) node _T_386 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_387 = and(_T_385, _T_386) node _T_388 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_389 = and(_T_387, _T_388) node _T_390 = or(_T_333, _T_340) node _T_391 = or(_T_390, _T_347) node _T_392 = or(_T_391, _T_354) node _T_393 = or(_T_392, _T_361) node _T_394 = or(_T_393, _T_368) node _T_395 = or(_T_394, _T_375) node _T_396 = or(_T_395, _T_382) node _T_397 = or(_T_396, _T_389) node _T_398 = or(_T_326, _T_397) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_398, UInt<1>(0h1), "") : assert_7 node _T_402 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_403 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_404 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_411 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_414 = and(_T_412, _T_413) node _T_415 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_416 = and(_T_414, _T_415) node _T_417 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_418 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_421 = and(_T_419, _T_420) node _T_422 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_423 = and(_T_421, _T_422) node _T_424 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_425 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_428 = and(_T_426, _T_427) node _T_429 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_430 = and(_T_428, _T_429) node _T_431 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_432 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_435 = and(_T_433, _T_434) node _T_436 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_437 = and(_T_435, _T_436) node _T_438 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_439 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_440 = and(_T_438, _T_439) node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_442 = and(_T_440, _T_441) node _T_443 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_446 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_449 = and(_T_447, _T_448) node _T_450 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_453 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_454 = and(_T_452, _T_453) node _T_455 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_456 = and(_T_454, _T_455) node _T_457 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_460 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_461 = and(_T_459, _T_460) node _T_462 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_463 = and(_T_461, _T_462) node _T_464 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(_T_409, _T_416) node _T_467 = or(_T_466, _T_423) node _T_468 = or(_T_467, _T_430) node _T_469 = or(_T_468, _T_437) node _T_470 = or(_T_469, _T_444) node _T_471 = or(_T_470, _T_451) node _T_472 = or(_T_471, _T_458) node _T_473 = or(_T_472, _T_465) node _T_474 = or(_T_402, _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_474, UInt<1>(0h1), "") : assert_8

module NoCMonitor_4( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_109 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_110 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [7:0] io_in_a_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_a_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [8:0] a_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a29d64s8k1z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_16 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a29d64s8k1z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a29d64s8k1z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_66 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_67 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBuffer_a29d64s8k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [7:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_16 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s8k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s8k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (2'h0), // @[Decoupled.scala:362:21] .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_denied (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (1'h0), // @[Decoupled.scala:362:21] .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IDPool_5 : input clock : Clock input reset : Reset output io : { flip free : { valid : UInt<1>, bits : UInt<3>}, alloc : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<3>}} regreset bitmap : UInt<8>, clock, reset, UInt<8>(0hff) regreset select : UInt<3>, clock, reset, UInt<3>(0h0) regreset valid : UInt<1>, clock, reset, UInt<1>(0h1) connect io.alloc.valid, valid connect io.alloc.bits, select node taken_shiftAmount = bits(io.alloc.bits, 2, 0) node _taken_T = dshl(UInt<1>(0h1), taken_shiftAmount) node _taken_T_1 = bits(_taken_T, 7, 0) node taken = mux(io.alloc.ready, _taken_T_1, UInt<1>(0h0)) node allocated_shiftAmount = bits(io.free.bits, 2, 0) node _allocated_T = dshl(UInt<1>(0h1), allocated_shiftAmount) node _allocated_T_1 = bits(_allocated_T, 7, 0) node allocated = mux(io.free.valid, _allocated_T_1, UInt<1>(0h0)) node _bitmap1_T = not(taken) node _bitmap1_T_1 = and(bitmap, _bitmap1_T) node bitmap1 = or(_bitmap1_T_1, allocated) node _select1_T = bits(bitmap1, 0, 0) node _select1_T_1 = bits(bitmap1, 1, 1) node _select1_T_2 = bits(bitmap1, 2, 2) node _select1_T_3 = bits(bitmap1, 3, 3) node _select1_T_4 = bits(bitmap1, 4, 4) node _select1_T_5 = bits(bitmap1, 5, 5) node _select1_T_6 = bits(bitmap1, 6, 6) node _select1_T_7 = bits(bitmap1, 7, 7) node _select1_T_8 = mux(_select1_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _select1_T_9 = mux(_select1_T_5, UInt<3>(0h5), _select1_T_8) node _select1_T_10 = mux(_select1_T_4, UInt<3>(0h4), _select1_T_9) node _select1_T_11 = mux(_select1_T_3, UInt<2>(0h3), _select1_T_10) node _select1_T_12 = mux(_select1_T_2, UInt<2>(0h2), _select1_T_11) node _select1_T_13 = mux(_select1_T_1, UInt<1>(0h1), _select1_T_12) node select1 = mux(_select1_T, UInt<1>(0h0), _select1_T_13) node _valid1_T = orr(bitmap) node _valid1_T_1 = bits(bitmap, 0, 0) node _valid1_T_2 = bits(bitmap, 1, 1) node _valid1_T_3 = bits(bitmap, 2, 2) node _valid1_T_4 = bits(bitmap, 3, 3) node _valid1_T_5 = bits(bitmap, 4, 4) node _valid1_T_6 = bits(bitmap, 5, 5) node _valid1_T_7 = bits(bitmap, 6, 6) node _valid1_T_8 = bits(bitmap, 7, 7) node _valid1_T_9 = add(_valid1_T_1, _valid1_T_2) node _valid1_T_10 = bits(_valid1_T_9, 1, 0) node _valid1_T_11 = add(_valid1_T_3, _valid1_T_4) node _valid1_T_12 = bits(_valid1_T_11, 1, 0) node _valid1_T_13 = add(_valid1_T_10, _valid1_T_12) node _valid1_T_14 = bits(_valid1_T_13, 2, 0) node _valid1_T_15 = add(_valid1_T_5, _valid1_T_6) node _valid1_T_16 = bits(_valid1_T_15, 1, 0) node _valid1_T_17 = add(_valid1_T_7, _valid1_T_8) node _valid1_T_18 = bits(_valid1_T_17, 1, 0) node _valid1_T_19 = add(_valid1_T_16, _valid1_T_18) node _valid1_T_20 = bits(_valid1_T_19, 2, 0) node _valid1_T_21 = add(_valid1_T_14, _valid1_T_20) node _valid1_T_22 = bits(_valid1_T_21, 3, 0) node _valid1_T_23 = eq(_valid1_T_22, UInt<1>(0h1)) node _valid1_T_24 = and(_valid1_T_23, io.alloc.ready) node _valid1_T_25 = eq(_valid1_T_24, UInt<1>(0h0)) node _valid1_T_26 = and(_valid1_T, _valid1_T_25) node valid1 = or(_valid1_T_26, io.free.valid) node _T = or(io.alloc.ready, io.free.valid) when _T : connect bitmap, bitmap1 connect valid, valid1 node _T_1 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_2 = and(_T_1, io.free.valid) node _T_3 = or(io.alloc.ready, _T_2) when _T_3 : connect select, select1 node _T_4 = eq(io.free.valid, UInt<1>(0h0)) node _T_5 = not(taken) node _T_6 = and(bitmap, _T_5) node _T_7 = dshr(_T_6, io.free.bits) node _T_8 = bits(_T_7, 0, 0) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_4, _T_9) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:44 assert (!io.free.valid || !(bitmap & ~taken)(io.free.bits))\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _T_14 = orr(bitmap) node _T_15 = eq(valid, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:48 assert (valid === bitmap.orR)\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node _T_19 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_20 = and(_T_19, io.free.valid) node _T_21 = or(io.alloc.ready, _T_20) reg REG : UInt<1>, clock connect REG, _T_21 node _T_22 = and(io.alloc.valid, REG) when _T_22 : node _T_23 = bits(bitmap, 0, 0) node _T_24 = bits(bitmap, 1, 1) node _T_25 = bits(bitmap, 2, 2) node _T_26 = bits(bitmap, 3, 3) node _T_27 = bits(bitmap, 4, 4) node _T_28 = bits(bitmap, 5, 5) node _T_29 = bits(bitmap, 6, 6) node _T_30 = bits(bitmap, 7, 7) node _T_31 = mux(_T_29, UInt<3>(0h6), UInt<3>(0h7)) node _T_32 = mux(_T_28, UInt<3>(0h5), _T_31) node _T_33 = mux(_T_27, UInt<3>(0h4), _T_32) node _T_34 = mux(_T_26, UInt<2>(0h3), _T_33) node _T_35 = mux(_T_25, UInt<2>(0h2), _T_34) node _T_36 = mux(_T_24, UInt<1>(0h1), _T_35) node _T_37 = mux(_T_23, UInt<1>(0h0), _T_36) node _T_38 = eq(select, _T_37) node _T_39 = asUInt(reset) node _T_40 = eq(_T_39, UInt<1>(0h0)) when _T_40 : node _T_41 = eq(_T_38, UInt<1>(0h0)) when _T_41 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:52 assert (select === PriorityEncoder(bitmap))\n") : printf_2 assert(clock, _T_38, UInt<1>(0h1), "") : assert_2

module IDPool_5( // @[IDPool.scala:8:7] input clock, // @[IDPool.scala:8:7] input reset, // @[IDPool.scala:8:7] input io_free_valid, // @[IDPool.scala:12:14] input [2:0] io_free_bits, // @[IDPool.scala:12:14] input io_alloc_ready, // @[IDPool.scala:12:14] output io_alloc_valid, // @[IDPool.scala:12:14] output [2:0] io_alloc_bits // @[IDPool.scala:12:14] ); wire [2:0] io_alloc_bits_0; // @[IDPool.scala:8:7] wire io_free_valid_0 = io_free_valid; // @[IDPool.scala:8:7] wire [2:0] io_free_bits_0 = io_free_bits; // @[IDPool.scala:8:7] wire io_alloc_ready_0 = io_alloc_ready; // @[IDPool.scala:8:7] wire [2:0] allocated_shiftAmount = io_free_bits_0; // @[OneHot.scala:64:49] wire [2:0] taken_shiftAmount = io_alloc_bits_0; // @[OneHot.scala:64:49] wire io_alloc_valid_0; // @[IDPool.scala:8:7] reg [7:0] bitmap; // @[IDPool.scala:18:23] reg [2:0] select; // @[IDPool.scala:19:23] assign io_alloc_bits_0 = select; // @[IDPool.scala:8:7, :19:23] reg valid; // @[IDPool.scala:20:23] assign io_alloc_valid_0 = valid; // @[IDPool.scala:8:7, :20:23] wire [7:0] _taken_T = 8'h1 << taken_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _taken_T_1 = _taken_T; // @[OneHot.scala:65:{12,27}] wire [7:0] taken = io_alloc_ready_0 ? _taken_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _allocated_T = 8'h1 << allocated_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _allocated_T_1 = _allocated_T; // @[OneHot.scala:65:{12,27}] wire [7:0] allocated = io_free_valid_0 ? _allocated_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _bitmap1_T = ~taken; // @[IDPool.scala:25:19, :27:27] wire [7:0] _bitmap1_T_1 = bitmap & _bitmap1_T; // @[IDPool.scala:18:23, :27:{25,27}] wire [7:0] bitmap1 = _bitmap1_T_1 | allocated; // @[IDPool.scala:26:22, :27:{25,35}] wire _select1_T = bitmap1[0]; // @[OneHot.scala:48:45] wire _select1_T_1 = bitmap1[1]; // @[OneHot.scala:48:45] wire _select1_T_2 = bitmap1[2]; // @[OneHot.scala:48:45] wire _select1_T_3 = bitmap1[3]; // @[OneHot.scala:48:45] wire _select1_T_4 = bitmap1[4]; // @[OneHot.scala:48:45] wire _select1_T_5 = bitmap1[5]; // @[OneHot.scala:48:45] wire _select1_T_6 = bitmap1[6]; // @[OneHot.scala:48:45] wire _select1_T_7 = bitmap1[7]; // @[OneHot.scala:48:45] wire [2:0] _select1_T_8 = {2'h3, ~_select1_T_6}; // @[OneHot.scala:48:45] wire [2:0] _select1_T_9 = _select1_T_5 ? 3'h5 : _select1_T_8; // @[OneHot.scala:48:45] wire [2:0] _select1_T_10 = _select1_T_4 ? 3'h4 : _select1_T_9; // @[OneHot.scala:48:45] wire [2:0] _select1_T_11 = _select1_T_3 ? 3'h3 : _select1_T_10; // @[OneHot.scala:48:45] wire [2:0] _select1_T_12 = _select1_T_2 ? 3'h2 : _select1_T_11; // @[OneHot.scala:48:45] wire [2:0] _select1_T_13 = _select1_T_1 ? 3'h1 : _select1_T_12; // @[OneHot.scala:48:45] wire [2:0] select1 = _select1_T ? 3'h0 : _select1_T_13; // @[OneHot.scala:48:45] wire _valid1_T = |bitmap; // @[IDPool.scala:18:23, :29:28] wire _valid1_T_1 = bitmap[0]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_2 = bitmap[1]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_3 = bitmap[2]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_4 = bitmap[3]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_5 = bitmap[4]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_6 = bitmap[5]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_7 = bitmap[6]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_8 = bitmap[7]; // @[IDPool.scala:18:23, :29:46] wire [1:0] _valid1_T_9 = {1'h0, _valid1_T_1} + {1'h0, _valid1_T_2}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_10 = _valid1_T_9; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_11 = {1'h0, _valid1_T_3} + {1'h0, _valid1_T_4}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_12 = _valid1_T_11; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_13 = {1'h0, _valid1_T_10} + {1'h0, _valid1_T_12}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_14 = _valid1_T_13; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_15 = {1'h0, _valid1_T_5} + {1'h0, _valid1_T_6}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_16 = _valid1_T_15; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_17 = {1'h0, _valid1_T_7} + {1'h0, _valid1_T_8}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_18 = _valid1_T_17; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_19 = {1'h0, _valid1_T_16} + {1'h0, _valid1_T_18}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_20 = _valid1_T_19; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_21 = {1'h0, _valid1_T_14} + {1'h0, _valid1_T_20}; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_22 = _valid1_T_21; // @[IDPool.scala:29:46] wire _valid1_T_23 = _valid1_T_22 == 4'h1; // @[IDPool.scala:29:{46,55}] wire _valid1_T_24 = _valid1_T_23 & io_alloc_ready_0; // @[IDPool.scala:8:7, :29:{55,64}] wire _valid1_T_25 = ~_valid1_T_24; // @[IDPool.scala:29:{35,64}] wire _valid1_T_26 = _valid1_T & _valid1_T_25; // @[IDPool.scala:29:{28,32,35}] wire valid1 = _valid1_T_26 | io_free_valid_0; // @[IDPool.scala:8:7, :29:32, :30:17] reg REG; // @[IDPool.scala:51:36]

Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i64_e5_s11 : output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 63, 63) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32) node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33) node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34) node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35) node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36) node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37) node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38) node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39) node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40) node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41) node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42) node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43) node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44) node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45) node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46) node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47) node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48) node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49) node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50) node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51) node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52) node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53) node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54) node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55) node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56) node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57) node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58) node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59) node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60) node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61) node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62) node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63) node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f)) node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64) node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65) node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66) node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67) node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68) node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69) node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70) node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71) node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72) node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73) node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74) node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75) node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76) node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77) node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78) node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79) node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80) node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81) node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82) node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83) node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84) node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85) node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86) node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87) node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88) node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89) node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90) node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91) node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92) node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93) node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94) node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95) node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96) node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97) node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98) node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99) node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100) node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101) node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102) node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103) node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104) node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105) node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106) node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107) node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108) node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109) node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110) node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111) node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112) node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113) node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114) node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115) node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116) node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117) node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118) node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119) node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120) node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121) node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122) node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123) node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module INToRecFN_i64_e5_s11( // @[INToRecFN.scala:43:7] input io_signedIn, // @[INToRecFN.scala:46:16] input [63:0] io_in, // @[INToRecFN.scala:46:16] input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16] output [16:0] io_out, // @[INToRecFN.scala:46:16] output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16] ); wire intAsRawFloat_sign = io_signedIn & io_in[63]; // @[rawFloatFromIN.scala:51:{29,34}] wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? 64'h0 - io_in : io_in; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [5:0] intAsRawFloat_adjustedNormDist = intAsRawFloat_absIn[63] ? 6'h0 : intAsRawFloat_absIn[62] ? 6'h1 : intAsRawFloat_absIn[61] ? 6'h2 : intAsRawFloat_absIn[60] ? 6'h3 : intAsRawFloat_absIn[59] ? 6'h4 : intAsRawFloat_absIn[58] ? 6'h5 : intAsRawFloat_absIn[57] ? 6'h6 : intAsRawFloat_absIn[56] ? 6'h7 : intAsRawFloat_absIn[55] ? 6'h8 : intAsRawFloat_absIn[54] ? 6'h9 : intAsRawFloat_absIn[53] ? 6'hA : intAsRawFloat_absIn[52] ? 6'hB : intAsRawFloat_absIn[51] ? 6'hC : intAsRawFloat_absIn[50] ? 6'hD : intAsRawFloat_absIn[49] ? 6'hE : intAsRawFloat_absIn[48] ? 6'hF : intAsRawFloat_absIn[47] ? 6'h10 : intAsRawFloat_absIn[46] ? 6'h11 : intAsRawFloat_absIn[45] ? 6'h12 : intAsRawFloat_absIn[44] ? 6'h13 : intAsRawFloat_absIn[43] ? 6'h14 : intAsRawFloat_absIn[42] ? 6'h15 : intAsRawFloat_absIn[41] ? 6'h16 : intAsRawFloat_absIn[40] ? 6'h17 : intAsRawFloat_absIn[39] ? 6'h18 : intAsRawFloat_absIn[38] ? 6'h19 : intAsRawFloat_absIn[37] ? 6'h1A : intAsRawFloat_absIn[36] ? 6'h1B : intAsRawFloat_absIn[35] ? 6'h1C : intAsRawFloat_absIn[34] ? 6'h1D : intAsRawFloat_absIn[33] ? 6'h1E : intAsRawFloat_absIn[32] ? 6'h1F : intAsRawFloat_absIn[31] ? 6'h20 : intAsRawFloat_absIn[30] ? 6'h21 : intAsRawFloat_absIn[29] ? 6'h22 : intAsRawFloat_absIn[28] ? 6'h23 : intAsRawFloat_absIn[27] ? 6'h24 : intAsRawFloat_absIn[26] ? 6'h25 : intAsRawFloat_absIn[25] ? 6'h26 : intAsRawFloat_absIn[24] ? 6'h27 : intAsRawFloat_absIn[23] ? 6'h28 : intAsRawFloat_absIn[22] ? 6'h29 : intAsRawFloat_absIn[21] ? 6'h2A : intAsRawFloat_absIn[20] ? 6'h2B : intAsRawFloat_absIn[19] ? 6'h2C : intAsRawFloat_absIn[18] ? 6'h2D : intAsRawFloat_absIn[17] ? 6'h2E : intAsRawFloat_absIn[16] ? 6'h2F : intAsRawFloat_absIn[15] ? 6'h30 : intAsRawFloat_absIn[14] ? 6'h31 : intAsRawFloat_absIn[13] ? 6'h32 : intAsRawFloat_absIn[12] ? 6'h33 : intAsRawFloat_absIn[11] ? 6'h34 : intAsRawFloat_absIn[10] ? 6'h35 : intAsRawFloat_absIn[9] ? 6'h36 : intAsRawFloat_absIn[8] ? 6'h37 : intAsRawFloat_absIn[7] ? 6'h38 : intAsRawFloat_absIn[6] ? 6'h39 : intAsRawFloat_absIn[5] ? 6'h3A : intAsRawFloat_absIn[4] ? 6'h3B : intAsRawFloat_absIn[3] ? 6'h3C : intAsRawFloat_absIn[2] ? 6'h3D : {5'h1F, ~(intAsRawFloat_absIn[1])}; // @[Mux.scala:50:70] wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_absIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (~(_intAsRawFloat_sig_T[63])), // @[rawFloatFromIN.scala:56:{22,41}, :62:{23,28}] .io_in_sign (intAsRawFloat_sign), // @[rawFloatFromIN.scala:51:29] .io_in_sExp ({3'h2, ~intAsRawFloat_adjustedNormDist}), // @[Mux.scala:50:70] .io_in_sig ({1'h0, _intAsRawFloat_sig_T[63:0]}), // @[rawFloatFromIN.scala:52:31, :56:{22,41}, :65:20] .io_roundingMode (io_roundingMode), .io_out (io_out), .io_exceptionFlags (io_exceptionFlags) ); // @[INToRecFN.scala:60:15] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_197 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_197( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_85 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_85( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_23 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_46 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_23 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id) node _T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0h8) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h3) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<2>(0h3), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<2> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0h8)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_16 = eq(UInt<5>(0h16), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(UInt<5>(0h17), io.in.bits.egress_id) when _T_17 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_18 = eq(UInt<5>(0h18), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(route_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_47 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_23 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_26 = and(vcalloc_q.io.enq.valid, _T_25) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_2 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_16 = or(_out_bundle_bits_out_virt_channel_T_15, _out_bundle_bits_out_virt_channel_T_13) node _out_bundle_bits_out_virt_channel_T_17 = or(_out_bundle_bits_out_virt_channel_T_16, _out_bundle_bits_out_virt_channel_T_14) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_17 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1

module IngressUnit_23( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'h4; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'h6; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 4'h8; // @[IngressUnit.scala:30:72] wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {2'h0, {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, _route_buffer_io_enq_bits_flow_egress_node_id_T_1} | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_3}}}; // @[Mux.scala:30:73] wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_plic : input clock : Clock input reset : Reset output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fragmenter of TLFragmenter_PLIC connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect fragmenter.auto.anon_in, tlOut connect tlIn, auto.tl_in connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready extmodule plusarg_reader_52 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_53 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLInterconnectCoupler_cbus_to_plic( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_PLIC fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_366 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_366( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module SourceD_7 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<128>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, flip bs_rdat : { data : UInt<128>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, bs_wdat : { data : UInt<128>}, flip evict_req : { set : UInt<11>, way : UInt<4>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<11>, way : UInt<4>}, grant_safe : UInt<1>} wire s1_valid : UInt<1> wire s2_valid : UInt<1> wire s3_valid : UInt<1> wire s2_ready : UInt<1> wire s3_ready : UInt<1> wire s4_ready : UInt<1> regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _s1_req_reg_T = eq(busy, UInt<1>(0h0)) node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid) reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when _s1_req_reg_T_1 : connect s1_req_reg, io.req.bits node _s1_req_T = eq(busy, UInt<1>(0h0)) node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg) wire s1_x_bypass : UInt<2> node _s1_latch_bypass_T = or(busy, io.req.valid) node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0)) node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready) reg s1_latch_bypass : UInt<1>, clock connect s1_latch_bypass, _s1_latch_bypass_T_2 reg s1_bypass_r : UInt<2>, clock when s1_latch_bypass : connect s1_bypass_r, s1_x_bypass node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r) node _s1_mask_sizeOH_T = or(s1_req.size, UInt<4>(0h0)) node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 1, 0) node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount) node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 3, 0) node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<4>(0hf)) node s1_mask_sub_0_1 = geq(s1_req.size, UInt<3>(0h4)) node s1_mask_size = bits(s1_mask_sizeOH, 3, 3) node s1_mask_bit = bits(s1_req.offset, 3, 3) node s1_mask_nbit = eq(s1_mask_bit, UInt<1>(0h0)) node s1_mask_eq = and(UInt<1>(0h1), s1_mask_nbit) node _s1_mask_acc_T = and(s1_mask_size, s1_mask_eq) node s1_mask_acc = or(s1_mask_sub_0_1, _s1_mask_acc_T) node s1_mask_eq_1 = and(UInt<1>(0h1), s1_mask_bit) node _s1_mask_acc_T_1 = and(s1_mask_size, s1_mask_eq_1) node s1_mask_acc_1 = or(s1_mask_sub_0_1, _s1_mask_acc_T_1) node _s1_mask_T = cat(s1_mask_acc_1, s1_mask_acc) node _s1_mask_T_1 = not(s1_bypass) node s1_mask = and(_s1_mask_T, _s1_mask_T_1) node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6)) node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2)) node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1) node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7)) node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3) node _s1_need_r_T = orr(s1_mask) node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0]) node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5)) node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2) node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0)) node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4) node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0)) node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h3)) node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7) node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8) node _s1_valid_r_T = or(busy, io.req.valid) node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r) node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0)) node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2) node _s1_need_pb_T = bits(s1_req.opcode, 2, 2) node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0)) node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0) node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2) node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5)) node _s1_single_T_1 = or(_s1_single_T, s1_grant) node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6)) node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2) node s1_retires = eq(s1_single, UInt<1>(0h0)) node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size) node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0) node _s1_beats1_T_2 = not(_s1_beats1_T_1) node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 4) node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3) node _s1_beat_T = shr(s1_req.offset, 4) node s1_beat = or(_s1_beat_T, s1_counter) node s1_last = eq(s1_counter, s1_beats1) node s1_first = eq(s1_counter, UInt<1>(0h0)) node _T = eq(s1_latch_bypass, UInt<1>(0h0)) node _T_1 = or(busy, io.req.valid) node _T_2 = eq(s1_need_r, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) connect io.bs_radr.valid, s1_valid_r connect io.bs_radr.bits.noop, UInt<1>(0h0) connect io.bs_radr.bits.way, s1_req.way connect io.bs_radr.bits.set, s1_req.set connect io.bs_radr.bits.beat, s1_beat connect io.bs_radr.bits.mask, s1_mask node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_radr.valid, _T_4) inst queue of Queue3_BankedStoreInnerDecoded_7 connect queue.clock, clock connect queue.reset, reset node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid) reg queue_io_enq_valid_REG : UInt<1>, clock connect queue_io_enq_valid_REG, _queue_io_enq_valid_T reg queue_io_enq_valid_REG_1 : UInt<1>, clock connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG connect queue.io.enq.valid, queue_io_enq_valid_REG_1 connect queue.io.enq.bits.data, io.bs_rdat.data node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0)) node _T_7 = or(_T_6, queue.io.enq.ready) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid || queue.io.enq.ready)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid) when _T_12 : connect s1_block_r, UInt<1>(0h1) when io.req.valid : connect busy, UInt<1>(0h1) node _T_13 = and(s1_valid, s2_ready) when _T_13 : node _s1_counter_T = add(s1_counter, UInt<1>(0h1)) node _s1_counter_T_1 = tail(_s1_counter_T, 1) connect s1_counter, _s1_counter_T_1 connect s1_block_r, UInt<1>(0h0) when s1_last : connect s1_counter, UInt<1>(0h0) connect busy, UInt<1>(0h0) node _T_14 = eq(s2_ready, UInt<1>(0h0)) node _T_15 = and(s1_valid, _T_14) node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _s1_valid_T = or(busy, io.req.valid) node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0)) node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready) node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2) connect s1_valid, _s1_valid_T_3 node s2_latch = and(s1_valid, s2_ready) regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_beat : UInt<2>, clock when s2_latch : connect s2_beat, s1_beat reg s2_bypass : UInt<2>, clock when s2_latch : connect s2_bypass, s1_bypass reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s2_latch : connect s2_req, s1_req reg s2_last : UInt<1>, clock when s2_latch : connect s2_last, s1_last reg s2_need_r : UInt<1>, clock when s2_latch : connect s2_need_r, s1_need_r reg s2_need_pb : UInt<1>, clock when s2_latch : connect s2_need_pb, s1_need_pb reg s2_retires : UInt<1>, clock when s2_latch : connect s2_retires, s1_retires node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0)) node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first) reg s2_need_d : UInt<1>, clock when s2_latch : connect s2_need_d, _s2_need_d_T_1 wire s2_pdata_raw : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>} reg s2_pdata_r : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s2_valid_pb : connect s2_pdata_r, s2_pdata_raw node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r) node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data) connect s2_pdata_raw.data, _s2_pdata_raw_data_T node _s2_pdata_raw_mask_T = not(UInt<16>(0h0)) node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T) connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1 node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt) connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0]) connect io.pb_pop.valid, _io_pb_pop_valid_T connect io.pb_pop.bits.index, s2_req.put connect io.pb_pop.bits.last, s2_last node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0)) node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T) connect io.rel_pop.valid, _io_rel_pop_valid_T_1 connect io.rel_pop.bits.index, s2_req.put connect io.rel_pop.bits.last, s2_last node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0)) node _T_17 = and(io.pb_pop.valid, _T_16) node _T_18 = eq(io.rel_pop.ready, UInt<1>(0h0)) node _T_19 = and(io.rel_pop.valid, _T_18) node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready) when pb_ready : connect s2_valid_pb, UInt<1>(0h0) node _T_20 = and(s2_valid, s3_ready) when _T_20 : connect s2_full, UInt<1>(0h0) when s2_latch : connect s2_valid_pb, s1_need_pb when s2_latch : connect s2_full, UInt<1>(0h1) node _T_21 = eq(s3_ready, UInt<1>(0h0)) node _T_22 = and(s2_valid, _T_21) node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_valid_T_1 = or(_s2_valid_T, pb_ready) node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1) connect s2_valid, _s2_valid_T_2 node _s2_ready_T = eq(s2_full, UInt<1>(0h0)) node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready) node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2) node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3) connect s2_ready, _s2_ready_T_4 node s3_latch = and(s2_valid, s3_ready) regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0) reg s3_beat : UInt<2>, clock when s3_latch : connect s3_beat, s2_beat reg s3_bypass : UInt<2>, clock when s3_latch : connect s3_bypass, s2_bypass reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s3_latch : connect s3_req, s2_req node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode) reg s3_last : UInt<1>, clock when s3_latch : connect s3_last, s2_last reg s3_pdata : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s3_latch : connect s3_pdata, s2_pdata reg s3_need_pb : UInt<1>, clock when s3_latch : connect s3_need_pb, s2_need_pb reg s3_retires : UInt<1>, clock when s3_latch : connect s3_retires, s2_retires reg s3_need_r : UInt<1>, clock when s3_latch : connect s3_need_r, s2_need_r node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6)) node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7)) node s3_acq = or(_s3_acq_T, _s3_acq_T_1) wire s3_bypass_data : UInt node _s3_rdata_T = bits(s3_bypass, 0, 0) node _s3_rdata_T_1 = bits(s3_bypass, 1, 1) node _s3_rdata_T_2 = bits(s3_bypass_data, 63, 0) node _s3_rdata_T_3 = bits(s3_bypass_data, 127, 64) node _s3_rdata_T_4 = bits(queue.io.deq.bits.data, 63, 0) node _s3_rdata_T_5 = bits(queue.io.deq.bits.data, 127, 64) node _s3_rdata_T_6 = mux(_s3_rdata_T, _s3_rdata_T_2, _s3_rdata_T_4) node _s3_rdata_T_7 = mux(_s3_rdata_T_1, _s3_rdata_T_3, _s3_rdata_T_5) node s3_rdata = cat(_s3_rdata_T_7, _s3_rdata_T_6) node _grant_T = eq(s3_req.param, UInt<2>(0h2)) node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5)) wire resp_opcode : UInt<3>[8] connect resp_opcode[0], UInt<1>(0h0) connect resp_opcode[1], UInt<1>(0h0) connect resp_opcode[2], UInt<1>(0h1) connect resp_opcode[3], UInt<1>(0h1) connect resp_opcode[4], UInt<1>(0h1) connect resp_opcode[5], UInt<2>(0h2) connect resp_opcode[6], grant connect resp_opcode[7], UInt<3>(0h4) wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect io.d, d connect d.valid, s3_valid_d node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6)) connect d.bits.opcode, _d_bits_opcode_T node _d_bits_param_T = and(s3_req.prio[0], s3_acq) node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0)) node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1)) node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0)) connect d.bits.param, _d_bits_param_T_3 connect d.bits.size, s3_req.size connect d.bits.source, s3_req.source connect d.bits.sink, s3_req.sink connect d.bits.denied, s3_req.bad connect d.bits.data, s3_rdata node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0) node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T) connect d.bits.corrupt, _d_bits_corrupt_T_1 node _queue_io_deq_ready_T = and(s3_valid, s4_ready) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _T_23 = eq(s3_full, UInt<1>(0h0)) node _T_24 = eq(s3_need_r, UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = or(_T_25, queue.io.deq.valid) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full || !s3_need_r || queue.io.deq.valid)\n") : printf_1 assert(clock, _T_26, UInt<1>(0h1), "") : assert_1 when d.ready : connect s3_valid_d, UInt<1>(0h0) node _T_30 = and(s3_valid, s4_ready) when _T_30 : connect s3_full, UInt<1>(0h0) when s3_latch : connect s3_valid_d, s2_need_d when s3_latch : connect s3_full, UInt<1>(0h1) node _T_31 = eq(s4_ready, UInt<1>(0h0)) node _T_32 = and(s3_valid, _T_31) node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0)) node _s3_valid_T_1 = or(_s3_valid_T, d.ready) node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1) connect s3_valid, _s3_valid_T_2 node _s3_ready_T = eq(s3_full, UInt<1>(0h0)) node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0)) node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready) node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2) node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3) connect s3_ready, _s3_ready_T_4 node _s4_latch_T = and(s3_valid, s3_retires) node s4_latch = and(_s4_latch_T, s4_ready) regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0) reg s4_beat : UInt<2>, clock when s4_latch : connect s4_beat, s3_beat reg s4_need_r : UInt<1>, clock when s4_latch : connect s4_need_r, s3_need_r reg s4_need_bs : UInt<1>, clock when s4_latch : connect s4_need_bs, s3_need_pb reg s4_need_pb : UInt<1>, clock when s4_latch : connect s4_need_pb, s3_need_pb reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s4_latch : connect s4_req, s3_req reg s4_adjusted_opcode : UInt<3>, clock when s4_latch : connect s4_adjusted_opcode, s3_adjusted_opcode reg s4_pdata : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s4_latch : connect s4_pdata, s3_pdata reg s4_rdata : UInt<128>, clock when s4_latch : connect s4_rdata, s3_rdata inst atomics of Atomics_7 connect atomics.clock, clock connect atomics.reset, reset connect atomics.io.write, s4_req.prio[2] connect atomics.io.a.opcode, s4_adjusted_opcode connect atomics.io.a.param, s4_req.param connect atomics.io.a.size, UInt<1>(0h0) connect atomics.io.a.source, UInt<1>(0h0) connect atomics.io.a.address, UInt<1>(0h0) connect atomics.io.a.mask, s4_pdata.mask connect atomics.io.a.data, s4_pdata.data invalidate atomics.io.a.corrupt connect atomics.io.data_in, s4_rdata node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs) connect io.bs_wadr.valid, _io_bs_wadr_valid_T connect io.bs_wadr.bits.noop, UInt<1>(0h0) connect io.bs_wadr.bits.way, s4_req.way connect io.bs_wadr.bits.set, s4_req.set connect io.bs_wadr.bits.beat, s4_beat node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0) node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1) node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2) node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3) node _io_bs_wadr_bits_mask_T_4 = bits(s4_pdata.mask, 4, 4) node _io_bs_wadr_bits_mask_T_5 = bits(s4_pdata.mask, 5, 5) node _io_bs_wadr_bits_mask_T_6 = bits(s4_pdata.mask, 6, 6) node _io_bs_wadr_bits_mask_T_7 = bits(s4_pdata.mask, 7, 7) node _io_bs_wadr_bits_mask_T_8 = bits(s4_pdata.mask, 8, 8) node _io_bs_wadr_bits_mask_T_9 = bits(s4_pdata.mask, 9, 9) node _io_bs_wadr_bits_mask_T_10 = bits(s4_pdata.mask, 10, 10) node _io_bs_wadr_bits_mask_T_11 = bits(s4_pdata.mask, 11, 11) node _io_bs_wadr_bits_mask_T_12 = bits(s4_pdata.mask, 12, 12) node _io_bs_wadr_bits_mask_T_13 = bits(s4_pdata.mask, 13, 13) node _io_bs_wadr_bits_mask_T_14 = bits(s4_pdata.mask, 14, 14) node _io_bs_wadr_bits_mask_T_15 = bits(s4_pdata.mask, 15, 15) node _io_bs_wadr_bits_mask_T_16 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1) node _io_bs_wadr_bits_mask_T_17 = or(_io_bs_wadr_bits_mask_T_16, _io_bs_wadr_bits_mask_T_2) node _io_bs_wadr_bits_mask_T_18 = or(_io_bs_wadr_bits_mask_T_17, _io_bs_wadr_bits_mask_T_3) node _io_bs_wadr_bits_mask_T_19 = or(_io_bs_wadr_bits_mask_T_18, _io_bs_wadr_bits_mask_T_4) node _io_bs_wadr_bits_mask_T_20 = or(_io_bs_wadr_bits_mask_T_19, _io_bs_wadr_bits_mask_T_5) node _io_bs_wadr_bits_mask_T_21 = or(_io_bs_wadr_bits_mask_T_20, _io_bs_wadr_bits_mask_T_6) node _io_bs_wadr_bits_mask_T_22 = or(_io_bs_wadr_bits_mask_T_21, _io_bs_wadr_bits_mask_T_7) node _io_bs_wadr_bits_mask_T_23 = or(_io_bs_wadr_bits_mask_T_8, _io_bs_wadr_bits_mask_T_9) node _io_bs_wadr_bits_mask_T_24 = or(_io_bs_wadr_bits_mask_T_23, _io_bs_wadr_bits_mask_T_10) node _io_bs_wadr_bits_mask_T_25 = or(_io_bs_wadr_bits_mask_T_24, _io_bs_wadr_bits_mask_T_11) node _io_bs_wadr_bits_mask_T_26 = or(_io_bs_wadr_bits_mask_T_25, _io_bs_wadr_bits_mask_T_12) node _io_bs_wadr_bits_mask_T_27 = or(_io_bs_wadr_bits_mask_T_26, _io_bs_wadr_bits_mask_T_13) node _io_bs_wadr_bits_mask_T_28 = or(_io_bs_wadr_bits_mask_T_27, _io_bs_wadr_bits_mask_T_14) node _io_bs_wadr_bits_mask_T_29 = or(_io_bs_wadr_bits_mask_T_28, _io_bs_wadr_bits_mask_T_15) node _io_bs_wadr_bits_mask_T_30 = cat(_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22) connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_30 connect io.bs_wdat.data, atomics.io.data_out node _T_33 = and(s4_full, s4_need_pb) node _T_34 = and(_T_33, s4_pdata.corrupt) node _T_35 = eq(_T_34, UInt<1>(0h0)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2 assert(clock, _T_35, UInt<1>(0h1), "") : assert_2 node _T_39 = eq(io.bs_wadr.ready, UInt<1>(0h0)) node _T_40 = and(io.bs_wadr.valid, _T_39) node _T_41 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_42 = and(s4_req.prio[0], _T_41) node _T_43 = eq(s4_req.param, UInt<3>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_46 = and(s4_req.prio[0], _T_45) node _T_47 = eq(s4_req.param, UInt<3>(0h1)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_50 = and(s4_req.prio[0], _T_49) node _T_51 = eq(s4_req.param, UInt<3>(0h2)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_54 = and(s4_req.prio[0], _T_53) node _T_55 = eq(s4_req.param, UInt<3>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_58 = and(s4_req.prio[0], _T_57) node _T_59 = eq(s4_req.param, UInt<3>(0h4)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_62 = and(s4_req.prio[0], _T_61) node _T_63 = eq(s4_req.param, UInt<3>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_66 = and(s4_req.prio[0], _T_65) node _T_67 = eq(s4_req.param, UInt<3>(0h1)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_70 = and(s4_req.prio[0], _T_69) node _T_71 = eq(s4_req.param, UInt<3>(0h2)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_74 = and(s4_req.prio[0], _T_73) node _T_75 = eq(s4_req.param, UInt<3>(0h3)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(s4_need_bs, UInt<1>(0h0)) node _T_78 = or(io.bs_wadr.ready, _T_77) when _T_78 : connect s4_full, UInt<1>(0h0) when s4_latch : connect s4_full, UInt<1>(0h1) node _s4_ready_T = eq(s3_retires, UInt<1>(0h0)) node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0)) node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1) node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready) node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0)) node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4) connect s4_ready, _s4_ready_T_5 node _retire_T = eq(s4_need_bs, UInt<1>(0h0)) node _retire_T_1 = or(io.bs_wadr.ready, _retire_T) node retire = and(s4_full, _retire_T_1) reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when retire : connect s5_req, s4_req reg s5_beat : UInt<2>, clock when retire : connect s5_beat, s4_beat reg s5_dat : UInt<128>, clock when retire : connect s5_dat, atomics.io.data_out reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when retire : connect s6_req, s5_req reg s6_beat : UInt<2>, clock when retire : connect s6_beat, s5_beat reg s6_dat : UInt<128>, clock when retire : connect s6_dat, s5_dat reg s7_dat : UInt<128>, clock when retire : connect s7_dat, s6_dat node pre_s3_req = mux(s3_latch, s2_req, s3_req) node pre_s4_req = mux(s4_latch, s3_req, s4_req) node pre_s5_req = mux(retire, s4_req, s5_req) node pre_s6_req = mux(retire, s5_req, s6_req) node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat) node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat) node pre_s5_beat = mux(retire, s4_beat, s5_beat) node pre_s6_beat = mux(retire, s5_beat, s6_beat) node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat) node pre_s6_dat = mux(retire, s5_dat, s6_dat) node pre_s7_dat = mux(retire, s6_dat, s7_dat) node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0)) node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T) node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0)) node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full) node pre_s4_full = or(s4_latch, _pre_s4_full_T_3) node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set) node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way) node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1) node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat) node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3) node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full) node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set) node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way) node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1) node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat) node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3) node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set) node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way) node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1) node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat) node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3) node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<4>(0h0)) node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 1, 0) node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount) node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 3, 0) node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_4_bypass_sub_0_1 = geq(pre_s4_req.size, UInt<3>(0h4)) node pre_s3_4_bypass_size = bits(pre_s3_4_bypass_sizeOH, 3, 3) node pre_s3_4_bypass_bit = bits(pre_s4_req.offset, 3, 3) node pre_s3_4_bypass_nbit = eq(pre_s3_4_bypass_bit, UInt<1>(0h0)) node pre_s3_4_bypass_eq = and(UInt<1>(0h1), pre_s3_4_bypass_nbit) node _pre_s3_4_bypass_acc_T = and(pre_s3_4_bypass_size, pre_s3_4_bypass_eq) node pre_s3_4_bypass_acc = or(pre_s3_4_bypass_sub_0_1, _pre_s3_4_bypass_acc_T) node pre_s3_4_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_4_bypass_bit) node _pre_s3_4_bypass_acc_T_1 = and(pre_s3_4_bypass_size, pre_s3_4_bypass_eq_1) node pre_s3_4_bypass_acc_1 = or(pre_s3_4_bypass_sub_0_1, _pre_s3_4_bypass_acc_T_1) node _pre_s3_4_bypass_T = cat(pre_s3_4_bypass_acc_1, pre_s3_4_bypass_acc) node pre_s3_4_bypass = mux(pre_s3_4_match, _pre_s3_4_bypass_T, UInt<1>(0h0)) node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<4>(0h0)) node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 1, 0) node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount) node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 3, 0) node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_5_bypass_sub_0_1 = geq(pre_s5_req.size, UInt<3>(0h4)) node pre_s3_5_bypass_size = bits(pre_s3_5_bypass_sizeOH, 3, 3) node pre_s3_5_bypass_bit = bits(pre_s5_req.offset, 3, 3) node pre_s3_5_bypass_nbit = eq(pre_s3_5_bypass_bit, UInt<1>(0h0)) node pre_s3_5_bypass_eq = and(UInt<1>(0h1), pre_s3_5_bypass_nbit) node _pre_s3_5_bypass_acc_T = and(pre_s3_5_bypass_size, pre_s3_5_bypass_eq) node pre_s3_5_bypass_acc = or(pre_s3_5_bypass_sub_0_1, _pre_s3_5_bypass_acc_T) node pre_s3_5_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_5_bypass_bit) node _pre_s3_5_bypass_acc_T_1 = and(pre_s3_5_bypass_size, pre_s3_5_bypass_eq_1) node pre_s3_5_bypass_acc_1 = or(pre_s3_5_bypass_sub_0_1, _pre_s3_5_bypass_acc_T_1) node _pre_s3_5_bypass_T = cat(pre_s3_5_bypass_acc_1, pre_s3_5_bypass_acc) node pre_s3_5_bypass = mux(pre_s3_5_match, _pre_s3_5_bypass_T, UInt<1>(0h0)) node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<4>(0h0)) node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 1, 0) node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount) node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 3, 0) node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_6_bypass_sub_0_1 = geq(pre_s6_req.size, UInt<3>(0h4)) node pre_s3_6_bypass_size = bits(pre_s3_6_bypass_sizeOH, 3, 3) node pre_s3_6_bypass_bit = bits(pre_s6_req.offset, 3, 3) node pre_s3_6_bypass_nbit = eq(pre_s3_6_bypass_bit, UInt<1>(0h0)) node pre_s3_6_bypass_eq = and(UInt<1>(0h1), pre_s3_6_bypass_nbit) node _pre_s3_6_bypass_acc_T = and(pre_s3_6_bypass_size, pre_s3_6_bypass_eq) node pre_s3_6_bypass_acc = or(pre_s3_6_bypass_sub_0_1, _pre_s3_6_bypass_acc_T) node pre_s3_6_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_6_bypass_bit) node _pre_s3_6_bypass_acc_T_1 = and(pre_s3_6_bypass_size, pre_s3_6_bypass_eq_1) node pre_s3_6_bypass_acc_1 = or(pre_s3_6_bypass_sub_0_1, _pre_s3_6_bypass_acc_T_1) node _pre_s3_6_bypass_T = cat(pre_s3_6_bypass_acc_1, pre_s3_6_bypass_acc) node pre_s3_6_bypass = mux(pre_s3_6_match, _pre_s3_6_bypass_T, UInt<1>(0h0)) reg s3_bypass_data_REG : UInt, clock connect s3_bypass_data_REG, pre_s3_4_bypass node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0) node _s3_bypass_data_T_1 = bits(pre_s3_6_bypass, 1, 1) node _s3_bypass_data_T_2 = bits(pre_s6_dat, 63, 0) node _s3_bypass_data_T_3 = bits(pre_s6_dat, 127, 64) node _s3_bypass_data_T_4 = bits(pre_s7_dat, 63, 0) node _s3_bypass_data_T_5 = bits(pre_s7_dat, 127, 64) node _s3_bypass_data_T_6 = mux(_s3_bypass_data_T, _s3_bypass_data_T_2, _s3_bypass_data_T_4) node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_1, _s3_bypass_data_T_3, _s3_bypass_data_T_5) node _s3_bypass_data_T_8 = cat(_s3_bypass_data_T_7, _s3_bypass_data_T_6) node _s3_bypass_data_T_9 = bits(pre_s3_5_bypass, 0, 0) node _s3_bypass_data_T_10 = bits(pre_s3_5_bypass, 1, 1) node _s3_bypass_data_T_11 = bits(pre_s5_dat, 63, 0) node _s3_bypass_data_T_12 = bits(pre_s5_dat, 127, 64) node _s3_bypass_data_T_13 = bits(_s3_bypass_data_T_8, 63, 0) node _s3_bypass_data_T_14 = bits(_s3_bypass_data_T_8, 127, 64) node _s3_bypass_data_T_15 = mux(_s3_bypass_data_T_9, _s3_bypass_data_T_11, _s3_bypass_data_T_13) node _s3_bypass_data_T_16 = mux(_s3_bypass_data_T_10, _s3_bypass_data_T_12, _s3_bypass_data_T_14) node _s3_bypass_data_T_17 = cat(_s3_bypass_data_T_16, _s3_bypass_data_T_15) reg s3_bypass_data_REG_1 : UInt, clock connect s3_bypass_data_REG_1, _s3_bypass_data_T_17 node _s3_bypass_data_T_18 = bits(s3_bypass_data_REG, 0, 0) node _s3_bypass_data_T_19 = bits(s3_bypass_data_REG, 1, 1) node _s3_bypass_data_T_20 = bits(atomics.io.data_out, 63, 0) node _s3_bypass_data_T_21 = bits(atomics.io.data_out, 127, 64) node _s3_bypass_data_T_22 = bits(s3_bypass_data_REG_1, 63, 0) node _s3_bypass_data_T_23 = bits(s3_bypass_data_REG_1, 127, 64) node _s3_bypass_data_T_24 = mux(_s3_bypass_data_T_18, _s3_bypass_data_T_20, _s3_bypass_data_T_22) node _s3_bypass_data_T_25 = mux(_s3_bypass_data_T_19, _s3_bypass_data_T_21, _s3_bypass_data_T_23) node _s3_bypass_data_T_26 = cat(_s3_bypass_data_T_25, _s3_bypass_data_T_24) connect s3_bypass_data, _s3_bypass_data_T_26 node _s1_2_match_T = eq(s2_req.set, s1_req.set) node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way) node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1) node _s1_2_match_T_3 = eq(s2_beat, s1_beat) node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3) node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full) node s1_2_match = and(_s1_2_match_T_5, s2_retires) node _s1_3_match_T = eq(s3_req.set, s1_req.set) node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way) node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1) node _s1_3_match_T_3 = eq(s3_beat, s1_beat) node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3) node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full) node s1_3_match = and(_s1_3_match_T_5, s3_retires) node _s1_4_match_T = eq(s4_req.set, s1_req.set) node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way) node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1) node _s1_4_match_T_3 = eq(s4_beat, s1_beat) node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3) node s1_4_match = and(_s1_4_match_T_4, s4_full) node s2 = eq(s1_2_match, UInt<1>(0h1)) node s3 = eq(s1_3_match, UInt<1>(0h0)) node s4 = eq(s1_4_match, UInt<1>(0h0)) node _T_79 = and(io.req.valid, s2) node _T_80 = and(_T_79, s3) node _T_81 = and(_T_80, s4) node s2_1 = eq(s1_2_match, UInt<1>(0h1)) node s3_1 = eq(s1_3_match, UInt<1>(0h0)) node s4_1 = eq(s1_4_match, UInt<1>(0h0)) node _T_82 = and(io.req.valid, s2_1) node _T_83 = and(_T_82, s3_1) node _T_84 = and(_T_83, s4_1) node s2_2 = eq(s1_2_match, UInt<1>(0h1)) node s3_2 = eq(s1_3_match, UInt<1>(0h0)) node s4_2 = eq(s1_4_match, UInt<1>(0h0)) node _T_85 = and(io.req.valid, s2_2) node _T_86 = and(_T_85, s3_2) node _T_87 = and(_T_86, s4_2) node s2_3 = eq(s1_2_match, UInt<1>(0h1)) node s3_3 = eq(s1_3_match, UInt<1>(0h0)) node s4_3 = eq(s1_4_match, UInt<1>(0h0)) node _T_88 = and(io.req.valid, s2_3) node _T_89 = and(_T_88, s3_3) node _T_90 = and(_T_89, s4_3) node s2_4 = eq(s1_2_match, UInt<1>(0h1)) node s3_4 = eq(s1_3_match, UInt<1>(0h0)) node s4_4 = eq(s1_4_match, UInt<1>(0h0)) node _T_91 = and(io.req.valid, s2_4) node _T_92 = and(_T_91, s3_4) node _T_93 = and(_T_92, s4_4) node s2_5 = eq(s1_2_match, UInt<1>(0h1)) node s3_5 = eq(s1_3_match, UInt<1>(0h0)) node s4_5 = eq(s1_4_match, UInt<1>(0h0)) node _T_94 = and(io.req.valid, s2_5) node _T_95 = and(_T_94, s3_5) node _T_96 = and(_T_95, s4_5) node s2_6 = eq(s1_2_match, UInt<1>(0h1)) node s3_6 = eq(s1_3_match, UInt<1>(0h0)) node s4_6 = eq(s1_4_match, UInt<1>(0h0)) node _T_97 = and(io.req.valid, s2_6) node _T_98 = and(_T_97, s3_6) node _T_99 = and(_T_98, s4_6) node s2_7 = eq(s1_2_match, UInt<1>(0h1)) node s3_7 = eq(s1_3_match, UInt<1>(0h0)) node s4_7 = eq(s1_4_match, UInt<1>(0h0)) node _T_100 = and(io.req.valid, s2_7) node _T_101 = and(_T_100, s3_7) node _T_102 = and(_T_101, s4_7) node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<4>(0h0)) node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 1, 0) node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount) node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 3, 0) node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_2_bypass_sub_0_1 = geq(s2_req.size, UInt<3>(0h4)) node s1_2_bypass_size = bits(s1_2_bypass_sizeOH, 3, 3) node s1_2_bypass_bit = bits(s2_req.offset, 3, 3) node s1_2_bypass_nbit = eq(s1_2_bypass_bit, UInt<1>(0h0)) node s1_2_bypass_eq = and(UInt<1>(0h1), s1_2_bypass_nbit) node _s1_2_bypass_acc_T = and(s1_2_bypass_size, s1_2_bypass_eq) node s1_2_bypass_acc = or(s1_2_bypass_sub_0_1, _s1_2_bypass_acc_T) node s1_2_bypass_eq_1 = and(UInt<1>(0h1), s1_2_bypass_bit) node _s1_2_bypass_acc_T_1 = and(s1_2_bypass_size, s1_2_bypass_eq_1) node s1_2_bypass_acc_1 = or(s1_2_bypass_sub_0_1, _s1_2_bypass_acc_T_1) node _s1_2_bypass_T = cat(s1_2_bypass_acc_1, s1_2_bypass_acc) node s1_2_bypass = mux(s1_2_match, _s1_2_bypass_T, UInt<1>(0h0)) node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<4>(0h0)) node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 1, 0) node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount) node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 3, 0) node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_3_bypass_sub_0_1 = geq(s3_req.size, UInt<3>(0h4)) node s1_3_bypass_size = bits(s1_3_bypass_sizeOH, 3, 3) node s1_3_bypass_bit = bits(s3_req.offset, 3, 3) node s1_3_bypass_nbit = eq(s1_3_bypass_bit, UInt<1>(0h0)) node s1_3_bypass_eq = and(UInt<1>(0h1), s1_3_bypass_nbit) node _s1_3_bypass_acc_T = and(s1_3_bypass_size, s1_3_bypass_eq) node s1_3_bypass_acc = or(s1_3_bypass_sub_0_1, _s1_3_bypass_acc_T) node s1_3_bypass_eq_1 = and(UInt<1>(0h1), s1_3_bypass_bit) node _s1_3_bypass_acc_T_1 = and(s1_3_bypass_size, s1_3_bypass_eq_1) node s1_3_bypass_acc_1 = or(s1_3_bypass_sub_0_1, _s1_3_bypass_acc_T_1) node _s1_3_bypass_T = cat(s1_3_bypass_acc_1, s1_3_bypass_acc) node s1_3_bypass = mux(s1_3_match, _s1_3_bypass_T, UInt<1>(0h0)) node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<4>(0h0)) node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 1, 0) node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount) node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 3, 0) node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_4_bypass_sub_0_1 = geq(s4_req.size, UInt<3>(0h4)) node s1_4_bypass_size = bits(s1_4_bypass_sizeOH, 3, 3) node s1_4_bypass_bit = bits(s4_req.offset, 3, 3) node s1_4_bypass_nbit = eq(s1_4_bypass_bit, UInt<1>(0h0)) node s1_4_bypass_eq = and(UInt<1>(0h1), s1_4_bypass_nbit) node _s1_4_bypass_acc_T = and(s1_4_bypass_size, s1_4_bypass_eq) node s1_4_bypass_acc = or(s1_4_bypass_sub_0_1, _s1_4_bypass_acc_T) node s1_4_bypass_eq_1 = and(UInt<1>(0h1), s1_4_bypass_bit) node _s1_4_bypass_acc_T_1 = and(s1_4_bypass_size, s1_4_bypass_eq_1) node s1_4_bypass_acc_1 = or(s1_4_bypass_sub_0_1, _s1_4_bypass_acc_T_1) node _s1_4_bypass_T = cat(s1_4_bypass_acc_1, s1_4_bypass_acc) node s1_4_bypass = mux(s1_4_match, _s1_4_bypass_T, UInt<1>(0h0)) node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass) node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass) connect s1_x_bypass, _s1_x_bypass_T_1 node _io_evict_safe_T = eq(busy, UInt<1>(0h0)) node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way) node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1) node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set) node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3) node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way) node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6) node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set) node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8) node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9) node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way) node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12) node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set) node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14) node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15) node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way) node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18) node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set) node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20) node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21) connect io.evict_safe, _io_evict_safe_T_22 node _io_grant_safe_T = eq(busy, UInt<1>(0h0)) node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way) node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1) node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set) node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3) node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way) node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6) node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set) node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8) node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9) node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way) node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12) node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set) node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14) node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15) node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way) node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18) node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set) node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20) node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21) connect io.grant_safe, _io_grant_safe_T_22

module SourceD_7( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [5:0] io_req_bits_source, // @[SourceD.scala:50:14] input [8:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [10:0] io_req_bits_set, // @[SourceD.scala:50:14] input [3:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [3:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [5:0] io_d_bits_source, // @[SourceD.scala:50:14] output [3:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [127:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [15:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] input io_rel_pop_ready, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_rel_beat_data, // @[SourceD.scala:50:14] input io_rel_beat_corrupt, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [3:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [10:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [127:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [3:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [10:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [127:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [10:0] io_evict_req_set, // @[SourceD.scala:50:14] input [3:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [10:0] io_grant_req_set, // @[SourceD.scala:50:14] input [3:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [127:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire [127:0] _queue_io_deq_bits_data; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [3:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [3:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [15:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [127:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [10:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [3:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [10:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [3:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire s1_mask_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_5_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_6_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_2_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_3_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [15:0] _s2_pdata_raw_mask_T = 16'hFFFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [5:0] d_bits_source; // @[SourceD.scala:218:15] wire [3:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [127:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [3:0] s1_req_way; // @[SourceD.scala:88:19] wire [10:0] s1_req_set; // @[SourceD.scala:88:19] wire [1:0] s1_beat; // @[SourceD.scala:102:56] wire [1:0] s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire [1:0] _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:275:30] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [3:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [127:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [10:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [10:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [127:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [1:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [8:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [10:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [3:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [3:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [8:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [3:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire [1:0] _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire [1:0] s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy | io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 | s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg [1:0] s1_bypass_r; // @[SourceD.scala:91:62] wire [1:0] s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [3:0] _s1_mask_sizeOH_T = {1'h0, s1_req_size}; // @[Misc.scala:202:34] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire s1_mask_sub_0_1 = s1_req_size[2]; // @[Misc.scala:206:21] wire s1_mask_bit = s1_req_offset[3]; // @[Misc.scala:210:26] wire s1_mask_eq_1 = s1_mask_bit; // @[Misc.scala:210:26, :214:27] wire s1_mask_nbit = ~s1_mask_bit; // @[Misc.scala:210:26, :211:20] wire s1_mask_eq = s1_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _s1_mask_acc_T = s1_mask_eq; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc = s1_mask_sub_0_1 | _s1_mask_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _s1_mask_acc_T_1 = s1_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc_1 = s1_mask_sub_0_1 | _s1_mask_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire [1:0] _s1_mask_T = {s1_mask_acc_1, s1_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] _s1_mask_T_1 = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T & _s1_mask_T_1; // @[Misc.scala:222:10] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 | _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T = |s1_mask; // @[SourceD.scala:92:76, :94:27] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = |s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 | _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T | s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [1:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:4]; // @[package.scala:243:46] wire [1:0] s1_beats1 = s1_single ? 2'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [1:0] _s1_beat_T = s1_req_offset[5:4]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T | s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 2'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [2:0] _s1_counter_T = {1'h0, s1_counter} + 3'h1; // @[SourceD.scala:86:27, :130:30] wire [1:0] _s1_counter_T_1 = _s1_counter_T[1:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 | io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [1:0] s2_beat; // @[SourceD.scala:149:26] reg [1:0] s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] reg [5:0] s2_req_source; // @[SourceD.scala:151:25] reg [8:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [10:0] s2_req_set; // @[SourceD.scala:151:25] reg [3:0] s2_req_sink; // @[SourceD.scala:151:25] reg [3:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T | s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [127:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [15:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [127:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [15:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [127:0] s2_pdata_r_data; // @[package.scala:88:63] reg [15:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [127:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [15:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 16'hFFFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T | pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 | pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T | _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [1:0] s3_beat; // @[SourceD.scala:192:26] wire [1:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg [1:0] s3_bypass; // @[SourceD.scala:193:28] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] reg [5:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [8:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [10:0] s3_req_set; // @[SourceD.scala:194:25] reg [3:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [3:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [8:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [10:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [3:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [3:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [127:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [15:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T | _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [127:0] _s3_bypass_data_T_26; // @[package.scala:45:27] wire [127:0] s3_bypass_data; // @[SourceD.scala:206:28] wire _s3_rdata_T = s3_bypass[0]; // @[SourceD.scala:193:28, :208:78] wire _s3_rdata_T_1 = s3_bypass[1]; // @[SourceD.scala:193:28, :208:78] wire [63:0] _s3_rdata_T_2 = s3_bypass_data[63:0]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_3 = s3_bypass_data[127:64]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_4 = _queue_io_deq_bits_data[63:0]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_5 = _queue_io_deq_bits_data[127:64]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_6 = _s3_rdata_T ? _s3_rdata_T_2 : _s3_rdata_T_4; // @[SourceD.scala:207:78, :208:78, :210:75] wire [63:0] _s3_rdata_T_7 = _s3_rdata_T_1 ? _s3_rdata_T_3 : _s3_rdata_T_5; // @[SourceD.scala:207:78, :208:78, :210:75] wire [127:0] s3_rdata = {_s3_rdata_T_7, _s3_rdata_T_6}; // @[package.scala:45:27] assign d_bits_data = s3_rdata; // @[package.scala:45:27] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = |s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T | d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 | d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T | _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [1:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [1:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] reg [5:0] s4_req_source; // @[SourceD.scala:253:25] reg [8:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [10:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [3:0] s4_req_sink; // @[SourceD.scala:253:25] reg [3:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [8:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [10:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [3:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [3:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [127:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [15:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [127:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = s4_pdata_mask[8]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_9 = s4_pdata_mask[9]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_10 = s4_pdata_mask[10]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_11 = s4_pdata_mask[11]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_12 = s4_pdata_mask[12]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_13 = s4_pdata_mask[13]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_14 = s4_pdata_mask[14]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_15 = s4_pdata_mask[15]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_16 = _io_bs_wadr_bits_mask_T | _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_17 = _io_bs_wadr_bits_mask_T_16 | _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_18 = _io_bs_wadr_bits_mask_T_17 | _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_19 = _io_bs_wadr_bits_mask_T_18 | _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_20 = _io_bs_wadr_bits_mask_T_19 | _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_21 = _io_bs_wadr_bits_mask_T_20 | _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_22 = _io_bs_wadr_bits_mask_T_21 | _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_23 = _io_bs_wadr_bits_mask_T_8 | _io_bs_wadr_bits_mask_T_9; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_24 = _io_bs_wadr_bits_mask_T_23 | _io_bs_wadr_bits_mask_T_10; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_25 = _io_bs_wadr_bits_mask_T_24 | _io_bs_wadr_bits_mask_T_11; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_26 = _io_bs_wadr_bits_mask_T_25 | _io_bs_wadr_bits_mask_T_12; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_27 = _io_bs_wadr_bits_mask_T_26 | _io_bs_wadr_bits_mask_T_13; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_28 = _io_bs_wadr_bits_mask_T_27 | _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_29 = _io_bs_wadr_bits_mask_T_28 | _io_bs_wadr_bits_mask_T_15; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_30 = {_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22}; // @[SourceD.scala:275:{30,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:48:7, :275:30]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_226 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_226( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<12>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<12>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<12>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<12>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<12>, source : UInt<5>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<12>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<2>, clock reg probes_toN : UInt<2>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<4>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 3, 0) node _req_clientBit_T = shr(request.source, 4) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<1>(0h1)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<4>(0h8)) node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<4>(0h0)) node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 3, 0) node _req_clientBit_T_6 = shr(request.source, 4) node _req_clientBit_T_7 = eq(_req_clientBit_T_6, UInt<1>(0h0)) node _req_clientBit_T_8 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1) node _req_clientBit_T_9 = and(_req_clientBit_T_7, _req_clientBit_T_8) node _req_clientBit_T_10 = leq(req_clientBit_uncommonBits_1, UInt<4>(0h8)) node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10) node req_clientBit = cat(_req_clientBit_T_11, _req_clientBit_T_5) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,false,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,false,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,false,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,false,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(_T_110, UInt<1>(0h0)) node _T_112 = asUInt(reset) node _T_113 = eq(_T_112, UInt<1>(0h0)) when _T_113 : node _T_114 = eq(_T_111, UInt<1>(0h0)) when _T_114 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_111, UInt<1>(0h1), "") : assert_14 node _T_115 = eq(before, UInt<4>(0h8)) node _T_116 = eq(after, UInt<3>(0h5)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_118, UInt<1>(0h1), "") : assert_15 node _T_122 = eq(before, UInt<4>(0h8)) node _T_123 = eq(after, UInt<3>(0h4)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_125, UInt<1>(0h1), "") : assert_16 node _T_129 = eq(before, UInt<4>(0h8)) node _T_130 = eq(after, UInt<3>(0h6)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(_T_131, UInt<1>(0h0)) node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_T_132, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_132, UInt<1>(0h1), "") : assert_17 node _T_136 = eq(before, UInt<4>(0h8)) node _T_137 = eq(after, UInt<2>(0h3)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(before, UInt<4>(0h8)) node _T_140 = eq(after, UInt<2>(0h2)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(_T_141, UInt<1>(0h0)) node _T_143 = asUInt(reset) node _T_144 = eq(_T_143, UInt<1>(0h0)) when _T_144 : node _T_145 = eq(_T_142, UInt<1>(0h0)) when _T_145 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_142, UInt<1>(0h1), "") : assert_18 node _T_146 = eq(before, UInt<1>(0h1)) node _T_147 = eq(after, UInt<4>(0h8)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_149, UInt<1>(0h1), "") : assert_19 node _T_153 = eq(before, UInt<1>(0h1)) node _T_154 = eq(after, UInt<1>(0h0)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(_T_155, UInt<1>(0h0)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_156, UInt<1>(0h1), "") : assert_20 node _T_160 = eq(before, UInt<1>(0h1)) node _T_161 = eq(after, UInt<3>(0h7)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(_T_162, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_163, UInt<1>(0h1), "") : assert_21 node _T_167 = eq(before, UInt<1>(0h1)) node _T_168 = eq(after, UInt<3>(0h5)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_170, UInt<1>(0h1), "") : assert_22 node _T_174 = eq(before, UInt<1>(0h1)) node _T_175 = eq(after, UInt<3>(0h4)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = asUInt(reset) node _T_179 = eq(_T_178, UInt<1>(0h0)) when _T_179 : node _T_180 = eq(_T_177, UInt<1>(0h0)) when _T_180 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_177, UInt<1>(0h1), "") : assert_23 node _T_181 = eq(before, UInt<1>(0h1)) node _T_182 = eq(after, UInt<3>(0h6)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(_T_183, UInt<1>(0h0)) node _T_185 = asUInt(reset) node _T_186 = eq(_T_185, UInt<1>(0h0)) when _T_186 : node _T_187 = eq(_T_184, UInt<1>(0h0)) when _T_187 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_184, UInt<1>(0h1), "") : assert_24 node _T_188 = eq(before, UInt<1>(0h1)) node _T_189 = eq(after, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(_T_190, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(before, UInt<1>(0h1)) node _T_196 = eq(after, UInt<2>(0h2)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = asUInt(reset) node _T_200 = eq(_T_199, UInt<1>(0h0)) when _T_200 : node _T_201 = eq(_T_198, UInt<1>(0h0)) when _T_201 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_198, UInt<1>(0h1), "") : assert_26 node _T_202 = eq(before, UInt<1>(0h0)) node _T_203 = eq(after, UInt<4>(0h8)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(_T_204, UInt<1>(0h0)) node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(_T_205, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_205, UInt<1>(0h1), "") : assert_27 node _T_209 = eq(before, UInt<1>(0h0)) node _T_210 = eq(after, UInt<1>(0h1)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(_T_211, UInt<1>(0h0)) node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(_T_212, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_212, UInt<1>(0h1), "") : assert_28 node _T_216 = eq(before, UInt<1>(0h0)) node _T_217 = eq(after, UInt<3>(0h7)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(_T_218, UInt<1>(0h0)) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_219, UInt<1>(0h1), "") : assert_29 node _T_223 = eq(before, UInt<1>(0h0)) node _T_224 = eq(after, UInt<3>(0h5)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(_T_225, UInt<1>(0h0)) node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(_T_226, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_226, UInt<1>(0h1), "") : assert_30 node _T_230 = eq(before, UInt<1>(0h0)) node _T_231 = eq(after, UInt<3>(0h6)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_233, UInt<1>(0h1), "") : assert_31 node _T_237 = eq(before, UInt<1>(0h0)) node _T_238 = eq(after, UInt<3>(0h4)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(_T_239, UInt<1>(0h0)) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_240, UInt<1>(0h1), "") : assert_32 node _T_244 = eq(before, UInt<1>(0h0)) node _T_245 = eq(after, UInt<2>(0h3)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(_T_246, UInt<1>(0h0)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_247, UInt<1>(0h1), "") : assert_33 node _T_251 = eq(before, UInt<1>(0h0)) node _T_252 = eq(after, UInt<2>(0h2)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_254, UInt<1>(0h1), "") : assert_34 node _T_258 = eq(before, UInt<3>(0h7)) node _T_259 = eq(after, UInt<4>(0h8)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_T_261, UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_261, UInt<1>(0h1), "") : assert_35 node _T_265 = eq(before, UInt<3>(0h7)) node _T_266 = eq(after, UInt<1>(0h1)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_268, UInt<1>(0h1), "") : assert_36 node _T_272 = eq(before, UInt<3>(0h7)) node _T_273 = eq(after, UInt<1>(0h0)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_275, UInt<1>(0h1), "") : assert_37 node _T_279 = eq(before, UInt<3>(0h7)) node _T_280 = eq(after, UInt<3>(0h5)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_282, UInt<1>(0h1), "") : assert_38 node _T_286 = eq(before, UInt<3>(0h7)) node _T_287 = eq(after, UInt<3>(0h6)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = asUInt(reset) node _T_291 = eq(_T_290, UInt<1>(0h0)) when _T_291 : node _T_292 = eq(_T_289, UInt<1>(0h0)) when _T_292 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_289, UInt<1>(0h1), "") : assert_39 node _T_293 = eq(before, UInt<3>(0h7)) node _T_294 = eq(after, UInt<3>(0h4)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(_T_295, UInt<1>(0h0)) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_296, UInt<1>(0h1), "") : assert_40 node _T_300 = eq(before, UInt<3>(0h7)) node _T_301 = eq(after, UInt<2>(0h3)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(before, UInt<3>(0h7)) node _T_304 = eq(after, UInt<2>(0h2)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(_T_305, UInt<1>(0h0)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_306, UInt<1>(0h1), "") : assert_41 node _T_310 = eq(before, UInt<3>(0h5)) node _T_311 = eq(after, UInt<4>(0h8)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_313, UInt<1>(0h1), "") : assert_42 node _T_317 = eq(before, UInt<3>(0h5)) node _T_318 = eq(after, UInt<1>(0h1)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(_T_319, UInt<1>(0h0)) node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_T_320, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_320, UInt<1>(0h1), "") : assert_43 node _T_324 = eq(before, UInt<3>(0h5)) node _T_325 = eq(after, UInt<1>(0h0)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(_T_326, UInt<1>(0h0)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_327, UInt<1>(0h1), "") : assert_44 node _T_331 = eq(before, UInt<3>(0h5)) node _T_332 = eq(after, UInt<3>(0h7)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(before, UInt<3>(0h5)) node _T_335 = eq(after, UInt<3>(0h6)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_337, UInt<1>(0h1), "") : assert_45 node _T_341 = eq(before, UInt<3>(0h5)) node _T_342 = eq(after, UInt<3>(0h4)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(_T_343, UInt<1>(0h0)) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_344, UInt<1>(0h1), "") : assert_46 node _T_348 = eq(before, UInt<3>(0h5)) node _T_349 = eq(after, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _T_351 = eq(before, UInt<3>(0h5)) node _T_352 = eq(after, UInt<2>(0h2)) node _T_353 = and(_T_351, _T_352) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_354, UInt<1>(0h1), "") : assert_47 node _T_358 = eq(before, UInt<3>(0h6)) node _T_359 = eq(after, UInt<4>(0h8)) node _T_360 = and(_T_358, _T_359) node _T_361 = eq(_T_360, UInt<1>(0h0)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_361, UInt<1>(0h1), "") : assert_48 node _T_365 = eq(before, UInt<3>(0h6)) node _T_366 = eq(after, UInt<1>(0h1)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(_T_367, UInt<1>(0h0)) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_368, UInt<1>(0h1), "") : assert_49 node _T_372 = eq(before, UInt<3>(0h6)) node _T_373 = eq(after, UInt<1>(0h0)) node _T_374 = and(_T_372, _T_373) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_375, UInt<1>(0h1), "") : assert_50 node _T_379 = eq(before, UInt<3>(0h6)) node _T_380 = eq(after, UInt<3>(0h7)) node _T_381 = and(_T_379, _T_380) node _T_382 = eq(_T_381, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_382, UInt<1>(0h1), "") : assert_51 node _T_386 = eq(before, UInt<3>(0h6)) node _T_387 = eq(after, UInt<3>(0h5)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(_T_388, UInt<1>(0h0)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_389, UInt<1>(0h1), "") : assert_52 node _T_393 = eq(before, UInt<3>(0h6)) node _T_394 = eq(after, UInt<3>(0h4)) node _T_395 = and(_T_393, _T_394) node _T_396 = eq(_T_395, UInt<1>(0h0)) node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(_T_396, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_396, UInt<1>(0h1), "") : assert_53 node _T_400 = eq(before, UInt<3>(0h6)) node _T_401 = eq(after, UInt<2>(0h3)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(_T_402, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_403, UInt<1>(0h1), "") : assert_54 node _T_407 = eq(before, UInt<3>(0h6)) node _T_408 = eq(after, UInt<2>(0h2)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(before, UInt<3>(0h4)) node _T_411 = eq(after, UInt<4>(0h8)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(_T_412, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_413, UInt<1>(0h1), "") : assert_55 node _T_417 = eq(before, UInt<3>(0h4)) node _T_418 = eq(after, UInt<1>(0h1)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(_T_419, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_420, UInt<1>(0h1), "") : assert_56 node _T_424 = eq(before, UInt<3>(0h4)) node _T_425 = eq(after, UInt<1>(0h0)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_427, UInt<1>(0h1), "") : assert_57 node _T_431 = eq(before, UInt<3>(0h4)) node _T_432 = eq(after, UInt<3>(0h7)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(_T_433, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_434, UInt<1>(0h1), "") : assert_58 node _T_438 = eq(before, UInt<3>(0h4)) node _T_439 = eq(after, UInt<3>(0h5)) node _T_440 = and(_T_438, _T_439) node _T_441 = eq(_T_440, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_441, UInt<1>(0h1), "") : assert_59 node _T_445 = eq(before, UInt<3>(0h4)) node _T_446 = eq(after, UInt<3>(0h6)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(before, UInt<3>(0h4)) node _T_449 = eq(after, UInt<2>(0h3)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(_T_450, UInt<1>(0h0)) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_451, UInt<1>(0h1), "") : assert_60 node _T_455 = eq(before, UInt<3>(0h4)) node _T_456 = eq(after, UInt<2>(0h2)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(before, UInt<2>(0h3)) node _T_459 = eq(after, UInt<4>(0h8)) node _T_460 = and(_T_458, _T_459) node _T_461 = eq(_T_460, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_461, UInt<1>(0h1), "") : assert_61 node _T_465 = eq(before, UInt<2>(0h3)) node _T_466 = eq(after, UInt<1>(0h1)) node _T_467 = and(_T_465, _T_466) node _T_468 = eq(_T_467, UInt<1>(0h0)) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_468, UInt<1>(0h1), "") : assert_62 node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<1>(0h0)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_475, UInt<1>(0h1), "") : assert_63 node _T_479 = eq(before, UInt<2>(0h3)) node _T_480 = eq(after, UInt<3>(0h7)) node _T_481 = and(_T_479, _T_480) node _T_482 = eq(before, UInt<2>(0h3)) node _T_483 = eq(after, UInt<3>(0h5)) node _T_484 = and(_T_482, _T_483) node _T_485 = eq(before, UInt<2>(0h3)) node _T_486 = eq(after, UInt<3>(0h6)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(before, UInt<2>(0h3)) node _T_489 = eq(after, UInt<3>(0h4)) node _T_490 = and(_T_488, _T_489) node _T_491 = eq(before, UInt<2>(0h3)) node _T_492 = eq(after, UInt<2>(0h2)) node _T_493 = and(_T_491, _T_492) node _T_494 = eq(before, UInt<2>(0h2)) node _T_495 = eq(after, UInt<4>(0h8)) node _T_496 = and(_T_494, _T_495) node _T_497 = eq(_T_496, UInt<1>(0h0)) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_497, UInt<1>(0h1), "") : assert_64 node _T_501 = eq(before, UInt<2>(0h2)) node _T_502 = eq(after, UInt<1>(0h1)) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(_T_503, UInt<1>(0h0)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_504, UInt<1>(0h1), "") : assert_65 node _T_508 = eq(before, UInt<2>(0h2)) node _T_509 = eq(after, UInt<1>(0h0)) node _T_510 = and(_T_508, _T_509) node _T_511 = eq(_T_510, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_511, UInt<1>(0h1), "") : assert_66 node _T_515 = eq(before, UInt<2>(0h2)) node _T_516 = eq(after, UInt<3>(0h7)) node _T_517 = and(_T_515, _T_516) node _T_518 = eq(_T_517, UInt<1>(0h0)) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_518, UInt<1>(0h1), "") : assert_67 node _T_522 = eq(before, UInt<2>(0h2)) node _T_523 = eq(after, UInt<3>(0h5)) node _T_524 = and(_T_522, _T_523) node _T_525 = eq(_T_524, UInt<1>(0h0)) node _T_526 = asUInt(reset) node _T_527 = eq(_T_526, UInt<1>(0h0)) when _T_527 : node _T_528 = eq(_T_525, UInt<1>(0h0)) when _T_528 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_68 assert(clock, _T_525, UInt<1>(0h1), "") : assert_68 node _T_529 = eq(before, UInt<2>(0h2)) node _T_530 = eq(after, UInt<3>(0h6)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(before, UInt<2>(0h2)) node _T_533 = eq(after, UInt<3>(0h4)) node _T_534 = and(_T_532, _T_533) node _T_535 = eq(before, UInt<2>(0h2)) node _T_536 = eq(after, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(_T_537, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_69 assert(clock, _T_538, UInt<1>(0h1), "") : assert_69 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<4>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 3, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 4) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<1>(0h1)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<4>(0h8)) node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4) node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<4>(0h0)) node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 3, 0) node _probe_bit_T_6 = shr(io.sinkc.bits.source, 4) node _probe_bit_T_7 = eq(_probe_bit_T_6, UInt<1>(0h0)) node _probe_bit_T_8 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1) node _probe_bit_T_9 = and(_probe_bit_T_7, _probe_bit_T_8) node _probe_bit_T_10 = leq(probe_bit_uncommonBits_1, UInt<4>(0h8)) node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10) node probe_bit = cat(_probe_bit_T_11, _probe_bit_T_5) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_542 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_543 = and(probe_toN, _T_542) node _T_544 = eq(probe_toN, UInt<1>(0h0)) node _T_545 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_546 = and(_T_544, _T_545) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_547 = eq(set_pprobeack, UInt<1>(0h0)) node _T_548 = and(_T_547, w_rprobeackfirst) node _T_549 = and(set_pprobeack, w_rprobeackfirst) node _T_550 = neq(meta.state, UInt<2>(0h0)) node _T_551 = eq(io.sinkc.bits.tag, meta.tag) node _T_552 = and(_T_550, _T_551) node _T_553 = and(_T_552, io.sinkc.bits.data) when _T_553 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_554 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_555 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_556 = or(_T_554, _T_555) when _T_556 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_557 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_558 = eq(request.offset, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) node _T_560 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_561 = neq(request.offset, UInt<1>(0h0)) node _T_562 = and(_T_560, _T_561) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_563 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_563 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<4>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 3, 0) node _new_clientBit_T = shr(new_request.source, 4) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<1>(0h1)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<4>(0h8)) node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<4>(0h0)) node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 3, 0) node _new_clientBit_T_6 = shr(new_request.source, 4) node _new_clientBit_T_7 = eq(_new_clientBit_T_6, UInt<1>(0h0)) node _new_clientBit_T_8 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1) node _new_clientBit_T_9 = and(_new_clientBit_T_7, _new_clientBit_T_8) node _new_clientBit_T_10 = leq(new_clientBit_uncommonBits_1, UInt<4>(0h8)) node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10) node new_clientBit = cat(_new_clientBit_T_11, _new_clientBit_T_5) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_564 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_564 : node _T_565 = eq(prior, UInt<4>(0h8)) node _T_566 = eq(prior, UInt<1>(0h1)) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_70 assert(clock, _T_567, UInt<1>(0h1), "") : assert_70 node _T_571 = eq(prior, UInt<1>(0h0)) node _T_572 = eq(_T_571, UInt<1>(0h0)) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_71 assert(clock, _T_572, UInt<1>(0h1), "") : assert_71 node _T_576 = eq(prior, UInt<3>(0h7)) node _T_577 = eq(prior, UInt<3>(0h5)) node _T_578 = eq(prior, UInt<3>(0h4)) node _T_579 = eq(prior, UInt<3>(0h6)) node _T_580 = eq(prior, UInt<2>(0h3)) node _T_581 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_582 = eq(request_valid, UInt<1>(0h0)) node _T_583 = and(io.schedule.ready, io.schedule.valid) node _T_584 = and(no_wait, _T_583) node _T_585 = or(_T_582, _T_584) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_72 assert(clock, _T_585, UInt<1>(0h1), "") : assert_72 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_589 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_590 = or(io.directory.valid, _T_589) when _T_590 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_591 = and(new_request.prio[2], UInt<1>(0h1)) when _T_591 : connect s_execute, UInt<1>(0h0) node _T_592 = bits(new_request.opcode, 0, 0) node _T_593 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_594 = and(_T_592, _T_593) when _T_594 : connect s_writeback, UInt<1>(0h0) node _T_595 = eq(new_request.param, UInt<3>(0h0)) node _T_596 = eq(new_request.param, UInt<3>(0h4)) node _T_597 = or(_T_595, _T_596) node _T_598 = eq(new_meta.state, UInt<2>(0h2)) node _T_599 = and(_T_597, _T_598) when _T_599 : connect s_writeback, UInt<1>(0h0) node _T_600 = eq(new_request.param, UInt<3>(0h1)) node _T_601 = eq(new_request.param, UInt<3>(0h2)) node _T_602 = or(_T_600, _T_601) node _T_603 = eq(new_request.param, UInt<3>(0h5)) node _T_604 = or(_T_602, _T_603) node _T_605 = and(new_meta.clients, new_clientBit) node _T_606 = neq(_T_605, UInt<1>(0h0)) node _T_607 = and(_T_604, _T_606) when _T_607 : connect s_writeback, UInt<1>(0h0) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(new_meta.hit, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_73 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_73 else : node _T_611 = and(new_request.control, UInt<1>(0h1)) when _T_611 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_612 = neq(new_meta.clients, UInt<1>(0h0)) node _T_613 = and(UInt<1>(0h1), _T_612) when _T_613 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_614 = eq(new_meta.hit, UInt<1>(0h0)) node _T_615 = neq(new_meta.state, UInt<2>(0h0)) node _T_616 = and(_T_614, _T_615) when _T_616 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_617 = neq(new_meta.clients, UInt<1>(0h0)) node _T_618 = and(UInt<1>(0h1), _T_617) when _T_618 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_619 = eq(new_meta.hit, UInt<1>(0h0)) node _T_620 = eq(new_meta.state, UInt<2>(0h1)) node _T_621 = and(_T_620, new_needT) node _T_622 = or(_T_619, _T_621) when _T_622 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_623 = eq(new_meta.state, UInt<2>(0h2)) node _T_624 = or(new_needT, _T_623) node _T_625 = and(new_meta.hit, _T_624) node _T_626 = not(new_skipProbe) node _T_627 = and(new_meta.clients, _T_626) node _T_628 = neq(_T_627, UInt<1>(0h0)) node _T_629 = and(_T_625, _T_628) node _T_630 = and(UInt<1>(0h1), _T_629) when _T_630 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_631 = eq(new_request.opcode, UInt<3>(0h6)) node _T_632 = eq(new_request.opcode, UInt<3>(0h7)) node _T_633 = or(_T_631, _T_632) when _T_633 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_634 = bits(new_request.opcode, 2, 2) node _T_635 = eq(_T_634, UInt<1>(0h0)) node _T_636 = and(_T_635, new_meta.hit) node _T_637 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_638 = and(_T_636, _T_637) when _T_638 : connect s_writeback, UInt<1>(0h0)

module MSHR_5( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [4:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [11:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [11:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [11:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [4:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [11:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [4:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [11:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [11:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [4:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [11:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [11:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [11:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [4:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [11:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [1:0] _io_schedule_bits_b_bits_clients_T = 2'h3; // @[MSHR.scala:289:53] wire [1:0] _last_probe_T_1 = 2'h3; // @[MSHR.scala:459:66] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] excluded_client = 2'h0; // @[MSHR.scala:279:28] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire [11:0] invalid_tag = 12'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [4:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [11:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [11:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [11:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [4:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [4:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [11:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [4:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [4:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [4:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [4:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [11:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire [1:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [11:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [11:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [3:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T = request_source[4]; // @[Parameters.scala:54:10] wire _req_clientBit_T_6 = request_source[4]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_7 = ~_req_clientBit_T_6; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 12'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [3:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10] wire _probe_bit_T_6 = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_7 = ~_probe_bit_T_6; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_10 = probe_bit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48] wire [1:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [11:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [4:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [11:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [4:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [4:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_631 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_631; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_631; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [3:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T = new_request_source[4]; // @[Parameters.scala:54:10] wire _new_clientBit_T_6 = new_request_source[4]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_7 = ~_new_clientBit_T_6; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_590 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_86 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<10>(0h200))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = and(_T_19, _T_24) node _T_26 = or(UInt<1>(0h0), _T_25) node _T_27 = and(_T_18, _T_26) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_33 = and(_T_31, _T_32) node _T_34 = or(UInt<1>(0h0), _T_33) node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<10>(0h200))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = and(_T_34, _T_39) node _T_41 = or(UInt<1>(0h0), _T_40) node _T_42 = and(UInt<1>(0h0), _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_42, UInt<1>(0h1), "") : assert_3 node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_49, UInt<1>(0h1), "") : assert_5 node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(is_aligned, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_56, UInt<1>(0h1), "") : assert_7 node _T_60 = not(io.in.a.bits.mask) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_61, UInt<1>(0h1), "") : assert_8 node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_69 : node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_71 = and(UInt<1>(0h0), _T_70) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<10>(0h200))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = and(_T_73, _T_78) node _T_80 = or(UInt<1>(0h0), _T_79) node _T_81 = and(_T_72, _T_80) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_81, UInt<1>(0h1), "") : assert_10 node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_87 = and(_T_85, _T_86) node _T_88 = or(UInt<1>(0h0), _T_87) node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<10>(0h200))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = and(_T_88, _T_93) node _T_95 = or(UInt<1>(0h0), _T_94) node _T_96 = and(UInt<1>(0h0), _T_95) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_96, UInt<1>(0h1), "") : assert_11 node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_103, UInt<1>(0h1), "") : assert_13 node _T_107 = asUInt(reset) node _T_108 = eq(_T_107, UInt<1>(0h0)) when _T_108 : node _T_109 = eq(is_aligned, UInt<1>(0h0)) when _T_109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_110, UInt<1>(0h1), "") : assert_15 node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_114, UInt<1>(0h1), "") : assert_16 node _T_118 = not(io.in.a.bits.mask) node _T_119 = eq(_T_118, UInt<1>(0h0)) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_119, UInt<1>(0h1), "") : assert_17 node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_T_123, UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_123, UInt<1>(0h1), "") : assert_18 node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_127 : node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_130 = and(_T_128, _T_129) node _T_131 = or(UInt<1>(0h0), _T_130) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_131, UInt<1>(0h1), "") : assert_19 node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_137 = and(_T_135, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<10>(0h200))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = and(_T_138, _T_143) node _T_145 = or(UInt<1>(0h0), _T_144) node _T_146 = asUInt(reset) node _T_147 = eq(_T_146, UInt<1>(0h0)) when _T_147 : node _T_148 = eq(_T_145, UInt<1>(0h0)) when _T_148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_145, UInt<1>(0h1), "") : assert_20 node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(is_aligned, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_155, UInt<1>(0h1), "") : assert_23 node _T_159 = eq(io.in.a.bits.mask, mask) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_159, UInt<1>(0h1), "") : assert_24 node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_163, UInt<1>(0h1), "") : assert_25 node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = or(UInt<1>(0h0), _T_170) node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_174 = and(_T_172, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<10>(0h200))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = and(_T_175, _T_180) node _T_182 = or(UInt<1>(0h0), _T_181) node _T_183 = and(_T_171, _T_182) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_183, UInt<1>(0h1), "") : assert_26 node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(is_aligned, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_193, UInt<1>(0h1), "") : assert_29 node _T_197 = eq(io.in.a.bits.mask, mask) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_197, UInt<1>(0h1), "") : assert_30 node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_201 : node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_203 = and(UInt<1>(0h0), _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_207 = and(_T_205, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<10>(0h200))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = and(_T_208, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(_T_204, _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_216, UInt<1>(0h1), "") : assert_31 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(is_aligned, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(_T_226, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_226, UInt<1>(0h1), "") : assert_34 node _T_230 = not(mask) node _T_231 = and(io.in.a.bits.mask, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_232, UInt<1>(0h1), "") : assert_35 node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_236 : node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_238 = and(UInt<1>(0h0), _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<10>(0h200))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = and(_T_240, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = and(_T_239, _T_247) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_248, UInt<1>(0h1), "") : assert_36 node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(is_aligned, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_258, UInt<1>(0h1), "") : assert_39 node _T_262 = eq(io.in.a.bits.mask, mask) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_262, UInt<1>(0h1), "") : assert_40 node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_266 : node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_268 = and(UInt<1>(0h0), _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<10>(0h200))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = and(_T_270, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = and(_T_269, _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_278, UInt<1>(0h1), "") : assert_41 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(is_aligned, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_288, UInt<1>(0h1), "") : assert_44 node _T_292 = eq(io.in.a.bits.mask, mask) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_292, UInt<1>(0h1), "") : assert_45 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_296 : node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_298 = and(UInt<1>(0h0), _T_297) node _T_299 = or(UInt<1>(0h0), _T_298) node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<10>(0h200))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = and(_T_300, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = and(_T_299, _T_307) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_308, UInt<1>(0h1), "") : assert_46 node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(is_aligned, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_318, UInt<1>(0h1), "") : assert_49 node _T_322 = eq(io.in.a.bits.mask, mask) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_322, UInt<1>(0h1), "") : assert_50 node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_327 = asUInt(reset) node _T_328 = eq(_T_327, UInt<1>(0h0)) when _T_328 : node _T_329 = eq(_T_326, UInt<1>(0h0)) when _T_329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_326, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_331 = asUInt(reset) node _T_332 = eq(_T_331, UInt<1>(0h0)) when _T_332 : node _T_333 = eq(_T_330, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_330, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_334 : node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_338, UInt<1>(0h1), "") : assert_54 node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_342, UInt<1>(0h1), "") : assert_55 node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_346, UInt<1>(0h1), "") : assert_56 node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(_T_350, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_350, UInt<1>(0h1), "") : assert_57 node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_354 : node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(sink_ok, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_361, UInt<1>(0h1), "") : assert_60 node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_365, UInt<1>(0h1), "") : assert_61 node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_369, UInt<1>(0h1), "") : assert_62 node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_373, UInt<1>(0h1), "") : assert_63 node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_378 = or(UInt<1>(0h1), _T_377) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_378, UInt<1>(0h1), "") : assert_64 node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_382 : node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(sink_ok, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_389, UInt<1>(0h1), "") : assert_67 node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_393, UInt<1>(0h1), "") : assert_68 node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_397, UInt<1>(0h1), "") : assert_69 node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_402 = or(_T_401, io.in.d.bits.corrupt) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_402, UInt<1>(0h1), "") : assert_70 node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_407 = or(UInt<1>(0h1), _T_406) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_407, UInt<1>(0h1), "") : assert_71 node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_411 : node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_415, UInt<1>(0h1), "") : assert_73 node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_419, UInt<1>(0h1), "") : assert_74 node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_424 = or(UInt<1>(0h1), _T_423) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_424, UInt<1>(0h1), "") : assert_75 node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_428 : node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_432, UInt<1>(0h1), "") : assert_77 node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_437 = or(_T_436, io.in.d.bits.corrupt) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_437, UInt<1>(0h1), "") : assert_78 node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_442 = or(UInt<1>(0h1), _T_441) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_442, UInt<1>(0h1), "") : assert_79 node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_450, UInt<1>(0h1), "") : assert_81 node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_454, UInt<1>(0h1), "") : assert_82 node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_459 = or(UInt<1>(0h1), _T_458) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_459, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_463, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_467, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_471, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_475 = eq(a_first, UInt<1>(0h0)) node _T_476 = and(io.in.a.valid, _T_475) when _T_476 : node _T_477 = eq(io.in.a.bits.opcode, opcode) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_477, UInt<1>(0h1), "") : assert_87 node _T_481 = eq(io.in.a.bits.param, param) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_481, UInt<1>(0h1), "") : assert_88 node _T_485 = eq(io.in.a.bits.size, size) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_485, UInt<1>(0h1), "") : assert_89 node _T_489 = eq(io.in.a.bits.source, source) node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_T_489, UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_489, UInt<1>(0h1), "") : assert_90 node _T_493 = eq(io.in.a.bits.address, address) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_493, UInt<1>(0h1), "") : assert_91 node _T_497 = and(io.in.a.ready, io.in.a.valid) node _T_498 = and(_T_497, a_first) when _T_498 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_499 = eq(d_first, UInt<1>(0h0)) node _T_500 = and(io.in.d.valid, _T_499) when _T_500 : node _T_501 = eq(io.in.d.bits.opcode, opcode_1) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_501, UInt<1>(0h1), "") : assert_92 node _T_505 = eq(io.in.d.bits.param, param_1) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_505, UInt<1>(0h1), "") : assert_93 node _T_509 = eq(io.in.d.bits.size, size_1) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_509, UInt<1>(0h1), "") : assert_94 node _T_513 = eq(io.in.d.bits.source, source_1) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_513, UInt<1>(0h1), "") : assert_95 node _T_517 = eq(io.in.d.bits.sink, sink) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_517, UInt<1>(0h1), "") : assert_96 node _T_521 = eq(io.in.d.bits.denied, denied) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_521, UInt<1>(0h1), "") : assert_97 node _T_525 = and(io.in.d.ready, io.in.d.valid) node _T_526 = and(_T_525, d_first) when _T_526 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_527 = and(io.in.a.valid, a_first_1) node _T_528 = and(_T_527, UInt<1>(0h1)) when _T_528 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_529 = and(io.in.a.ready, io.in.a.valid) node _T_530 = and(_T_529, a_first_1) node _T_531 = and(_T_530, UInt<1>(0h1)) when _T_531 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_532 = dshr(inflight, io.in.a.bits.source) node _T_533 = bits(_T_532, 0, 0) node _T_534 = eq(_T_533, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_534, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_538 = and(io.in.d.valid, d_first_1) node _T_539 = and(_T_538, UInt<1>(0h1)) node _T_540 = eq(d_release_ack, UInt<1>(0h0)) node _T_541 = and(_T_539, _T_540) when _T_541 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_542 = and(io.in.d.ready, io.in.d.valid) node _T_543 = and(_T_542, d_first_1) node _T_544 = and(_T_543, UInt<1>(0h1)) node _T_545 = eq(d_release_ack, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) when _T_546 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_551 = dshr(inflight, io.in.d.bits.source) node _T_552 = bits(_T_551, 0, 0) node _T_553 = or(_T_552, same_cycle_resp) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_553, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_559 = or(_T_557, _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_559, UInt<1>(0h1), "") : assert_100 node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_563, UInt<1>(0h1), "") : assert_101 else : node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_569 = or(_T_567, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_569, UInt<1>(0h1), "") : assert_102 node _T_573 = eq(io.in.d.bits.size, a_size_lookup) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_573, UInt<1>(0h1), "") : assert_103 node _T_577 = and(io.in.d.valid, d_first_1) node _T_578 = and(_T_577, a_first_1) node _T_579 = and(_T_578, io.in.a.valid) node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_581 = and(_T_579, _T_580) node _T_582 = eq(d_release_ack, UInt<1>(0h0)) node _T_583 = and(_T_581, _T_582) when _T_583 : node _T_584 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_585 = or(_T_584, io.in.a.ready) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_585, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_206 node _T_589 = orr(inflight) node _T_590 = eq(_T_589, UInt<1>(0h0)) node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_592 = or(_T_590, _T_591) node _T_593 = lt(watchdog, plusarg_reader.out) node _T_594 = or(_T_592, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_594, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_598 = and(io.in.a.ready, io.in.a.valid) node _T_599 = and(io.in.d.ready, io.in.d.valid) node _T_600 = or(_T_598, _T_599) when _T_600 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_601 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_604 = and(_T_602, _T_603) node _T_605 = and(_T_601, _T_604) when _T_605 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_607 = and(_T_606, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_610 = and(_T_608, _T_609) node _T_611 = and(_T_607, _T_610) when _T_611 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_612 = dshr(inflight_1, _WIRE_15.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = eq(_T_613, UInt<1>(0h0)) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_614, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_618 = and(io.in.d.valid, d_first_2) node _T_619 = and(_T_618, UInt<1>(0h1)) node _T_620 = and(_T_619, d_release_ack_1) when _T_620 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_621 = and(io.in.d.ready, io.in.d.valid) node _T_622 = and(_T_621, d_first_2) node _T_623 = and(_T_622, UInt<1>(0h1)) node _T_624 = and(_T_623, d_release_ack_1) when _T_624 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_625 = and(io.in.d.valid, d_first_2) node _T_626 = and(_T_625, UInt<1>(0h1)) node _T_627 = and(_T_626, d_release_ack_1) when _T_627 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_628 = dshr(inflight_1, io.in.d.bits.source) node _T_629 = bits(_T_628, 0, 0) node _T_630 = or(_T_629, same_cycle_resp_1) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_630, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_634, UInt<1>(0h1), "") : assert_108 else : node _T_638 = eq(io.in.d.bits.size, c_size_lookup) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_638, UInt<1>(0h1), "") : assert_109 node _T_642 = and(io.in.d.valid, d_first_2) node _T_643 = and(_T_642, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_644 = and(_T_643, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_646 = and(_T_644, _T_645) node _T_647 = and(_T_646, d_release_ack_1) node _T_648 = eq(c_probe_ack, UInt<1>(0h0)) node _T_649 = and(_T_647, _T_648) when _T_649 : node _T_650 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_651 = or(_T_650, _WIRE_23.ready) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_651, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_207 node _T_655 = orr(inflight_1) node _T_656 = eq(_T_655, UInt<1>(0h0)) node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_658 = or(_T_656, _T_657) node _T_659 = lt(watchdog_1, plusarg_reader_1.out) node _T_660 = or(_T_658, _T_659) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_660, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_665 = and(io.in.d.ready, io.in.d.valid) node _T_666 = or(_T_664, _T_665) when _T_666 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_86( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_21 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<3>(0h6)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_39 = shr(io.in.a.bits.source, 3) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<3>(0h4)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<3>(0h4)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[18] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_36 connect _source_ok_WIRE[12], _source_ok_T_37 connect _source_ok_WIRE[13], _source_ok_T_38 connect _source_ok_WIRE[14], _source_ok_T_44 connect _source_ok_WIRE[15], _source_ok_T_45 connect _source_ok_WIRE[16], _source_ok_T_46 connect _source_ok_WIRE[17], _source_ok_T_47 node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[7]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[8]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[9]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[10]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[11]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[12]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[13]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[14]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[15]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[16]) node source_ok = or(_source_ok_T_63, _source_ok_WIRE[17]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_112 = shr(io.in.a.bits.source, 3) node _T_113 = eq(_T_112, UInt<3>(0h6)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_120 = cvt(_T_119) node _T_121 = and(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = asSInt(_T_121) node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = or(_T_118, _T_123) node _T_125 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_126 = eq(_T_125, UInt<1>(0h0)) node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = or(_T_126, _T_131) node _T_133 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<1>(0h0))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = or(_T_134, _T_139) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_141 = shr(io.in.a.bits.source, 3) node _T_142 = eq(_T_141, UInt<3>(0h4)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_5) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(_T_146, UInt<1>(0h0)) node _T_148 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_149 = cvt(_T_148) node _T_150 = and(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = asSInt(_T_150) node _T_152 = eq(_T_151, asSInt(UInt<1>(0h0))) node _T_153 = or(_T_147, _T_152) node _T_154 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = or(_T_155, _T_160) node _T_162 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_163 = eq(_T_162, UInt<1>(0h0)) node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = or(_T_163, _T_168) node _T_170 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_171 = eq(_T_170, UInt<1>(0h0)) node _T_172 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = or(_T_171, _T_176) node _T_178 = and(_T_11, _T_24) node _T_179 = and(_T_178, _T_37) node _T_180 = and(_T_179, _T_50) node _T_181 = and(_T_180, _T_63) node _T_182 = and(_T_181, _T_71) node _T_183 = and(_T_182, _T_79) node _T_184 = and(_T_183, _T_87) node _T_185 = and(_T_184, _T_95) node _T_186 = and(_T_185, _T_103) node _T_187 = and(_T_186, _T_111) node _T_188 = and(_T_187, _T_124) node _T_189 = and(_T_188, _T_132) node _T_190 = and(_T_189, _T_140) node _T_191 = and(_T_190, _T_153) node _T_192 = and(_T_191, _T_161) node _T_193 = and(_T_192, _T_169) node _T_194 = and(_T_193, _T_177) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_194, UInt<1>(0h1), "") : assert_1 node _T_198 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_198 : node _T_199 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_200 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_201 = and(_T_199, _T_200) node _T_202 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_203 = shr(io.in.a.bits.source, 2) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = leq(UInt<1>(0h0), uncommonBits_6) node _T_206 = and(_T_204, _T_205) node _T_207 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_208 = and(_T_206, _T_207) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_209 = shr(io.in.a.bits.source, 2) node _T_210 = eq(_T_209, UInt<1>(0h1)) node _T_211 = leq(UInt<1>(0h0), uncommonBits_7) node _T_212 = and(_T_210, _T_211) node _T_213 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_214 = and(_T_212, _T_213) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_215 = shr(io.in.a.bits.source, 2) node _T_216 = eq(_T_215, UInt<2>(0h2)) node _T_217 = leq(UInt<1>(0h0), uncommonBits_8) node _T_218 = and(_T_216, _T_217) node _T_219 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_220 = and(_T_218, _T_219) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_221 = shr(io.in.a.bits.source, 2) node _T_222 = eq(_T_221, UInt<2>(0h3)) node _T_223 = leq(UInt<1>(0h0), uncommonBits_9) node _T_224 = and(_T_222, _T_223) node _T_225 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_226 = and(_T_224, _T_225) node _T_227 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_228 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_229 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_230 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_231 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_233 = shr(io.in.a.bits.source, 3) node _T_234 = eq(_T_233, UInt<3>(0h6)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_10) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_241 = shr(io.in.a.bits.source, 3) node _T_242 = eq(_T_241, UInt<3>(0h4)) node _T_243 = leq(UInt<1>(0h0), uncommonBits_11) node _T_244 = and(_T_242, _T_243) node _T_245 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_250 = or(_T_202, _T_208) node _T_251 = or(_T_250, _T_214) node _T_252 = or(_T_251, _T_220) node _T_253 = or(_T_252, _T_226) node _T_254 = or(_T_253, _T_227) node _T_255 = or(_T_254, _T_228) node _T_256 = or(_T_255, _T_229) node _T_257 = or(_T_256, _T_230) node _T_258 = or(_T_257, _T_231) node _T_259 = or(_T_258, _T_232) node _T_260 = or(_T_259, _T_238) node _T_261 = or(_T_260, _T_239) node _T_262 = or(_T_261, _T_240) node _T_263 = or(_T_262, _T_246) node _T_264 = or(_T_263, _T_247) node _T_265 = or(_T_264, _T_248) node _T_266 = or(_T_265, _T_249) node _T_267 = and(_T_201, _T_266) node _T_268 = or(UInt<1>(0h0), _T_267) node _T_269 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_270 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_271 = cvt(_T_270) node _T_272 = and(_T_271, asSInt(UInt<14>(0h2000))) node _T_273 = asSInt(_T_272) node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0))) node _T_275 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_276 = cvt(_T_275) node _T_277 = and(_T_276, asSInt(UInt<13>(0h1000))) node _T_278 = asSInt(_T_277) node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0))) node _T_280 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_281 = cvt(_T_280) node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000))) node _T_283 = asSInt(_T_282) node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_286 = cvt(_T_285) node _T_287 = and(_T_286, asSInt(UInt<18>(0h2f000))) node _T_288 = asSInt(_T_287) node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) node _T_290 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<17>(0h10000))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_296 = cvt(_T_295) node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000))) node _T_298 = asSInt(_T_297) node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0))) node _T_300 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<27>(0h4000000))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_306 = cvt(_T_305) node _T_307 = and(_T_306, asSInt(UInt<13>(0h1000))) node _T_308 = asSInt(_T_307) node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0))) node _T_310 = or(_T_274, _T_279) node _T_311 = or(_T_310, _T_284) node _T_312 = or(_T_311, _T_289) node _T_313 = or(_T_312, _T_294) node _T_314 = or(_T_313, _T_299) node _T_315 = or(_T_314, _T_304) node _T_316 = or(_T_315, _T_309) node _T_317 = and(_T_269, _T_316) node _T_318 = or(UInt<1>(0h0), _T_317) node _T_319 = and(_T_268, _T_318) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_319, UInt<1>(0h1), "") : assert_2 node _T_323 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_324 = shr(io.in.a.bits.source, 2) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = leq(UInt<1>(0h0), uncommonBits_12) node _T_327 = and(_T_325, _T_326) node _T_328 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_329 = and(_T_327, _T_328) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_330 = shr(io.in.a.bits.source, 2) node _T_331 = eq(_T_330, UInt<1>(0h1)) node _T_332 = leq(UInt<1>(0h0), uncommonBits_13) node _T_333 = and(_T_331, _T_332) node _T_334 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_335 = and(_T_333, _T_334) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_336 = shr(io.in.a.bits.source, 2) node _T_337 = eq(_T_336, UInt<2>(0h2)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_14) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_342 = shr(io.in.a.bits.source, 2) node _T_343 = eq(_T_342, UInt<2>(0h3)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_15) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_350 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_351 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_352 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_353 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_354 = shr(io.in.a.bits.source, 3) node _T_355 = eq(_T_354, UInt<3>(0h6)) node _T_356 = leq(UInt<1>(0h0), uncommonBits_16) node _T_357 = and(_T_355, _T_356) node _T_358 = leq(uncommonBits_16, UInt<3>(0h4)) node _T_359 = and(_T_357, _T_358) node _T_360 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_361 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_362 = shr(io.in.a.bits.source, 3) node _T_363 = eq(_T_362, UInt<3>(0h4)) node _T_364 = leq(UInt<1>(0h0), uncommonBits_17) node _T_365 = and(_T_363, _T_364) node _T_366 = leq(uncommonBits_17, UInt<3>(0h4)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_369 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_370 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[18] connect _WIRE[0], _T_323 connect _WIRE[1], _T_329 connect _WIRE[2], _T_335 connect _WIRE[3], _T_341 connect _WIRE[4], _T_347 connect _WIRE[5], _T_348 connect _WIRE[6], _T_349 connect _WIRE[7], _T_350 connect _WIRE[8], _T_351 connect _WIRE[9], _T_352 connect _WIRE[10], _T_353 connect _WIRE[11], _T_359 connect _WIRE[12], _T_360 connect _WIRE[13], _T_361 connect _WIRE[14], _T_367 connect _WIRE[15], _T_368 connect _WIRE[16], _T_369 connect _WIRE[17], _T_370 node _T_371 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_372 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_373 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_374 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_375 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_376 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_377 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_380 = mux(_WIRE[5], _T_371, UInt<1>(0h0)) node _T_381 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_383 = mux(_WIRE[8], _T_372, UInt<1>(0h0)) node _T_384 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_385 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = mux(_WIRE[11], _T_373, UInt<1>(0h0)) node _T_387 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_388 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_389 = mux(_WIRE[14], _T_374, UInt<1>(0h0)) node _T_390 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_391 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_392 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_393 = or(_T_375, _T_376) node _T_394 = or(_T_393, _T_377) node _T_395 = or(_T_394, _T_378) node _T_396 = or(_T_395, _T_379) node _T_397 = or(_T_396, _T_380) node _T_398 = or(_T_397, _T_381) node _T_399 = or(_T_398, _T_382) node _T_400 = or(_T_399, _T_383) node _T_401 = or(_T_400, _T_384) node _T_402 = or(_T_401, _T_385) node _T_403 = or(_T_402, _T_386) node _T_404 = or(_T_403, _T_387) node _T_405 = or(_T_404, _T_388) node _T_406 = or(_T_405, _T_389) node _T_407 = or(_T_406, _T_390) node _T_408 = or(_T_407, _T_391) node _T_409 = or(_T_408, _T_392) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_409 node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_412 = and(_T_410, _T_411) node _T_413 = or(UInt<1>(0h0), _T_412) node _T_414 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<14>(0h2000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<18>(0h2f000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<17>(0h10000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<13>(0h1000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<27>(0h4000000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_450 = cvt(_T_449) node _T_451 = and(_T_450, asSInt(UInt<13>(0h1000))) node _T_452 = asSInt(_T_451) node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) node _T_454 = or(_T_418, _T_423) node _T_455 = or(_T_454, _T_428) node _T_456 = or(_T_455, _T_433) node _T_457 = or(_T_456, _T_438) node _T_458 = or(_T_457, _T_443) node _T_459 = or(_T_458, _T_448) node _T_460 = or(_T_459, _T_453) node _T_461 = and(_T_413, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = and(_WIRE_1, _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_463, UInt<1>(0h1), "") : assert_3 node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(source_ok, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_470 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(_T_470, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_470, UInt<1>(0h1), "") : assert_5 node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(is_aligned, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_477 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_477, UInt<1>(0h1), "") : assert_7 node _T_481 = not(io.in.a.bits.mask) node _T_482 = eq(_T_481, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_482, UInt<1>(0h1), "") : assert_8 node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_486, UInt<1>(0h1), "") : assert_9 node _T_490 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_490 : node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_493 = and(_T_491, _T_492) node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_495 = shr(io.in.a.bits.source, 2) node _T_496 = eq(_T_495, UInt<1>(0h0)) node _T_497 = leq(UInt<1>(0h0), uncommonBits_18) node _T_498 = and(_T_496, _T_497) node _T_499 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_500 = and(_T_498, _T_499) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_501 = shr(io.in.a.bits.source, 2) node _T_502 = eq(_T_501, UInt<1>(0h1)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_19) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<2>(0h2)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_20) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<2>(0h3)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_21) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_520 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_521 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_524 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 2, 0) node _T_525 = shr(io.in.a.bits.source, 3) node _T_526 = eq(_T_525, UInt<3>(0h6)) node _T_527 = leq(UInt<1>(0h0), uncommonBits_22) node _T_528 = and(_T_526, _T_527) node _T_529 = leq(uncommonBits_22, UInt<3>(0h4)) node _T_530 = and(_T_528, _T_529) node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 2, 0) node _T_533 = shr(io.in.a.bits.source, 3) node _T_534 = eq(_T_533, UInt<3>(0h4)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_23) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_23, UInt<3>(0h4)) node _T_538 = and(_T_536, _T_537) node _T_539 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_540 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_541 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_542 = or(_T_494, _T_500) node _T_543 = or(_T_542, _T_506) node _T_544 = or(_T_543, _T_512) node _T_545 = or(_T_544, _T_518) node _T_546 = or(_T_545, _T_519) node _T_547 = or(_T_546, _T_520) node _T_548 = or(_T_547, _T_521) node _T_549 = or(_T_548, _T_522) node _T_550 = or(_T_549, _T_523) node _T_551 = or(_T_550, _T_524) node _T_552 = or(_T_551, _T_530) node _T_553 = or(_T_552, _T_531) node _T_554 = or(_T_553, _T_532) node _T_555 = or(_T_554, _T_538) node _T_556 = or(_T_555, _T_539) node _T_557 = or(_T_556, _T_540) node _T_558 = or(_T_557, _T_541) node _T_559 = and(_T_493, _T_558) node _T_560 = or(UInt<1>(0h0), _T_559) node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_562 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<14>(0h2000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_568 = cvt(_T_567) node _T_569 = and(_T_568, asSInt(UInt<13>(0h1000))) node _T_570 = asSInt(_T_569) node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0))) node _T_572 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<17>(0h10000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_578 = cvt(_T_577) node _T_579 = and(_T_578, asSInt(UInt<18>(0h2f000))) node _T_580 = asSInt(_T_579) node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0))) node _T_582 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_583 = cvt(_T_582) node _T_584 = and(_T_583, asSInt(UInt<17>(0h10000))) node _T_585 = asSInt(_T_584) node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0))) node _T_587 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_588 = cvt(_T_587) node _T_589 = and(_T_588, asSInt(UInt<13>(0h1000))) node _T_590 = asSInt(_T_589) node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0))) node _T_592 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_593 = cvt(_T_592) node _T_594 = and(_T_593, asSInt(UInt<27>(0h4000000))) node _T_595 = asSInt(_T_594) node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0))) node _T_597 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_598 = cvt(_T_597) node _T_599 = and(_T_598, asSInt(UInt<13>(0h1000))) node _T_600 = asSInt(_T_599) node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0))) node _T_602 = or(_T_566, _T_571) node _T_603 = or(_T_602, _T_576) node _T_604 = or(_T_603, _T_581) node _T_605 = or(_T_604, _T_586) node _T_606 = or(_T_605, _T_591) node _T_607 = or(_T_606, _T_596) node _T_608 = or(_T_607, _T_601) node _T_609 = and(_T_561, _T_608) node _T_610 = or(UInt<1>(0h0), _T_609) node _T_611 = and(_T_560, _T_610) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_611, UInt<1>(0h1), "") : assert_10 node _T_615 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_616 = shr(io.in.a.bits.source, 2) node _T_617 = eq(_T_616, UInt<1>(0h0)) node _T_618 = leq(UInt<1>(0h0), uncommonBits_24) node _T_619 = and(_T_617, _T_618) node _T_620 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_621 = and(_T_619, _T_620) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_622 = shr(io.in.a.bits.source, 2) node _T_623 = eq(_T_622, UInt<1>(0h1)) node _T_624 = leq(UInt<1>(0h0), uncommonBits_25) node _T_625 = and(_T_623, _T_624) node _T_626 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_627 = and(_T_625, _T_626) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_628 = shr(io.in.a.bits.source, 2) node _T_629 = eq(_T_628, UInt<2>(0h2)) node _T_630 = leq(UInt<1>(0h0), uncommonBits_26) node _T_631 = and(_T_629, _T_630) node _T_632 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_633 = and(_T_631, _T_632) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_634 = shr(io.in.a.bits.source, 2) node _T_635 = eq(_T_634, UInt<2>(0h3)) node _T_636 = leq(UInt<1>(0h0), uncommonBits_27) node _T_637 = and(_T_635, _T_636) node _T_638 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_639 = and(_T_637, _T_638) node _T_640 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_641 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_642 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_643 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_644 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_645 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 2, 0) node _T_646 = shr(io.in.a.bits.source, 3) node _T_647 = eq(_T_646, UInt<3>(0h6)) node _T_648 = leq(UInt<1>(0h0), uncommonBits_28) node _T_649 = and(_T_647, _T_648) node _T_650 = leq(uncommonBits_28, UInt<3>(0h4)) node _T_651 = and(_T_649, _T_650) node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_653 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_654 = shr(io.in.a.bits.source, 3) node _T_655 = eq(_T_654, UInt<3>(0h4)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_29) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_659 = and(_T_657, _T_658) node _T_660 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_661 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_662 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[18] connect _WIRE_2[0], _T_615 connect _WIRE_2[1], _T_621 connect _WIRE_2[2], _T_627 connect _WIRE_2[3], _T_633 connect _WIRE_2[4], _T_639 connect _WIRE_2[5], _T_640 connect _WIRE_2[6], _T_641 connect _WIRE_2[7], _T_642 connect _WIRE_2[8], _T_643 connect _WIRE_2[9], _T_644 connect _WIRE_2[10], _T_645 connect _WIRE_2[11], _T_651 connect _WIRE_2[12], _T_652 connect _WIRE_2[13], _T_653 connect _WIRE_2[14], _T_659 connect _WIRE_2[15], _T_660 connect _WIRE_2[16], _T_661 connect _WIRE_2[17], _T_662 node _T_663 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_664 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_665 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_666 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_667 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_668 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_669 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_670 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_671 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_672 = mux(_WIRE_2[5], _T_663, UInt<1>(0h0)) node _T_673 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_674 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = mux(_WIRE_2[8], _T_664, UInt<1>(0h0)) node _T_676 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_678 = mux(_WIRE_2[11], _T_665, UInt<1>(0h0)) node _T_679 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_680 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_681 = mux(_WIRE_2[14], _T_666, UInt<1>(0h0)) node _T_682 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_683 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_684 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_685 = or(_T_667, _T_668) node _T_686 = or(_T_685, _T_669) node _T_687 = or(_T_686, _T_670) node _T_688 = or(_T_687, _T_671) node _T_689 = or(_T_688, _T_672) node _T_690 = or(_T_689, _T_673) node _T_691 = or(_T_690, _T_674) node _T_692 = or(_T_691, _T_675) node _T_693 = or(_T_692, _T_676) node _T_694 = or(_T_693, _T_677) node _T_695 = or(_T_694, _T_678) node _T_696 = or(_T_695, _T_679) node _T_697 = or(_T_696, _T_680) node _T_698 = or(_T_697, _T_681) node _T_699 = or(_T_698, _T_682) node _T_700 = or(_T_699, _T_683) node _T_701 = or(_T_700, _T_684) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_701 node _T_702 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_703 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_704 = and(_T_702, _T_703) node _T_705 = or(UInt<1>(0h0), _T_704) node _T_706 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<14>(0h2000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<13>(0h1000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<18>(0h2f000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<27>(0h4000000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = or(_T_710, _T_715) node _T_747 = or(_T_746, _T_720) node _T_748 = or(_T_747, _T_725) node _T_749 = or(_T_748, _T_730) node _T_750 = or(_T_749, _T_735) node _T_751 = or(_T_750, _T_740) node _T_752 = or(_T_751, _T_745) node _T_753 = and(_T_705, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = and(_WIRE_3, _T_754) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_755, UInt<1>(0h1), "") : assert_11 node _T_759 = asUInt(reset) node _T_760 = eq(_T_759, UInt<1>(0h0)) when _T_760 : node _T_761 = eq(source_ok, UInt<1>(0h0)) when _T_761 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_762 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_762, UInt<1>(0h1), "") : assert_13 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(is_aligned, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_769 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_769, UInt<1>(0h1), "") : assert_15 node _T_773 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_773, UInt<1>(0h1), "") : assert_16 node _T_777 = not(io.in.a.bits.mask) node _T_778 = eq(_T_777, UInt<1>(0h0)) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_778, UInt<1>(0h1), "") : assert_17 node _T_782 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_782, UInt<1>(0h1), "") : assert_18 node _T_786 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_786 : node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_789 = and(_T_787, _T_788) node _T_790 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_791 = shr(io.in.a.bits.source, 2) node _T_792 = eq(_T_791, UInt<1>(0h0)) node _T_793 = leq(UInt<1>(0h0), uncommonBits_30) node _T_794 = and(_T_792, _T_793) node _T_795 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_796 = and(_T_794, _T_795) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_797 = shr(io.in.a.bits.source, 2) node _T_798 = eq(_T_797, UInt<1>(0h1)) node _T_799 = leq(UInt<1>(0h0), uncommonBits_31) node _T_800 = and(_T_798, _T_799) node _T_801 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_802 = and(_T_800, _T_801) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_803 = shr(io.in.a.bits.source, 2) node _T_804 = eq(_T_803, UInt<2>(0h2)) node _T_805 = leq(UInt<1>(0h0), uncommonBits_32) node _T_806 = and(_T_804, _T_805) node _T_807 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_808 = and(_T_806, _T_807) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<2>(0h3)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_33) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _T_815 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_816 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_817 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_818 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_819 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_820 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_821 = shr(io.in.a.bits.source, 3) node _T_822 = eq(_T_821, UInt<3>(0h6)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_34) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_826 = and(_T_824, _T_825) node _T_827 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_828 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 2, 0) node _T_829 = shr(io.in.a.bits.source, 3) node _T_830 = eq(_T_829, UInt<3>(0h4)) node _T_831 = leq(UInt<1>(0h0), uncommonBits_35) node _T_832 = and(_T_830, _T_831) node _T_833 = leq(uncommonBits_35, UInt<3>(0h4)) node _T_834 = and(_T_832, _T_833) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_837 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_838 = or(_T_790, _T_796) node _T_839 = or(_T_838, _T_802) node _T_840 = or(_T_839, _T_808) node _T_841 = or(_T_840, _T_814) node _T_842 = or(_T_841, _T_815) node _T_843 = or(_T_842, _T_816) node _T_844 = or(_T_843, _T_817) node _T_845 = or(_T_844, _T_818) node _T_846 = or(_T_845, _T_819) node _T_847 = or(_T_846, _T_820) node _T_848 = or(_T_847, _T_826) node _T_849 = or(_T_848, _T_827) node _T_850 = or(_T_849, _T_828) node _T_851 = or(_T_850, _T_834) node _T_852 = or(_T_851, _T_835) node _T_853 = or(_T_852, _T_836) node _T_854 = or(_T_853, _T_837) node _T_855 = and(_T_789, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(_T_856, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_856, UInt<1>(0h1), "") : assert_19 node _T_860 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_861 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_862 = and(_T_860, _T_861) node _T_863 = or(UInt<1>(0h0), _T_862) node _T_864 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<13>(0h1000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = and(_T_863, _T_868) node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_872 = and(_T_870, _T_871) node _T_873 = or(UInt<1>(0h0), _T_872) node _T_874 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<14>(0h2000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<18>(0h2f000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<17>(0h10000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = or(_T_878, _T_883) node _T_910 = or(_T_909, _T_888) node _T_911 = or(_T_910, _T_893) node _T_912 = or(_T_911, _T_898) node _T_913 = or(_T_912, _T_903) node _T_914 = or(_T_913, _T_908) node _T_915 = and(_T_873, _T_914) node _T_916 = or(UInt<1>(0h0), _T_869) node _T_917 = or(_T_916, _T_915) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_917, UInt<1>(0h1), "") : assert_20 node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(source_ok, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(is_aligned, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_927 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(_T_927, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_927, UInt<1>(0h1), "") : assert_23 node _T_931 = eq(io.in.a.bits.mask, mask) node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(_T_931, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_931, UInt<1>(0h1), "") : assert_24 node _T_935 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_935, UInt<1>(0h1), "") : assert_25 node _T_939 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_939 : node _T_940 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_941 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_942 = and(_T_940, _T_941) node _T_943 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_944 = shr(io.in.a.bits.source, 2) node _T_945 = eq(_T_944, UInt<1>(0h0)) node _T_946 = leq(UInt<1>(0h0), uncommonBits_36) node _T_947 = and(_T_945, _T_946) node _T_948 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_949 = and(_T_947, _T_948) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_950 = shr(io.in.a.bits.source, 2) node _T_951 = eq(_T_950, UInt<1>(0h1)) node _T_952 = leq(UInt<1>(0h0), uncommonBits_37) node _T_953 = and(_T_951, _T_952) node _T_954 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_955 = and(_T_953, _T_954) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_956 = shr(io.in.a.bits.source, 2) node _T_957 = eq(_T_956, UInt<2>(0h2)) node _T_958 = leq(UInt<1>(0h0), uncommonBits_38) node _T_959 = and(_T_957, _T_958) node _T_960 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_961 = and(_T_959, _T_960) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_962 = shr(io.in.a.bits.source, 2) node _T_963 = eq(_T_962, UInt<2>(0h3)) node _T_964 = leq(UInt<1>(0h0), uncommonBits_39) node _T_965 = and(_T_963, _T_964) node _T_966 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_967 = and(_T_965, _T_966) node _T_968 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_969 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_970 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_971 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_972 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_973 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_974 = shr(io.in.a.bits.source, 3) node _T_975 = eq(_T_974, UInt<3>(0h6)) node _T_976 = leq(UInt<1>(0h0), uncommonBits_40) node _T_977 = and(_T_975, _T_976) node _T_978 = leq(uncommonBits_40, UInt<3>(0h4)) node _T_979 = and(_T_977, _T_978) node _T_980 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_981 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_982 = shr(io.in.a.bits.source, 3) node _T_983 = eq(_T_982, UInt<3>(0h4)) node _T_984 = leq(UInt<1>(0h0), uncommonBits_41) node _T_985 = and(_T_983, _T_984) node _T_986 = leq(uncommonBits_41, UInt<3>(0h4)) node _T_987 = and(_T_985, _T_986) node _T_988 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_989 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_990 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_991 = or(_T_943, _T_949) node _T_992 = or(_T_991, _T_955) node _T_993 = or(_T_992, _T_961) node _T_994 = or(_T_993, _T_967) node _T_995 = or(_T_994, _T_968) node _T_996 = or(_T_995, _T_969) node _T_997 = or(_T_996, _T_970) node _T_998 = or(_T_997, _T_971) node _T_999 = or(_T_998, _T_972) node _T_1000 = or(_T_999, _T_973) node _T_1001 = or(_T_1000, _T_979) node _T_1002 = or(_T_1001, _T_980) node _T_1003 = or(_T_1002, _T_981) node _T_1004 = or(_T_1003, _T_987) node _T_1005 = or(_T_1004, _T_988) node _T_1006 = or(_T_1005, _T_989) node _T_1007 = or(_T_1006, _T_990) node _T_1008 = and(_T_942, _T_1007) node _T_1009 = or(UInt<1>(0h0), _T_1008) node _T_1010 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1011 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1012 = and(_T_1010, _T_1011) node _T_1013 = or(UInt<1>(0h0), _T_1012) node _T_1014 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<13>(0h1000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = and(_T_1013, _T_1018) node _T_1020 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1021 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1022 = and(_T_1020, _T_1021) node _T_1023 = or(UInt<1>(0h0), _T_1022) node _T_1024 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<14>(0h2000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1030 = cvt(_T_1029) node _T_1031 = and(_T_1030, asSInt(UInt<18>(0h2f000))) node _T_1032 = asSInt(_T_1031) node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0))) node _T_1034 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1035 = cvt(_T_1034) node _T_1036 = and(_T_1035, asSInt(UInt<17>(0h10000))) node _T_1037 = asSInt(_T_1036) node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0))) node _T_1039 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1040 = cvt(_T_1039) node _T_1041 = and(_T_1040, asSInt(UInt<13>(0h1000))) node _T_1042 = asSInt(_T_1041) node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) node _T_1044 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1045 = cvt(_T_1044) node _T_1046 = and(_T_1045, asSInt(UInt<27>(0h4000000))) node _T_1047 = asSInt(_T_1046) node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) node _T_1049 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1050 = cvt(_T_1049) node _T_1051 = and(_T_1050, asSInt(UInt<13>(0h1000))) node _T_1052 = asSInt(_T_1051) node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = or(_T_1028, _T_1033) node _T_1055 = or(_T_1054, _T_1038) node _T_1056 = or(_T_1055, _T_1043) node _T_1057 = or(_T_1056, _T_1048) node _T_1058 = or(_T_1057, _T_1053) node _T_1059 = and(_T_1023, _T_1058) node _T_1060 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1061 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1062 = cvt(_T_1061) node _T_1063 = and(_T_1062, asSInt(UInt<17>(0h10000))) node _T_1064 = asSInt(_T_1063) node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0))) node _T_1066 = and(_T_1060, _T_1065) node _T_1067 = or(UInt<1>(0h0), _T_1019) node _T_1068 = or(_T_1067, _T_1059) node _T_1069 = or(_T_1068, _T_1066) node _T_1070 = and(_T_1009, _T_1069) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_26 node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(source_ok, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(is_aligned, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1080 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_29 node _T_1084 = eq(io.in.a.bits.mask, mask) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_30 node _T_1088 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1088 : node _T_1089 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1090 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1091 = and(_T_1089, _T_1090) node _T_1092 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1093 = shr(io.in.a.bits.source, 2) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) node _T_1095 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1098 = and(_T_1096, _T_1097) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1099 = shr(io.in.a.bits.source, 2) node _T_1100 = eq(_T_1099, UInt<1>(0h1)) node _T_1101 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1104 = and(_T_1102, _T_1103) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1105 = shr(io.in.a.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h2)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1111 = shr(io.in.a.bits.source, 2) node _T_1112 = eq(_T_1111, UInt<2>(0h3)) node _T_1113 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1114 = and(_T_1112, _T_1113) node _T_1115 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1116 = and(_T_1114, _T_1115) node _T_1117 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1118 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1119 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1120 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1121 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1122 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_1123 = shr(io.in.a.bits.source, 3) node _T_1124 = eq(_T_1123, UInt<3>(0h6)) node _T_1125 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1126 = and(_T_1124, _T_1125) node _T_1127 = leq(uncommonBits_46, UInt<3>(0h4)) node _T_1128 = and(_T_1126, _T_1127) node _T_1129 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1130 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_1131 = shr(io.in.a.bits.source, 3) node _T_1132 = eq(_T_1131, UInt<3>(0h4)) node _T_1133 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1134 = and(_T_1132, _T_1133) node _T_1135 = leq(uncommonBits_47, UInt<3>(0h4)) node _T_1136 = and(_T_1134, _T_1135) node _T_1137 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1138 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1139 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1140 = or(_T_1092, _T_1098) node _T_1141 = or(_T_1140, _T_1104) node _T_1142 = or(_T_1141, _T_1110) node _T_1143 = or(_T_1142, _T_1116) node _T_1144 = or(_T_1143, _T_1117) node _T_1145 = or(_T_1144, _T_1118) node _T_1146 = or(_T_1145, _T_1119) node _T_1147 = or(_T_1146, _T_1120) node _T_1148 = or(_T_1147, _T_1121) node _T_1149 = or(_T_1148, _T_1122) node _T_1150 = or(_T_1149, _T_1128) node _T_1151 = or(_T_1150, _T_1129) node _T_1152 = or(_T_1151, _T_1130) node _T_1153 = or(_T_1152, _T_1136) node _T_1154 = or(_T_1153, _T_1137) node _T_1155 = or(_T_1154, _T_1138) node _T_1156 = or(_T_1155, _T_1139) node _T_1157 = and(_T_1091, _T_1156) node _T_1158 = or(UInt<1>(0h0), _T_1157) node _T_1159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1160 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1161 = and(_T_1159, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1164 = cvt(_T_1163) node _T_1165 = and(_T_1164, asSInt(UInt<13>(0h1000))) node _T_1166 = asSInt(_T_1165) node _T_1167 = eq(_T_1166, asSInt(UInt<1>(0h0))) node _T_1168 = and(_T_1162, _T_1167) node _T_1169 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1170 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1171 = and(_T_1169, _T_1170) node _T_1172 = or(UInt<1>(0h0), _T_1171) node _T_1173 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1174 = cvt(_T_1173) node _T_1175 = and(_T_1174, asSInt(UInt<14>(0h2000))) node _T_1176 = asSInt(_T_1175) node _T_1177 = eq(_T_1176, asSInt(UInt<1>(0h0))) node _T_1178 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1179 = cvt(_T_1178) node _T_1180 = and(_T_1179, asSInt(UInt<18>(0h2f000))) node _T_1181 = asSInt(_T_1180) node _T_1182 = eq(_T_1181, asSInt(UInt<1>(0h0))) node _T_1183 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1184 = cvt(_T_1183) node _T_1185 = and(_T_1184, asSInt(UInt<17>(0h10000))) node _T_1186 = asSInt(_T_1185) node _T_1187 = eq(_T_1186, asSInt(UInt<1>(0h0))) node _T_1188 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1189 = cvt(_T_1188) node _T_1190 = and(_T_1189, asSInt(UInt<13>(0h1000))) node _T_1191 = asSInt(_T_1190) node _T_1192 = eq(_T_1191, asSInt(UInt<1>(0h0))) node _T_1193 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1194 = cvt(_T_1193) node _T_1195 = and(_T_1194, asSInt(UInt<27>(0h4000000))) node _T_1196 = asSInt(_T_1195) node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0))) node _T_1198 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1199 = cvt(_T_1198) node _T_1200 = and(_T_1199, asSInt(UInt<13>(0h1000))) node _T_1201 = asSInt(_T_1200) node _T_1202 = eq(_T_1201, asSInt(UInt<1>(0h0))) node _T_1203 = or(_T_1177, _T_1182) node _T_1204 = or(_T_1203, _T_1187) node _T_1205 = or(_T_1204, _T_1192) node _T_1206 = or(_T_1205, _T_1197) node _T_1207 = or(_T_1206, _T_1202) node _T_1208 = and(_T_1172, _T_1207) node _T_1209 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1210 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<17>(0h10000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = and(_T_1209, _T_1214) node _T_1216 = or(UInt<1>(0h0), _T_1168) node _T_1217 = or(_T_1216, _T_1208) node _T_1218 = or(_T_1217, _T_1215) node _T_1219 = and(_T_1158, _T_1218) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_31 node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(source_ok, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(is_aligned, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1229 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_34 node _T_1233 = not(mask) node _T_1234 = and(io.in.a.bits.mask, _T_1233) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_35 node _T_1239 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1239 : node _T_1240 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1241 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1242 = and(_T_1240, _T_1241) node _T_1243 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1244 = shr(io.in.a.bits.source, 2) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) node _T_1246 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1247 = and(_T_1245, _T_1246) node _T_1248 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1249 = and(_T_1247, _T_1248) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1250 = shr(io.in.a.bits.source, 2) node _T_1251 = eq(_T_1250, UInt<1>(0h1)) node _T_1252 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1253 = and(_T_1251, _T_1252) node _T_1254 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1255 = and(_T_1253, _T_1254) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1256 = shr(io.in.a.bits.source, 2) node _T_1257 = eq(_T_1256, UInt<2>(0h2)) node _T_1258 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1259 = and(_T_1257, _T_1258) node _T_1260 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1261 = and(_T_1259, _T_1260) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1262 = shr(io.in.a.bits.source, 2) node _T_1263 = eq(_T_1262, UInt<2>(0h3)) node _T_1264 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1265 = and(_T_1263, _T_1264) node _T_1266 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1267 = and(_T_1265, _T_1266) node _T_1268 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1269 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1270 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1271 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1272 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1273 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 2, 0) node _T_1274 = shr(io.in.a.bits.source, 3) node _T_1275 = eq(_T_1274, UInt<3>(0h6)) node _T_1276 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1277 = and(_T_1275, _T_1276) node _T_1278 = leq(uncommonBits_52, UInt<3>(0h4)) node _T_1279 = and(_T_1277, _T_1278) node _T_1280 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1281 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_1282 = shr(io.in.a.bits.source, 3) node _T_1283 = eq(_T_1282, UInt<3>(0h4)) node _T_1284 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1285 = and(_T_1283, _T_1284) node _T_1286 = leq(uncommonBits_53, UInt<3>(0h4)) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1289 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1290 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1291 = or(_T_1243, _T_1249) node _T_1292 = or(_T_1291, _T_1255) node _T_1293 = or(_T_1292, _T_1261) node _T_1294 = or(_T_1293, _T_1267) node _T_1295 = or(_T_1294, _T_1268) node _T_1296 = or(_T_1295, _T_1269) node _T_1297 = or(_T_1296, _T_1270) node _T_1298 = or(_T_1297, _T_1271) node _T_1299 = or(_T_1298, _T_1272) node _T_1300 = or(_T_1299, _T_1273) node _T_1301 = or(_T_1300, _T_1279) node _T_1302 = or(_T_1301, _T_1280) node _T_1303 = or(_T_1302, _T_1281) node _T_1304 = or(_T_1303, _T_1287) node _T_1305 = or(_T_1304, _T_1288) node _T_1306 = or(_T_1305, _T_1289) node _T_1307 = or(_T_1306, _T_1290) node _T_1308 = and(_T_1242, _T_1307) node _T_1309 = or(UInt<1>(0h0), _T_1308) node _T_1310 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1311 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1312 = and(_T_1310, _T_1311) node _T_1313 = or(UInt<1>(0h0), _T_1312) node _T_1314 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1315 = cvt(_T_1314) node _T_1316 = and(_T_1315, asSInt(UInt<15>(0h5000))) node _T_1317 = asSInt(_T_1316) node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0))) node _T_1319 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1320 = cvt(_T_1319) node _T_1321 = and(_T_1320, asSInt(UInt<13>(0h1000))) node _T_1322 = asSInt(_T_1321) node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0))) node _T_1324 = or(_T_1318, _T_1323) node _T_1325 = and(_T_1313, _T_1324) node _T_1326 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1327 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1328 = cvt(_T_1327) node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000))) node _T_1330 = asSInt(_T_1329) node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) node _T_1332 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<17>(0h10000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1338 = cvt(_T_1337) node _T_1339 = and(_T_1338, asSInt(UInt<18>(0h2f000))) node _T_1340 = asSInt(_T_1339) node _T_1341 = eq(_T_1340, asSInt(UInt<1>(0h0))) node _T_1342 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1343 = cvt(_T_1342) node _T_1344 = and(_T_1343, asSInt(UInt<17>(0h10000))) node _T_1345 = asSInt(_T_1344) node _T_1346 = eq(_T_1345, asSInt(UInt<1>(0h0))) node _T_1347 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1348 = cvt(_T_1347) node _T_1349 = and(_T_1348, asSInt(UInt<13>(0h1000))) node _T_1350 = asSInt(_T_1349) node _T_1351 = eq(_T_1350, asSInt(UInt<1>(0h0))) node _T_1352 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1353 = cvt(_T_1352) node _T_1354 = and(_T_1353, asSInt(UInt<27>(0h4000000))) node _T_1355 = asSInt(_T_1354) node _T_1356 = eq(_T_1355, asSInt(UInt<1>(0h0))) node _T_1357 = or(_T_1331, _T_1336) node _T_1358 = or(_T_1357, _T_1341) node _T_1359 = or(_T_1358, _T_1346) node _T_1360 = or(_T_1359, _T_1351) node _T_1361 = or(_T_1360, _T_1356) node _T_1362 = and(_T_1326, _T_1361) node _T_1363 = or(UInt<1>(0h0), _T_1325) node _T_1364 = or(_T_1363, _T_1362) node _T_1365 = and(_T_1309, _T_1364) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_36 node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(source_ok, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(is_aligned, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1375 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_39 node _T_1379 = eq(io.in.a.bits.mask, mask) node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(_T_1379, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1379, UInt<1>(0h1), "") : assert_40 node _T_1383 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1383 : node _T_1384 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1385 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1386 = and(_T_1384, _T_1385) node _T_1387 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1388 = shr(io.in.a.bits.source, 2) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) node _T_1390 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1391 = and(_T_1389, _T_1390) node _T_1392 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1393 = and(_T_1391, _T_1392) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1394 = shr(io.in.a.bits.source, 2) node _T_1395 = eq(_T_1394, UInt<1>(0h1)) node _T_1396 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1397 = and(_T_1395, _T_1396) node _T_1398 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1399 = and(_T_1397, _T_1398) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1400 = shr(io.in.a.bits.source, 2) node _T_1401 = eq(_T_1400, UInt<2>(0h2)) node _T_1402 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1403 = and(_T_1401, _T_1402) node _T_1404 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1405 = and(_T_1403, _T_1404) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1406 = shr(io.in.a.bits.source, 2) node _T_1407 = eq(_T_1406, UInt<2>(0h3)) node _T_1408 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1409 = and(_T_1407, _T_1408) node _T_1410 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1411 = and(_T_1409, _T_1410) node _T_1412 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1413 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1414 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1415 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1416 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1417 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 2, 0) node _T_1418 = shr(io.in.a.bits.source, 3) node _T_1419 = eq(_T_1418, UInt<3>(0h6)) node _T_1420 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1421 = and(_T_1419, _T_1420) node _T_1422 = leq(uncommonBits_58, UInt<3>(0h4)) node _T_1423 = and(_T_1421, _T_1422) node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0) node _T_1426 = shr(io.in.a.bits.source, 3) node _T_1427 = eq(_T_1426, UInt<3>(0h4)) node _T_1428 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1429 = and(_T_1427, _T_1428) node _T_1430 = leq(uncommonBits_59, UInt<3>(0h4)) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1433 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1434 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1435 = or(_T_1387, _T_1393) node _T_1436 = or(_T_1435, _T_1399) node _T_1437 = or(_T_1436, _T_1405) node _T_1438 = or(_T_1437, _T_1411) node _T_1439 = or(_T_1438, _T_1412) node _T_1440 = or(_T_1439, _T_1413) node _T_1441 = or(_T_1440, _T_1414) node _T_1442 = or(_T_1441, _T_1415) node _T_1443 = or(_T_1442, _T_1416) node _T_1444 = or(_T_1443, _T_1417) node _T_1445 = or(_T_1444, _T_1423) node _T_1446 = or(_T_1445, _T_1424) node _T_1447 = or(_T_1446, _T_1425) node _T_1448 = or(_T_1447, _T_1431) node _T_1449 = or(_T_1448, _T_1432) node _T_1450 = or(_T_1449, _T_1433) node _T_1451 = or(_T_1450, _T_1434) node _T_1452 = and(_T_1386, _T_1451) node _T_1453 = or(UInt<1>(0h0), _T_1452) node _T_1454 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1455 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1456 = and(_T_1454, _T_1455) node _T_1457 = or(UInt<1>(0h0), _T_1456) node _T_1458 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1459 = cvt(_T_1458) node _T_1460 = and(_T_1459, asSInt(UInt<15>(0h5000))) node _T_1461 = asSInt(_T_1460) node _T_1462 = eq(_T_1461, asSInt(UInt<1>(0h0))) node _T_1463 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1464 = cvt(_T_1463) node _T_1465 = and(_T_1464, asSInt(UInt<13>(0h1000))) node _T_1466 = asSInt(_T_1465) node _T_1467 = eq(_T_1466, asSInt(UInt<1>(0h0))) node _T_1468 = or(_T_1462, _T_1467) node _T_1469 = and(_T_1457, _T_1468) node _T_1470 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1471 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1472 = cvt(_T_1471) node _T_1473 = and(_T_1472, asSInt(UInt<13>(0h1000))) node _T_1474 = asSInt(_T_1473) node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0))) node _T_1476 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<17>(0h10000))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1482 = cvt(_T_1481) node _T_1483 = and(_T_1482, asSInt(UInt<18>(0h2f000))) node _T_1484 = asSInt(_T_1483) node _T_1485 = eq(_T_1484, asSInt(UInt<1>(0h0))) node _T_1486 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1487 = cvt(_T_1486) node _T_1488 = and(_T_1487, asSInt(UInt<17>(0h10000))) node _T_1489 = asSInt(_T_1488) node _T_1490 = eq(_T_1489, asSInt(UInt<1>(0h0))) node _T_1491 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1492 = cvt(_T_1491) node _T_1493 = and(_T_1492, asSInt(UInt<13>(0h1000))) node _T_1494 = asSInt(_T_1493) node _T_1495 = eq(_T_1494, asSInt(UInt<1>(0h0))) node _T_1496 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1497 = cvt(_T_1496) node _T_1498 = and(_T_1497, asSInt(UInt<27>(0h4000000))) node _T_1499 = asSInt(_T_1498) node _T_1500 = eq(_T_1499, asSInt(UInt<1>(0h0))) node _T_1501 = or(_T_1475, _T_1480) node _T_1502 = or(_T_1501, _T_1485) node _T_1503 = or(_T_1502, _T_1490) node _T_1504 = or(_T_1503, _T_1495) node _T_1505 = or(_T_1504, _T_1500) node _T_1506 = and(_T_1470, _T_1505) node _T_1507 = or(UInt<1>(0h0), _T_1469) node _T_1508 = or(_T_1507, _T_1506) node _T_1509 = and(_T_1453, _T_1508) node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(_T_1509, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1509, UInt<1>(0h1), "") : assert_41 node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(source_ok, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(is_aligned, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1519 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_44 node _T_1523 = eq(io.in.a.bits.mask, mask) node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(_T_1523, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1523, UInt<1>(0h1), "") : assert_45 node _T_1527 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1527 : node _T_1528 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1529 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1530 = and(_T_1528, _T_1529) node _T_1531 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1532 = shr(io.in.a.bits.source, 2) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) node _T_1534 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1535 = and(_T_1533, _T_1534) node _T_1536 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1537 = and(_T_1535, _T_1536) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1538 = shr(io.in.a.bits.source, 2) node _T_1539 = eq(_T_1538, UInt<1>(0h1)) node _T_1540 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1541 = and(_T_1539, _T_1540) node _T_1542 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1543 = and(_T_1541, _T_1542) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1544 = shr(io.in.a.bits.source, 2) node _T_1545 = eq(_T_1544, UInt<2>(0h2)) node _T_1546 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1547 = and(_T_1545, _T_1546) node _T_1548 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1549 = and(_T_1547, _T_1548) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1550 = shr(io.in.a.bits.source, 2) node _T_1551 = eq(_T_1550, UInt<2>(0h3)) node _T_1552 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1553 = and(_T_1551, _T_1552) node _T_1554 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1555 = and(_T_1553, _T_1554) node _T_1556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0) node _T_1562 = shr(io.in.a.bits.source, 3) node _T_1563 = eq(_T_1562, UInt<3>(0h6)) node _T_1564 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1565 = and(_T_1563, _T_1564) node _T_1566 = leq(uncommonBits_64, UInt<3>(0h4)) node _T_1567 = and(_T_1565, _T_1566) node _T_1568 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1569 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 2, 0) node _T_1570 = shr(io.in.a.bits.source, 3) node _T_1571 = eq(_T_1570, UInt<3>(0h4)) node _T_1572 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1573 = and(_T_1571, _T_1572) node _T_1574 = leq(uncommonBits_65, UInt<3>(0h4)) node _T_1575 = and(_T_1573, _T_1574) node _T_1576 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1578 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1579 = or(_T_1531, _T_1537) node _T_1580 = or(_T_1579, _T_1543) node _T_1581 = or(_T_1580, _T_1549) node _T_1582 = or(_T_1581, _T_1555) node _T_1583 = or(_T_1582, _T_1556) node _T_1584 = or(_T_1583, _T_1557) node _T_1585 = or(_T_1584, _T_1558) node _T_1586 = or(_T_1585, _T_1559) node _T_1587 = or(_T_1586, _T_1560) node _T_1588 = or(_T_1587, _T_1561) node _T_1589 = or(_T_1588, _T_1567) node _T_1590 = or(_T_1589, _T_1568) node _T_1591 = or(_T_1590, _T_1569) node _T_1592 = or(_T_1591, _T_1575) node _T_1593 = or(_T_1592, _T_1576) node _T_1594 = or(_T_1593, _T_1577) node _T_1595 = or(_T_1594, _T_1578) node _T_1596 = and(_T_1530, _T_1595) node _T_1597 = or(UInt<1>(0h0), _T_1596) node _T_1598 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1599 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1600 = and(_T_1598, _T_1599) node _T_1601 = or(UInt<1>(0h0), _T_1600) node _T_1602 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = and(_T_1601, _T_1606) node _T_1608 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1609 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1610 = cvt(_T_1609) node _T_1611 = and(_T_1610, asSInt(UInt<14>(0h2000))) node _T_1612 = asSInt(_T_1611) node _T_1613 = eq(_T_1612, asSInt(UInt<1>(0h0))) node _T_1614 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1615 = cvt(_T_1614) node _T_1616 = and(_T_1615, asSInt(UInt<17>(0h10000))) node _T_1617 = asSInt(_T_1616) node _T_1618 = eq(_T_1617, asSInt(UInt<1>(0h0))) node _T_1619 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1620 = cvt(_T_1619) node _T_1621 = and(_T_1620, asSInt(UInt<18>(0h2f000))) node _T_1622 = asSInt(_T_1621) node _T_1623 = eq(_T_1622, asSInt(UInt<1>(0h0))) node _T_1624 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1625 = cvt(_T_1624) node _T_1626 = and(_T_1625, asSInt(UInt<17>(0h10000))) node _T_1627 = asSInt(_T_1626) node _T_1628 = eq(_T_1627, asSInt(UInt<1>(0h0))) node _T_1629 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1630 = cvt(_T_1629) node _T_1631 = and(_T_1630, asSInt(UInt<13>(0h1000))) node _T_1632 = asSInt(_T_1631) node _T_1633 = eq(_T_1632, asSInt(UInt<1>(0h0))) node _T_1634 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1635 = cvt(_T_1634) node _T_1636 = and(_T_1635, asSInt(UInt<27>(0h4000000))) node _T_1637 = asSInt(_T_1636) node _T_1638 = eq(_T_1637, asSInt(UInt<1>(0h0))) node _T_1639 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1640 = cvt(_T_1639) node _T_1641 = and(_T_1640, asSInt(UInt<13>(0h1000))) node _T_1642 = asSInt(_T_1641) node _T_1643 = eq(_T_1642, asSInt(UInt<1>(0h0))) node _T_1644 = or(_T_1613, _T_1618) node _T_1645 = or(_T_1644, _T_1623) node _T_1646 = or(_T_1645, _T_1628) node _T_1647 = or(_T_1646, _T_1633) node _T_1648 = or(_T_1647, _T_1638) node _T_1649 = or(_T_1648, _T_1643) node _T_1650 = and(_T_1608, _T_1649) node _T_1651 = or(UInt<1>(0h0), _T_1607) node _T_1652 = or(_T_1651, _T_1650) node _T_1653 = and(_T_1597, _T_1652) node _T_1654 = asUInt(reset) node _T_1655 = eq(_T_1654, UInt<1>(0h0)) when _T_1655 : node _T_1656 = eq(_T_1653, UInt<1>(0h0)) when _T_1656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1653, UInt<1>(0h1), "") : assert_46 node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(source_ok, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1660 = asUInt(reset) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(is_aligned, UInt<1>(0h0)) when _T_1662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1663 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_49 node _T_1667 = eq(io.in.a.bits.mask, mask) node _T_1668 = asUInt(reset) node _T_1669 = eq(_T_1668, UInt<1>(0h0)) when _T_1669 : node _T_1670 = eq(_T_1667, UInt<1>(0h0)) when _T_1670 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1667, UInt<1>(0h1), "") : assert_50 node _T_1671 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1672 = asUInt(reset) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(_T_1671, UInt<1>(0h0)) when _T_1674 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1671, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1675 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(_T_1675, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1675, UInt<1>(0h1), "") : assert_52 node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_65 = shr(io.in.d.bits.source, 2) node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h0)) node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_71 = shr(io.in.d.bits.source, 2) node _source_ok_T_72 = eq(_source_ok_T_71, UInt<1>(0h1)) node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 2) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h2)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_83 = shr(io.in.d.bits.source, 2) node _source_ok_T_84 = eq(_source_ok_T_83, UInt<2>(0h3)) node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) node _source_ok_T_87 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 2, 0) node _source_ok_T_95 = shr(io.in.d.bits.source, 3) node _source_ok_T_96 = eq(_source_ok_T_95, UInt<3>(0h6)) node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_T_99 = leq(source_ok_uncommonBits_10, UInt<3>(0h4)) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 3) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_11, UInt<3>(0h4)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[18] connect _source_ok_WIRE_1[0], _source_ok_T_64 connect _source_ok_WIRE_1[1], _source_ok_T_70 connect _source_ok_WIRE_1[2], _source_ok_T_76 connect _source_ok_WIRE_1[3], _source_ok_T_82 connect _source_ok_WIRE_1[4], _source_ok_T_88 connect _source_ok_WIRE_1[5], _source_ok_T_89 connect _source_ok_WIRE_1[6], _source_ok_T_90 connect _source_ok_WIRE_1[7], _source_ok_T_91 connect _source_ok_WIRE_1[8], _source_ok_T_92 connect _source_ok_WIRE_1[9], _source_ok_T_93 connect _source_ok_WIRE_1[10], _source_ok_T_94 connect _source_ok_WIRE_1[11], _source_ok_T_100 connect _source_ok_WIRE_1[12], _source_ok_T_101 connect _source_ok_WIRE_1[13], _source_ok_T_102 connect _source_ok_WIRE_1[14], _source_ok_T_108 connect _source_ok_WIRE_1[15], _source_ok_T_109 connect _source_ok_WIRE_1[16], _source_ok_T_110 connect _source_ok_WIRE_1[17], _source_ok_T_111 node _source_ok_T_112 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[2]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[3]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[4]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[5]) node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[6]) node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[7]) node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[8]) node _source_ok_T_120 = or(_source_ok_T_119, _source_ok_WIRE_1[9]) node _source_ok_T_121 = or(_source_ok_T_120, _source_ok_WIRE_1[10]) node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_1[11]) node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_1[12]) node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_1[13]) node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_1[14]) node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_1[15]) node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_1[16]) node source_ok_1 = or(_source_ok_T_127, _source_ok_WIRE_1[17]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1679 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1679 : node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(source_ok_1, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1683 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_54 node _T_1687 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_55 node _T_1691 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_56 node _T_1695 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_57 node _T_1699 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1699 : node _T_1700 = asUInt(reset) node _T_1701 = eq(_T_1700, UInt<1>(0h0)) when _T_1701 : node _T_1702 = eq(source_ok_1, UInt<1>(0h0)) when _T_1702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1703 = asUInt(reset) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) when _T_1704 : node _T_1705 = eq(sink_ok, UInt<1>(0h0)) when _T_1705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1706 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1707 = asUInt(reset) node _T_1708 = eq(_T_1707, UInt<1>(0h0)) when _T_1708 : node _T_1709 = eq(_T_1706, UInt<1>(0h0)) when _T_1709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1706, UInt<1>(0h1), "") : assert_60 node _T_1710 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1711 = asUInt(reset) node _T_1712 = eq(_T_1711, UInt<1>(0h0)) when _T_1712 : node _T_1713 = eq(_T_1710, UInt<1>(0h0)) when _T_1713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1710, UInt<1>(0h1), "") : assert_61 node _T_1714 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_62 node _T_1718 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1719 = asUInt(reset) node _T_1720 = eq(_T_1719, UInt<1>(0h0)) when _T_1720 : node _T_1721 = eq(_T_1718, UInt<1>(0h0)) when _T_1721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1718, UInt<1>(0h1), "") : assert_63 node _T_1722 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1723 = or(UInt<1>(0h1), _T_1722) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_64 node _T_1727 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1727 : node _T_1728 = asUInt(reset) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) when _T_1729 : node _T_1730 = eq(source_ok_1, UInt<1>(0h0)) when _T_1730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1731 = asUInt(reset) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) when _T_1732 : node _T_1733 = eq(sink_ok, UInt<1>(0h0)) when _T_1733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1734 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1735 = asUInt(reset) node _T_1736 = eq(_T_1735, UInt<1>(0h0)) when _T_1736 : node _T_1737 = eq(_T_1734, UInt<1>(0h0)) when _T_1737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1734, UInt<1>(0h1), "") : assert_67 node _T_1738 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1739 = asUInt(reset) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) when _T_1740 : node _T_1741 = eq(_T_1738, UInt<1>(0h0)) when _T_1741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1738, UInt<1>(0h1), "") : assert_68 node _T_1742 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1743 = asUInt(reset) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) when _T_1744 : node _T_1745 = eq(_T_1742, UInt<1>(0h0)) when _T_1745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1742, UInt<1>(0h1), "") : assert_69 node _T_1746 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1747 = or(_T_1746, io.in.d.bits.corrupt) node _T_1748 = asUInt(reset) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) when _T_1749 : node _T_1750 = eq(_T_1747, UInt<1>(0h0)) when _T_1750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1747, UInt<1>(0h1), "") : assert_70 node _T_1751 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1752 = or(UInt<1>(0h1), _T_1751) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_71 node _T_1756 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1756 : node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(source_ok_1, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1760 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1761 = asUInt(reset) node _T_1762 = eq(_T_1761, UInt<1>(0h0)) when _T_1762 : node _T_1763 = eq(_T_1760, UInt<1>(0h0)) when _T_1763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1760, UInt<1>(0h1), "") : assert_73 node _T_1764 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1765 = asUInt(reset) node _T_1766 = eq(_T_1765, UInt<1>(0h0)) when _T_1766 : node _T_1767 = eq(_T_1764, UInt<1>(0h0)) when _T_1767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1764, UInt<1>(0h1), "") : assert_74 node _T_1768 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1769 = or(UInt<1>(0h1), _T_1768) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_75 node _T_1773 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1773 : node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(source_ok_1, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1777 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1778 = asUInt(reset) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) when _T_1779 : node _T_1780 = eq(_T_1777, UInt<1>(0h0)) when _T_1780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1777, UInt<1>(0h1), "") : assert_77 node _T_1781 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1782 = or(_T_1781, io.in.d.bits.corrupt) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_78 node _T_1786 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1787 = or(UInt<1>(0h1), _T_1786) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_79 node _T_1791 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1791 : node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(source_ok_1, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1795 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_81 node _T_1799 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_82 node _T_1803 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1804 = or(UInt<1>(0h1), _T_1803) node _T_1805 = asUInt(reset) node _T_1806 = eq(_T_1805, UInt<1>(0h0)) when _T_1806 : node _T_1807 = eq(_T_1804, UInt<1>(0h0)) when _T_1807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1804, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1808 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1809 = asUInt(reset) node _T_1810 = eq(_T_1809, UInt<1>(0h0)) when _T_1810 : node _T_1811 = eq(_T_1808, UInt<1>(0h0)) when _T_1811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1808, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1812 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1813 = asUInt(reset) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) when _T_1814 : node _T_1815 = eq(_T_1812, UInt<1>(0h0)) when _T_1815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1812, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1816 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1817 = asUInt(reset) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(_T_1816, UInt<1>(0h0)) when _T_1819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1816, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1820 = eq(a_first, UInt<1>(0h0)) node _T_1821 = and(io.in.a.valid, _T_1820) when _T_1821 : node _T_1822 = eq(io.in.a.bits.opcode, opcode) node _T_1823 = asUInt(reset) node _T_1824 = eq(_T_1823, UInt<1>(0h0)) when _T_1824 : node _T_1825 = eq(_T_1822, UInt<1>(0h0)) when _T_1825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1822, UInt<1>(0h1), "") : assert_87 node _T_1826 = eq(io.in.a.bits.param, param) node _T_1827 = asUInt(reset) node _T_1828 = eq(_T_1827, UInt<1>(0h0)) when _T_1828 : node _T_1829 = eq(_T_1826, UInt<1>(0h0)) when _T_1829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1826, UInt<1>(0h1), "") : assert_88 node _T_1830 = eq(io.in.a.bits.size, size) node _T_1831 = asUInt(reset) node _T_1832 = eq(_T_1831, UInt<1>(0h0)) when _T_1832 : node _T_1833 = eq(_T_1830, UInt<1>(0h0)) when _T_1833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1830, UInt<1>(0h1), "") : assert_89 node _T_1834 = eq(io.in.a.bits.source, source) node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(_T_1834, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1834, UInt<1>(0h1), "") : assert_90 node _T_1838 = eq(io.in.a.bits.address, address) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_91 node _T_1842 = and(io.in.a.ready, io.in.a.valid) node _T_1843 = and(_T_1842, a_first) when _T_1843 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1844 = eq(d_first, UInt<1>(0h0)) node _T_1845 = and(io.in.d.valid, _T_1844) when _T_1845 : node _T_1846 = eq(io.in.d.bits.opcode, opcode_1) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_92 node _T_1850 = eq(io.in.d.bits.param, param_1) node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(_T_1850, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1850, UInt<1>(0h1), "") : assert_93 node _T_1854 = eq(io.in.d.bits.size, size_1) node _T_1855 = asUInt(reset) node _T_1856 = eq(_T_1855, UInt<1>(0h0)) when _T_1856 : node _T_1857 = eq(_T_1854, UInt<1>(0h0)) when _T_1857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1854, UInt<1>(0h1), "") : assert_94 node _T_1858 = eq(io.in.d.bits.source, source_1) node _T_1859 = asUInt(reset) node _T_1860 = eq(_T_1859, UInt<1>(0h0)) when _T_1860 : node _T_1861 = eq(_T_1858, UInt<1>(0h0)) when _T_1861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1858, UInt<1>(0h1), "") : assert_95 node _T_1862 = eq(io.in.d.bits.sink, sink) node _T_1863 = asUInt(reset) node _T_1864 = eq(_T_1863, UInt<1>(0h0)) when _T_1864 : node _T_1865 = eq(_T_1862, UInt<1>(0h0)) when _T_1865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1862, UInt<1>(0h1), "") : assert_96 node _T_1866 = eq(io.in.d.bits.denied, denied) node _T_1867 = asUInt(reset) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) when _T_1868 : node _T_1869 = eq(_T_1866, UInt<1>(0h0)) when _T_1869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1866, UInt<1>(0h1), "") : assert_97 node _T_1870 = and(io.in.d.ready, io.in.d.valid) node _T_1871 = and(_T_1870, d_first) when _T_1871 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<1032> connect a_sizes_set, UInt<1032>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1872 = and(io.in.a.valid, a_first_1) node _T_1873 = and(_T_1872, UInt<1>(0h1)) when _T_1873 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1874 = and(io.in.a.ready, io.in.a.valid) node _T_1875 = and(_T_1874, a_first_1) node _T_1876 = and(_T_1875, UInt<1>(0h1)) when _T_1876 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1877 = dshr(inflight, io.in.a.bits.source) node _T_1878 = bits(_T_1877, 0, 0) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<1032> connect d_sizes_clr, UInt<1032>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1883 = and(io.in.d.valid, d_first_1) node _T_1884 = and(_T_1883, UInt<1>(0h1)) node _T_1885 = eq(d_release_ack, UInt<1>(0h0)) node _T_1886 = and(_T_1884, _T_1885) when _T_1886 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1887 = and(io.in.d.ready, io.in.d.valid) node _T_1888 = and(_T_1887, d_first_1) node _T_1889 = and(_T_1888, UInt<1>(0h1)) node _T_1890 = eq(d_release_ack, UInt<1>(0h0)) node _T_1891 = and(_T_1889, _T_1890) when _T_1891 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1892 = and(io.in.d.valid, d_first_1) node _T_1893 = and(_T_1892, UInt<1>(0h1)) node _T_1894 = eq(d_release_ack, UInt<1>(0h0)) node _T_1895 = and(_T_1893, _T_1894) when _T_1895 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1896 = dshr(inflight, io.in.d.bits.source) node _T_1897 = bits(_T_1896, 0, 0) node _T_1898 = or(_T_1897, same_cycle_resp) node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(_T_1898, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1898, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1902 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1903 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1904 = or(_T_1902, _T_1903) node _T_1905 = asUInt(reset) node _T_1906 = eq(_T_1905, UInt<1>(0h0)) when _T_1906 : node _T_1907 = eq(_T_1904, UInt<1>(0h0)) when _T_1907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1904, UInt<1>(0h1), "") : assert_100 node _T_1908 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(_T_1908, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1908, UInt<1>(0h1), "") : assert_101 else : node _T_1912 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1913 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1914 = or(_T_1912, _T_1913) node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(_T_1914, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1914, UInt<1>(0h1), "") : assert_102 node _T_1918 = eq(io.in.d.bits.size, a_size_lookup) node _T_1919 = asUInt(reset) node _T_1920 = eq(_T_1919, UInt<1>(0h0)) when _T_1920 : node _T_1921 = eq(_T_1918, UInt<1>(0h0)) when _T_1921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1918, UInt<1>(0h1), "") : assert_103 node _T_1922 = and(io.in.d.valid, d_first_1) node _T_1923 = and(_T_1922, a_first_1) node _T_1924 = and(_T_1923, io.in.a.valid) node _T_1925 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1926 = and(_T_1924, _T_1925) node _T_1927 = eq(d_release_ack, UInt<1>(0h0)) node _T_1928 = and(_T_1926, _T_1927) when _T_1928 : node _T_1929 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1930 = or(_T_1929, io.in.a.ready) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_42 node _T_1934 = orr(inflight) node _T_1935 = eq(_T_1934, UInt<1>(0h0)) node _T_1936 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1937 = or(_T_1935, _T_1936) node _T_1938 = lt(watchdog, plusarg_reader.out) node _T_1939 = or(_T_1937, _T_1938) node _T_1940 = asUInt(reset) node _T_1941 = eq(_T_1940, UInt<1>(0h0)) when _T_1941 : node _T_1942 = eq(_T_1939, UInt<1>(0h0)) when _T_1942 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1939, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1943 = and(io.in.a.ready, io.in.a.valid) node _T_1944 = and(io.in.d.ready, io.in.d.valid) node _T_1945 = or(_T_1943, _T_1944) when _T_1945 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<1032> connect c_sizes_set, UInt<1032>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1946 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1947 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1948 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1949 = and(_T_1947, _T_1948) node _T_1950 = and(_T_1946, _T_1949) when _T_1950 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1951 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1952 = and(_T_1951, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1953 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1954 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1955 = and(_T_1953, _T_1954) node _T_1956 = and(_T_1952, _T_1955) when _T_1956 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1957 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1958 = bits(_T_1957, 0, 0) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) node _T_1960 = asUInt(reset) node _T_1961 = eq(_T_1960, UInt<1>(0h0)) when _T_1961 : node _T_1962 = eq(_T_1959, UInt<1>(0h0)) when _T_1962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1959, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<1032> connect d_sizes_clr_1, UInt<1032>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1963 = and(io.in.d.valid, d_first_2) node _T_1964 = and(_T_1963, UInt<1>(0h1)) node _T_1965 = and(_T_1964, d_release_ack_1) when _T_1965 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1966 = and(io.in.d.ready, io.in.d.valid) node _T_1967 = and(_T_1966, d_first_2) node _T_1968 = and(_T_1967, UInt<1>(0h1)) node _T_1969 = and(_T_1968, d_release_ack_1) when _T_1969 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1970 = and(io.in.d.valid, d_first_2) node _T_1971 = and(_T_1970, UInt<1>(0h1)) node _T_1972 = and(_T_1971, d_release_ack_1) when _T_1972 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1973 = dshr(inflight_1, io.in.d.bits.source) node _T_1974 = bits(_T_1973, 0, 0) node _T_1975 = or(_T_1974, same_cycle_resp_1) node _T_1976 = asUInt(reset) node _T_1977 = eq(_T_1976, UInt<1>(0h0)) when _T_1977 : node _T_1978 = eq(_T_1975, UInt<1>(0h0)) when _T_1978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1975, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1979 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1980 = asUInt(reset) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) when _T_1981 : node _T_1982 = eq(_T_1979, UInt<1>(0h0)) when _T_1982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1979, UInt<1>(0h1), "") : assert_108 else : node _T_1983 = eq(io.in.d.bits.size, c_size_lookup) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_109 node _T_1987 = and(io.in.d.valid, d_first_2) node _T_1988 = and(_T_1987, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1989 = and(_T_1988, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1990 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1991 = and(_T_1989, _T_1990) node _T_1992 = and(_T_1991, d_release_ack_1) node _T_1993 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1994 = and(_T_1992, _T_1993) when _T_1994 : node _T_1995 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1996 = or(_T_1995, _WIRE_27.ready) node _T_1997 = asUInt(reset) node _T_1998 = eq(_T_1997, UInt<1>(0h0)) when _T_1998 : node _T_1999 = eq(_T_1996, UInt<1>(0h0)) when _T_1999 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1996, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_43 node _T_2000 = orr(inflight_1) node _T_2001 = eq(_T_2000, UInt<1>(0h0)) node _T_2002 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2003 = or(_T_2001, _T_2002) node _T_2004 = lt(watchdog_1, plusarg_reader_1.out) node _T_2005 = or(_T_2003, _T_2004) node _T_2006 = asUInt(reset) node _T_2007 = eq(_T_2006, UInt<1>(0h0)) when _T_2007 : node _T_2008 = eq(_T_2005, UInt<1>(0h0)) when _T_2008 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2005, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2009 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2010 = and(io.in.d.ready, io.in.d.valid) node _T_2011 = or(_T_2009, _T_2010) when _T_2011 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_21( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_63 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31] wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_117 = _source_ok_T_116 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_118 = _source_ok_T_117 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_119 = _source_ok_T_118 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_120 = _source_ok_T_119 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_121 = _source_ok_T_120 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_122 = _source_ok_T_121 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_123 = _source_ok_T_122 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_124 = _source_ok_T_123 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_125 = _source_ok_T_124 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_126 = _source_ok_T_125 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_127 = _source_ok_T_126 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_127 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _T_1943 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1943; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1943; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_2011 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2011; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2011; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2011; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1876 = _T_1943 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1876 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1876 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1876 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1876 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1876 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1922 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1922 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1891 = _T_2011 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1891 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1891 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1891 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1987 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1987 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1969 = _T_2011 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1969 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1969 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1969 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_522 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_522( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}} wire _in_flight_WIRE : UInt<1>[8] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_38 = and(_T_36, _T_37) node _T_39 = or(_T_17, _T_24) node _T_40 = or(_T_39, _T_31) node _T_41 = or(_T_40, _T_38) node _T_42 = or(_T_10, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 node _T_46 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_69 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_74 = and(_T_72, _T_73) node _T_75 = or(_T_53, _T_60) node _T_76 = or(_T_75, _T_67) node _T_77 = or(_T_76, _T_74) node _T_78 = or(_T_46, _T_77) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_89 = and(_T_87, _T_88) node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_105 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_110 = and(_T_108, _T_109) node _T_111 = or(_T_89, _T_96) node _T_112 = or(_T_111, _T_103) node _T_113 = or(_T_112, _T_110) node _T_114 = or(_T_82, _T_113) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_114, UInt<1>(0h1), "") : assert_4 node _T_118 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_119 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_120 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_121 = and(_T_119, _T_120) node _T_122 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_123 = and(_T_121, _T_122) node _T_124 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_125 = and(_T_123, _T_124) node _T_126 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_127 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_134 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_139 = and(_T_137, _T_138) node _T_140 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_141 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_142 = and(_T_140, _T_141) node _T_143 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_146 = and(_T_144, _T_145) node _T_147 = or(_T_125, _T_132) node _T_148 = or(_T_147, _T_139) node _T_149 = or(_T_148, _T_146) node _T_150 = or(_T_118, _T_149) node _T_151 = asUInt(reset) node _T_152 = eq(_T_151, UInt<1>(0h0)) when _T_152 : node _T_153 = eq(_T_150, UInt<1>(0h0)) when _T_153 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_150, UInt<1>(0h1), "") : assert_5 node _T_154 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_156 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_163 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_170 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_177 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_184 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_191 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_194 = and(_T_192, _T_193) node _T_195 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_196 = and(_T_194, _T_195) node _T_197 = or(_T_161, _T_168) node _T_198 = or(_T_197, _T_175) node _T_199 = or(_T_198, _T_182) node _T_200 = or(_T_199, _T_189) node _T_201 = or(_T_200, _T_196) node _T_202 = or(_T_154, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_202, UInt<1>(0h1), "") : assert_6 node _T_206 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_207 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_208 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_215 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_222 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_229 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_236 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_243 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_244 = and(_T_242, _T_243) node _T_245 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_248 = and(_T_246, _T_247) node _T_249 = or(_T_213, _T_220) node _T_250 = or(_T_249, _T_227) node _T_251 = or(_T_250, _T_234) node _T_252 = or(_T_251, _T_241) node _T_253 = or(_T_252, _T_248) node _T_254 = or(_T_206, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_254, UInt<1>(0h1), "") : assert_7 node _T_258 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_259 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_260 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_261 = and(_T_259, _T_260) node _T_262 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_263 = and(_T_261, _T_262) node _T_264 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_267 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_268 = and(_T_266, _T_267) node _T_269 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_272 = and(_T_270, _T_271) node _T_273 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_274 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_279 = and(_T_277, _T_278) node _T_280 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_281 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_282 = and(_T_280, _T_281) node _T_283 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_284 = and(_T_282, _T_283) node _T_285 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_286 = and(_T_284, _T_285) node _T_287 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_288 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _T_290 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_291 = and(_T_289, _T_290) node _T_292 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_295 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_300 = and(_T_298, _T_299) node _T_301 = or(_T_265, _T_272) node _T_302 = or(_T_301, _T_279) node _T_303 = or(_T_302, _T_286) node _T_304 = or(_T_303, _T_293) node _T_305 = or(_T_304, _T_300) node _T_306 = or(_T_258, _T_305) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_306, UInt<1>(0h1), "") : assert_8

module NoCMonitor_16( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to this FIRRTL code module PE_290 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_34 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_290( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_34 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_429 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_429( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module LoopMatmulLdA : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { max_i : UInt<16>, max_k : UInt<16>, pad_i : UInt<2>, pad_k : UInt<2>, dram_addr : UInt<40>, dram_stride : UInt<40>, transpose : UInt<1>, addr_start : UInt<14>, loop_id : UInt<1>, is_resadd : UInt<1>}}, cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, i : UInt<16>, k : UInt<16>, idle : UInt<1>, flip rob_overloaded : UInt<1>, loop_id : UInt<1>} regreset state : UInt<1>, clock, reset, UInt<1>(0h0) reg req : { max_i : UInt<16>, max_k : UInt<16>, pad_i : UInt<2>, pad_k : UInt<2>, dram_addr : UInt<40>, dram_stride : UInt<40>, transpose : UInt<1>, addr_start : UInt<14>, loop_id : UInt<1>, is_resadd : UInt<1>}, clock reg i : UInt<16>, clock reg k : UInt<16>, clock node row_iterator = mux(req.transpose, k, i) node col_iterator = mux(req.transpose, i, k) node max_row_iterator = mux(req.transpose, req.max_k, req.max_i) node max_col_iterator = mux(req.transpose, req.max_i, req.max_k) node row_pad = mux(req.transpose, req.pad_k, req.pad_i) node col_pad = mux(req.transpose, req.pad_i, req.pad_k) node max_col_dim = mux(req.transpose, req.max_i, req.max_k) node _max_blocks_T = leq(max_col_dim, UInt<3>(0h4)) node max_blocks = mux(_max_blocks_T, max_col_dim, UInt<3>(0h4)) node _dram_offset_T = mul(row_iterator, req.dram_stride) node _dram_offset_T_1 = add(_dram_offset_T, col_iterator) node _dram_offset_T_2 = tail(_dram_offset_T_1, 1) node _dram_offset_T_3 = mul(_dram_offset_T_2, UInt<3>(0h4)) node dram_offset = mul(_dram_offset_T_3, UInt<3>(0h4)) node _dram_addr_T = and(dram_offset, UInt<32>(0hffffffff)) node _dram_addr_T_1 = add(req.dram_addr, _dram_addr_T) node dram_addr = tail(_dram_addr_T_1, 1) node _sp_addr_T = mul(row_iterator, max_col_iterator) node _sp_addr_T_1 = add(_sp_addr_T, col_iterator) node _sp_addr_T_2 = tail(_sp_addr_T_1, 1) node _sp_addr_T_3 = mul(_sp_addr_T_2, UInt<3>(0h4)) node _sp_addr_T_4 = add(req.addr_start, _sp_addr_T_3) node sp_addr = tail(_sp_addr_T_4, 1) node _blocks_T = add(col_iterator, max_blocks) node _blocks_T_1 = tail(_blocks_T, 1) node _blocks_T_2 = leq(_blocks_T_1, max_col_iterator) node _blocks_T_3 = sub(max_col_iterator, col_iterator) node _blocks_T_4 = tail(_blocks_T_3, 1) node blocks = mux(_blocks_T_2, max_blocks, _blocks_T_4) node _cols_T = mul(blocks, UInt<3>(0h4)) node _cols_T_1 = add(col_iterator, blocks) node _cols_T_2 = tail(_cols_T_1, 1) node _cols_T_3 = geq(_cols_T_2, max_col_iterator) node _cols_T_4 = mux(_cols_T_3, col_pad, UInt<1>(0h0)) node _cols_T_5 = sub(_cols_T, _cols_T_4) node cols = tail(_cols_T_5, 1) node _rows_T = sub(max_row_iterator, UInt<1>(0h1)) node _rows_T_1 = tail(_rows_T, 1) node _rows_T_2 = eq(row_iterator, _rows_T_1) node _rows_T_3 = mux(_rows_T_2, row_pad, UInt<1>(0h0)) node _rows_T_4 = sub(UInt<3>(0h4), _rows_T_3) node rows = tail(_rows_T_4, 1) wire mvin_cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} invalidate mvin_cmd.status.uie invalidate mvin_cmd.status.sie invalidate mvin_cmd.status.hie invalidate mvin_cmd.status.mie invalidate mvin_cmd.status.upie invalidate mvin_cmd.status.spie invalidate mvin_cmd.status.ube invalidate mvin_cmd.status.mpie invalidate mvin_cmd.status.spp invalidate mvin_cmd.status.vs invalidate mvin_cmd.status.mpp invalidate mvin_cmd.status.fs invalidate mvin_cmd.status.xs invalidate mvin_cmd.status.mprv invalidate mvin_cmd.status.sum invalidate mvin_cmd.status.mxr invalidate mvin_cmd.status.tvm invalidate mvin_cmd.status.tw invalidate mvin_cmd.status.tsr invalidate mvin_cmd.status.zero1 invalidate mvin_cmd.status.sd_rv32 invalidate mvin_cmd.status.uxl invalidate mvin_cmd.status.sxl invalidate mvin_cmd.status.sbe invalidate mvin_cmd.status.mbe invalidate mvin_cmd.status.gva invalidate mvin_cmd.status.mpv invalidate mvin_cmd.status.zero2 invalidate mvin_cmd.status.sd invalidate mvin_cmd.status.v invalidate mvin_cmd.status.prv invalidate mvin_cmd.status.dv invalidate mvin_cmd.status.dprv invalidate mvin_cmd.status.isa invalidate mvin_cmd.status.wfi invalidate mvin_cmd.status.cease invalidate mvin_cmd.status.debug invalidate mvin_cmd.rs2 invalidate mvin_cmd.rs1 invalidate mvin_cmd.inst.opcode invalidate mvin_cmd.inst.rd invalidate mvin_cmd.inst.xs2 invalidate mvin_cmd.inst.xs1 invalidate mvin_cmd.inst.xd invalidate mvin_cmd.inst.rs1 invalidate mvin_cmd.inst.rs2 invalidate mvin_cmd.inst.funct connect mvin_cmd.inst.funct, UInt<2>(0h2) connect mvin_cmd.rs1, dram_addr wire mvin_cmd_rs2 : { _spacer2 : UInt<13>, num_rows : UInt<3>, _spacer1 : UInt<11>, num_cols : UInt<5>, _spacer0 : UInt<0>, local_addr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}} invalidate mvin_cmd_rs2.local_addr.data invalidate mvin_cmd_rs2.local_addr.garbage_bit invalidate mvin_cmd_rs2.local_addr.garbage invalidate mvin_cmd_rs2.local_addr.norm_cmd invalidate mvin_cmd_rs2.local_addr.read_full_acc_row invalidate mvin_cmd_rs2.local_addr.accumulate invalidate mvin_cmd_rs2.local_addr.is_acc_addr invalidate mvin_cmd_rs2._spacer0 invalidate mvin_cmd_rs2.num_cols invalidate mvin_cmd_rs2._spacer1 invalidate mvin_cmd_rs2.num_rows invalidate mvin_cmd_rs2._spacer2 connect mvin_cmd_rs2.num_rows, rows connect mvin_cmd_rs2.num_cols, cols wire _mvin_cmd_rs2_local_addr_result_result_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _mvin_cmd_rs2_local_addr_result_result_WIRE_1 : UInt<32> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_1, sp_addr node _mvin_cmd_rs2_local_addr_result_result_T = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 13, 0) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.data, _mvin_cmd_rs2_local_addr_result_result_T node _mvin_cmd_rs2_local_addr_result_result_T_1 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 14, 14) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.garbage_bit, _mvin_cmd_rs2_local_addr_result_result_T_1 node _mvin_cmd_rs2_local_addr_result_result_T_2 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 25, 15) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.garbage, _mvin_cmd_rs2_local_addr_result_result_T_2 node _mvin_cmd_rs2_local_addr_result_result_T_3 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 28, 26) wire _mvin_cmd_rs2_local_addr_result_result_WIRE_2 : UInt<3> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_2, _mvin_cmd_rs2_local_addr_result_result_T_3 wire _mvin_cmd_rs2_local_addr_result_result_WIRE_3 : UInt<3> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_3, _mvin_cmd_rs2_local_addr_result_result_WIRE_2 connect _mvin_cmd_rs2_local_addr_result_result_WIRE.norm_cmd, _mvin_cmd_rs2_local_addr_result_result_WIRE_3 node _mvin_cmd_rs2_local_addr_result_result_T_4 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 29, 29) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.read_full_acc_row, _mvin_cmd_rs2_local_addr_result_result_T_4 node _mvin_cmd_rs2_local_addr_result_result_T_5 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 30, 30) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.accumulate, _mvin_cmd_rs2_local_addr_result_result_T_5 node _mvin_cmd_rs2_local_addr_result_result_T_6 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_1, 31, 31) connect _mvin_cmd_rs2_local_addr_result_result_WIRE.is_acc_addr, _mvin_cmd_rs2_local_addr_result_result_T_6 wire mvin_cmd_rs2_local_addr_result_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvin_cmd_rs2_local_addr_result_result, _mvin_cmd_rs2_local_addr_result_result_WIRE connect mvin_cmd_rs2_local_addr_result_result.garbage, UInt<1>(0h0) wire mvin_cmd_rs2_local_addr_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvin_cmd_rs2_local_addr_result, mvin_cmd_rs2_local_addr_result_result connect mvin_cmd_rs2_local_addr_result.is_acc_addr, UInt<1>(0h0) connect mvin_cmd_rs2_local_addr_result.accumulate, UInt<1>(0h0) connect mvin_cmd_rs2_local_addr_result.read_full_acc_row, UInt<1>(0h0) connect mvin_cmd_rs2.local_addr, mvin_cmd_rs2_local_addr_result node _mvin_cmd_rs2_T = asUInt(mvin_cmd_rs2.local_addr.norm_cmd) node mvin_cmd_rs2_lo_hi = cat(mvin_cmd_rs2.local_addr.garbage, mvin_cmd_rs2.local_addr.garbage_bit) node mvin_cmd_rs2_lo = cat(mvin_cmd_rs2_lo_hi, mvin_cmd_rs2.local_addr.data) node mvin_cmd_rs2_hi_lo = cat(mvin_cmd_rs2.local_addr.read_full_acc_row, _mvin_cmd_rs2_T) node mvin_cmd_rs2_hi_hi = cat(mvin_cmd_rs2.local_addr.is_acc_addr, mvin_cmd_rs2.local_addr.accumulate) node mvin_cmd_rs2_hi = cat(mvin_cmd_rs2_hi_hi, mvin_cmd_rs2_hi_lo) node _mvin_cmd_rs2_T_1 = cat(mvin_cmd_rs2_hi, mvin_cmd_rs2_lo) node mvin_cmd_rs2_lo_hi_1 = cat(mvin_cmd_rs2.num_cols, mvin_cmd_rs2._spacer0) node mvin_cmd_rs2_lo_1 = cat(mvin_cmd_rs2_lo_hi_1, _mvin_cmd_rs2_T_1) node mvin_cmd_rs2_hi_hi_1 = cat(mvin_cmd_rs2._spacer2, mvin_cmd_rs2.num_rows) node mvin_cmd_rs2_hi_1 = cat(mvin_cmd_rs2_hi_hi_1, mvin_cmd_rs2._spacer1) node _mvin_cmd_rs2_T_2 = cat(mvin_cmd_rs2_hi_1, mvin_cmd_rs2_lo_1) connect mvin_cmd.rs2, _mvin_cmd_rs2_T_2 when req.is_resadd : wire _mvin_cmd_rs2_local_addr_result_result_WIRE_4 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _mvin_cmd_rs2_local_addr_result_result_WIRE_5 : UInt<32> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_5, sp_addr node _mvin_cmd_rs2_local_addr_result_result_T_7 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 13, 0) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.data, _mvin_cmd_rs2_local_addr_result_result_T_7 node _mvin_cmd_rs2_local_addr_result_result_T_8 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 14, 14) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.garbage_bit, _mvin_cmd_rs2_local_addr_result_result_T_8 node _mvin_cmd_rs2_local_addr_result_result_T_9 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 25, 15) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.garbage, _mvin_cmd_rs2_local_addr_result_result_T_9 node _mvin_cmd_rs2_local_addr_result_result_T_10 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 28, 26) wire _mvin_cmd_rs2_local_addr_result_result_WIRE_6 : UInt<3> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_6, _mvin_cmd_rs2_local_addr_result_result_T_10 wire _mvin_cmd_rs2_local_addr_result_result_WIRE_7 : UInt<3> connect _mvin_cmd_rs2_local_addr_result_result_WIRE_7, _mvin_cmd_rs2_local_addr_result_result_WIRE_6 connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.norm_cmd, _mvin_cmd_rs2_local_addr_result_result_WIRE_7 node _mvin_cmd_rs2_local_addr_result_result_T_11 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 29, 29) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.read_full_acc_row, _mvin_cmd_rs2_local_addr_result_result_T_11 node _mvin_cmd_rs2_local_addr_result_result_T_12 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 30, 30) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.accumulate, _mvin_cmd_rs2_local_addr_result_result_T_12 node _mvin_cmd_rs2_local_addr_result_result_T_13 = bits(_mvin_cmd_rs2_local_addr_result_result_WIRE_5, 31, 31) connect _mvin_cmd_rs2_local_addr_result_result_WIRE_4.is_acc_addr, _mvin_cmd_rs2_local_addr_result_result_T_13 wire mvin_cmd_rs2_local_addr_result_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvin_cmd_rs2_local_addr_result_result_1, _mvin_cmd_rs2_local_addr_result_result_WIRE_4 connect mvin_cmd_rs2_local_addr_result_result_1.garbage, UInt<1>(0h0) wire mvin_cmd_rs2_local_addr_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect mvin_cmd_rs2_local_addr_result_1, mvin_cmd_rs2_local_addr_result_result_1 connect mvin_cmd_rs2_local_addr_result_1.is_acc_addr, UInt<1>(0h1) connect mvin_cmd_rs2_local_addr_result_1.accumulate, UInt<1>(0h0) connect mvin_cmd_rs2_local_addr_result_1.read_full_acc_row, UInt<1>(0h0) connect mvin_cmd_rs2.local_addr, mvin_cmd_rs2_local_addr_result_1 node _io_req_ready_T = eq(state, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T connect io.i, i connect io.k, k node _io_idle_T = eq(state, UInt<1>(0h0)) connect io.idle, _io_idle_T node _io_cmd_valid_T = neq(state, UInt<1>(0h0)) node _io_cmd_valid_T_1 = eq(io.rob_overloaded, UInt<1>(0h0)) node _io_cmd_valid_T_2 = and(_io_cmd_valid_T, _io_cmd_valid_T_1) node _io_cmd_valid_T_3 = neq(req.dram_addr, UInt<1>(0h0)) node _io_cmd_valid_T_4 = and(_io_cmd_valid_T_2, _io_cmd_valid_T_3) connect io.cmd.valid, _io_cmd_valid_T_4 connect io.cmd.bits, mvin_cmd connect io.loop_id, req.loop_id node _T = eq(req.dram_addr, UInt<1>(0h0)) when _T : connect state, UInt<1>(0h0) else : node _T_1 = and(io.cmd.ready, io.cmd.valid) when _T_1 : node i_blocks = mux(req.transpose, max_blocks, UInt<1>(0h1)) node k_blocks = mux(req.transpose, UInt<1>(0h1), max_blocks) node _next_i_max_T = sub(req.max_i, UInt<1>(0h1)) node next_i_max = tail(_next_i_max_T, 1) node _next_i_T = add(i, i_blocks) node _next_i_T_1 = tail(_next_i_T, 1) node _next_i_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _next_i_T_3 = add(i, i_blocks) node _next_i_T_4 = gt(_next_i_T_3, next_i_max) node _next_i_T_5 = mux(_next_i_T_4, UInt<1>(0h0), _next_i_T_1) node next_i = mux(_next_i_T_2, i, _next_i_T_5) node _next_k_T = eq(next_i, UInt<1>(0h0)) node _next_k_max_T = sub(req.max_k, UInt<1>(0h1)) node next_k_max = tail(_next_k_max_T, 1) node _next_k_T_1 = add(k, k_blocks) node _next_k_T_2 = tail(_next_k_T_1, 1) node _next_k_T_3 = eq(_next_k_T, UInt<1>(0h0)) node _next_k_T_4 = add(k, k_blocks) node _next_k_T_5 = gt(_next_k_T_4, next_k_max) node _next_k_T_6 = mux(_next_k_T_5, UInt<1>(0h0), _next_k_T_2) node next_k = mux(_next_k_T_3, k, _next_k_T_6) connect i, next_i connect k, next_k node _T_2 = eq(next_i, UInt<1>(0h0)) node _T_3 = eq(next_k, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect state, UInt<1>(0h0) node _T_5 = and(io.req.ready, io.req.valid) when _T_5 : connect req, io.req.bits connect state, UInt<1>(0h1) connect i, UInt<1>(0h0) connect k, UInt<1>(0h0)

module LoopMatmulLdA( // @[LoopMatmul.scala:28:7] input clock, // @[LoopMatmul.scala:28:7] input reset, // @[LoopMatmul.scala:28:7] output io_req_ready, // @[LoopMatmul.scala:31:14] input io_req_valid, // @[LoopMatmul.scala:31:14] input [15:0] io_req_bits_max_i, // @[LoopMatmul.scala:31:14] input [15:0] io_req_bits_max_k, // @[LoopMatmul.scala:31:14] input [1:0] io_req_bits_pad_i, // @[LoopMatmul.scala:31:14] input [1:0] io_req_bits_pad_k, // @[LoopMatmul.scala:31:14] input [39:0] io_req_bits_dram_addr, // @[LoopMatmul.scala:31:14] input [39:0] io_req_bits_dram_stride, // @[LoopMatmul.scala:31:14] input io_req_bits_transpose, // @[LoopMatmul.scala:31:14] input [13:0] io_req_bits_addr_start, // @[LoopMatmul.scala:31:14] input io_req_bits_loop_id, // @[LoopMatmul.scala:31:14] input io_req_bits_is_resadd, // @[LoopMatmul.scala:31:14] input io_cmd_ready, // @[LoopMatmul.scala:31:14] output io_cmd_valid, // @[LoopMatmul.scala:31:14] output [63:0] io_cmd_bits_rs1, // @[LoopMatmul.scala:31:14] output [63:0] io_cmd_bits_rs2, // @[LoopMatmul.scala:31:14] output [15:0] io_i, // @[LoopMatmul.scala:31:14] output [15:0] io_k, // @[LoopMatmul.scala:31:14] output io_idle, // @[LoopMatmul.scala:31:14] input io_rob_overloaded, // @[LoopMatmul.scala:31:14] output io_loop_id // @[LoopMatmul.scala:31:14] ); wire _mvin_cmd_rs2_local_addr_result_result_WIRE_4_is_acc_addr; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_4_accumulate; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_4_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_4_norm_cmd; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_4_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_4_data; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37] wire [4:0] mvin_cmd_rs2_num_cols; // @[LoopMatmul.scala:78:26] wire [2:0] mvin_cmd_rs2_local_addr_norm_cmd; // @[LoopMatmul.scala:78:26] wire io_req_valid_0 = io_req_valid; // @[LoopMatmul.scala:28:7] wire [15:0] io_req_bits_max_i_0 = io_req_bits_max_i; // @[LoopMatmul.scala:28:7] wire [15:0] io_req_bits_max_k_0 = io_req_bits_max_k; // @[LoopMatmul.scala:28:7] wire [1:0] io_req_bits_pad_i_0 = io_req_bits_pad_i; // @[LoopMatmul.scala:28:7] wire [1:0] io_req_bits_pad_k_0 = io_req_bits_pad_k; // @[LoopMatmul.scala:28:7] wire [39:0] io_req_bits_dram_addr_0 = io_req_bits_dram_addr; // @[LoopMatmul.scala:28:7] wire [39:0] io_req_bits_dram_stride_0 = io_req_bits_dram_stride; // @[LoopMatmul.scala:28:7] wire io_req_bits_transpose_0 = io_req_bits_transpose; // @[LoopMatmul.scala:28:7] wire [13:0] io_req_bits_addr_start_0 = io_req_bits_addr_start; // @[LoopMatmul.scala:28:7] wire io_req_bits_loop_id_0 = io_req_bits_loop_id; // @[LoopMatmul.scala:28:7] wire io_req_bits_is_resadd_0 = io_req_bits_is_resadd; // @[LoopMatmul.scala:28:7] wire io_cmd_ready_0 = io_cmd_ready; // @[LoopMatmul.scala:28:7] wire io_rob_overloaded_0 = io_rob_overloaded; // @[LoopMatmul.scala:28:7] wire [12:0] mvin_cmd_rs2__spacer2 = 13'h0; // @[LoopMatmul.scala:78:26] wire mvin_cmd_rs2_local_addr_result_1_is_acc_addr = 1'h1; // @[LocalAddr.scala:129:26] wire [10:0] mvin_cmd_rs2__spacer1 = 11'h0; // @[LoopMatmul.scala:78:26] wire [10:0] mvin_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopMatmul.scala:78:26] wire [10:0] mvin_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] mvin_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:116:26] wire [10:0] mvin_cmd_rs2_local_addr_result_result_1_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] mvin_cmd_rs2_local_addr_result_1_garbage = 11'h0; // @[LocalAddr.scala:129:26] wire [7:0] io_cmd_bits_status_zero1 = 8'h0; // @[LoopMatmul.scala:28:7] wire [7:0] mvin_cmd_status_zero1 = 8'h0; // @[LoopMatmul.scala:73:22] wire [22:0] io_cmd_bits_status_zero2 = 23'h0; // @[LoopMatmul.scala:28:7] wire [22:0] mvin_cmd_status_zero2 = 23'h0; // @[LoopMatmul.scala:73:22] wire [1:0] io_cmd_bits_status_dprv = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_prv = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_sxl = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_uxl = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_xs = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_fs = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_mpp = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] io_cmd_bits_status_vs = 2'h0; // @[LoopMatmul.scala:28:7] wire [1:0] mvin_cmd_status_dprv = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_prv = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_sxl = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_uxl = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_xs = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_fs = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_mpp = 2'h0; // @[LoopMatmul.scala:73:22] wire [1:0] mvin_cmd_status_vs = 2'h0; // @[LoopMatmul.scala:73:22] wire [31:0] io_cmd_bits_status_isa = 32'h0; // @[LoopMatmul.scala:28:7] wire [31:0] mvin_cmd_status_isa = 32'h0; // @[LoopMatmul.scala:73:22] wire [6:0] io_cmd_bits_inst_opcode = 7'h0; // @[LoopMatmul.scala:28:7] wire [6:0] mvin_cmd_inst_opcode = 7'h0; // @[LoopMatmul.scala:73:22] wire io_cmd_bits_inst_xd = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_inst_xs1 = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_inst_xs2 = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_debug = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_cease = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_wfi = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_dv = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_v = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_sd = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mpv = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_gva = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mbe = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_sbe = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_tsr = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_tw = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_tvm = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mxr = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_sum = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mprv = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_spp = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mpie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_ube = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_spie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_upie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_mie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_hie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_sie = 1'h0; // @[LoopMatmul.scala:28:7] wire io_cmd_bits_status_uie = 1'h0; // @[LoopMatmul.scala:28:7] wire mvin_cmd_inst_xd = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_inst_xs1 = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_inst_xs2 = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_debug = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_cease = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_wfi = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_dv = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_v = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_sd = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mpv = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_gva = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mbe = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_sbe = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_sd_rv32 = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_tsr = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_tw = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_tvm = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mxr = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_sum = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mprv = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_spp = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mpie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_ube = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_spie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_upie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_mie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_hie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_sie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_status_uie = 1'h0; // @[LoopMatmul.scala:73:22] wire mvin_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopMatmul.scala:78:26] wire mvin_cmd_rs2_local_addr_read_full_acc_row = 1'h0; // @[LoopMatmul.scala:78:26] wire mvin_cmd_rs2_local_addr_result_is_acc_addr = 1'h0; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_result_read_full_acc_row = 1'h0; // @[LocalAddr.scala:116:26] wire mvin_cmd_rs2_local_addr_result_1_accumulate = 1'h0; // @[LocalAddr.scala:129:26] wire mvin_cmd_rs2_local_addr_result_1_read_full_acc_row = 1'h0; // @[LocalAddr.scala:129:26] wire _next_i_T_2 = 1'h0; // @[Util.scala:42:8] wire [4:0] io_cmd_bits_inst_rs2 = 5'h0; // @[LoopMatmul.scala:28:7] wire [4:0] io_cmd_bits_inst_rs1 = 5'h0; // @[LoopMatmul.scala:28:7] wire [4:0] io_cmd_bits_inst_rd = 5'h0; // @[LoopMatmul.scala:28:7] wire [4:0] mvin_cmd_inst_rs2 = 5'h0; // @[LoopMatmul.scala:73:22] wire [4:0] mvin_cmd_inst_rs1 = 5'h0; // @[LoopMatmul.scala:73:22] wire [4:0] mvin_cmd_inst_rd = 5'h0; // @[LoopMatmul.scala:73:22] wire [6:0] io_cmd_bits_inst_funct = 7'h2; // @[LoopMatmul.scala:28:7] wire [6:0] mvin_cmd_inst_funct = 7'h2; // @[LoopMatmul.scala:73:22] wire _io_req_ready_T; // @[LoopMatmul.scala:88:25] wire _io_cmd_valid_T_4; // @[LoopMatmul.scala:93:56] wire [63:0] mvin_cmd_rs1; // @[LoopMatmul.scala:73:22] wire [63:0] mvin_cmd_rs2; // @[LoopMatmul.scala:73:22] wire _io_idle_T; // @[LoopMatmul.scala:91:20] wire io_req_ready_0; // @[LoopMatmul.scala:28:7] wire [63:0] io_cmd_bits_rs1_0; // @[LoopMatmul.scala:28:7] wire [63:0] io_cmd_bits_rs2_0; // @[LoopMatmul.scala:28:7] wire io_cmd_valid_0; // @[LoopMatmul.scala:28:7] wire [15:0] io_i_0; // @[LoopMatmul.scala:28:7] wire [15:0] io_k_0; // @[LoopMatmul.scala:28:7] wire io_idle_0; // @[LoopMatmul.scala:28:7] wire io_loop_id_0; // @[LoopMatmul.scala:28:7] reg state; // @[LoopMatmul.scala:45:22] wire _io_cmd_valid_T = state; // @[LoopMatmul.scala:45:22, :93:25] reg [15:0] req_max_i; // @[LoopMatmul.scala:47:16] reg [15:0] req_max_k; // @[LoopMatmul.scala:47:16] reg [1:0] req_pad_i; // @[LoopMatmul.scala:47:16] reg [1:0] req_pad_k; // @[LoopMatmul.scala:47:16] reg [39:0] req_dram_addr; // @[LoopMatmul.scala:47:16] reg [39:0] req_dram_stride; // @[LoopMatmul.scala:47:16] reg req_transpose; // @[LoopMatmul.scala:47:16] reg [13:0] req_addr_start; // @[LoopMatmul.scala:47:16] reg req_loop_id; // @[LoopMatmul.scala:47:16] assign io_loop_id_0 = req_loop_id; // @[LoopMatmul.scala:28:7, :47:16] reg req_is_resadd; // @[LoopMatmul.scala:47:16] wire mvin_cmd_rs2_local_addr_is_acc_addr = req_is_resadd; // @[LoopMatmul.scala:47:16, :78:26] reg [15:0] i; // @[LoopMatmul.scala:49:14] assign io_i_0 = i; // @[LoopMatmul.scala:28:7, :49:14] reg [15:0] k; // @[LoopMatmul.scala:50:14] assign io_k_0 = k; // @[LoopMatmul.scala:28:7, :50:14] wire [15:0] row_iterator = req_transpose ? k : i; // @[LoopMatmul.scala:47:16, :49:14, :50:14, :52:25] wire [15:0] col_iterator = req_transpose ? i : k; // @[LoopMatmul.scala:47:16, :49:14, :50:14, :53:25] wire [15:0] max_row_iterator = req_transpose ? req_max_k : req_max_i; // @[LoopMatmul.scala:47:16, :55:29] wire [15:0] _GEN = req_transpose ? req_max_i : req_max_k; // @[LoopMatmul.scala:47:16, :56:29] wire [15:0] max_col_iterator; // @[LoopMatmul.scala:56:29] assign max_col_iterator = _GEN; // @[LoopMatmul.scala:56:29] wire [15:0] max_col_dim; // @[LoopMatmul.scala:61:24] assign max_col_dim = _GEN; // @[LoopMatmul.scala:56:29, :61:24] wire [1:0] row_pad = req_transpose ? req_pad_k : req_pad_i; // @[LoopMatmul.scala:47:16, :58:20] wire [1:0] col_pad = req_transpose ? req_pad_i : req_pad_k; // @[LoopMatmul.scala:47:16, :59:20] wire _max_blocks_T = max_col_dim < 16'h5; // @[LoopMatmul.scala:61:24, :62:36] wire [15:0] max_blocks = _max_blocks_T ? max_col_dim : 16'h4; // @[LoopMatmul.scala:61:24, :62:{23,36}] wire [55:0] _dram_offset_T = {40'h0, row_iterator} * {16'h0, req_dram_stride}; // @[LoopMatmul.scala:47:16, :52:25, :66:35] wire [56:0] _dram_offset_T_1 = {1'h0, _dram_offset_T} + {41'h0, col_iterator}; // @[LoopMatmul.scala:53:25, :66:{35,53}] wire [55:0] _dram_offset_T_2 = _dram_offset_T_1[55:0]; // @[LoopMatmul.scala:66:53] wire [58:0] _dram_offset_T_3 = {1'h0, _dram_offset_T_2, 2'h0}; // @[LoopMatmul.scala:66:{53,69}] wire [61:0] dram_offset = {1'h0, _dram_offset_T_3, 2'h0}; // @[LoopMatmul.scala:66:{69,84}] wire [61:0] _dram_addr_T = {30'h0, dram_offset[31:0]}; // @[LoopMatmul.scala:66:84, :1139:17] wire [62:0] _dram_addr_T_1 = {23'h0, req_dram_addr} + {1'h0, _dram_addr_T}; // @[LoopMatmul.scala:47:16, :67:33, :1139:17] wire [61:0] dram_addr = _dram_addr_T_1[61:0]; // @[LoopMatmul.scala:67:33] wire [31:0] _sp_addr_T = {16'h0, row_iterator} * {16'h0, max_col_iterator}; // @[LoopMatmul.scala:52:25, :56:29, :68:47] wire [32:0] _sp_addr_T_1 = {1'h0, _sp_addr_T} + {17'h0, col_iterator}; // @[LoopMatmul.scala:53:25, :68:{47,66}] wire [31:0] _sp_addr_T_2 = _sp_addr_T_1[31:0]; // @[LoopMatmul.scala:68:66] wire [34:0] _sp_addr_T_3 = {1'h0, _sp_addr_T_2, 2'h0}; // @[LoopMatmul.scala:68:{66,82}] wire [35:0] _sp_addr_T_4 = {22'h0, req_addr_start} + {1'h0, _sp_addr_T_3}; // @[LoopMatmul.scala:47:16, :68:{31,82}] wire [34:0] sp_addr = _sp_addr_T_4[34:0]; // @[LoopMatmul.scala:68:31] wire [16:0] _GEN_0 = {1'h0, col_iterator}; // @[LoopMatmul.scala:53:25, :69:33] wire [16:0] _blocks_T = _GEN_0 + {1'h0, max_blocks}; // @[LoopMatmul.scala:62:23, :69:33] wire [15:0] _blocks_T_1 = _blocks_T[15:0]; // @[LoopMatmul.scala:69:33] wire _blocks_T_2 = _blocks_T_1 <= max_col_iterator; // @[LoopMatmul.scala:56:29, :69:{33,46}] wire [16:0] _blocks_T_3 = {1'h0, max_col_iterator} - _GEN_0; // @[LoopMatmul.scala:56:29, :69:{33,95}] wire [15:0] _blocks_T_4 = _blocks_T_3[15:0]; // @[LoopMatmul.scala:69:95] wire [15:0] blocks = _blocks_T_2 ? max_blocks : _blocks_T_4; // @[LoopMatmul.scala:62:23, :69:{19,46,95}] wire [18:0] _cols_T = {1'h0, blocks, 2'h0}; // @[LoopMatmul.scala:69:19, :70:22] wire [16:0] _cols_T_1 = _GEN_0 + {1'h0, blocks}; // @[LoopMatmul.scala:69:{19,33}, :70:57] wire [15:0] _cols_T_2 = _cols_T_1[15:0]; // @[LoopMatmul.scala:70:57] wire _cols_T_3 = _cols_T_2 >= max_col_iterator; // @[LoopMatmul.scala:56:29, :70:{57,66}] wire [1:0] _cols_T_4 = _cols_T_3 ? col_pad : 2'h0; // @[LoopMatmul.scala:59:20, :70:{43,66}] wire [19:0] _cols_T_5 = {1'h0, _cols_T} - {18'h0, _cols_T_4}; // @[LoopMatmul.scala:70:{22,38,43}] wire [18:0] cols = _cols_T_5[18:0]; // @[LoopMatmul.scala:70:38] wire [16:0] _rows_T = {1'h0, max_row_iterator} - 17'h1; // @[LoopMatmul.scala:55:29, :71:66] wire [15:0] _rows_T_1 = _rows_T[15:0]; // @[LoopMatmul.scala:71:66] wire _rows_T_2 = row_iterator == _rows_T_1; // @[LoopMatmul.scala:52:25, :71:{46,66}] wire [1:0] _rows_T_3 = _rows_T_2 ? row_pad : 2'h0; // @[LoopMatmul.scala:58:20, :71:{32,46}] wire [3:0] _rows_T_4 = 4'h4 - {2'h0, _rows_T_3}; // @[LoopMatmul.scala:71:{27,32}] wire [2:0] rows = _rows_T_4[2:0]; // @[LoopMatmul.scala:71:27] wire [2:0] mvin_cmd_rs2_num_rows = rows; // @[LoopMatmul.scala:71:27, :78:26] assign io_cmd_bits_rs1_0 = mvin_cmd_rs1; // @[LoopMatmul.scala:28:7, :73:22] wire [63:0] _mvin_cmd_rs2_T_2; // @[LoopMatmul.scala:83:32] assign io_cmd_bits_rs2_0 = mvin_cmd_rs2; // @[LoopMatmul.scala:28:7, :73:22] assign mvin_cmd_rs1 = {2'h0, dram_addr}; // @[LoopMatmul.scala:67:33, :73:22, :76:16] wire [4:0] mvin_cmd_rs2_lo_hi_1 = mvin_cmd_rs2_num_cols; // @[LoopMatmul.scala:78:26, :83:32] wire [2:0] _mvin_cmd_rs2_T = mvin_cmd_rs2_local_addr_norm_cmd; // @[LoopMatmul.scala:78:26, :83:32] wire mvin_cmd_rs2_local_addr_garbage_bit; // @[LoopMatmul.scala:78:26] wire [13:0] mvin_cmd_rs2_local_addr_data; // @[LoopMatmul.scala:78:26] assign mvin_cmd_rs2_num_cols = cols[4:0]; // @[LoopMatmul.scala:70:38, :78:26, :81:25] wire _mvin_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_accumulate = _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] mvin_cmd_rs2_local_addr_result_result_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] mvin_cmd_rs2_local_addr_result_result_data = _mvin_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}] wire [31:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_1 = sp_addr[31:0]; // @[LoopMatmul.scala:68:31] wire [31:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_5 = sp_addr[31:0]; // @[LoopMatmul.scala:68:31] assign _mvin_cmd_rs2_local_addr_result_result_T = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_data = _mvin_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_1 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_2 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_garbage = _mvin_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_T_3 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_2 = _mvin_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_3 = _mvin_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_4 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_5 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_accumulate = _mvin_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_6 = _mvin_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire [2:0] mvin_cmd_rs2_local_addr_result_norm_cmd = mvin_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :116:26] wire mvin_cmd_rs2_local_addr_result_garbage_bit = mvin_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :116:26] wire [13:0] mvin_cmd_rs2_local_addr_result_data = mvin_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :116:26] wire [11:0] mvin_cmd_rs2_lo_hi = {11'h0, mvin_cmd_rs2_local_addr_garbage_bit}; // @[LoopMatmul.scala:78:26, :83:32] wire [25:0] mvin_cmd_rs2_lo = {mvin_cmd_rs2_lo_hi, mvin_cmd_rs2_local_addr_data}; // @[LoopMatmul.scala:78:26, :83:32] wire [3:0] mvin_cmd_rs2_hi_lo = {1'h0, _mvin_cmd_rs2_T}; // @[LoopMatmul.scala:83:32] wire [1:0] mvin_cmd_rs2_hi_hi = {mvin_cmd_rs2_local_addr_is_acc_addr, 1'h0}; // @[LoopMatmul.scala:78:26, :83:32] wire [5:0] mvin_cmd_rs2_hi = {mvin_cmd_rs2_hi_hi, mvin_cmd_rs2_hi_lo}; // @[LoopMatmul.scala:83:32] wire [31:0] _mvin_cmd_rs2_T_1 = {mvin_cmd_rs2_hi, mvin_cmd_rs2_lo}; // @[LoopMatmul.scala:83:32] wire [36:0] mvin_cmd_rs2_lo_1 = {mvin_cmd_rs2_lo_hi_1, _mvin_cmd_rs2_T_1}; // @[LoopMatmul.scala:83:32] wire [15:0] mvin_cmd_rs2_hi_hi_1 = {13'h0, mvin_cmd_rs2_num_rows}; // @[LoopMatmul.scala:78:26, :83:32] wire [26:0] mvin_cmd_rs2_hi_1 = {mvin_cmd_rs2_hi_hi_1, 11'h0}; // @[LoopMatmul.scala:83:32] assign _mvin_cmd_rs2_T_2 = {mvin_cmd_rs2_hi_1, mvin_cmd_rs2_lo_1}; // @[LoopMatmul.scala:83:32] assign mvin_cmd_rs2 = _mvin_cmd_rs2_T_2; // @[LoopMatmul.scala:73:22, :83:32] wire _mvin_cmd_rs2_local_addr_result_result_T_13; // @[LocalAddr.scala:108:37] wire _mvin_cmd_rs2_local_addr_result_result_T_12; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_1_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_11; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_1_accumulate = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_7; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_1_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_T_9; // @[LocalAddr.scala:108:37] wire [2:0] mvin_cmd_rs2_local_addr_result_result_1_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _mvin_cmd_rs2_local_addr_result_result_T_8; // @[LocalAddr.scala:108:37] wire [13:0] _mvin_cmd_rs2_local_addr_result_result_T_7; // @[LocalAddr.scala:108:37] wire mvin_cmd_rs2_local_addr_result_result_1_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] mvin_cmd_rs2_local_addr_result_result_1_data = _mvin_cmd_rs2_local_addr_result_result_WIRE_4_data; // @[LocalAddr.scala:108:{26,37}] assign _mvin_cmd_rs2_local_addr_result_result_T_7 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[13:0]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_data = _mvin_cmd_rs2_local_addr_result_result_T_7; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_8 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[14]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_garbage_bit = _mvin_cmd_rs2_local_addr_result_result_T_8; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_9 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_4_garbage = _mvin_cmd_rs2_local_addr_result_result_T_9; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_T_10 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _mvin_cmd_rs2_local_addr_result_result_WIRE_6 = _mvin_cmd_rs2_local_addr_result_result_T_10; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_7 = _mvin_cmd_rs2_local_addr_result_result_WIRE_6; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_norm_cmd = _mvin_cmd_rs2_local_addr_result_result_WIRE_7; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_11 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[29]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_read_full_acc_row = _mvin_cmd_rs2_local_addr_result_result_T_11; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_12 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[30]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_accumulate = _mvin_cmd_rs2_local_addr_result_result_T_12; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_T_13 = _mvin_cmd_rs2_local_addr_result_result_WIRE_5[31]; // @[LocalAddr.scala:108:37] assign _mvin_cmd_rs2_local_addr_result_result_WIRE_4_is_acc_addr = _mvin_cmd_rs2_local_addr_result_result_T_13; // @[LocalAddr.scala:108:37] wire [2:0] mvin_cmd_rs2_local_addr_result_1_norm_cmd = mvin_cmd_rs2_local_addr_result_result_1_norm_cmd; // @[LocalAddr.scala:108:26, :129:26] wire mvin_cmd_rs2_local_addr_result_1_garbage_bit = mvin_cmd_rs2_local_addr_result_result_1_garbage_bit; // @[LocalAddr.scala:108:26, :129:26] wire [13:0] mvin_cmd_rs2_local_addr_result_1_data = mvin_cmd_rs2_local_addr_result_result_1_data; // @[LocalAddr.scala:108:26, :129:26] assign mvin_cmd_rs2_local_addr_norm_cmd = req_is_resadd ? mvin_cmd_rs2_local_addr_result_1_norm_cmd : mvin_cmd_rs2_local_addr_result_norm_cmd; // @[LoopMatmul.scala:47:16, :78:26, :82:27, :84:22, :85:29] assign mvin_cmd_rs2_local_addr_garbage_bit = req_is_resadd ? mvin_cmd_rs2_local_addr_result_1_garbage_bit : mvin_cmd_rs2_local_addr_result_garbage_bit; // @[LoopMatmul.scala:47:16, :78:26, :82:27, :84:22, :85:29] assign mvin_cmd_rs2_local_addr_data = req_is_resadd ? mvin_cmd_rs2_local_addr_result_1_data : mvin_cmd_rs2_local_addr_result_data; // @[LoopMatmul.scala:47:16, :78:26, :82:27, :84:22, :85:29] assign _io_req_ready_T = ~state; // @[LoopMatmul.scala:45:22, :88:25] assign io_req_ready_0 = _io_req_ready_T; // @[LoopMatmul.scala:28:7, :88:25] assign _io_idle_T = ~state; // @[LoopMatmul.scala:45:22, :88:25, :91:20] assign io_idle_0 = _io_idle_T; // @[LoopMatmul.scala:28:7, :91:20] wire _io_cmd_valid_T_1 = ~io_rob_overloaded_0; // @[LoopMatmul.scala:28:7, :93:37] wire _io_cmd_valid_T_2 = _io_cmd_valid_T & _io_cmd_valid_T_1; // @[LoopMatmul.scala:93:{25,34,37}] wire _io_cmd_valid_T_3 = |req_dram_addr; // @[LoopMatmul.scala:47:16, :93:73] assign _io_cmd_valid_T_4 = _io_cmd_valid_T_2 & _io_cmd_valid_T_3; // @[LoopMatmul.scala:93:{34,56,73}] assign io_cmd_valid_0 = _io_cmd_valid_T_4; // @[LoopMatmul.scala:28:7, :93:56] wire [15:0] i_blocks = req_transpose ? max_blocks : 16'h1; // @[LoopMatmul.scala:47:16, :62:23, :102:23] wire [15:0] k_blocks = req_transpose ? 16'h1 : max_blocks; // @[LoopMatmul.scala:47:16, :62:23, :103:23] wire [16:0] _next_i_max_T = {1'h0, req_max_i} - 17'h1; // @[Util.scala:39:28] wire [15:0] next_i_max = _next_i_max_T[15:0]; // @[Util.scala:39:28] wire [16:0] _GEN_1 = {1'h0, i} + {1'h0, i_blocks}; // @[Util.scala:41:15] wire [16:0] _next_i_T; // @[Util.scala:41:15] assign _next_i_T = _GEN_1; // @[Util.scala:41:15] wire [16:0] _next_i_T_3; // @[Util.scala:43:11] assign _next_i_T_3 = _GEN_1; // @[Util.scala:41:15, :43:11] wire [15:0] _next_i_T_1 = _next_i_T[15:0]; // @[Util.scala:41:15] wire _next_i_T_4 = _next_i_T_3 > {1'h0, next_i_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_i_T_5 = _next_i_T_4 ? 16'h0 : _next_i_T_1; // @[Mux.scala:126:16] wire [15:0] next_i = _next_i_T_5; // @[Mux.scala:126:16] wire _next_k_T = next_i == 16'h0; // @[Mux.scala:126:16] wire [16:0] _next_k_max_T = {1'h0, req_max_k} - 17'h1; // @[Util.scala:39:28] wire [15:0] next_k_max = _next_k_max_T[15:0]; // @[Util.scala:39:28] wire [16:0] _GEN_2 = {1'h0, k} + {1'h0, k_blocks}; // @[Util.scala:41:15] wire [16:0] _next_k_T_1; // @[Util.scala:41:15] assign _next_k_T_1 = _GEN_2; // @[Util.scala:41:15] wire [16:0] _next_k_T_4; // @[Util.scala:43:11] assign _next_k_T_4 = _GEN_2; // @[Util.scala:41:15, :43:11] wire [15:0] _next_k_T_2 = _next_k_T_1[15:0]; // @[Util.scala:41:15] wire _next_k_T_3 = ~_next_k_T; // @[Util.scala:42:8] wire _next_k_T_5 = _next_k_T_4 > {1'h0, next_k_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_k_T_6 = _next_k_T_5 ? 16'h0 : _next_k_T_2; // @[Mux.scala:126:16] wire [15:0] next_k = _next_k_T_3 ? k : _next_k_T_6; // @[Mux.scala:126:16] wire _T_1 = io_cmd_ready_0 & io_cmd_valid_0; // @[Decoupled.scala:51:35] wire _T_5 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[LoopMatmul.scala:28:7] if (reset) // @[LoopMatmul.scala:28:7] state <= 1'h0; // @[LoopMatmul.scala:45:22] else // @[LoopMatmul.scala:28:7] state <= _T_5 | ~(~(|req_dram_addr) | _T_1 & _next_k_T & next_k == 16'h0) & state; // @[Mux.scala:126:16] if (_T_5) begin // @[Decoupled.scala:51:35] req_max_i <= io_req_bits_max_i_0; // @[LoopMatmul.scala:28:7, :47:16] req_max_k <= io_req_bits_max_k_0; // @[LoopMatmul.scala:28:7, :47:16] req_pad_i <= io_req_bits_pad_i_0; // @[LoopMatmul.scala:28:7, :47:16] req_pad_k <= io_req_bits_pad_k_0; // @[LoopMatmul.scala:28:7, :47:16] req_dram_addr <= io_req_bits_dram_addr_0; // @[LoopMatmul.scala:28:7, :47:16] req_dram_stride <= io_req_bits_dram_stride_0; // @[LoopMatmul.scala:28:7, :47:16] req_transpose <= io_req_bits_transpose_0; // @[LoopMatmul.scala:28:7, :47:16] req_addr_start <= io_req_bits_addr_start_0; // @[LoopMatmul.scala:28:7, :47:16] req_loop_id <= io_req_bits_loop_id_0; // @[LoopMatmul.scala:28:7, :47:16] req_is_resadd <= io_req_bits_is_resadd_0; // @[LoopMatmul.scala:28:7, :47:16] i <= 16'h0; // @[LoopMatmul.scala:49:14] k <= 16'h0; // @[LoopMatmul.scala:50:14] end else if ((|req_dram_addr) & _T_1) begin // @[Decoupled.scala:51:35] i <= next_i; // @[Mux.scala:126:16] k <= next_k; // @[Mux.scala:126:16] end always @(posedge) assign io_req_ready = io_req_ready_0; // @[LoopMatmul.scala:28:7] assign io_cmd_valid = io_cmd_valid_0; // @[LoopMatmul.scala:28:7] assign io_cmd_bits_rs1 = io_cmd_bits_rs1_0; // @[LoopMatmul.scala:28:7] assign io_cmd_bits_rs2 = io_cmd_bits_rs2_0; // @[LoopMatmul.scala:28:7] assign io_i = io_i_0; // @[LoopMatmul.scala:28:7] assign io_k = io_k_0; // @[LoopMatmul.scala:28:7] assign io_idle = io_idle_0; // @[LoopMatmul.scala:28:7] assign io_loop_id = io_loop_id_0; // @[LoopMatmul.scala:28:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<7>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<7>(0h40)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<7>(0h40)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<7>(0h40)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)

module MSHR_5( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 7'h40; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 7'h40; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_54 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_54( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ReRoCCManagerControl_1 : input clock : Clock input reset : Reset output auto : { flip ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip mgr_busy : UInt<1>, flip rocc_busy : UInt<1>} wire ctrlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate ctrlNodeIn.d.bits.corrupt invalidate ctrlNodeIn.d.bits.data invalidate ctrlNodeIn.d.bits.denied invalidate ctrlNodeIn.d.bits.sink invalidate ctrlNodeIn.d.bits.source invalidate ctrlNodeIn.d.bits.size invalidate ctrlNodeIn.d.bits.param invalidate ctrlNodeIn.d.bits.opcode invalidate ctrlNodeIn.d.valid invalidate ctrlNodeIn.d.ready invalidate ctrlNodeIn.a.bits.corrupt invalidate ctrlNodeIn.a.bits.data invalidate ctrlNodeIn.a.bits.mask invalidate ctrlNodeIn.a.bits.address invalidate ctrlNodeIn.a.bits.source invalidate ctrlNodeIn.a.bits.size invalidate ctrlNodeIn.a.bits.param invalidate ctrlNodeIn.a.bits.opcode invalidate ctrlNodeIn.a.valid invalidate ctrlNodeIn.a.ready inst monitor of TLMonitor_78 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, ctrlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, ctrlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, ctrlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, ctrlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, ctrlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, ctrlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, ctrlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, ctrlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, ctrlNodeIn.d.valid connect monitor.io.in.d.ready, ctrlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, ctrlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, ctrlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, ctrlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, ctrlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, ctrlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, ctrlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, ctrlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, ctrlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, ctrlNodeIn.a.valid connect monitor.io.in.a.ready, ctrlNodeIn.a.ready connect ctrlNodeIn, auto.ctrl_in wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}} node _in_bits_read_T = eq(ctrlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(ctrlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, ctrlNodeIn.a.bits.data connect in.bits.mask, ctrlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, ctrlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, ctrlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}} connect out_front.bits, in.bits inst out_back_front_q of Queue1_RegMapperInput_i9_m8_2 connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front node out_maskMatch = not(UInt<9>(0h1)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[2] wire out_wivalid : UInt<1>[2] wire out_roready : UInt<1>[2] wire out_woready : UInt<1>[2] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_4 = bits(out_back_front_q.io.deq.bits.data, 7, 0) node _out_T_5 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_6 = and(UInt<1>(0h1), out_f_roready) node _out_T_7 = eq(out_rimask, UInt<1>(0h0)) node _out_T_8 = eq(out_wimask, UInt<1>(0h0)) node _out_T_9 = eq(out_romask, UInt<1>(0h0)) node _out_T_10 = eq(out_womask, UInt<1>(0h0)) node _out_T_11 = or(io.mgr_busy, UInt<8>(0h0)) node _out_T_12 = bits(_out_T_11, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 7, 0) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 7, 0) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 7, 0) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 7, 0) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_13 = bits(out_back_front_q.io.deq.bits.data, 7, 0) node _out_T_14 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_15 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_16 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_17 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_18 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_19 = eq(out_womask_1, UInt<1>(0h0)) node _out_T_20 = or(io.rocc_busy, UInt<8>(0h0)) node _out_T_21 = bits(_out_T_20, 7, 0) node out_iindex = bits(out_front.bits.index, 0, 0) node _out_iindex_T = bits(out_front.bits.index, 1, 1) node _out_iindex_T_1 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_2 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_3 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_4 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_5 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_6 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_7 = bits(out_front.bits.index, 8, 8) node out_oindex = bits(out_back_front_q.io.deq.bits.index, 0, 0) node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 1, 1) node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 2, 2) node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 3, 3) node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 4, 4) node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 5, 5) node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 6, 6) node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 7, 7) node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 8, 8) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) node _out_rifireMux_T_10 = geq(out_iindex, UInt<2>(0h2)) wire _out_rifireMux_WIRE : UInt<1>[2] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 node out_rifireMux = mux(_out_rifireMux_T_10, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) node _out_wifireMux_T_11 = geq(out_iindex, UInt<2>(0h2)) wire _out_wifireMux_WIRE : UInt<1>[2] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 node out_wifireMux = mux(_out_wifireMux_T_11, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) node _out_rofireMux_T_10 = geq(out_oindex, UInt<2>(0h2)) wire _out_rofireMux_WIRE : UInt<1>[2] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 node out_rofireMux = mux(_out_rofireMux_T_10, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) node _out_wofireMux_T_11 = geq(out_oindex, UInt<2>(0h2)) wire _out_wofireMux_WIRE : UInt<1>[2] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 node out_wofireMux = mux(_out_wofireMux_T_11, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_back_front_q.io.deq.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE : UInt<1>[2] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE_1 : UInt<8>[2] connect _out_out_bits_data_WIRE_1[0], _out_T_12 connect _out_out_bits_data_WIRE_1[1], _out_T_21 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_back_front_q.io.deq.bits.extra connect in.valid, ctrlNodeIn.a.valid connect ctrlNodeIn.a.ready, in.ready connect ctrlNodeIn.d.valid, out.valid connect out.ready, ctrlNodeIn.d.ready wire ctrlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect ctrlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect ctrlNodeIn_d_bits_d.param, UInt<1>(0h0) connect ctrlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect ctrlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect ctrlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect ctrlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate ctrlNodeIn_d_bits_d.data connect ctrlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect ctrlNodeIn.d.bits.corrupt, ctrlNodeIn_d_bits_d.corrupt connect ctrlNodeIn.d.bits.data, ctrlNodeIn_d_bits_d.data connect ctrlNodeIn.d.bits.denied, ctrlNodeIn_d_bits_d.denied connect ctrlNodeIn.d.bits.sink, ctrlNodeIn_d_bits_d.sink connect ctrlNodeIn.d.bits.source, ctrlNodeIn_d_bits_d.source connect ctrlNodeIn.d.bits.size, ctrlNodeIn_d_bits_d.size connect ctrlNodeIn.d.bits.param, ctrlNodeIn_d_bits_d.param connect ctrlNodeIn.d.bits.opcode, ctrlNodeIn_d_bits_d.opcode connect ctrlNodeIn.d.bits.data, out.bits.data node _ctrlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect ctrlNodeIn.d.bits.opcode, _ctrlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)

module ReRoCCManagerControl_1( // @[Control.scala:49:9] input clock, // @[Control.scala:49:9] input reset, // @[Control.scala:49:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_mgr_busy, // @[Control.scala:50:16] input io_rocc_busy // @[Control.scala:50:16] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [6:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:49:9] wire [6:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:49:9] wire [11:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:49:9] wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:49:9] wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:49:9] wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:49:9] wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:49:9] wire io_mgr_busy_0 = io_mgr_busy; // @[Control.scala:49:9] wire io_rocc_busy_0 = io_rocc_busy; // @[Control.scala:49:9] wire [8:0] out_maskMatch = 9'h1FE; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] ctrlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] ctrlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:49:9] wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:49:9] wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:49:9] wire ctrlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire ctrlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire ctrlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_10 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_11 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_10 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_11 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire ctrlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire ctrlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire ctrlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:49:9] wire ctrlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] ctrlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] ctrlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire ctrlNodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:49:9] wire [6:0] ctrlNodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:49:9] wire [11:0] ctrlNodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:49:9] wire [7:0] ctrlNodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:49:9] wire [63:0] ctrlNodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:49:9] wire ctrlNodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:49:9] wire ctrlNodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:49:9] wire ctrlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] ctrlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] ctrlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] ctrlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] ctrlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_ctrl_in_a_ready_0; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:49:9] wire [6:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:49:9] wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:49:9] wire auto_ctrl_in_d_valid_0; // @[Control.scala:49:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_ctrl_in_a_ready_0 = ctrlNodeIn_a_ready; // @[Control.scala:49:9] wire in_valid = ctrlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [2:0] in_bits_extra_tlrr_extra_size = ctrlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [6:0] in_bits_extra_tlrr_extra_source = ctrlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = ctrlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = ctrlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = ctrlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_valid_0 = ctrlNodeIn_d_valid; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_opcode_0 = ctrlNodeIn_d_bits_opcode; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_size_0 = ctrlNodeIn_d_bits_size; // @[Control.scala:49:9] wire [6:0] ctrlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_source_0 = ctrlNodeIn_d_bits_source; // @[Control.scala:49:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_bits_data_0 = ctrlNodeIn_d_bits_data; // @[Control.scala:49:9] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] _in_bits_index_T; // @[Edges.scala:192:34] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [2:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = ctrlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T = ctrlNodeIn_a_bits_address[11:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T; // @[RegisterRouter.scala:73:18] wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _ctrlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign ctrlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [2:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index & 9'h1FE; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1FE; // @[RegisterRouter.scala:87:24] wire _GEN = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_13 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_7 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11 = {7'h0, io_mgr_busy_0}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12 = _out_T_11; // @[RegisterRouter.scala:87:24] wire [7:0] _out_out_bits_data_WIRE_1_0 = _out_T_12; // @[MuxLiteral.scala:49:48] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_14 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_15 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_16 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_20 = {7'h0, io_rocc_busy_0}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_21 = _out_T_20; // @[RegisterRouter.scala:87:24] wire [7:0] _out_out_bits_data_WIRE_1_1 = _out_T_21; // @[MuxLiteral.scala:49:48] wire out_iindex = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire out_oindex = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_frontSel_T = 2'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire _GEN_1 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _GEN_2 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = out_oindex ? _out_out_bits_data_WIRE_1 : _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire [7:0] _out_out_bits_data_T_3 = out_oindex ? _out_out_bits_data_WIRE_1_1 : _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] wire [7:0] _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 8'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = {56'h0, _out_out_bits_data_T_4}; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_bits_size = ctrlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign ctrlNodeIn_d_bits_source = ctrlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign ctrlNodeIn_d_bits_opcode = {2'h0, _ctrlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_78 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (ctrlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (ctrlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (ctrlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (ctrlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (ctrlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (ctrlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (ctrlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (ctrlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (ctrlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (ctrlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (ctrlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (ctrlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (ctrlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (ctrlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (ctrlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (ctrlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_RegMapperInput_i9_m8_2 out_back_front_q ( // @[RegisterRouter.scala:87:24] .clock (clock), .reset (reset), .io_enq_ready (out_front_ready), .io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24] .io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24] .io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24] .io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24] .io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24] .io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24] .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source), .io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size) ); // @[RegisterRouter.scala:87:24] assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:49:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_253 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_270 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_253( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_270 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) wire _source_ok_WIRE : UInt<1>[5] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 node _source_ok_T_25 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_26 = or(_source_ok_T_25, _source_ok_WIRE[2]) node _source_ok_T_27 = or(_source_ok_T_26, _source_ok_WIRE[3]) node source_ok = or(_source_ok_T_27, _source_ok_WIRE[4]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = and(_T_11, _T_24) node _T_65 = and(_T_64, _T_37) node _T_66 = and(_T_65, _T_50) node _T_67 = and(_T_66, _T_63) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_67, UInt<1>(0h1), "") : assert_1 node _T_71 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_71 : node _T_72 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_73 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_76 = shr(io.in.a.bits.source, 2) node _T_77 = eq(_T_76, UInt<1>(0h0)) node _T_78 = leq(UInt<1>(0h0), uncommonBits_4) node _T_79 = and(_T_77, _T_78) node _T_80 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_81 = and(_T_79, _T_80) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_82 = shr(io.in.a.bits.source, 2) node _T_83 = eq(_T_82, UInt<1>(0h1)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_5) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_87 = and(_T_85, _T_86) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_88 = shr(io.in.a.bits.source, 2) node _T_89 = eq(_T_88, UInt<2>(0h2)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_6) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_93 = and(_T_91, _T_92) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_94 = shr(io.in.a.bits.source, 2) node _T_95 = eq(_T_94, UInt<2>(0h3)) node _T_96 = leq(UInt<1>(0h0), uncommonBits_7) node _T_97 = and(_T_95, _T_96) node _T_98 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(_T_75, _T_81) node _T_101 = or(_T_100, _T_87) node _T_102 = or(_T_101, _T_93) node _T_103 = or(_T_102, _T_99) node _T_104 = and(_T_74, _T_103) node _T_105 = or(UInt<1>(0h0), _T_104) node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<13>(0h1000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<18>(0h2f000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<13>(0h1000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<27>(0h4000000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<13>(0h1000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = or(_T_111, _T_116) node _T_148 = or(_T_147, _T_121) node _T_149 = or(_T_148, _T_126) node _T_150 = or(_T_149, _T_131) node _T_151 = or(_T_150, _T_136) node _T_152 = or(_T_151, _T_141) node _T_153 = or(_T_152, _T_146) node _T_154 = and(_T_106, _T_153) node _T_155 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_156 = or(UInt<1>(0h0), _T_155) node _T_157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<29>(0h10000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = and(_T_156, _T_167) node _T_169 = or(UInt<1>(0h0), _T_154) node _T_170 = or(_T_169, _T_168) node _T_171 = and(_T_105, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_171, UInt<1>(0h1), "") : assert_2 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<14>(0h2000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<13>(0h1000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<17>(0h10000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<18>(0h2f000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<13>(0h1000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<17>(0h10000))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<27>(0h4000000))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_220 = cvt(_T_219) node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000))) node _T_222 = asSInt(_T_221) node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0))) node _T_224 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_225 = cvt(_T_224) node _T_226 = and(_T_225, asSInt(UInt<29>(0h10000000))) node _T_227 = asSInt(_T_226) node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = or(_T_183, _T_188) node _T_230 = or(_T_229, _T_193) node _T_231 = or(_T_230, _T_198) node _T_232 = or(_T_231, _T_203) node _T_233 = or(_T_232, _T_208) node _T_234 = or(_T_233, _T_213) node _T_235 = or(_T_234, _T_218) node _T_236 = or(_T_235, _T_223) node _T_237 = or(_T_236, _T_228) node _T_238 = and(_T_178, _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = and(UInt<1>(0h0), _T_239) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_240, UInt<1>(0h1), "") : assert_3 node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(source_ok, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_247 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_247, UInt<1>(0h1), "") : assert_5 node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(is_aligned, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_254 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_254, UInt<1>(0h1), "") : assert_7 node _T_258 = not(io.in.a.bits.mask) node _T_259 = eq(_T_258, UInt<1>(0h0)) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_259, UInt<1>(0h1), "") : assert_8 node _T_263 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_263, UInt<1>(0h1), "") : assert_9 node _T_267 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_267 : node _T_268 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_269 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_8) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h1)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_9) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h2)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_10) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h3)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_11) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _T_296 = or(_T_271, _T_277) node _T_297 = or(_T_296, _T_283) node _T_298 = or(_T_297, _T_289) node _T_299 = or(_T_298, _T_295) node _T_300 = and(_T_270, _T_299) node _T_301 = or(UInt<1>(0h0), _T_300) node _T_302 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_303 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<14>(0h2000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<17>(0h10000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<18>(0h2f000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<27>(0h4000000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_307, _T_312) node _T_344 = or(_T_343, _T_317) node _T_345 = or(_T_344, _T_322) node _T_346 = or(_T_345, _T_327) node _T_347 = or(_T_346, _T_332) node _T_348 = or(_T_347, _T_337) node _T_349 = or(_T_348, _T_342) node _T_350 = and(_T_302, _T_349) node _T_351 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_359 = cvt(_T_358) node _T_360 = and(_T_359, asSInt(UInt<29>(0h10000000))) node _T_361 = asSInt(_T_360) node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) node _T_363 = or(_T_357, _T_362) node _T_364 = and(_T_352, _T_363) node _T_365 = or(UInt<1>(0h0), _T_350) node _T_366 = or(_T_365, _T_364) node _T_367 = and(_T_301, _T_366) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_367, UInt<1>(0h1), "") : assert_10 node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<14>(0h2000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_386 = cvt(_T_385) node _T_387 = and(_T_386, asSInt(UInt<17>(0h10000))) node _T_388 = asSInt(_T_387) node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0))) node _T_390 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_391 = cvt(_T_390) node _T_392 = and(_T_391, asSInt(UInt<18>(0h2f000))) node _T_393 = asSInt(_T_392) node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0))) node _T_395 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<17>(0h10000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<17>(0h10000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_411 = cvt(_T_410) node _T_412 = and(_T_411, asSInt(UInt<27>(0h4000000))) node _T_413 = asSInt(_T_412) node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0))) node _T_415 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_416 = cvt(_T_415) node _T_417 = and(_T_416, asSInt(UInt<13>(0h1000))) node _T_418 = asSInt(_T_417) node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0))) node _T_420 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_421 = cvt(_T_420) node _T_422 = and(_T_421, asSInt(UInt<29>(0h10000000))) node _T_423 = asSInt(_T_422) node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0))) node _T_425 = or(_T_379, _T_384) node _T_426 = or(_T_425, _T_389) node _T_427 = or(_T_426, _T_394) node _T_428 = or(_T_427, _T_399) node _T_429 = or(_T_428, _T_404) node _T_430 = or(_T_429, _T_409) node _T_431 = or(_T_430, _T_414) node _T_432 = or(_T_431, _T_419) node _T_433 = or(_T_432, _T_424) node _T_434 = and(_T_374, _T_433) node _T_435 = or(UInt<1>(0h0), _T_434) node _T_436 = and(UInt<1>(0h0), _T_435) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_436, UInt<1>(0h1), "") : assert_11 node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(source_ok, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_443 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_443, UInt<1>(0h1), "") : assert_13 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(is_aligned, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_450 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_450, UInt<1>(0h1), "") : assert_15 node _T_454 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_454, UInt<1>(0h1), "") : assert_16 node _T_458 = not(io.in.a.bits.mask) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_459, UInt<1>(0h1), "") : assert_17 node _T_463 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_463, UInt<1>(0h1), "") : assert_18 node _T_467 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_467 : node _T_468 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_469 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_470 = and(_T_468, _T_469) node _T_471 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_472 = shr(io.in.a.bits.source, 2) node _T_473 = eq(_T_472, UInt<1>(0h0)) node _T_474 = leq(UInt<1>(0h0), uncommonBits_12) node _T_475 = and(_T_473, _T_474) node _T_476 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_477 = and(_T_475, _T_476) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_478 = shr(io.in.a.bits.source, 2) node _T_479 = eq(_T_478, UInt<1>(0h1)) node _T_480 = leq(UInt<1>(0h0), uncommonBits_13) node _T_481 = and(_T_479, _T_480) node _T_482 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_483 = and(_T_481, _T_482) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<2>(0h2)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_14) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<2>(0h3)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_15) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(_T_471, _T_477) node _T_497 = or(_T_496, _T_483) node _T_498 = or(_T_497, _T_489) node _T_499 = or(_T_498, _T_495) node _T_500 = and(_T_470, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_501, UInt<1>(0h1), "") : assert_19 node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = or(UInt<1>(0h0), _T_507) node _T_509 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<13>(0h1000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = and(_T_508, _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<14>(0h2000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<17>(0h10000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<18>(0h2f000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<17>(0h10000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<17>(0h10000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<27>(0h4000000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<29>(0h10000000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = or(_T_523, _T_528) node _T_565 = or(_T_564, _T_533) node _T_566 = or(_T_565, _T_538) node _T_567 = or(_T_566, _T_543) node _T_568 = or(_T_567, _T_548) node _T_569 = or(_T_568, _T_553) node _T_570 = or(_T_569, _T_558) node _T_571 = or(_T_570, _T_563) node _T_572 = and(_T_518, _T_571) node _T_573 = or(UInt<1>(0h0), _T_514) node _T_574 = or(_T_573, _T_572) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_574, UInt<1>(0h1), "") : assert_20 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(source_ok, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(is_aligned, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_584 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_584, UInt<1>(0h1), "") : assert_23 node _T_588 = eq(io.in.a.bits.mask, mask) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_588, UInt<1>(0h1), "") : assert_24 node _T_592 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_593 = asUInt(reset) node _T_594 = eq(_T_593, UInt<1>(0h0)) when _T_594 : node _T_595 = eq(_T_592, UInt<1>(0h0)) when _T_595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_592, UInt<1>(0h1), "") : assert_25 node _T_596 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_596 : node _T_597 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_598 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_601 = shr(io.in.a.bits.source, 2) node _T_602 = eq(_T_601, UInt<1>(0h0)) node _T_603 = leq(UInt<1>(0h0), uncommonBits_16) node _T_604 = and(_T_602, _T_603) node _T_605 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_606 = and(_T_604, _T_605) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_607 = shr(io.in.a.bits.source, 2) node _T_608 = eq(_T_607, UInt<1>(0h1)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_17) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_613 = shr(io.in.a.bits.source, 2) node _T_614 = eq(_T_613, UInt<2>(0h2)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_18) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_619 = shr(io.in.a.bits.source, 2) node _T_620 = eq(_T_619, UInt<2>(0h3)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_19) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_624 = and(_T_622, _T_623) node _T_625 = or(_T_600, _T_606) node _T_626 = or(_T_625, _T_612) node _T_627 = or(_T_626, _T_618) node _T_628 = or(_T_627, _T_624) node _T_629 = and(_T_599, _T_628) node _T_630 = or(UInt<1>(0h0), _T_629) node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = and(_T_634, _T_639) node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_643 = and(_T_641, _T_642) node _T_644 = or(UInt<1>(0h0), _T_643) node _T_645 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<14>(0h2000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<18>(0h2f000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<17>(0h10000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<27>(0h4000000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<13>(0h1000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<29>(0h10000000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = or(_T_649, _T_654) node _T_686 = or(_T_685, _T_659) node _T_687 = or(_T_686, _T_664) node _T_688 = or(_T_687, _T_669) node _T_689 = or(_T_688, _T_674) node _T_690 = or(_T_689, _T_679) node _T_691 = or(_T_690, _T_684) node _T_692 = and(_T_644, _T_691) node _T_693 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<17>(0h10000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = and(_T_693, _T_698) node _T_700 = or(UInt<1>(0h0), _T_640) node _T_701 = or(_T_700, _T_692) node _T_702 = or(_T_701, _T_699) node _T_703 = and(_T_630, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_703, UInt<1>(0h1), "") : assert_26 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_713 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_713, UInt<1>(0h1), "") : assert_29 node _T_717 = eq(io.in.a.bits.mask, mask) node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(_T_717, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_717, UInt<1>(0h1), "") : assert_30 node _T_721 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_721 : node _T_722 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_723 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_726 = shr(io.in.a.bits.source, 2) node _T_727 = eq(_T_726, UInt<1>(0h0)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_20) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_731 = and(_T_729, _T_730) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_732 = shr(io.in.a.bits.source, 2) node _T_733 = eq(_T_732, UInt<1>(0h1)) node _T_734 = leq(UInt<1>(0h0), uncommonBits_21) node _T_735 = and(_T_733, _T_734) node _T_736 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_737 = and(_T_735, _T_736) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_738 = shr(io.in.a.bits.source, 2) node _T_739 = eq(_T_738, UInt<2>(0h2)) node _T_740 = leq(UInt<1>(0h0), uncommonBits_22) node _T_741 = and(_T_739, _T_740) node _T_742 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_743 = and(_T_741, _T_742) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_744 = shr(io.in.a.bits.source, 2) node _T_745 = eq(_T_744, UInt<2>(0h3)) node _T_746 = leq(UInt<1>(0h0), uncommonBits_23) node _T_747 = and(_T_745, _T_746) node _T_748 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(_T_725, _T_731) node _T_751 = or(_T_750, _T_737) node _T_752 = or(_T_751, _T_743) node _T_753 = or(_T_752, _T_749) node _T_754 = and(_T_724, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = and(_T_759, _T_764) node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_768 = and(_T_766, _T_767) node _T_769 = or(UInt<1>(0h0), _T_768) node _T_770 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<14>(0h2000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<18>(0h2f000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<13>(0h1000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<27>(0h4000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<29>(0h10000000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = or(_T_774, _T_779) node _T_811 = or(_T_810, _T_784) node _T_812 = or(_T_811, _T_789) node _T_813 = or(_T_812, _T_794) node _T_814 = or(_T_813, _T_799) node _T_815 = or(_T_814, _T_804) node _T_816 = or(_T_815, _T_809) node _T_817 = and(_T_769, _T_816) node _T_818 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_819 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<17>(0h10000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = and(_T_818, _T_823) node _T_825 = or(UInt<1>(0h0), _T_765) node _T_826 = or(_T_825, _T_817) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_828, UInt<1>(0h1), "") : assert_31 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(source_ok, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_838 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_838, UInt<1>(0h1), "") : assert_34 node _T_842 = not(mask) node _T_843 = and(io.in.a.bits.mask, _T_842) node _T_844 = eq(_T_843, UInt<1>(0h0)) node _T_845 = asUInt(reset) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(_T_844, UInt<1>(0h0)) when _T_847 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_844, UInt<1>(0h1), "") : assert_35 node _T_848 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_848 : node _T_849 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_850 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_851 = and(_T_849, _T_850) node _T_852 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h0)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_24) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<1>(0h1)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_25) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_865 = shr(io.in.a.bits.source, 2) node _T_866 = eq(_T_865, UInt<2>(0h2)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_26) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_870 = and(_T_868, _T_869) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_871 = shr(io.in.a.bits.source, 2) node _T_872 = eq(_T_871, UInt<2>(0h3)) node _T_873 = leq(UInt<1>(0h0), uncommonBits_27) node _T_874 = and(_T_872, _T_873) node _T_875 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_876 = and(_T_874, _T_875) node _T_877 = or(_T_852, _T_858) node _T_878 = or(_T_877, _T_864) node _T_879 = or(_T_878, _T_870) node _T_880 = or(_T_879, _T_876) node _T_881 = and(_T_851, _T_880) node _T_882 = or(UInt<1>(0h0), _T_881) node _T_883 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_884 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _T_886 = or(UInt<1>(0h0), _T_885) node _T_887 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_888 = cvt(_T_887) node _T_889 = and(_T_888, asSInt(UInt<14>(0h2000))) node _T_890 = asSInt(_T_889) node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0))) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<18>(0h2f000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<17>(0h10000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_908 = cvt(_T_907) node _T_909 = and(_T_908, asSInt(UInt<13>(0h1000))) node _T_910 = asSInt(_T_909) node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0))) node _T_912 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_913 = cvt(_T_912) node _T_914 = and(_T_913, asSInt(UInt<27>(0h4000000))) node _T_915 = asSInt(_T_914) node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0))) node _T_917 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = or(_T_891, _T_896) node _T_923 = or(_T_922, _T_901) node _T_924 = or(_T_923, _T_906) node _T_925 = or(_T_924, _T_911) node _T_926 = or(_T_925, _T_916) node _T_927 = or(_T_926, _T_921) node _T_928 = and(_T_886, _T_927) node _T_929 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_930 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_931 = cvt(_T_930) node _T_932 = and(_T_931, asSInt(UInt<17>(0h10000))) node _T_933 = asSInt(_T_932) node _T_934 = eq(_T_933, asSInt(UInt<1>(0h0))) node _T_935 = and(_T_929, _T_934) node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_938 = and(_T_936, _T_937) node _T_939 = or(UInt<1>(0h0), _T_938) node _T_940 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_941 = cvt(_T_940) node _T_942 = and(_T_941, asSInt(UInt<17>(0h10000))) node _T_943 = asSInt(_T_942) node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0))) node _T_945 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<29>(0h10000000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = or(_T_944, _T_949) node _T_951 = and(_T_939, _T_950) node _T_952 = or(UInt<1>(0h0), _T_928) node _T_953 = or(_T_952, _T_935) node _T_954 = or(_T_953, _T_951) node _T_955 = and(_T_882, _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_955, UInt<1>(0h1), "") : assert_36 node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(source_ok, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(is_aligned, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_965 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_965, UInt<1>(0h1), "") : assert_39 node _T_969 = eq(io.in.a.bits.mask, mask) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_969, UInt<1>(0h1), "") : assert_40 node _T_973 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_973 : node _T_974 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_975 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_976 = and(_T_974, _T_975) node _T_977 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_978 = shr(io.in.a.bits.source, 2) node _T_979 = eq(_T_978, UInt<1>(0h0)) node _T_980 = leq(UInt<1>(0h0), uncommonBits_28) node _T_981 = and(_T_979, _T_980) node _T_982 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_983 = and(_T_981, _T_982) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_984 = shr(io.in.a.bits.source, 2) node _T_985 = eq(_T_984, UInt<1>(0h1)) node _T_986 = leq(UInt<1>(0h0), uncommonBits_29) node _T_987 = and(_T_985, _T_986) node _T_988 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_989 = and(_T_987, _T_988) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_990 = shr(io.in.a.bits.source, 2) node _T_991 = eq(_T_990, UInt<2>(0h2)) node _T_992 = leq(UInt<1>(0h0), uncommonBits_30) node _T_993 = and(_T_991, _T_992) node _T_994 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_995 = and(_T_993, _T_994) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<2>(0h3)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_31) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _T_1002 = or(_T_977, _T_983) node _T_1003 = or(_T_1002, _T_989) node _T_1004 = or(_T_1003, _T_995) node _T_1005 = or(_T_1004, _T_1001) node _T_1006 = and(_T_976, _T_1005) node _T_1007 = or(UInt<1>(0h0), _T_1006) node _T_1008 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1009 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1010 = and(_T_1008, _T_1009) node _T_1011 = or(UInt<1>(0h0), _T_1010) node _T_1012 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<14>(0h2000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1023 = cvt(_T_1022) node _T_1024 = and(_T_1023, asSInt(UInt<18>(0h2f000))) node _T_1025 = asSInt(_T_1024) node _T_1026 = eq(_T_1025, asSInt(UInt<1>(0h0))) node _T_1027 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1028 = cvt(_T_1027) node _T_1029 = and(_T_1028, asSInt(UInt<17>(0h10000))) node _T_1030 = asSInt(_T_1029) node _T_1031 = eq(_T_1030, asSInt(UInt<1>(0h0))) node _T_1032 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1033 = cvt(_T_1032) node _T_1034 = and(_T_1033, asSInt(UInt<13>(0h1000))) node _T_1035 = asSInt(_T_1034) node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0))) node _T_1037 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1038 = cvt(_T_1037) node _T_1039 = and(_T_1038, asSInt(UInt<27>(0h4000000))) node _T_1040 = asSInt(_T_1039) node _T_1041 = eq(_T_1040, asSInt(UInt<1>(0h0))) node _T_1042 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1043 = cvt(_T_1042) node _T_1044 = and(_T_1043, asSInt(UInt<13>(0h1000))) node _T_1045 = asSInt(_T_1044) node _T_1046 = eq(_T_1045, asSInt(UInt<1>(0h0))) node _T_1047 = or(_T_1016, _T_1021) node _T_1048 = or(_T_1047, _T_1026) node _T_1049 = or(_T_1048, _T_1031) node _T_1050 = or(_T_1049, _T_1036) node _T_1051 = or(_T_1050, _T_1041) node _T_1052 = or(_T_1051, _T_1046) node _T_1053 = and(_T_1011, _T_1052) node _T_1054 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1055 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1056 = cvt(_T_1055) node _T_1057 = and(_T_1056, asSInt(UInt<17>(0h10000))) node _T_1058 = asSInt(_T_1057) node _T_1059 = eq(_T_1058, asSInt(UInt<1>(0h0))) node _T_1060 = and(_T_1054, _T_1059) node _T_1061 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1062 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = or(UInt<1>(0h0), _T_1063) node _T_1065 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1066 = cvt(_T_1065) node _T_1067 = and(_T_1066, asSInt(UInt<17>(0h10000))) node _T_1068 = asSInt(_T_1067) node _T_1069 = eq(_T_1068, asSInt(UInt<1>(0h0))) node _T_1070 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1071 = cvt(_T_1070) node _T_1072 = and(_T_1071, asSInt(UInt<29>(0h10000000))) node _T_1073 = asSInt(_T_1072) node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0))) node _T_1075 = or(_T_1069, _T_1074) node _T_1076 = and(_T_1064, _T_1075) node _T_1077 = or(UInt<1>(0h0), _T_1053) node _T_1078 = or(_T_1077, _T_1060) node _T_1079 = or(_T_1078, _T_1076) node _T_1080 = and(_T_1007, _T_1079) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_41 node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(source_ok, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(is_aligned, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1090 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_44 node _T_1094 = eq(io.in.a.bits.mask, mask) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_45 node _T_1098 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1098 : node _T_1099 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1101 = and(_T_1099, _T_1100) node _T_1102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1103 = shr(io.in.a.bits.source, 2) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) node _T_1105 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1108 = and(_T_1106, _T_1107) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1109 = shr(io.in.a.bits.source, 2) node _T_1110 = eq(_T_1109, UInt<1>(0h1)) node _T_1111 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1112 = and(_T_1110, _T_1111) node _T_1113 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1114 = and(_T_1112, _T_1113) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1115 = shr(io.in.a.bits.source, 2) node _T_1116 = eq(_T_1115, UInt<2>(0h2)) node _T_1117 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1120 = and(_T_1118, _T_1119) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1121 = shr(io.in.a.bits.source, 2) node _T_1122 = eq(_T_1121, UInt<2>(0h3)) node _T_1123 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1124 = and(_T_1122, _T_1123) node _T_1125 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1126 = and(_T_1124, _T_1125) node _T_1127 = or(_T_1102, _T_1108) node _T_1128 = or(_T_1127, _T_1114) node _T_1129 = or(_T_1128, _T_1120) node _T_1130 = or(_T_1129, _T_1126) node _T_1131 = and(_T_1101, _T_1130) node _T_1132 = or(UInt<1>(0h0), _T_1131) node _T_1133 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1134 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1135 = and(_T_1133, _T_1134) node _T_1136 = or(UInt<1>(0h0), _T_1135) node _T_1137 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<13>(0h1000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = and(_T_1136, _T_1141) node _T_1143 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1144 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<14>(0h2000))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1150 = cvt(_T_1149) node _T_1151 = and(_T_1150, asSInt(UInt<17>(0h10000))) node _T_1152 = asSInt(_T_1151) node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0))) node _T_1154 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1155 = cvt(_T_1154) node _T_1156 = and(_T_1155, asSInt(UInt<18>(0h2f000))) node _T_1157 = asSInt(_T_1156) node _T_1158 = eq(_T_1157, asSInt(UInt<1>(0h0))) node _T_1159 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1160 = cvt(_T_1159) node _T_1161 = and(_T_1160, asSInt(UInt<17>(0h10000))) node _T_1162 = asSInt(_T_1161) node _T_1163 = eq(_T_1162, asSInt(UInt<1>(0h0))) node _T_1164 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1165 = cvt(_T_1164) node _T_1166 = and(_T_1165, asSInt(UInt<13>(0h1000))) node _T_1167 = asSInt(_T_1166) node _T_1168 = eq(_T_1167, asSInt(UInt<1>(0h0))) node _T_1169 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1170 = cvt(_T_1169) node _T_1171 = and(_T_1170, asSInt(UInt<27>(0h4000000))) node _T_1172 = asSInt(_T_1171) node _T_1173 = eq(_T_1172, asSInt(UInt<1>(0h0))) node _T_1174 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1175 = cvt(_T_1174) node _T_1176 = and(_T_1175, asSInt(UInt<13>(0h1000))) node _T_1177 = asSInt(_T_1176) node _T_1178 = eq(_T_1177, asSInt(UInt<1>(0h0))) node _T_1179 = or(_T_1148, _T_1153) node _T_1180 = or(_T_1179, _T_1158) node _T_1181 = or(_T_1180, _T_1163) node _T_1182 = or(_T_1181, _T_1168) node _T_1183 = or(_T_1182, _T_1173) node _T_1184 = or(_T_1183, _T_1178) node _T_1185 = and(_T_1143, _T_1184) node _T_1186 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1187 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = or(UInt<1>(0h0), _T_1188) node _T_1190 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<17>(0h10000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<29>(0h10000000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = or(_T_1194, _T_1199) node _T_1201 = and(_T_1189, _T_1200) node _T_1202 = or(UInt<1>(0h0), _T_1142) node _T_1203 = or(_T_1202, _T_1185) node _T_1204 = or(_T_1203, _T_1201) node _T_1205 = and(_T_1132, _T_1204) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_46 node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(source_ok, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(is_aligned, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1215 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_49 node _T_1219 = eq(io.in.a.bits.mask, mask) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_50 node _T_1223 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1227 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_52 node _source_ok_T_28 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_29 = shr(io.in.d.bits.source, 2) node _source_ok_T_30 = eq(_source_ok_T_29, UInt<1>(0h0)) node _source_ok_T_31 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_T_33 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h1)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<2>(0h2)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h3)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) wire _source_ok_WIRE_1 : UInt<1>[5] connect _source_ok_WIRE_1[0], _source_ok_T_28 connect _source_ok_WIRE_1[1], _source_ok_T_34 connect _source_ok_WIRE_1[2], _source_ok_T_40 connect _source_ok_WIRE_1[3], _source_ok_T_46 connect _source_ok_WIRE_1[4], _source_ok_T_52 node _source_ok_T_53 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE_1[2]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE_1[3]) node source_ok_1 = or(_source_ok_T_55, _source_ok_WIRE_1[4]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1231 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1231 : node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(source_ok_1, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1235 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_54 node _T_1239 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_55 node _T_1243 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_56 node _T_1247 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_57 node _T_1251 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1251 : node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(source_ok_1, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(sink_ok, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1258 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_60 node _T_1262 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_61 node _T_1266 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_62 node _T_1270 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_63 node _T_1274 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1275 = or(UInt<1>(0h1), _T_1274) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_64 node _T_1279 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1279 : node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(source_ok_1, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(sink_ok, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1286 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_67 node _T_1290 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_68 node _T_1294 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_69 node _T_1298 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1299 = or(_T_1298, io.in.d.bits.corrupt) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_70 node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1304 = or(UInt<1>(0h1), _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_71 node _T_1308 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1308 : node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(source_ok_1, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1312 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_73 node _T_1316 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_74 node _T_1320 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1321 = or(UInt<1>(0h1), _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_75 node _T_1325 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1325 : node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(source_ok_1, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1329 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1330 = asUInt(reset) node _T_1331 = eq(_T_1330, UInt<1>(0h0)) when _T_1331 : node _T_1332 = eq(_T_1329, UInt<1>(0h0)) when _T_1332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1329, UInt<1>(0h1), "") : assert_77 node _T_1333 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1334 = or(_T_1333, io.in.d.bits.corrupt) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_78 node _T_1338 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1339 = or(UInt<1>(0h1), _T_1338) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_79 node _T_1343 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1343 : node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(source_ok_1, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1347 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_81 node _T_1351 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_82 node _T_1355 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1356 = or(UInt<1>(0h1), _T_1355) node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(_T_1356, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1356, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1360 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1364 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1368 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1372 = eq(a_first, UInt<1>(0h0)) node _T_1373 = and(io.in.a.valid, _T_1372) when _T_1373 : node _T_1374 = eq(io.in.a.bits.opcode, opcode) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_87 node _T_1378 = eq(io.in.a.bits.param, param) node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(_T_1378, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1378, UInt<1>(0h1), "") : assert_88 node _T_1382 = eq(io.in.a.bits.size, size) node _T_1383 = asUInt(reset) node _T_1384 = eq(_T_1383, UInt<1>(0h0)) when _T_1384 : node _T_1385 = eq(_T_1382, UInt<1>(0h0)) when _T_1385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1382, UInt<1>(0h1), "") : assert_89 node _T_1386 = eq(io.in.a.bits.source, source) node _T_1387 = asUInt(reset) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) when _T_1388 : node _T_1389 = eq(_T_1386, UInt<1>(0h0)) when _T_1389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1386, UInt<1>(0h1), "") : assert_90 node _T_1390 = eq(io.in.a.bits.address, address) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_91 node _T_1394 = and(io.in.a.ready, io.in.a.valid) node _T_1395 = and(_T_1394, a_first) when _T_1395 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1396 = eq(d_first, UInt<1>(0h0)) node _T_1397 = and(io.in.d.valid, _T_1396) when _T_1397 : node _T_1398 = eq(io.in.d.bits.opcode, opcode_1) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_92 node _T_1402 = eq(io.in.d.bits.param, param_1) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_93 node _T_1406 = eq(io.in.d.bits.size, size_1) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_94 node _T_1410 = eq(io.in.d.bits.source, source_1) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_95 node _T_1414 = eq(io.in.d.bits.sink, sink) node _T_1415 = asUInt(reset) node _T_1416 = eq(_T_1415, UInt<1>(0h0)) when _T_1416 : node _T_1417 = eq(_T_1414, UInt<1>(0h0)) when _T_1417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1414, UInt<1>(0h1), "") : assert_96 node _T_1418 = eq(io.in.d.bits.denied, denied) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_97 node _T_1422 = and(io.in.d.ready, io.in.d.valid) node _T_1423 = and(_T_1422, d_first) when _T_1423 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes : UInt<136>, clock, reset, UInt<136>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<17> connect a_set, UInt<17>(0h0) wire a_set_wo_ready : UInt<17> connect a_set_wo_ready, UInt<17>(0h0) wire a_opcodes_set : UInt<68> connect a_opcodes_set, UInt<68>(0h0) wire a_sizes_set : UInt<136> connect a_sizes_set, UInt<136>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1424 = and(io.in.a.valid, a_first_1) node _T_1425 = and(_T_1424, UInt<1>(0h1)) when _T_1425 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1426 = and(io.in.a.ready, io.in.a.valid) node _T_1427 = and(_T_1426, a_first_1) node _T_1428 = and(_T_1427, UInt<1>(0h1)) when _T_1428 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1429 = dshr(inflight, io.in.a.bits.source) node _T_1430 = bits(_T_1429, 0, 0) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<17> connect d_clr, UInt<17>(0h0) wire d_clr_wo_ready : UInt<17> connect d_clr_wo_ready, UInt<17>(0h0) wire d_opcodes_clr : UInt<68> connect d_opcodes_clr, UInt<68>(0h0) wire d_sizes_clr : UInt<136> connect d_sizes_clr, UInt<136>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1435 = and(io.in.d.valid, d_first_1) node _T_1436 = and(_T_1435, UInt<1>(0h1)) node _T_1437 = eq(d_release_ack, UInt<1>(0h0)) node _T_1438 = and(_T_1436, _T_1437) when _T_1438 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1439 = and(io.in.d.ready, io.in.d.valid) node _T_1440 = and(_T_1439, d_first_1) node _T_1441 = and(_T_1440, UInt<1>(0h1)) node _T_1442 = eq(d_release_ack, UInt<1>(0h0)) node _T_1443 = and(_T_1441, _T_1442) when _T_1443 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1444 = and(io.in.d.valid, d_first_1) node _T_1445 = and(_T_1444, UInt<1>(0h1)) node _T_1446 = eq(d_release_ack, UInt<1>(0h0)) node _T_1447 = and(_T_1445, _T_1446) when _T_1447 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1448 = dshr(inflight, io.in.d.bits.source) node _T_1449 = bits(_T_1448, 0, 0) node _T_1450 = or(_T_1449, same_cycle_resp) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1454 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1455 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1456 = or(_T_1454, _T_1455) node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(_T_1456, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1456, UInt<1>(0h1), "") : assert_100 node _T_1460 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_101 else : node _T_1464 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1465 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1466 = or(_T_1464, _T_1465) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_102 node _T_1470 = eq(io.in.d.bits.size, a_size_lookup) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_103 node _T_1474 = and(io.in.d.valid, d_first_1) node _T_1475 = and(_T_1474, a_first_1) node _T_1476 = and(_T_1475, io.in.a.valid) node _T_1477 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1478 = and(_T_1476, _T_1477) node _T_1479 = eq(d_release_ack, UInt<1>(0h0)) node _T_1480 = and(_T_1478, _T_1479) when _T_1480 : node _T_1481 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1482 = or(_T_1481, io.in.a.ready) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_104 node _T_1486 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1487 = orr(a_set_wo_ready) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) node _T_1489 = or(_T_1486, _T_1488) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader node _T_1493 = orr(inflight) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) node _T_1495 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1496 = or(_T_1494, _T_1495) node _T_1497 = lt(watchdog, plusarg_reader.out) node _T_1498 = or(_T_1496, _T_1497) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1502 = and(io.in.a.ready, io.in.a.valid) node _T_1503 = and(io.in.d.ready, io.in.d.valid) node _T_1504 = or(_T_1502, _T_1503) when _T_1504 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes_1 : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes_1 : UInt<136>, clock, reset, UInt<136>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<17> connect c_set, UInt<17>(0h0) wire c_set_wo_ready : UInt<17> connect c_set_wo_ready, UInt<17>(0h0) wire c_opcodes_set : UInt<68> connect c_opcodes_set, UInt<68>(0h0) wire c_sizes_set : UInt<136> connect c_sizes_set, UInt<136>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1505 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1506 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1507 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1508 = and(_T_1506, _T_1507) node _T_1509 = and(_T_1505, _T_1508) when _T_1509 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1510 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1511 = and(_T_1510, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1512 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1513 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1514 = and(_T_1512, _T_1513) node _T_1515 = and(_T_1511, _T_1514) when _T_1515 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1516 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1517 = bits(_T_1516, 0, 0) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(_T_1518, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1518, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<17> connect d_clr_1, UInt<17>(0h0) wire d_clr_wo_ready_1 : UInt<17> connect d_clr_wo_ready_1, UInt<17>(0h0) wire d_opcodes_clr_1 : UInt<68> connect d_opcodes_clr_1, UInt<68>(0h0) wire d_sizes_clr_1 : UInt<136> connect d_sizes_clr_1, UInt<136>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1522 = and(io.in.d.valid, d_first_2) node _T_1523 = and(_T_1522, UInt<1>(0h1)) node _T_1524 = and(_T_1523, d_release_ack_1) when _T_1524 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1525 = and(io.in.d.ready, io.in.d.valid) node _T_1526 = and(_T_1525, d_first_2) node _T_1527 = and(_T_1526, UInt<1>(0h1)) node _T_1528 = and(_T_1527, d_release_ack_1) when _T_1528 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1529 = and(io.in.d.valid, d_first_2) node _T_1530 = and(_T_1529, UInt<1>(0h1)) node _T_1531 = and(_T_1530, d_release_ack_1) when _T_1531 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1532 = dshr(inflight_1, io.in.d.bits.source) node _T_1533 = bits(_T_1532, 0, 0) node _T_1534 = or(_T_1533, same_cycle_resp_1) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1538 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_109 else : node _T_1542 = eq(io.in.d.bits.size, c_size_lookup) node _T_1543 = asUInt(reset) node _T_1544 = eq(_T_1543, UInt<1>(0h0)) when _T_1544 : node _T_1545 = eq(_T_1542, UInt<1>(0h0)) when _T_1545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1542, UInt<1>(0h1), "") : assert_110 node _T_1546 = and(io.in.d.valid, d_first_2) node _T_1547 = and(_T_1546, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1548 = and(_T_1547, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1549 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1550 = and(_T_1548, _T_1549) node _T_1551 = and(_T_1550, d_release_ack_1) node _T_1552 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1553 = and(_T_1551, _T_1552) when _T_1553 : node _T_1554 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1555 = or(_T_1554, _WIRE_23.ready) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_111 node _T_1559 = orr(c_set_wo_ready) when _T_1559 : node _T_1560 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1561 = asUInt(reset) node _T_1562 = eq(_T_1561, UInt<1>(0h0)) when _T_1562 : node _T_1563 = eq(_T_1560, UInt<1>(0h0)) when _T_1563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1560, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_1 node _T_1564 = orr(inflight_1) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) node _T_1566 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1567 = or(_T_1565, _T_1566) node _T_1568 = lt(watchdog_1, plusarg_reader_1.out) node _T_1569 = or(_T_1567, _T_1568) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1573 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1574 = and(io.in.d.ready, io.in.d.valid) node _T_1575 = or(_T_1573, _T_1574) when _T_1575 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_2 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_3 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module HellaCacheArbiter_3 : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} reg s1_id : UInt, clock reg s2_id : UInt, clock connect s2_id, s1_id node _io_mem_keep_clock_enabled_T = or(io.requestor[0].keep_clock_enabled, io.requestor[1].keep_clock_enabled) connect io.mem.keep_clock_enabled, _io_mem_keep_clock_enabled_T node _io_mem_req_valid_T = or(io.requestor[0].req.valid, io.requestor[1].req.valid) connect io.mem.req.valid, _io_mem_req_valid_T connect io.requestor[0].req.ready, io.mem.req.ready node _io_requestor_1_req_ready_T = eq(io.requestor[0].req.valid, UInt<1>(0h0)) node _io_requestor_1_req_ready_T_1 = and(io.requestor[0].req.ready, _io_requestor_1_req_ready_T) connect io.requestor[1].req.ready, _io_requestor_1_req_ready_T_1 connect io.mem.req.bits, io.requestor[1].req.bits node _io_mem_req_bits_tag_T = cat(io.requestor[1].req.bits.tag, UInt<1>(0h1)) connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T connect s1_id, UInt<1>(0h1) connect io.mem.s1_kill, io.requestor[1].s1_kill connect io.mem.s1_data, io.requestor[1].s1_data connect io.mem.s2_kill, io.requestor[1].s2_kill when io.requestor[0].req.valid : connect io.mem.req.bits, io.requestor[0].req.bits node _io_mem_req_bits_tag_T_1 = cat(io.requestor[0].req.bits.tag, UInt<1>(0h0)) connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T_1 connect s1_id, UInt<1>(0h0) node _T = eq(s1_id, UInt<1>(0h0)) when _T : connect io.mem.s1_kill, io.requestor[0].s1_kill connect io.mem.s1_data, io.requestor[0].s1_data node _T_1 = eq(s2_id, UInt<1>(0h0)) when _T_1 : connect io.mem.s2_kill, io.requestor[0].s2_kill node _tag_hit_T = bits(io.mem.resp.bits.tag, 0, 0) node tag_hit = eq(_tag_hit_T, UInt<1>(0h0)) node _io_requestor_0_resp_valid_T = and(io.mem.resp.valid, tag_hit) connect io.requestor[0].resp.valid, _io_requestor_0_resp_valid_T connect io.requestor[0].s2_xcpt, io.mem.s2_xcpt connect io.requestor[0].s2_gpa, io.mem.s2_gpa connect io.requestor[0].s2_gpa_is_pte, io.mem.s2_gpa_is_pte connect io.requestor[0].ordered, io.mem.ordered connect io.requestor[0].store_pending, io.mem.store_pending connect io.requestor[0].perf, io.mem.perf node _io_requestor_0_s2_nack_T = eq(s2_id, UInt<1>(0h0)) node _io_requestor_0_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_0_s2_nack_T) connect io.requestor[0].s2_nack, _io_requestor_0_s2_nack_T_1 connect io.requestor[0].s2_nack_cause_raw, io.mem.s2_nack_cause_raw connect io.requestor[0].s2_uncached, io.mem.s2_uncached connect io.requestor[0].s2_paddr, io.mem.s2_paddr connect io.requestor[0].clock_enabled, io.mem.clock_enabled connect io.requestor[0].resp.bits, io.mem.resp.bits node _io_requestor_0_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) connect io.requestor[0].resp.bits.tag, _io_requestor_0_resp_bits_tag_T connect io.requestor[0].replay_next, io.mem.replay_next node _tag_hit_T_1 = bits(io.mem.resp.bits.tag, 0, 0) node tag_hit_1 = eq(_tag_hit_T_1, UInt<1>(0h1)) node _io_requestor_1_resp_valid_T = and(io.mem.resp.valid, tag_hit_1) connect io.requestor[1].resp.valid, _io_requestor_1_resp_valid_T connect io.requestor[1].s2_xcpt, io.mem.s2_xcpt connect io.requestor[1].s2_gpa, io.mem.s2_gpa connect io.requestor[1].s2_gpa_is_pte, io.mem.s2_gpa_is_pte connect io.requestor[1].ordered, io.mem.ordered connect io.requestor[1].store_pending, io.mem.store_pending connect io.requestor[1].perf, io.mem.perf node _io_requestor_1_s2_nack_T = eq(s2_id, UInt<1>(0h1)) node _io_requestor_1_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_1_s2_nack_T) connect io.requestor[1].s2_nack, _io_requestor_1_s2_nack_T_1 connect io.requestor[1].s2_nack_cause_raw, io.mem.s2_nack_cause_raw connect io.requestor[1].s2_uncached, io.mem.s2_uncached connect io.requestor[1].s2_paddr, io.mem.s2_paddr connect io.requestor[1].clock_enabled, io.mem.clock_enabled connect io.requestor[1].resp.bits, io.mem.resp.bits node _io_requestor_1_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) connect io.requestor[1].resp.bits.tag, _io_requestor_1_resp_bits_tag_T connect io.requestor[1].replay_next, io.mem.replay_next

module HellaCacheArbiter_3( // @[HellaCacheArbiter.scala:10:7] input clock, // @[HellaCacheArbiter.scala:10:7] input reset, // @[HellaCacheArbiter.scala:10:7] output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_0_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_0_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_1_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_1_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_1_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_1_s1_data_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_1_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_1_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_1_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_release, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_phys, // @[HellaCacheArbiter.scala:12:14] output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_mem_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_uncached, // @[HellaCacheArbiter.scala:12:14] input [31:0] io_mem_s2_paddr, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_mem_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] input io_mem_replay_next, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_s2_gpa, // @[HellaCacheArbiter.scala:12:14] input io_mem_ordered, // @[HellaCacheArbiter.scala:12:14] input io_mem_store_pending, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_acquire, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_release, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_grant, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_blocked, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterStore // @[HellaCacheArbiter.scala:12:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_req_bits_tag_0 = io_requestor_1_req_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_dprv_0 = io_requestor_1_req_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_dv_0 = io_requestor_1_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_s1_data_mask_0 = io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[HellaCacheArbiter.scala:10:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[HellaCacheArbiter.scala:10:7] wire io_mem_ordered_0 = io_mem_ordered; // @[HellaCacheArbiter.scala:10:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[HellaCacheArbiter.scala:10:7] wire [8:0] _io_mem_req_bits_tag_T_1 = 9'h0; // @[HellaCacheArbiter.scala:34:35] wire [1:0] io_requestor_0_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_requestor_0_req_bits_tag = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s1_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_keep_clock_enabled_T = 1'h0; // @[HellaCacheArbiter.scala:23:81] wire io_mem_req_bits_phys_0 = io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:25:63] wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] reg s1_id; // @[HellaCacheArbiter.scala:20:20] reg s2_id; // @[HellaCacheArbiter.scala:21:24] wire _io_requestor_1_s2_nack_T = s2_id; // @[HellaCacheArbiter.scala:21:24, :68:58] assign _io_mem_req_valid_T = io_requestor_0_req_valid_0 | io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign io_mem_req_valid_0 = _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:10:7, :25:63] wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] wire [8:0] _io_mem_req_bits_tag_T = {io_requestor_1_req_bits_tag_0, 1'h1}; // @[HellaCacheArbiter.scala:10:7, :34:35] assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_dprv_0 = io_requestor_0_req_valid_0 ? 2'h1 : io_requestor_1_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_dv_0 : io_requestor_1_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 8'h0 : _io_mem_req_bits_tag_T[7:0]; // @[HellaCacheArbiter.scala:10:7, :34:{29,35}, :50:26] assign io_mem_s1_kill_0 = ~s1_id & io_requestor_0_s1_kill_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :38:24, :51:{21,30}] assign io_mem_s1_data_data_0 = s1_id ? io_requestor_1_s1_data_data_0 : 64'h0; // @[HellaCacheArbiter.scala:10:7, :20:20, :39:24, :51:30] assign io_mem_s1_data_mask_0 = s1_id ? io_requestor_1_s1_data_mask_0 : 8'h0; // @[HellaCacheArbiter.scala:10:7, :20:20, :39:24, :51:30] wire _io_requestor_0_s2_nack_T = ~s2_id; // @[HellaCacheArbiter.scala:21:24, :52:21, :68:58] wire _tag_hit_T = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire _tag_hit_T_1 = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire tag_hit = ~_tag_hit_T; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] wire [6:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:1]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [6:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:1]; // @[HellaCacheArbiter.scala:10:7, :74:45] assign io_requestor_0_resp_bits_tag_0 = {1'h0, _io_requestor_0_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_1 = _tag_hit_T_1; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_1_resp_bits_tag_0 = {1'h0, _io_requestor_1_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] always @(posedge clock) begin // @[HellaCacheArbiter.scala:10:7] s1_id <= ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :28:67] s2_id <= s1_id; // @[HellaCacheArbiter.scala:20:20, :21:24] always @(posedge) assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_replay_next = io_requestor_0_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_release = io_requestor_0_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_tlbMiss = io_requestor_0_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_replay_next = io_requestor_1_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_release = io_requestor_1_perf_release_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_tlbMiss = io_requestor_1_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_phys = io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_mask = io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_127 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_211 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_127( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_211 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_72 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_89 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_72( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_89 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_36 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} inst input_buffer of InputBuffer_36 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) inst route_arbiter of Arbiter3_RouteComputerReq_36 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_10 : connect states[0].g, UInt<3>(0h2) connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id node _T_11 = and(io.router_req.ready, io.router_req.valid) when _T_11 : node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_12, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_16 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_17 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_18 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_18 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3] wire vcalloc_vals : UInt<1>[3] node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0]) node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11) node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12) node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15) node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_19 = and(io.router_req.ready, io.router_req.valid) when _T_19 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_20 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_21 = or(_T_20, vcalloc_vals[2]) when _T_21 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = bits(vcalloc_sel, 0, 0) node _mask_T_7 = bits(vcalloc_sel, 1, 1) node _mask_T_8 = bits(vcalloc_sel, 2, 2) node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_9, _mask_T_10) node _mask_T_13 = or(_mask_T_12, _mask_T_11) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_13 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3] node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3] node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32 connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6 wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3] node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42 connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1] node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_16 : UInt<2> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16 wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_62 connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65) wire _io_vcalloc_req_bits_WIRE_19 : UInt<4> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70) wire _io_vcalloc_req_bits_WIRE_20 : UInt<3> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_72 connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_21 : UInt<4> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_77 connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80) wire _io_vcalloc_req_bits_WIRE_22 : UInt<2> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].flow, states[0].flow node _T_22 = bits(vcalloc_sel, 0, 0) node _T_23 = and(vcalloc_vals[0], _T_22) node _T_24 = and(_T_23, io.vcalloc_req.ready) when _T_24 : connect states[0].g, UInt<3>(0h3) node _T_25 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_25 : connect vcalloc_vals[0], UInt<1>(0h1) connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[1] invalidate vcalloc_reqs[1].vc_sel.`2`[2] invalidate vcalloc_reqs[1].vc_sel.`3`[0] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[1] invalidate vcalloc_reqs[2].vc_sel.`2`[2] invalidate vcalloc_reqs[2].vc_sel.`3`[0] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready) node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1) connect io.debug.va_stall, _io_debug_va_stall_T_5 node _T_26 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_26 : node _T_27 = bits(vcalloc_sel, 0, 0) when _T_27 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_28 = bits(vcalloc_sel, 1, 1) when _T_28 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_29 = bits(vcalloc_sel, 2, 2) when _T_29 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_89 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1]) node _credit_available_T = cat(credit_available_hi, states[0].vc_sel.`0`[0]) node credit_available_hi_1 = cat(states[0].vc_sel.`1`[2], states[0].vc_sel.`1`[1]) node _credit_available_T_1 = cat(credit_available_hi_1, states[0].vc_sel.`1`[0]) node credit_available_hi_2 = cat(states[0].vc_sel.`2`[2], states[0].vc_sel.`2`[1]) node _credit_available_T_2 = cat(credit_available_hi_2, states[0].vc_sel.`2`[0]) node credit_available_lo = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_3 = cat(states[0].vc_sel.`3`[0], _credit_available_T_2) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo) node credit_available_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`0`[0]) node credit_available_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`1`[0]) node credit_available_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`2`[0]) node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4) node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], _credit_available_T_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_1) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_30 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_31 = and(_T_30, input_buffer.io.deq[0].bits.tail) when _T_31 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0] connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`3`[0] node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0) node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_9 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5) node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8 node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_10 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1) node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _vc_sel_WIRE : UInt<1>[3] node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4) node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_7 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_12 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_17 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_4 : UInt<1>[3] node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_22 connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_27 connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_32 connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7 connect vc_sel.`1`, _vc_sel_WIRE_4 wire _vc_sel_WIRE_8 : UInt<1>[3] node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_37 connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_42 connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10 node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_47 connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11 connect vc_sel.`2`, _vc_sel_WIRE_8 wire _vc_sel_WIRE_12 : UInt<1>[1] node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_52 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 connect vc_sel.`3`, _vc_sel_WIRE_12 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2]) node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2]) node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0]) node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2) node virt_channel_lo = bits(_virt_channel_T, 1, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3) node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1]) node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0]) node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2) node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0) node _virt_channel_T_6 = orr(virt_channel_hi_3) node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1) node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1) node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8) node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1]) node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0]) node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2) node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0)) node _virt_channel_T_16 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0)) node _virt_channel_T_17 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0)) node _virt_channel_T_18 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_19 = or(_virt_channel_T_15, _virt_channel_T_16) node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_17) node _virt_channel_T_21 = or(_virt_channel_T_20, _virt_channel_T_18) wire virt_channel : UInt<2> connect virt_channel, _virt_channel_T_21 node _T_32 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_32 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4) node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5) wire _salloc_outs_0_flit_payload_WIRE : UInt<145> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4) node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4) node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`1`[0], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[2], UInt<1>(0h0) connect states[0].vc_sel.`2`[1], UInt<1>(0h0) connect states[0].vc_sel.`2`[2], UInt<1>(0h0) invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`2`[1] invalidate states[1].vc_sel.`2`[2] invalidate states[1].vc_sel.`3`[0] invalidate states[1].g invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`2`[1] invalidate states[2].vc_sel.`2`[2] invalidate states[2].vc_sel.`3`[0] invalidate states[2].g node _T_33 = asUInt(reset) when _T_33 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0)

module InputUnit_36( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_2_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_57 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_57( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IBuf : input clock : Clock input reset : Reset output io : { flip imem : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip kill : UInt<1>, pc : UInt<34>, btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, inst : { flip ready : UInt<1>, valid : UInt<1>, bits : { xcpt0 : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, xcpt1 : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>, rvc : UInt<1>, inst : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, raw : UInt<32>}}[1]} regreset nBufValid : UInt<1>, clock, reset, UInt<1>(0h0) reg buf : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}, clock reg ibufBTBResp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock node pcWordBits = bits(io.imem.bits.pc, 1, 1) wire nReady : UInt<2> connect nReady, UInt<2>(0h0) node _nIC_T = add(io.imem.bits.btb.bridx, UInt<1>(0h1)) node _nIC_T_1 = mux(io.imem.bits.btb.taken, _nIC_T, UInt<2>(0h2)) node _nIC_T_2 = sub(_nIC_T_1, pcWordBits) node nIC = tail(_nIC_T_2, 1) node _nICReady_T = sub(nReady, nBufValid) node nICReady = tail(_nICReady_T, 1) node _nValid_T = mux(io.imem.valid, nIC, UInt<1>(0h0)) node _nValid_T_1 = add(_nValid_T, nBufValid) node nValid = tail(_nValid_T_1, 1) node _io_imem_ready_T = geq(nReady, nBufValid) node _io_imem_ready_T_1 = and(io.inst[0].ready, _io_imem_ready_T) node _io_imem_ready_T_2 = geq(nICReady, nIC) node _io_imem_ready_T_3 = sub(nIC, nICReady) node _io_imem_ready_T_4 = tail(_io_imem_ready_T_3, 1) node _io_imem_ready_T_5 = geq(UInt<1>(0h1), _io_imem_ready_T_4) node _io_imem_ready_T_6 = or(_io_imem_ready_T_2, _io_imem_ready_T_5) node _io_imem_ready_T_7 = and(_io_imem_ready_T_1, _io_imem_ready_T_6) connect io.imem.ready, _io_imem_ready_T_7 when io.inst[0].ready : node _nBufValid_T = geq(nReady, nBufValid) node _nBufValid_T_1 = eq(nBufValid, UInt<1>(0h0)) node _nBufValid_T_2 = or(_nBufValid_T, _nBufValid_T_1) node _nBufValid_T_3 = sub(nBufValid, nReady) node _nBufValid_T_4 = tail(_nBufValid_T_3, 1) node _nBufValid_T_5 = mux(_nBufValid_T_2, UInt<1>(0h0), _nBufValid_T_4) connect nBufValid, _nBufValid_T_5 node _T = geq(nReady, nBufValid) node _T_1 = and(io.imem.valid, _T) node _T_2 = lt(nICReady, nIC) node _T_3 = and(_T_1, _T_2) node _T_4 = sub(nIC, nICReady) node _T_5 = tail(_T_4, 1) node _T_6 = geq(UInt<1>(0h1), _T_5) node _T_7 = and(_T_3, _T_6) when _T_7 : node _shamt_T = add(pcWordBits, nICReady) node shamt = tail(_shamt_T, 1) node _nBufValid_T_6 = sub(nIC, nICReady) node _nBufValid_T_7 = tail(_nBufValid_T_6, 1) connect nBufValid, _nBufValid_T_7 connect buf, io.imem.bits node _buf_data_data_T = shr(io.imem.bits.data, 16) node _buf_data_data_T_1 = cat(_buf_data_data_T, _buf_data_data_T) node buf_data_data = cat(_buf_data_data_T_1, io.imem.bits.data) node _buf_data_T = shl(shamt, 4) node _buf_data_T_1 = dshr(buf_data_data, _buf_data_T) node _buf_data_T_2 = bits(_buf_data_T_1, 15, 0) connect buf.data, _buf_data_T_2 node _buf_pc_T = not(UInt<34>(0h3)) node _buf_pc_T_1 = and(io.imem.bits.pc, _buf_pc_T) node _buf_pc_T_2 = shl(nICReady, 1) node _buf_pc_T_3 = add(io.imem.bits.pc, _buf_pc_T_2) node _buf_pc_T_4 = tail(_buf_pc_T_3, 1) node _buf_pc_T_5 = and(_buf_pc_T_4, UInt<34>(0h3)) node _buf_pc_T_6 = or(_buf_pc_T_1, _buf_pc_T_5) connect buf.pc, _buf_pc_T_6 connect ibufBTBResp, io.imem.bits.btb when io.kill : connect nBufValid, UInt<1>(0h0) node _icShiftAmt_T = add(UInt<2>(0h2), nBufValid) node _icShiftAmt_T_1 = tail(_icShiftAmt_T, 1) node _icShiftAmt_T_2 = sub(_icShiftAmt_T_1, pcWordBits) node _icShiftAmt_T_3 = tail(_icShiftAmt_T_2, 1) node icShiftAmt = bits(_icShiftAmt_T_3, 1, 0) node _icData_T = bits(io.imem.bits.data, 15, 0) node _icData_T_1 = cat(_icData_T, _icData_T) node _icData_T_2 = cat(io.imem.bits.data, _icData_T_1) node _icData_data_T = shr(_icData_T_2, 48) node _icData_data_T_1 = cat(_icData_data_T, _icData_data_T) node _icData_data_T_2 = cat(_icData_data_T_1, _icData_data_T_1) node icData_data = cat(_icData_data_T_2, _icData_T_2) node _icData_T_3 = shl(icShiftAmt, 4) node _icData_T_4 = dshl(icData_data, _icData_T_3) node icData = bits(_icData_T_4, 95, 64) node _icMask_T = not(UInt<32>(0h0)) node _icMask_T_1 = shl(nBufValid, 4) node _icMask_T_2 = dshl(_icMask_T, _icMask_T_1) node icMask = bits(_icMask_T_2, 31, 0) node _inst_T = and(icData, icMask) node _inst_T_1 = not(icMask) node _inst_T_2 = and(buf.data, _inst_T_1) node inst = or(_inst_T, _inst_T_2) node _valid_T = dshl(UInt<1>(0h1), nValid) node _valid_T_1 = sub(_valid_T, UInt<1>(0h1)) node _valid_T_2 = tail(_valid_T_1, 1) node valid = bits(_valid_T_2, 1, 0) node _bufMask_T = dshl(UInt<1>(0h1), nBufValid) node _bufMask_T_1 = sub(_bufMask_T, UInt<1>(0h1)) node bufMask = tail(_bufMask_T_1, 1) node _xcpt_T = bits(bufMask, 0, 0) node xcpt_0 = mux(_xcpt_T, buf.xcpt, io.imem.bits.xcpt) node _xcpt_T_1 = bits(bufMask, 1, 1) node xcpt_1 = mux(_xcpt_T_1, buf.xcpt, io.imem.bits.xcpt) node buf_replay = mux(buf.replay, bufMask, UInt<1>(0h0)) node _ic_replay_T = not(bufMask) node _ic_replay_T_1 = and(valid, _ic_replay_T) node _ic_replay_T_2 = mux(io.imem.bits.replay, _ic_replay_T_1, UInt<1>(0h0)) node ic_replay = or(buf_replay, _ic_replay_T_2) node _T_8 = eq(io.imem.valid, UInt<1>(0h0)) node _T_9 = eq(io.imem.bits.btb.taken, UInt<1>(0h0)) node _T_10 = or(_T_8, _T_9) node _T_11 = geq(io.imem.bits.btb.bridx, pcWordBits) node _T_12 = or(_T_10, _T_11) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IBuf.scala:79 assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits)\n") : printf assert(clock, _T_12, UInt<1>(0h1), "") : assert connect io.btb_resp, io.imem.bits.btb node _io_pc_T = gt(nBufValid, UInt<1>(0h0)) node _io_pc_T_1 = mux(_io_pc_T, buf.pc, io.imem.bits.pc) connect io.pc, _io_pc_T_1 inst exp of RVCExpander connect exp.clock, clock connect exp.reset, reset connect exp.io.in, inst connect io.inst[0].bits.inst, exp.io.out connect io.inst[0].bits.raw, inst node _replay_T = dshr(ic_replay, UInt<1>(0h0)) node _replay_T_1 = bits(_replay_T, 0, 0) node _replay_T_2 = eq(exp.io.rvc, UInt<1>(0h0)) node _replay_T_3 = add(UInt<1>(0h0), UInt<1>(0h1)) node _replay_T_4 = tail(_replay_T_3, 1) node _replay_T_5 = dshr(ic_replay, _replay_T_4) node _replay_T_6 = bits(_replay_T_5, 0, 0) node _replay_T_7 = and(_replay_T_2, _replay_T_6) node replay = or(_replay_T_1, _replay_T_7) node _full_insn_T = add(UInt<1>(0h0), UInt<1>(0h1)) node _full_insn_T_1 = tail(_full_insn_T, 1) node _full_insn_T_2 = dshr(valid, _full_insn_T_1) node _full_insn_T_3 = bits(_full_insn_T_2, 0, 0) node _full_insn_T_4 = or(exp.io.rvc, _full_insn_T_3) node _full_insn_T_5 = dshr(buf_replay, UInt<1>(0h0)) node _full_insn_T_6 = bits(_full_insn_T_5, 0, 0) node full_insn = or(_full_insn_T_4, _full_insn_T_6) node _io_inst_0_valid_T = dshr(valid, UInt<1>(0h0)) node _io_inst_0_valid_T_1 = bits(_io_inst_0_valid_T, 0, 0) node _io_inst_0_valid_T_2 = and(_io_inst_0_valid_T_1, full_insn) connect io.inst[0].valid, _io_inst_0_valid_T_2 node _io_inst_0_bits_xcpt0_T = eq(UInt<1>(0h0), UInt<1>(0h1)) node _io_inst_0_bits_xcpt0_T_1 = mux(_io_inst_0_bits_xcpt0_T, xcpt_1, xcpt_0) connect io.inst[0].bits.xcpt0, _io_inst_0_bits_xcpt0_T_1 node _io_inst_0_bits_xcpt1_T = add(UInt<1>(0h0), UInt<1>(0h1)) node _io_inst_0_bits_xcpt1_T_1 = tail(_io_inst_0_bits_xcpt1_T, 1) node _io_inst_0_bits_xcpt1_T_2 = eq(_io_inst_0_bits_xcpt1_T_1, UInt<1>(0h1)) node _io_inst_0_bits_xcpt1_T_3 = mux(_io_inst_0_bits_xcpt1_T_2, xcpt_1, xcpt_0) node io_inst_0_bits_xcpt1_hi = cat(_io_inst_0_bits_xcpt1_T_3.pf.inst, _io_inst_0_bits_xcpt1_T_3.gf.inst) node _io_inst_0_bits_xcpt1_T_4 = cat(io_inst_0_bits_xcpt1_hi, _io_inst_0_bits_xcpt1_T_3.ae.inst) node _io_inst_0_bits_xcpt1_T_5 = mux(exp.io.rvc, UInt<1>(0h0), _io_inst_0_bits_xcpt1_T_4) wire _io_inst_0_bits_xcpt1_WIRE : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}} wire _io_inst_0_bits_xcpt1_WIRE_1 : UInt<3> connect _io_inst_0_bits_xcpt1_WIRE_1, _io_inst_0_bits_xcpt1_T_5 node _io_inst_0_bits_xcpt1_T_6 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 0, 0) connect _io_inst_0_bits_xcpt1_WIRE.ae.inst, _io_inst_0_bits_xcpt1_T_6 node _io_inst_0_bits_xcpt1_T_7 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 1, 1) connect _io_inst_0_bits_xcpt1_WIRE.gf.inst, _io_inst_0_bits_xcpt1_T_7 node _io_inst_0_bits_xcpt1_T_8 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 2, 2) connect _io_inst_0_bits_xcpt1_WIRE.pf.inst, _io_inst_0_bits_xcpt1_T_8 connect io.inst[0].bits.xcpt1, _io_inst_0_bits_xcpt1_WIRE connect io.inst[0].bits.replay, replay connect io.inst[0].bits.rvc, exp.io.rvc node _T_16 = dshr(bufMask, UInt<1>(0h0)) node _T_17 = bits(_T_16, 0, 0) node _T_18 = and(_T_17, exp.io.rvc) node _T_19 = add(UInt<1>(0h0), UInt<1>(0h1)) node _T_20 = tail(_T_19, 1) node _T_21 = dshr(bufMask, _T_20) node _T_22 = bits(_T_21, 0, 0) node _T_23 = or(_T_18, _T_22) when _T_23 : connect io.btb_resp, ibufBTBResp node _T_24 = or(UInt<1>(0h1), io.inst[0].ready) node _T_25 = and(full_insn, _T_24) when _T_25 : node _nReady_T = add(UInt<1>(0h0), UInt<1>(0h1)) node _nReady_T_1 = tail(_nReady_T, 1) node _nReady_T_2 = add(UInt<1>(0h0), UInt<2>(0h2)) node _nReady_T_3 = tail(_nReady_T_2, 1) node _nReady_T_4 = mux(exp.io.rvc, _nReady_T_1, _nReady_T_3) connect nReady, _nReady_T_4 node _T_26 = add(UInt<1>(0h0), UInt<1>(0h1)) node _T_27 = tail(_T_26, 1) node _T_28 = add(UInt<1>(0h0), UInt<2>(0h2)) node _T_29 = tail(_T_28, 1) node _T_30 = mux(exp.io.rvc, _T_27, _T_29) node _T_31 = shr(inst, 16) node _T_32 = shr(inst, 32) node _T_33 = mux(exp.io.rvc, _T_31, _T_32)

module IBuf( // @[IBuf.scala:21:7] input clock, // @[IBuf.scala:21:7] input reset, // @[IBuf.scala:21:7] output io_imem_ready, // @[IBuf.scala:22:14] input io_imem_valid, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_btb_cfiType, // @[IBuf.scala:22:14] input io_imem_bits_btb_taken, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_btb_mask, // @[IBuf.scala:22:14] input io_imem_bits_btb_bridx, // @[IBuf.scala:22:14] input [32:0] io_imem_bits_btb_target, // @[IBuf.scala:22:14] input [4:0] io_imem_bits_btb_entry, // @[IBuf.scala:22:14] input [7:0] io_imem_bits_btb_bht_history, // @[IBuf.scala:22:14] input io_imem_bits_btb_bht_value, // @[IBuf.scala:22:14] input [33:0] io_imem_bits_pc, // @[IBuf.scala:22:14] input [31:0] io_imem_bits_data, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_mask, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_pf_inst, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_gf_inst, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_ae_inst, // @[IBuf.scala:22:14] input io_imem_bits_replay, // @[IBuf.scala:22:14] input io_kill, // @[IBuf.scala:22:14] output [33:0] io_pc, // @[IBuf.scala:22:14] output [1:0] io_btb_resp_cfiType, // @[IBuf.scala:22:14] output io_btb_resp_taken, // @[IBuf.scala:22:14] output [1:0] io_btb_resp_mask, // @[IBuf.scala:22:14] output io_btb_resp_bridx, // @[IBuf.scala:22:14] output [32:0] io_btb_resp_target, // @[IBuf.scala:22:14] output [4:0] io_btb_resp_entry, // @[IBuf.scala:22:14] output [7:0] io_btb_resp_bht_history, // @[IBuf.scala:22:14] output io_btb_resp_bht_value, // @[IBuf.scala:22:14] input io_inst_0_ready, // @[IBuf.scala:22:14] output io_inst_0_valid, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_pf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_gf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_ae_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_pf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_gf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_ae_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_replay, // @[IBuf.scala:22:14] output io_inst_0_bits_rvc, // @[IBuf.scala:22:14] output [31:0] io_inst_0_bits_inst_bits, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rd, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs1, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs2, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs3, // @[IBuf.scala:22:14] output [31:0] io_inst_0_bits_raw // @[IBuf.scala:22:14] ); wire _exp_io_rvc; // @[IBuf.scala:86:21] wire io_imem_valid_0 = io_imem_valid; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_btb_cfiType_0 = io_imem_bits_btb_cfiType; // @[IBuf.scala:21:7] wire io_imem_bits_btb_taken_0 = io_imem_bits_btb_taken; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_btb_mask_0 = io_imem_bits_btb_mask; // @[IBuf.scala:21:7] wire io_imem_bits_btb_bridx_0 = io_imem_bits_btb_bridx; // @[IBuf.scala:21:7] wire [32:0] io_imem_bits_btb_target_0 = io_imem_bits_btb_target; // @[IBuf.scala:21:7] wire [4:0] io_imem_bits_btb_entry_0 = io_imem_bits_btb_entry; // @[IBuf.scala:21:7] wire [7:0] io_imem_bits_btb_bht_history_0 = io_imem_bits_btb_bht_history; // @[IBuf.scala:21:7] wire io_imem_bits_btb_bht_value_0 = io_imem_bits_btb_bht_value; // @[IBuf.scala:21:7] wire [33:0] io_imem_bits_pc_0 = io_imem_bits_pc; // @[IBuf.scala:21:7] wire [31:0] io_imem_bits_data_0 = io_imem_bits_data; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_mask_0 = io_imem_bits_mask; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_pf_inst_0 = io_imem_bits_xcpt_pf_inst; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_gf_inst_0 = io_imem_bits_xcpt_gf_inst; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_ae_inst_0 = io_imem_bits_xcpt_ae_inst; // @[IBuf.scala:21:7] wire io_imem_bits_replay_0 = io_imem_bits_replay; // @[IBuf.scala:21:7] wire io_kill_0 = io_kill; // @[IBuf.scala:21:7] wire io_inst_0_ready_0 = io_inst_0_ready; // @[IBuf.scala:21:7] wire [1:0] _replay_T_3 = 2'h1; // @[IBuf.scala:92:63] wire [1:0] _full_insn_T = 2'h1; // @[IBuf.scala:93:44] wire [1:0] _io_inst_0_bits_xcpt1_T = 2'h1; // @[IBuf.scala:96:59] wire [1:0] _nReady_T = 2'h1; // @[IBuf.scala:102:89] wire [1:0] _nReady_T_3 = 2'h2; // @[IBuf.scala:102:96] wire _replay_T_4 = 1'h1; // @[IBuf.scala:92:63] wire _full_insn_T_1 = 1'h1; // @[IBuf.scala:93:44] wire _io_inst_0_bits_xcpt1_T_1 = 1'h1; // @[IBuf.scala:96:59] wire _io_inst_0_bits_xcpt1_T_2 = 1'h1; // @[package.scala:39:86] wire _nReady_T_1 = 1'h1; // @[IBuf.scala:102:89] wire _io_inst_0_bits_xcpt0_T = 1'h0; // @[package.scala:39:86] wire [31:0] _icMask_T = 32'hFFFFFFFF; // @[IBuf.scala:71:17] wire [33:0] _buf_pc_T = 34'h3FFFFFFFC; // @[IBuf.scala:59:37] wire [2:0] _nReady_T_2 = 3'h2; // @[IBuf.scala:102:96] wire _io_imem_ready_T_7; // @[IBuf.scala:44:60] wire [33:0] _io_pc_T_1; // @[IBuf.scala:82:15] wire _io_inst_0_valid_T_2; // @[IBuf.scala:94:36] wire _io_inst_0_bits_xcpt0_T_1_pf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt0_T_1_gf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt0_T_1_ae_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_WIRE_pf_inst; // @[IBuf.scala:96:81] wire _io_inst_0_bits_xcpt1_WIRE_gf_inst; // @[IBuf.scala:96:81] wire _io_inst_0_bits_xcpt1_WIRE_ae_inst; // @[IBuf.scala:96:81] wire replay; // @[IBuf.scala:92:33] wire [31:0] inst; // @[IBuf.scala:72:30] wire io_imem_ready_0; // @[IBuf.scala:21:7] wire [7:0] io_btb_resp_bht_history_0; // @[IBuf.scala:21:7] wire io_btb_resp_bht_value_0; // @[IBuf.scala:21:7] wire [1:0] io_btb_resp_cfiType_0; // @[IBuf.scala:21:7] wire io_btb_resp_taken_0; // @[IBuf.scala:21:7] wire [1:0] io_btb_resp_mask_0; // @[IBuf.scala:21:7] wire io_btb_resp_bridx_0; // @[IBuf.scala:21:7] wire [32:0] io_btb_resp_target_0; // @[IBuf.scala:21:7] wire [4:0] io_btb_resp_entry_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_pf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_gf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_ae_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_pf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_gf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_ae_inst_0; // @[IBuf.scala:21:7] wire [31:0] io_inst_0_bits_inst_bits_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rd_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs1_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs2_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs3_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_replay_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_rvc_0; // @[IBuf.scala:21:7] wire [31:0] io_inst_0_bits_raw_0; // @[IBuf.scala:21:7] wire io_inst_0_valid_0; // @[IBuf.scala:21:7] wire [33:0] io_pc_0; // @[IBuf.scala:21:7] reg nBufValid; // @[IBuf.scala:34:47] wire _io_pc_T = nBufValid; // @[IBuf.scala:34:47, :82:26] reg [1:0] buf_btb_cfiType; // @[IBuf.scala:35:16] reg buf_btb_taken; // @[IBuf.scala:35:16] reg [1:0] buf_btb_mask; // @[IBuf.scala:35:16] reg buf_btb_bridx; // @[IBuf.scala:35:16] reg [32:0] buf_btb_target; // @[IBuf.scala:35:16] reg [4:0] buf_btb_entry; // @[IBuf.scala:35:16] reg [7:0] buf_btb_bht_history; // @[IBuf.scala:35:16] reg buf_btb_bht_value; // @[IBuf.scala:35:16] reg [33:0] buf_pc; // @[IBuf.scala:35:16] reg [31:0] buf_data; // @[IBuf.scala:35:16] reg [1:0] buf_mask; // @[IBuf.scala:35:16] reg buf_xcpt_pf_inst; // @[IBuf.scala:35:16] reg buf_xcpt_gf_inst; // @[IBuf.scala:35:16] reg buf_xcpt_ae_inst; // @[IBuf.scala:35:16] reg buf_replay; // @[IBuf.scala:35:16] reg [1:0] ibufBTBResp_cfiType; // @[IBuf.scala:36:24] reg ibufBTBResp_taken; // @[IBuf.scala:36:24] reg [1:0] ibufBTBResp_mask; // @[IBuf.scala:36:24] reg ibufBTBResp_bridx; // @[IBuf.scala:36:24] reg [32:0] ibufBTBResp_target; // @[IBuf.scala:36:24] reg [4:0] ibufBTBResp_entry; // @[IBuf.scala:36:24] reg [7:0] ibufBTBResp_bht_history; // @[IBuf.scala:36:24] reg ibufBTBResp_bht_value; // @[IBuf.scala:36:24] wire pcWordBits = io_imem_bits_pc_0[1]; // @[package.scala:163:13] wire [1:0] nReady; // @[IBuf.scala:40:27] wire [1:0] _nIC_T = {1'h0, io_imem_bits_btb_bridx_0} + 2'h1; // @[IBuf.scala:21:7, :41:64] wire [1:0] _nIC_T_1 = io_imem_bits_btb_taken_0 ? _nIC_T : 2'h2; // @[IBuf.scala:21:7, :41:{16,64}] wire [2:0] _GEN = {2'h0, pcWordBits}; // @[package.scala:163:13] wire [2:0] _nIC_T_2 = {1'h0, _nIC_T_1} - _GEN; // @[IBuf.scala:41:{16,86}] wire [1:0] nIC = _nIC_T_2[1:0]; // @[IBuf.scala:41:86] wire [2:0] _GEN_0 = {1'h0, nReady}; // @[IBuf.scala:40:27, :42:25] wire [2:0] _GEN_1 = {2'h0, nBufValid}; // @[IBuf.scala:34:47, :42:25] wire [2:0] _nICReady_T = _GEN_0 - _GEN_1; // @[IBuf.scala:42:25] wire [1:0] nICReady = _nICReady_T[1:0]; // @[IBuf.scala:42:25] wire [1:0] _nValid_T = io_imem_valid_0 ? nIC : 2'h0; // @[IBuf.scala:21:7, :41:86, :43:19] wire [2:0] _nValid_T_1 = {1'h0, _nValid_T} + _GEN_1; // @[IBuf.scala:42:25, :43:{19,45}] wire [1:0] nValid = _nValid_T_1[1:0]; // @[IBuf.scala:43:45] wire [1:0] _GEN_2 = {1'h0, nBufValid}; // @[IBuf.scala:34:47, :44:47] wire _T = nReady >= _GEN_2; // @[IBuf.scala:40:27, :44:47] wire _io_imem_ready_T; // @[IBuf.scala:44:47] assign _io_imem_ready_T = _T; // @[IBuf.scala:44:47] wire _nBufValid_T; // @[package.scala:218:33] assign _nBufValid_T = _T; // @[package.scala:218:33] wire _io_imem_ready_T_1 = io_inst_0_ready_0 & _io_imem_ready_T; // @[IBuf.scala:21:7, :44:{37,47}] wire _io_imem_ready_T_2 = nICReady >= nIC; // @[IBuf.scala:41:86, :42:25, :44:73] wire [2:0] _GEN_3 = {1'h0, nICReady}; // @[IBuf.scala:42:25, :44:94] wire [2:0] _T_4 = {1'h0, nIC} - _GEN_3; // @[IBuf.scala:41:86, :44:94] wire [2:0] _io_imem_ready_T_3; // @[IBuf.scala:44:94] assign _io_imem_ready_T_3 = _T_4; // @[IBuf.scala:44:94] wire [2:0] _nBufValid_T_6; // @[IBuf.scala:56:26] assign _nBufValid_T_6 = _T_4; // @[IBuf.scala:44:94, :56:26] wire [1:0] _io_imem_ready_T_4 = _io_imem_ready_T_3[1:0]; // @[IBuf.scala:44:94] wire _io_imem_ready_T_5 = ~(_io_imem_ready_T_4[1]); // @[IBuf.scala:44:{87,94}] wire _io_imem_ready_T_6 = _io_imem_ready_T_2 | _io_imem_ready_T_5; // @[IBuf.scala:44:{73,80,87}] assign _io_imem_ready_T_7 = _io_imem_ready_T_1 & _io_imem_ready_T_6; // @[IBuf.scala:44:{37,60,80}] assign io_imem_ready_0 = _io_imem_ready_T_7; // @[IBuf.scala:21:7, :44:60] wire _nBufValid_T_1 = ~nBufValid; // @[package.scala:218:43] wire _nBufValid_T_2 = _nBufValid_T | _nBufValid_T_1; // @[package.scala:218:{33,38,43}] wire [2:0] _nBufValid_T_3 = _GEN_1 - _GEN_0; // @[IBuf.scala:42:25, :48:61] wire [1:0] _nBufValid_T_4 = _nBufValid_T_3[1:0]; // @[IBuf.scala:48:61] wire [1:0] _nBufValid_T_5 = _nBufValid_T_2 ? 2'h0 : _nBufValid_T_4; // @[package.scala:218:38] wire [2:0] _shamt_T = _GEN + _GEN_3; // @[IBuf.scala:41:86, :44:94, :55:32] wire [1:0] shamt = _shamt_T[1:0]; // @[IBuf.scala:55:32] wire [1:0] _nBufValid_T_7 = _nBufValid_T_6[1:0]; // @[IBuf.scala:56:26] wire [15:0] _buf_data_data_T = io_imem_bits_data_0[31:16]; // @[IBuf.scala:21:7, :127:58] wire [31:0] _buf_data_data_T_1 = {2{_buf_data_data_T}}; // @[IBuf.scala:127:{24,58}] wire [63:0] buf_data_data = {_buf_data_data_T_1, io_imem_bits_data_0}; // @[IBuf.scala:21:7, :127:{19,24}] wire [5:0] _buf_data_T = {shamt, 4'h0}; // @[IBuf.scala:55:32, :128:19] wire [63:0] _buf_data_T_1 = buf_data_data >> _buf_data_T; // @[IBuf.scala:127:19, :128:{10,19}] wire [15:0] _buf_data_T_2 = _buf_data_T_1[15:0]; // @[IBuf.scala:58:61, :128:10] wire [33:0] _buf_pc_T_1 = io_imem_bits_pc_0 & 34'h3FFFFFFFC; // @[IBuf.scala:21:7, :59:35] wire [2:0] _buf_pc_T_2 = {nICReady, 1'h0}; // @[IBuf.scala:42:25, :59:80] wire [34:0] _buf_pc_T_3 = {1'h0, io_imem_bits_pc_0} + {32'h0, _buf_pc_T_2}; // @[IBuf.scala:21:7, :59:{68,80}] wire [33:0] _buf_pc_T_4 = _buf_pc_T_3[33:0]; // @[IBuf.scala:59:68] wire [33:0] _buf_pc_T_5 = _buf_pc_T_4 & 34'h3; // @[IBuf.scala:59:{68,109}] wire [33:0] _buf_pc_T_6 = _buf_pc_T_1 | _buf_pc_T_5; // @[IBuf.scala:59:{35,49,109}] wire [2:0] _icShiftAmt_T = _GEN_1 + 3'h2; // @[IBuf.scala:42:25, :68:34] wire [1:0] _icShiftAmt_T_1 = _icShiftAmt_T[1:0]; // @[IBuf.scala:68:34] wire [2:0] _icShiftAmt_T_2 = {1'h0, _icShiftAmt_T_1} - _GEN; // @[IBuf.scala:41:86, :68:{34,46}] wire [1:0] _icShiftAmt_T_3 = _icShiftAmt_T_2[1:0]; // @[IBuf.scala:68:46] wire [1:0] icShiftAmt = _icShiftAmt_T_3; // @[IBuf.scala:68:{46,59}] wire [15:0] _icData_T = io_imem_bits_data_0[15:0]; // @[IBuf.scala:21:7, :69:87] wire [31:0] _icData_T_1 = {2{_icData_T}}; // @[IBuf.scala:69:{57,87}] wire [63:0] _icData_T_2 = {io_imem_bits_data_0, _icData_T_1}; // @[IBuf.scala:21:7, :69:{33,57}] wire [15:0] _icData_data_T = _icData_T_2[63:48]; // @[IBuf.scala:69:33, :120:58] wire [31:0] _icData_data_T_1 = {2{_icData_data_T}}; // @[IBuf.scala:120:{24,58}] wire [63:0] _icData_data_T_2 = {2{_icData_data_T_1}}; // @[IBuf.scala:120:24] wire [127:0] icData_data = {_icData_data_T_2, _icData_T_2}; // @[IBuf.scala:69:33, :120:{19,24}] wire [5:0] _icData_T_3 = {icShiftAmt, 4'h0}; // @[IBuf.scala:68:59, :121:19] wire [190:0] _icData_T_4 = {63'h0, icData_data} << _icData_T_3; // @[IBuf.scala:120:19, :121:{10,19}] wire [31:0] icData = _icData_T_4[95:64]; // @[package.scala:163:13] wire [4:0] _icMask_T_1 = {nBufValid, 4'h0}; // @[IBuf.scala:34:47, :71:65] wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << _icMask_T_1; // @[IBuf.scala:71:{51,65}] wire [31:0] icMask = _icMask_T_2[31:0]; // @[IBuf.scala:71:{51,92}] wire [31:0] _inst_T = icData & icMask; // @[package.scala:163:13] wire [31:0] _inst_T_1 = ~icMask; // @[IBuf.scala:71:92, :72:43] wire [31:0] _inst_T_2 = buf_data & _inst_T_1; // @[IBuf.scala:35:16, :72:{41,43}] assign inst = _inst_T | _inst_T_2; // @[IBuf.scala:72:{21,30,41}] assign io_inst_0_bits_raw_0 = inst; // @[IBuf.scala:21:7, :72:30] wire [3:0] _valid_T = 4'h1 << nValid; // @[OneHot.scala:58:35] wire [4:0] _valid_T_1 = {1'h0, _valid_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _valid_T_2 = _valid_T_1[3:0]; // @[IBuf.scala:74:33] wire [1:0] valid = _valid_T_2[1:0]; // @[IBuf.scala:74:{33,39}] wire [1:0] _io_inst_0_valid_T = valid; // @[IBuf.scala:74:39, :94:32] wire [1:0] _bufMask_T = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [2:0] _bufMask_T_1 = {1'h0, _bufMask_T} - 3'h1; // @[OneHot.scala:58:35] wire [1:0] bufMask = _bufMask_T_1[1:0]; // @[IBuf.scala:75:37] wire _xcpt_T = bufMask[0]; // @[IBuf.scala:75:37, :76:61] wire xcpt_0_pf_inst = _xcpt_T ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_0_gf_inst = _xcpt_T ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_0_ae_inst = _xcpt_T ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] assign _io_inst_0_bits_xcpt0_T_1_pf_inst = xcpt_0_pf_inst; // @[package.scala:39:76] assign _io_inst_0_bits_xcpt0_T_1_gf_inst = xcpt_0_gf_inst; // @[package.scala:39:76] assign _io_inst_0_bits_xcpt0_T_1_ae_inst = xcpt_0_ae_inst; // @[package.scala:39:76] wire _xcpt_T_1 = bufMask[1]; // @[IBuf.scala:75:37, :76:61] wire xcpt_1_pf_inst = _xcpt_T_1 ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_1_gf_inst = _xcpt_T_1 ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_1_ae_inst = _xcpt_T_1 ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire _io_inst_0_bits_xcpt1_T_3_pf_inst = xcpt_1_pf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_T_3_gf_inst = xcpt_1_gf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_T_3_ae_inst = xcpt_1_ae_inst; // @[package.scala:39:76] wire [1:0] buf_replay_0 = buf_replay ? bufMask : 2'h0; // @[IBuf.scala:35:16, :75:37, :77:23] wire [1:0] _full_insn_T_5 = buf_replay_0; // @[IBuf.scala:77:23, :93:63] wire [1:0] _ic_replay_T = ~bufMask; // @[IBuf.scala:75:37, :78:65] wire [1:0] _ic_replay_T_1 = valid & _ic_replay_T; // @[IBuf.scala:74:39, :78:{63,65}] wire [1:0] _ic_replay_T_2 = io_imem_bits_replay_0 ? _ic_replay_T_1 : 2'h0; // @[IBuf.scala:21:7, :78:{35,63}] wire [1:0] ic_replay = buf_replay_0 | _ic_replay_T_2; // @[IBuf.scala:77:23, :78:{30,35}] wire [1:0] _replay_T = ic_replay; // @[IBuf.scala:78:30, :92:29]

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_76 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}} wire _in_flight_WIRE : UInt<1>[5] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = or(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_16 = or(_T_15, UInt<1>(0h0)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_21 = or(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_21, UInt<1>(0h1), "") : assert_4 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_28 = and(_T_26, _T_27) node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_32 = and(_T_30, _T_31) node _T_33 = or(_T_25, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_33, UInt<1>(0h1), "") : assert_5

module NoCMonitor_76( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to this FIRRTL code module TLXbar_prcibus_i1_o2_a21d64s10k1z3u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_109 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<10>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<10>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<10>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 9, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<21>(0h0) connect _WIRE_30.bits.source, UInt<10>(0h0) connect _WIRE_30.bits.size, UInt<3>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<21>(0h0) connect _WIRE_32.bits.source, UInt<10>(0h0) connect _WIRE_32.bits.size, UInt<3>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<21>(0h0) connect _WIRE_34.bits.source, UInt<10>(0h0) connect _WIRE_34.bits.size, UInt<3>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<21>(0h0) connect _WIRE_36.bits.source, UInt<10>(0h0) connect _WIRE_36.bits.size, UInt<3>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<21>(0h0) connect _WIRE_38.bits.source, UInt<10>(0h0) connect _WIRE_38.bits.size, UInt<3>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<21>(0h0) connect _WIRE_48.bits.source, UInt<10>(0h0) connect _WIRE_48.bits.size, UInt<3>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<21>(0h0) connect _WIRE_50.bits.source, UInt<10>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<21>(0h0) connect _WIRE_52.bits.source, UInt<10>(0h0) connect _WIRE_52.bits.size, UInt<3>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<21>(0h0) connect _WIRE_54.bits.source, UInt<10>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<21>(0h0) connect _WIRE_56.bits.source, UInt<10>(0h0) connect _WIRE_56.bits.size, UInt<3>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<21>(0h0) connect _WIRE_58.bits.source, UInt<10>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<21>(0h0) connect _WIRE_60.bits.source, UInt<10>(0h0) connect _WIRE_60.bits.size, UInt<3>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<21>(0h0) connect _WIRE_62.bits.source, UInt<10>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<21>(0h0) connect _addressC_WIRE.bits.source, UInt<10>(0h0) connect _addressC_WIRE.bits.size, UInt<3>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<18>(0h10000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<18>(0h10000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<21>(0h0) connect _requestBOI_WIRE.bits.source, UInt<10>(0h0) connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<10>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 9, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 10) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<10>(0h3ff)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<21>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<10>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<10>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 9, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 10) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<10>(0h3ff)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<10>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 9, 0) node _requestDOI_T = shr(out[0].d.bits.source, 10) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<10>(0h3ff)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<10>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 9, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 10) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<10>(0h3ff)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<21>(0h0) connect _beatsBO_WIRE.bits.source, UInt<10>(0h0) connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<21>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<10>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<21>(0h0) connect _beatsCI_WIRE.bits.source, UInt<10>(0h0) connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<21>(0h0) connect _portsBIO_WIRE.bits.source, UInt<10>(0h0) connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<21>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<10>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<21>(0h0) connect _portsCOI_WIRE.bits.source, UInt<10>(0h0) connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<21>(0h0) connect _WIRE_72.bits.source, UInt<10>(0h0) connect _WIRE_72.bits.size, UInt<3>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.address, UInt<21>(0h0) connect _WIRE_76.bits.source, UInt<10>(0h0) connect _WIRE_76.bits.size, UInt<3>(0h0) connect _WIRE_76.bits.param, UInt<3>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_78.bits.sink, UInt<1>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.mask, UInt<8>(0h0) connect _WIRE_80.bits.address, UInt<21>(0h0) connect _WIRE_80.bits.source, UInt<10>(0h0) connect _WIRE_80.bits.size, UInt<3>(0h0) connect _WIRE_80.bits.param, UInt<2>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.mask invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<10> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<3> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)

module TLXbar_prcibus_i1_o2_a21d64s10k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire [9:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [9:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [63:0] auto_anon_out_1_d_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] out_1_d_bits_data = 64'h0; // @[Xbar.scala:216:19] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _in_0_d_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_WIRE_param = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_denied = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _out_1_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_WIRE_sink = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_denied = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_10 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_11 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_6 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [20:0] _addressC_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _addressC_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _requestCIO_T = 21'h0; // @[Parameters.scala:137:31] wire [20:0] _requestCIO_T_5 = 21'h0; // @[Parameters.scala:137:31] wire [20:0] _requestBOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _requestBOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _requestBOI_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _requestBOI_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsBO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _beatsBO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsBO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _beatsBO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsCI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _beatsCI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _portsBIO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _portsBIO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] portsBIO_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] _portsBIO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _portsBIO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] portsBIO_filtered_1_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] _portsCOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _portsCOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] portsCOI_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] portsCOI_filtered_1_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [9:0] _addressC_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _addressC_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _requestBOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _requestBOI_uncommonBits_T = 10'h0; // @[Parameters.scala:52:29] wire [9:0] requestBOI_uncommonBits = 10'h0; // @[Parameters.scala:52:56] wire [9:0] _requestBOI_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _requestBOI_uncommonBits_T_1 = 10'h0; // @[Parameters.scala:52:29] wire [9:0] requestBOI_uncommonBits_1 = 10'h0; // @[Parameters.scala:52:56] wire [9:0] _beatsBO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _beatsBO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsBO_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _beatsBO_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsCI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _beatsCI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _portsBIO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _portsBIO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] portsBIO_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsBIO_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _portsBIO_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] portsBIO_filtered_1_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsCOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _portsCOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] portsCOI_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] portsCOI_filtered_1_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [21:0] _requestCIO_T_1 = 22'h0; // @[Parameters.scala:137:41] wire [21:0] _requestCIO_T_2 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_3 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_6 = 22'h0; // @[Parameters.scala:137:41] wire [21:0] _requestCIO_T_7 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_8 = 22'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [9:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [9:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [20:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [9:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [9:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [20:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [20:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [20:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [9:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [9:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [9:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [21:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] _requestAIO_T_2 = _requestAIO_T_1 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 22'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [20:0] _requestAIO_T_5 = {in_0_a_bits_address[20:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [21:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [21:0] _requestAIO_T_7 = _requestAIO_T_6 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 22'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [9:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [9:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to this FIRRTL code module PE_402 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_146 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_402( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_146 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module FlitToPhit_f32_p32 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}} reg data : UInt<32>[0], clock regreset beat : UInt<0>, clock, reset, UInt<0>(0h0) node _io_in_ready_T = eq(beat, UInt<1>(0h0)) node _io_in_ready_T_1 = and(io.out.ready, _io_in_ready_T) connect io.in.ready, _io_in_ready_T_1 node _io_out_valid_T = neq(beat, UInt<1>(0h0)) node _io_out_valid_T_1 = or(io.in.valid, _io_out_valid_T) connect io.out.valid, _io_out_valid_T_1 connect io.out.bits.phit, io.in.bits.flit node _T = and(io.out.ready, io.out.valid) when _T : node _beat_T = eq(beat, UInt<1>(0h0)) node _beat_T_1 = add(beat, UInt<1>(0h1)) node _beat_T_2 = tail(_beat_T_1, 1) node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2) connect beat, _beat_T_3 node _T_1 = eq(beat, UInt<1>(0h0)) when _T_1 : wire _WIRE : UInt<32>[1] wire _WIRE_1 : UInt<32> connect _WIRE_1, io.in.bits.flit node _T_2 = bits(_WIRE_1, 31, 0) connect _WIRE[0], _T_2

module FlitToPhit_f32_p32( // @[Serdes.scala:71:7] input clock, // @[Serdes.scala:71:7] input reset, // @[Serdes.scala:71:7] output io_in_ready, // @[Serdes.scala:73:14] input io_in_valid, // @[Serdes.scala:73:14] input [31:0] io_in_bits_flit, // @[Serdes.scala:73:14] input io_out_ready, // @[Serdes.scala:73:14] output io_out_valid, // @[Serdes.scala:73:14] output [31:0] io_out_bits_phit // @[Serdes.scala:73:14] ); wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:71:7] wire [31:0] io_in_bits_flit_0 = io_in_bits_flit; // @[Serdes.scala:71:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:71:7] wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T = 1'h1; // @[Serdes.scala:83:39] wire _beat_T = 1'h1; // @[Serdes.scala:88:22] wire _beat_T_2 = 1'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T_1; // @[Serdes.scala:83:31] wire _io_out_valid_T = 1'h0; // @[Serdes.scala:84:39] wire _beat_T_3 = 1'h0; // @[Serdes.scala:88:16] wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:71:7, :84:31] wire [31:0] io_out_bits_phit_0 = io_in_bits_flit_0; // @[Serdes.scala:71:7] assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:71:7, :83:31] wire io_in_ready_0; // @[Serdes.scala:71:7] wire io_out_valid_0; // @[Serdes.scala:71:7] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:71:7, :83:31] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:71:7, :84:31] assign io_in_ready = io_in_ready_0; // @[Serdes.scala:71:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:71:7] assign io_out_bits_phit = io_out_bits_phit_0; // @[Serdes.scala:71:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_8 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<15>(0h4000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<13>(0h1000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<18>(0h2f000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<27>(0h4000000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_38, _T_43) node _T_85 = or(_T_84, _T_48) node _T_86 = or(_T_85, _T_53) node _T_87 = or(_T_86, _T_58) node _T_88 = or(_T_87, _T_63) node _T_89 = or(_T_88, _T_68) node _T_90 = or(_T_89, _T_73) node _T_91 = or(_T_90, _T_78) node _T_92 = or(_T_91, _T_83) node _T_93 = and(_T_33, _T_92) node _T_94 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_95 = or(UInt<1>(0h0), _T_94) node _T_96 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<17>(0h10000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<29>(0h10000000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = or(_T_100, _T_105) node _T_107 = and(_T_95, _T_106) node _T_108 = or(UInt<1>(0h0), _T_93) node _T_109 = or(_T_108, _T_107) node _T_110 = and(_T_32, _T_109) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_110, UInt<1>(0h1), "") : assert_2 node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_115 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_114 connect _WIRE[1], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = or(_T_117, _T_118) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_119 node _T_120 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_121 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_122 = and(_T_120, _T_121) node _T_123 = or(UInt<1>(0h0), _T_122) node _T_124 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_125 = cvt(_T_124) node _T_126 = and(_T_125, asSInt(UInt<14>(0h2000))) node _T_127 = asSInt(_T_126) node _T_128 = eq(_T_127, asSInt(UInt<1>(0h0))) node _T_129 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_130 = cvt(_T_129) node _T_131 = and(_T_130, asSInt(UInt<13>(0h1000))) node _T_132 = asSInt(_T_131) node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0))) node _T_134 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<17>(0h10000))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<15>(0h4000))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<13>(0h1000))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<18>(0h2f000))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<17>(0h10000))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<13>(0h1000))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<17>(0h10000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<27>(0h4000000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<13>(0h1000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<29>(0h10000000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = or(_T_128, _T_133) node _T_185 = or(_T_184, _T_138) node _T_186 = or(_T_185, _T_143) node _T_187 = or(_T_186, _T_148) node _T_188 = or(_T_187, _T_153) node _T_189 = or(_T_188, _T_158) node _T_190 = or(_T_189, _T_163) node _T_191 = or(_T_190, _T_168) node _T_192 = or(_T_191, _T_173) node _T_193 = or(_T_192, _T_178) node _T_194 = or(_T_193, _T_183) node _T_195 = and(_T_123, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = and(_WIRE_1, _T_196) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_197, UInt<1>(0h1), "") : assert_3 node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(source_ok, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_204 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_204, UInt<1>(0h1), "") : assert_5 node _T_208 = asUInt(reset) node _T_209 = eq(_T_208, UInt<1>(0h0)) when _T_209 : node _T_210 = eq(is_aligned, UInt<1>(0h0)) when _T_210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_211 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_211, UInt<1>(0h1), "") : assert_7 node _T_215 = not(io.in.a.bits.mask) node _T_216 = eq(_T_215, UInt<1>(0h0)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_216, UInt<1>(0h1), "") : assert_8 node _T_220 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_220, UInt<1>(0h1), "") : assert_9 node _T_224 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_224 : node _T_225 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_226 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_229 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_230 = or(_T_228, _T_229) node _T_231 = and(_T_227, _T_230) node _T_232 = or(UInt<1>(0h0), _T_231) node _T_233 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_240 = cvt(_T_239) node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000))) node _T_242 = asSInt(_T_241) node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0))) node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_245 = cvt(_T_244) node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000))) node _T_247 = asSInt(_T_246) node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0))) node _T_249 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<15>(0h4000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<13>(0h1000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<18>(0h2f000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<17>(0h10000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<27>(0h4000000))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<13>(0h1000))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = or(_T_238, _T_243) node _T_285 = or(_T_284, _T_248) node _T_286 = or(_T_285, _T_253) node _T_287 = or(_T_286, _T_258) node _T_288 = or(_T_287, _T_263) node _T_289 = or(_T_288, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = and(_T_233, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_232, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _T_314 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_314 connect _WIRE_2[1], _T_315 node _T_316 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_317 = mux(_WIRE_2[0], _T_316, UInt<1>(0h0)) node _T_318 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = or(_T_317, _T_318) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_319 node _T_320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_322 = and(_T_320, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<14>(0h2000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<13>(0h1000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<15>(0h4000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<18>(0h2f000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<17>(0h10000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<13>(0h1000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_365 = cvt(_T_364) node _T_366 = and(_T_365, asSInt(UInt<17>(0h10000))) node _T_367 = asSInt(_T_366) node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0))) node _T_369 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<27>(0h4000000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<13>(0h1000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<29>(0h10000000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = or(_T_328, _T_333) node _T_385 = or(_T_384, _T_338) node _T_386 = or(_T_385, _T_343) node _T_387 = or(_T_386, _T_348) node _T_388 = or(_T_387, _T_353) node _T_389 = or(_T_388, _T_358) node _T_390 = or(_T_389, _T_363) node _T_391 = or(_T_390, _T_368) node _T_392 = or(_T_391, _T_373) node _T_393 = or(_T_392, _T_378) node _T_394 = or(_T_393, _T_383) node _T_395 = and(_T_323, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = and(_WIRE_3, _T_396) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_397, UInt<1>(0h1), "") : assert_11 node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(source_ok, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_404 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_404, UInt<1>(0h1), "") : assert_13 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(is_aligned, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_411 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_411, UInt<1>(0h1), "") : assert_15 node _T_415 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_415, UInt<1>(0h1), "") : assert_16 node _T_419 = not(io.in.a.bits.mask) node _T_420 = eq(_T_419, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_420, UInt<1>(0h1), "") : assert_17 node _T_424 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_424, UInt<1>(0h1), "") : assert_18 node _T_428 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_428 : node _T_429 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_430 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_433 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_434 = or(_T_432, _T_433) node _T_435 = and(_T_431, _T_434) node _T_436 = or(UInt<1>(0h0), _T_435) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_436, UInt<1>(0h1), "") : assert_19 node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_442 = and(_T_440, _T_441) node _T_443 = or(UInt<1>(0h0), _T_442) node _T_444 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<13>(0h1000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = and(_T_443, _T_448) node _T_450 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_451 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_452 = and(_T_450, _T_451) node _T_453 = or(UInt<1>(0h0), _T_452) node _T_454 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<14>(0h2000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_460 = cvt(_T_459) node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000))) node _T_462 = asSInt(_T_461) node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0))) node _T_464 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_465 = cvt(_T_464) node _T_466 = and(_T_465, asSInt(UInt<18>(0h2f000))) node _T_467 = asSInt(_T_466) node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0))) node _T_469 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_470 = cvt(_T_469) node _T_471 = and(_T_470, asSInt(UInt<17>(0h10000))) node _T_472 = asSInt(_T_471) node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0))) node _T_474 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_475 = cvt(_T_474) node _T_476 = and(_T_475, asSInt(UInt<13>(0h1000))) node _T_477 = asSInt(_T_476) node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0))) node _T_479 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_480 = cvt(_T_479) node _T_481 = and(_T_480, asSInt(UInt<17>(0h10000))) node _T_482 = asSInt(_T_481) node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0))) node _T_484 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_485 = cvt(_T_484) node _T_486 = and(_T_485, asSInt(UInt<27>(0h4000000))) node _T_487 = asSInt(_T_486) node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0))) node _T_489 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_490 = cvt(_T_489) node _T_491 = and(_T_490, asSInt(UInt<13>(0h1000))) node _T_492 = asSInt(_T_491) node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0))) node _T_494 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<29>(0h10000000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = or(_T_458, _T_463) node _T_500 = or(_T_499, _T_468) node _T_501 = or(_T_500, _T_473) node _T_502 = or(_T_501, _T_478) node _T_503 = or(_T_502, _T_483) node _T_504 = or(_T_503, _T_488) node _T_505 = or(_T_504, _T_493) node _T_506 = or(_T_505, _T_498) node _T_507 = and(_T_453, _T_506) node _T_508 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_509 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_510 = and(_T_508, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<15>(0h4000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = or(_T_516, _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = or(UInt<1>(0h0), _T_449) node _T_525 = or(_T_524, _T_507) node _T_526 = or(_T_525, _T_523) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_526, UInt<1>(0h1), "") : assert_20 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(source_ok, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(is_aligned, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_536 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(_T_536, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_536, UInt<1>(0h1), "") : assert_23 node _T_540 = eq(io.in.a.bits.mask, mask) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_540, UInt<1>(0h1), "") : assert_24 node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_544, UInt<1>(0h1), "") : assert_25 node _T_548 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_553 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_554 = or(_T_552, _T_553) node _T_555 = and(_T_551, _T_554) node _T_556 = or(UInt<1>(0h0), _T_555) node _T_557 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_558 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_559 = and(_T_557, _T_558) node _T_560 = or(UInt<1>(0h0), _T_559) node _T_561 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<13>(0h1000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = and(_T_560, _T_565) node _T_567 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_568 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_569 = and(_T_567, _T_568) node _T_570 = or(UInt<1>(0h0), _T_569) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<14>(0h2000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<18>(0h2f000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<17>(0h10000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<13>(0h1000))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<17>(0h10000))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<27>(0h4000000))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_602 = cvt(_T_601) node _T_603 = and(_T_602, asSInt(UInt<13>(0h1000))) node _T_604 = asSInt(_T_603) node _T_605 = eq(_T_604, asSInt(UInt<1>(0h0))) node _T_606 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_607 = cvt(_T_606) node _T_608 = and(_T_607, asSInt(UInt<29>(0h10000000))) node _T_609 = asSInt(_T_608) node _T_610 = eq(_T_609, asSInt(UInt<1>(0h0))) node _T_611 = or(_T_575, _T_580) node _T_612 = or(_T_611, _T_585) node _T_613 = or(_T_612, _T_590) node _T_614 = or(_T_613, _T_595) node _T_615 = or(_T_614, _T_600) node _T_616 = or(_T_615, _T_605) node _T_617 = or(_T_616, _T_610) node _T_618 = and(_T_570, _T_617) node _T_619 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_620 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<15>(0h4000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = or(_T_634, _T_639) node _T_641 = and(_T_629, _T_640) node _T_642 = or(UInt<1>(0h0), _T_566) node _T_643 = or(_T_642, _T_618) node _T_644 = or(_T_643, _T_625) node _T_645 = or(_T_644, _T_641) node _T_646 = and(_T_556, _T_645) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_646, UInt<1>(0h1), "") : assert_26 node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(source_ok, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(is_aligned, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_656 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_657 = asUInt(reset) node _T_658 = eq(_T_657, UInt<1>(0h0)) when _T_658 : node _T_659 = eq(_T_656, UInt<1>(0h0)) when _T_659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_656, UInt<1>(0h1), "") : assert_29 node _T_660 = eq(io.in.a.bits.mask, mask) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_660, UInt<1>(0h1), "") : assert_30 node _T_664 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_664 : node _T_665 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_666 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_667 = and(_T_665, _T_666) node _T_668 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_669 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_670 = or(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) node _T_672 = or(UInt<1>(0h0), _T_671) node _T_673 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_674 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_675 = and(_T_673, _T_674) node _T_676 = or(UInt<1>(0h0), _T_675) node _T_677 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<13>(0h1000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = and(_T_676, _T_681) node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_685 = and(_T_683, _T_684) node _T_686 = or(UInt<1>(0h0), _T_685) node _T_687 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_688 = cvt(_T_687) node _T_689 = and(_T_688, asSInt(UInt<14>(0h2000))) node _T_690 = asSInt(_T_689) node _T_691 = eq(_T_690, asSInt(UInt<1>(0h0))) node _T_692 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_693 = cvt(_T_692) node _T_694 = and(_T_693, asSInt(UInt<18>(0h2f000))) node _T_695 = asSInt(_T_694) node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0))) node _T_697 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_698 = cvt(_T_697) node _T_699 = and(_T_698, asSInt(UInt<17>(0h10000))) node _T_700 = asSInt(_T_699) node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0))) node _T_702 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_703 = cvt(_T_702) node _T_704 = and(_T_703, asSInt(UInt<13>(0h1000))) node _T_705 = asSInt(_T_704) node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0))) node _T_707 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_708 = cvt(_T_707) node _T_709 = and(_T_708, asSInt(UInt<17>(0h10000))) node _T_710 = asSInt(_T_709) node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0))) node _T_712 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_713 = cvt(_T_712) node _T_714 = and(_T_713, asSInt(UInt<27>(0h4000000))) node _T_715 = asSInt(_T_714) node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0))) node _T_717 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_718 = cvt(_T_717) node _T_719 = and(_T_718, asSInt(UInt<13>(0h1000))) node _T_720 = asSInt(_T_719) node _T_721 = eq(_T_720, asSInt(UInt<1>(0h0))) node _T_722 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_723 = cvt(_T_722) node _T_724 = and(_T_723, asSInt(UInt<29>(0h10000000))) node _T_725 = asSInt(_T_724) node _T_726 = eq(_T_725, asSInt(UInt<1>(0h0))) node _T_727 = or(_T_691, _T_696) node _T_728 = or(_T_727, _T_701) node _T_729 = or(_T_728, _T_706) node _T_730 = or(_T_729, _T_711) node _T_731 = or(_T_730, _T_716) node _T_732 = or(_T_731, _T_721) node _T_733 = or(_T_732, _T_726) node _T_734 = and(_T_686, _T_733) node _T_735 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_736 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = and(_T_735, _T_740) node _T_742 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_743 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_744 = and(_T_742, _T_743) node _T_745 = or(UInt<1>(0h0), _T_744) node _T_746 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<15>(0h4000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = or(_T_750, _T_755) node _T_757 = and(_T_745, _T_756) node _T_758 = or(UInt<1>(0h0), _T_682) node _T_759 = or(_T_758, _T_734) node _T_760 = or(_T_759, _T_741) node _T_761 = or(_T_760, _T_757) node _T_762 = and(_T_672, _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_762, UInt<1>(0h1), "") : assert_31 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(source_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(is_aligned, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_772 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_772, UInt<1>(0h1), "") : assert_34 node _T_776 = not(mask) node _T_777 = and(io.in.a.bits.mask, _T_776) node _T_778 = eq(_T_777, UInt<1>(0h0)) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_778, UInt<1>(0h1), "") : assert_35 node _T_782 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_782 : node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_785 = and(_T_783, _T_784) node _T_786 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_787 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_788 = or(_T_786, _T_787) node _T_789 = and(_T_785, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<15>(0h4000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<18>(0h2f000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<17>(0h10000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<27>(0h4000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<29>(0h10000000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = or(_T_799, _T_804) node _T_851 = or(_T_850, _T_809) node _T_852 = or(_T_851, _T_814) node _T_853 = or(_T_852, _T_819) node _T_854 = or(_T_853, _T_824) node _T_855 = or(_T_854, _T_829) node _T_856 = or(_T_855, _T_834) node _T_857 = or(_T_856, _T_839) node _T_858 = or(_T_857, _T_844) node _T_859 = or(_T_858, _T_849) node _T_860 = and(_T_794, _T_859) node _T_861 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_862 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_863 = cvt(_T_862) node _T_864 = and(_T_863, asSInt(UInt<17>(0h10000))) node _T_865 = asSInt(_T_864) node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0))) node _T_867 = and(_T_861, _T_866) node _T_868 = or(UInt<1>(0h0), _T_860) node _T_869 = or(_T_868, _T_867) node _T_870 = and(_T_790, _T_869) node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(_T_870, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_870, UInt<1>(0h1), "") : assert_36 node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(source_ok, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(is_aligned, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_880 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_880, UInt<1>(0h1), "") : assert_39 node _T_884 = eq(io.in.a.bits.mask, mask) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_884, UInt<1>(0h1), "") : assert_40 node _T_888 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_888 : node _T_889 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_890 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_891 = and(_T_889, _T_890) node _T_892 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_893 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_894 = or(_T_892, _T_893) node _T_895 = and(_T_891, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_898 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_899 = and(_T_897, _T_898) node _T_900 = or(UInt<1>(0h0), _T_899) node _T_901 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<14>(0h2000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<13>(0h1000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<15>(0h4000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<13>(0h1000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<18>(0h2f000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_927 = cvt(_T_926) node _T_928 = and(_T_927, asSInt(UInt<17>(0h10000))) node _T_929 = asSInt(_T_928) node _T_930 = eq(_T_929, asSInt(UInt<1>(0h0))) node _T_931 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_932 = cvt(_T_931) node _T_933 = and(_T_932, asSInt(UInt<13>(0h1000))) node _T_934 = asSInt(_T_933) node _T_935 = eq(_T_934, asSInt(UInt<1>(0h0))) node _T_936 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_937 = cvt(_T_936) node _T_938 = and(_T_937, asSInt(UInt<17>(0h10000))) node _T_939 = asSInt(_T_938) node _T_940 = eq(_T_939, asSInt(UInt<1>(0h0))) node _T_941 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_942 = cvt(_T_941) node _T_943 = and(_T_942, asSInt(UInt<27>(0h4000000))) node _T_944 = asSInt(_T_943) node _T_945 = eq(_T_944, asSInt(UInt<1>(0h0))) node _T_946 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_947 = cvt(_T_946) node _T_948 = and(_T_947, asSInt(UInt<13>(0h1000))) node _T_949 = asSInt(_T_948) node _T_950 = eq(_T_949, asSInt(UInt<1>(0h0))) node _T_951 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<29>(0h10000000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = or(_T_905, _T_910) node _T_957 = or(_T_956, _T_915) node _T_958 = or(_T_957, _T_920) node _T_959 = or(_T_958, _T_925) node _T_960 = or(_T_959, _T_930) node _T_961 = or(_T_960, _T_935) node _T_962 = or(_T_961, _T_940) node _T_963 = or(_T_962, _T_945) node _T_964 = or(_T_963, _T_950) node _T_965 = or(_T_964, _T_955) node _T_966 = and(_T_900, _T_965) node _T_967 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_968 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = and(_T_967, _T_972) node _T_974 = or(UInt<1>(0h0), _T_966) node _T_975 = or(_T_974, _T_973) node _T_976 = and(_T_896, _T_975) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_976, UInt<1>(0h1), "") : assert_41 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(is_aligned, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_986 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_986, UInt<1>(0h1), "") : assert_44 node _T_990 = eq(io.in.a.bits.mask, mask) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_990, UInt<1>(0h1), "") : assert_45 node _T_994 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_994 : node _T_995 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_996 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_997 = and(_T_995, _T_996) node _T_998 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_999 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_1000 = or(_T_998, _T_999) node _T_1001 = and(_T_997, _T_1000) node _T_1002 = or(UInt<1>(0h0), _T_1001) node _T_1003 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1004 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = or(UInt<1>(0h0), _T_1005) node _T_1007 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = and(_T_1006, _T_1011) node _T_1013 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1014 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<14>(0h2000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1020 = cvt(_T_1019) node _T_1021 = and(_T_1020, asSInt(UInt<17>(0h10000))) node _T_1022 = asSInt(_T_1021) node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0))) node _T_1024 = xor(io.in.a.bits.address, UInt<18>(0h20000)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<15>(0h4000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = xor(io.in.a.bits.address, UInt<18>(0h24000)) node _T_1030 = cvt(_T_1029) node _T_1031 = and(_T_1030, asSInt(UInt<13>(0h1000))) node _T_1032 = asSInt(_T_1031) node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0))) node _T_1034 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1035 = cvt(_T_1034) node _T_1036 = and(_T_1035, asSInt(UInt<18>(0h2f000))) node _T_1037 = asSInt(_T_1036) node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0))) node _T_1039 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1040 = cvt(_T_1039) node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000))) node _T_1042 = asSInt(_T_1041) node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) node _T_1044 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1045 = cvt(_T_1044) node _T_1046 = and(_T_1045, asSInt(UInt<13>(0h1000))) node _T_1047 = asSInt(_T_1046) node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) node _T_1049 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1050 = cvt(_T_1049) node _T_1051 = and(_T_1050, asSInt(UInt<27>(0h4000000))) node _T_1052 = asSInt(_T_1051) node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1055 = cvt(_T_1054) node _T_1056 = and(_T_1055, asSInt(UInt<13>(0h1000))) node _T_1057 = asSInt(_T_1056) node _T_1058 = eq(_T_1057, asSInt(UInt<1>(0h0))) node _T_1059 = or(_T_1018, _T_1023) node _T_1060 = or(_T_1059, _T_1028) node _T_1061 = or(_T_1060, _T_1033) node _T_1062 = or(_T_1061, _T_1038) node _T_1063 = or(_T_1062, _T_1043) node _T_1064 = or(_T_1063, _T_1048) node _T_1065 = or(_T_1064, _T_1053) node _T_1066 = or(_T_1065, _T_1058) node _T_1067 = and(_T_1013, _T_1066) node _T_1068 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1069 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = or(UInt<1>(0h0), _T_1070) node _T_1072 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1073 = cvt(_T_1072) node _T_1074 = and(_T_1073, asSInt(UInt<17>(0h10000))) node _T_1075 = asSInt(_T_1074) node _T_1076 = eq(_T_1075, asSInt(UInt<1>(0h0))) node _T_1077 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1078 = cvt(_T_1077) node _T_1079 = and(_T_1078, asSInt(UInt<29>(0h10000000))) node _T_1080 = asSInt(_T_1079) node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0))) node _T_1082 = or(_T_1076, _T_1081) node _T_1083 = and(_T_1071, _T_1082) node _T_1084 = or(UInt<1>(0h0), _T_1012) node _T_1085 = or(_T_1084, _T_1067) node _T_1086 = or(_T_1085, _T_1083) node _T_1087 = and(_T_1002, _T_1086) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_46 node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(is_aligned, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1097 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_49 node _T_1101 = eq(io.in.a.bits.mask, mask) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_50 node _T_1105 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1109 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1113 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1113 : node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(source_ok_1, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1117 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_54 node _T_1121 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_55 node _T_1125 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_56 node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_57 node _T_1133 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1133 : node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(source_ok_1, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(sink_ok, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1140 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_60 node _T_1144 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_61 node _T_1148 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_62 node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_63 node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1157 = or(UInt<1>(0h1), _T_1156) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_64 node _T_1161 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1161 : node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(source_ok_1, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(sink_ok, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1168 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_67 node _T_1172 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_68 node _T_1176 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_69 node _T_1180 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1181 = or(_T_1180, io.in.d.bits.corrupt) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_70 node _T_1185 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1186 = or(UInt<1>(0h1), _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_71 node _T_1190 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1190 : node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(source_ok_1, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1194 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_73 node _T_1198 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_74 node _T_1202 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1203 = or(UInt<1>(0h1), _T_1202) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_75 node _T_1207 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1207 : node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(source_ok_1, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1211 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_77 node _T_1215 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1216 = or(_T_1215, io.in.d.bits.corrupt) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_78 node _T_1220 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1221 = or(UInt<1>(0h1), _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_79 node _T_1225 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1225 : node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(source_ok_1, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1229 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_81 node _T_1233 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_82 node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1238 = or(UInt<1>(0h1), _T_1237) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1242 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_84 node _T_1246 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) node _T_1248 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<1>(0h0))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = or(_T_1247, _T_1252) node _T_1254 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) node _T_1256 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1257 = cvt(_T_1256) node _T_1258 = and(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = asSInt(_T_1258) node _T_1260 = eq(_T_1259, asSInt(UInt<1>(0h0))) node _T_1261 = or(_T_1255, _T_1260) node _T_1262 = and(_T_1253, _T_1261) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<18>(0h21000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<18>(0h22000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<13>(0h1000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<18>(0h23000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<13>(0h1000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<13>(0h1000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<17>(0h10000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_61 = cvt(_address_ok_T_60) node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<13>(0h1000))) node _address_ok_T_63 = asSInt(_address_ok_T_62) node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0))) node _address_ok_T_65 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_66 = cvt(_address_ok_T_65) node _address_ok_T_67 = and(_address_ok_T_66, asSInt(UInt<17>(0h10000))) node _address_ok_T_68 = asSInt(_address_ok_T_67) node _address_ok_T_69 = eq(_address_ok_T_68, asSInt(UInt<1>(0h0))) node _address_ok_T_70 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<27>(0h4000000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<29>(0h10000000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[17] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 connect _address_ok_WIRE[12], _address_ok_T_64 connect _address_ok_WIRE[13], _address_ok_T_69 connect _address_ok_WIRE[14], _address_ok_T_74 connect _address_ok_WIRE[15], _address_ok_T_79 connect _address_ok_WIRE[16], _address_ok_T_84 node _address_ok_T_85 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_86 = or(_address_ok_T_85, _address_ok_WIRE[2]) node _address_ok_T_87 = or(_address_ok_T_86, _address_ok_WIRE[3]) node _address_ok_T_88 = or(_address_ok_T_87, _address_ok_WIRE[4]) node _address_ok_T_89 = or(_address_ok_T_88, _address_ok_WIRE[5]) node _address_ok_T_90 = or(_address_ok_T_89, _address_ok_WIRE[6]) node _address_ok_T_91 = or(_address_ok_T_90, _address_ok_WIRE[7]) node _address_ok_T_92 = or(_address_ok_T_91, _address_ok_WIRE[8]) node _address_ok_T_93 = or(_address_ok_T_92, _address_ok_WIRE[9]) node _address_ok_T_94 = or(_address_ok_T_93, _address_ok_WIRE[10]) node _address_ok_T_95 = or(_address_ok_T_94, _address_ok_WIRE[11]) node _address_ok_T_96 = or(_address_ok_T_95, _address_ok_WIRE[12]) node _address_ok_T_97 = or(_address_ok_T_96, _address_ok_WIRE[13]) node _address_ok_T_98 = or(_address_ok_T_97, _address_ok_WIRE[14]) node _address_ok_T_99 = or(_address_ok_T_98, _address_ok_WIRE[15]) node address_ok = or(_address_ok_T_99, _address_ok_WIRE[16]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3) wire _legal_source_WIRE_1 : UInt<1> connect _legal_source_WIRE_1, _legal_source_T_4 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1266 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1266 : node _T_1267 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1268 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1267 connect _WIRE_4[1], _T_1268 node _T_1269 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1270 = mux(_WIRE_4[0], _T_1269, UInt<1>(0h0)) node _T_1271 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1272 = or(_T_1270, _T_1271) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1272 node _T_1273 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1274 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = or(UInt<1>(0h0), _T_1275) node _T_1277 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1278 = cvt(_T_1277) node _T_1279 = and(_T_1278, asSInt(UInt<14>(0h2000))) node _T_1280 = asSInt(_T_1279) node _T_1281 = eq(_T_1280, asSInt(UInt<1>(0h0))) node _T_1282 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<13>(0h1000))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1288 = cvt(_T_1287) node _T_1289 = and(_T_1288, asSInt(UInt<17>(0h10000))) node _T_1290 = asSInt(_T_1289) node _T_1291 = eq(_T_1290, asSInt(UInt<1>(0h0))) node _T_1292 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1293 = cvt(_T_1292) node _T_1294 = and(_T_1293, asSInt(UInt<15>(0h4000))) node _T_1295 = asSInt(_T_1294) node _T_1296 = eq(_T_1295, asSInt(UInt<1>(0h0))) node _T_1297 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<18>(0h2f000))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1308 = cvt(_T_1307) node _T_1309 = and(_T_1308, asSInt(UInt<17>(0h10000))) node _T_1310 = asSInt(_T_1309) node _T_1311 = eq(_T_1310, asSInt(UInt<1>(0h0))) node _T_1312 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1313 = cvt(_T_1312) node _T_1314 = and(_T_1313, asSInt(UInt<13>(0h1000))) node _T_1315 = asSInt(_T_1314) node _T_1316 = eq(_T_1315, asSInt(UInt<1>(0h0))) node _T_1317 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1318 = cvt(_T_1317) node _T_1319 = and(_T_1318, asSInt(UInt<17>(0h10000))) node _T_1320 = asSInt(_T_1319) node _T_1321 = eq(_T_1320, asSInt(UInt<1>(0h0))) node _T_1322 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1323 = cvt(_T_1322) node _T_1324 = and(_T_1323, asSInt(UInt<27>(0h4000000))) node _T_1325 = asSInt(_T_1324) node _T_1326 = eq(_T_1325, asSInt(UInt<1>(0h0))) node _T_1327 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1328 = cvt(_T_1327) node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000))) node _T_1330 = asSInt(_T_1329) node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) node _T_1332 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1333 = cvt(_T_1332) node _T_1334 = and(_T_1333, asSInt(UInt<29>(0h10000000))) node _T_1335 = asSInt(_T_1334) node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) node _T_1337 = or(_T_1281, _T_1286) node _T_1338 = or(_T_1337, _T_1291) node _T_1339 = or(_T_1338, _T_1296) node _T_1340 = or(_T_1339, _T_1301) node _T_1341 = or(_T_1340, _T_1306) node _T_1342 = or(_T_1341, _T_1311) node _T_1343 = or(_T_1342, _T_1316) node _T_1344 = or(_T_1343, _T_1321) node _T_1345 = or(_T_1344, _T_1326) node _T_1346 = or(_T_1345, _T_1331) node _T_1347 = or(_T_1346, _T_1336) node _T_1348 = and(_T_1276, _T_1347) node _T_1349 = or(UInt<1>(0h0), _T_1348) node _T_1350 = and(_WIRE_5, _T_1349) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_86 node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(address_ok, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(legal_source, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1363 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_90 node _T_1367 = eq(io.in.b.bits.mask, mask_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_91 node _T_1371 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_92 node _T_1375 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1375 : node _T_1376 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1377 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = or(UInt<1>(0h0), _T_1378) node _T_1380 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1381 = cvt(_T_1380) node _T_1382 = and(_T_1381, asSInt(UInt<14>(0h2000))) node _T_1383 = asSInt(_T_1382) node _T_1384 = eq(_T_1383, asSInt(UInt<1>(0h0))) node _T_1385 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1386 = cvt(_T_1385) node _T_1387 = and(_T_1386, asSInt(UInt<13>(0h1000))) node _T_1388 = asSInt(_T_1387) node _T_1389 = eq(_T_1388, asSInt(UInt<1>(0h0))) node _T_1390 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1391 = cvt(_T_1390) node _T_1392 = and(_T_1391, asSInt(UInt<17>(0h10000))) node _T_1393 = asSInt(_T_1392) node _T_1394 = eq(_T_1393, asSInt(UInt<1>(0h0))) node _T_1395 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1396 = cvt(_T_1395) node _T_1397 = and(_T_1396, asSInt(UInt<15>(0h4000))) node _T_1398 = asSInt(_T_1397) node _T_1399 = eq(_T_1398, asSInt(UInt<1>(0h0))) node _T_1400 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1401 = cvt(_T_1400) node _T_1402 = and(_T_1401, asSInt(UInt<13>(0h1000))) node _T_1403 = asSInt(_T_1402) node _T_1404 = eq(_T_1403, asSInt(UInt<1>(0h0))) node _T_1405 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1406 = cvt(_T_1405) node _T_1407 = and(_T_1406, asSInt(UInt<18>(0h2f000))) node _T_1408 = asSInt(_T_1407) node _T_1409 = eq(_T_1408, asSInt(UInt<1>(0h0))) node _T_1410 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1411 = cvt(_T_1410) node _T_1412 = and(_T_1411, asSInt(UInt<17>(0h10000))) node _T_1413 = asSInt(_T_1412) node _T_1414 = eq(_T_1413, asSInt(UInt<1>(0h0))) node _T_1415 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1416 = cvt(_T_1415) node _T_1417 = and(_T_1416, asSInt(UInt<13>(0h1000))) node _T_1418 = asSInt(_T_1417) node _T_1419 = eq(_T_1418, asSInt(UInt<1>(0h0))) node _T_1420 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1421 = cvt(_T_1420) node _T_1422 = and(_T_1421, asSInt(UInt<17>(0h10000))) node _T_1423 = asSInt(_T_1422) node _T_1424 = eq(_T_1423, asSInt(UInt<1>(0h0))) node _T_1425 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1426 = cvt(_T_1425) node _T_1427 = and(_T_1426, asSInt(UInt<27>(0h4000000))) node _T_1428 = asSInt(_T_1427) node _T_1429 = eq(_T_1428, asSInt(UInt<1>(0h0))) node _T_1430 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1431 = cvt(_T_1430) node _T_1432 = and(_T_1431, asSInt(UInt<13>(0h1000))) node _T_1433 = asSInt(_T_1432) node _T_1434 = eq(_T_1433, asSInt(UInt<1>(0h0))) node _T_1435 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<29>(0h10000000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = or(_T_1384, _T_1389) node _T_1441 = or(_T_1440, _T_1394) node _T_1442 = or(_T_1441, _T_1399) node _T_1443 = or(_T_1442, _T_1404) node _T_1444 = or(_T_1443, _T_1409) node _T_1445 = or(_T_1444, _T_1414) node _T_1446 = or(_T_1445, _T_1419) node _T_1447 = or(_T_1446, _T_1424) node _T_1448 = or(_T_1447, _T_1429) node _T_1449 = or(_T_1448, _T_1434) node _T_1450 = or(_T_1449, _T_1439) node _T_1451 = and(_T_1379, _T_1450) node _T_1452 = or(UInt<1>(0h0), _T_1451) node _T_1453 = and(UInt<1>(0h0), _T_1452) node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(_T_1453, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1453, UInt<1>(0h1), "") : assert_93 node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(address_ok, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(legal_source, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1466 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_97 node _T_1470 = eq(io.in.b.bits.mask, mask_1) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_98 node _T_1474 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(_T_1474, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1474, UInt<1>(0h1), "") : assert_99 node _T_1478 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1478 : node _T_1479 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1480 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1481 = and(_T_1479, _T_1480) node _T_1482 = or(UInt<1>(0h0), _T_1481) node _T_1483 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1484 = cvt(_T_1483) node _T_1485 = and(_T_1484, asSInt(UInt<14>(0h2000))) node _T_1486 = asSInt(_T_1485) node _T_1487 = eq(_T_1486, asSInt(UInt<1>(0h0))) node _T_1488 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1489 = cvt(_T_1488) node _T_1490 = and(_T_1489, asSInt(UInt<13>(0h1000))) node _T_1491 = asSInt(_T_1490) node _T_1492 = eq(_T_1491, asSInt(UInt<1>(0h0))) node _T_1493 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1494 = cvt(_T_1493) node _T_1495 = and(_T_1494, asSInt(UInt<17>(0h10000))) node _T_1496 = asSInt(_T_1495) node _T_1497 = eq(_T_1496, asSInt(UInt<1>(0h0))) node _T_1498 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1499 = cvt(_T_1498) node _T_1500 = and(_T_1499, asSInt(UInt<15>(0h4000))) node _T_1501 = asSInt(_T_1500) node _T_1502 = eq(_T_1501, asSInt(UInt<1>(0h0))) node _T_1503 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1504 = cvt(_T_1503) node _T_1505 = and(_T_1504, asSInt(UInt<13>(0h1000))) node _T_1506 = asSInt(_T_1505) node _T_1507 = eq(_T_1506, asSInt(UInt<1>(0h0))) node _T_1508 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1509 = cvt(_T_1508) node _T_1510 = and(_T_1509, asSInt(UInt<18>(0h2f000))) node _T_1511 = asSInt(_T_1510) node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0))) node _T_1513 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1514 = cvt(_T_1513) node _T_1515 = and(_T_1514, asSInt(UInt<17>(0h10000))) node _T_1516 = asSInt(_T_1515) node _T_1517 = eq(_T_1516, asSInt(UInt<1>(0h0))) node _T_1518 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1519 = cvt(_T_1518) node _T_1520 = and(_T_1519, asSInt(UInt<13>(0h1000))) node _T_1521 = asSInt(_T_1520) node _T_1522 = eq(_T_1521, asSInt(UInt<1>(0h0))) node _T_1523 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1524 = cvt(_T_1523) node _T_1525 = and(_T_1524, asSInt(UInt<17>(0h10000))) node _T_1526 = asSInt(_T_1525) node _T_1527 = eq(_T_1526, asSInt(UInt<1>(0h0))) node _T_1528 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1529 = cvt(_T_1528) node _T_1530 = and(_T_1529, asSInt(UInt<27>(0h4000000))) node _T_1531 = asSInt(_T_1530) node _T_1532 = eq(_T_1531, asSInt(UInt<1>(0h0))) node _T_1533 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1534 = cvt(_T_1533) node _T_1535 = and(_T_1534, asSInt(UInt<13>(0h1000))) node _T_1536 = asSInt(_T_1535) node _T_1537 = eq(_T_1536, asSInt(UInt<1>(0h0))) node _T_1538 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1539 = cvt(_T_1538) node _T_1540 = and(_T_1539, asSInt(UInt<29>(0h10000000))) node _T_1541 = asSInt(_T_1540) node _T_1542 = eq(_T_1541, asSInt(UInt<1>(0h0))) node _T_1543 = or(_T_1487, _T_1492) node _T_1544 = or(_T_1543, _T_1497) node _T_1545 = or(_T_1544, _T_1502) node _T_1546 = or(_T_1545, _T_1507) node _T_1547 = or(_T_1546, _T_1512) node _T_1548 = or(_T_1547, _T_1517) node _T_1549 = or(_T_1548, _T_1522) node _T_1550 = or(_T_1549, _T_1527) node _T_1551 = or(_T_1550, _T_1532) node _T_1552 = or(_T_1551, _T_1537) node _T_1553 = or(_T_1552, _T_1542) node _T_1554 = and(_T_1482, _T_1553) node _T_1555 = or(UInt<1>(0h0), _T_1554) node _T_1556 = and(UInt<1>(0h0), _T_1555) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_100 node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(address_ok, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(legal_source, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1566 = asUInt(reset) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) when _T_1567 : node _T_1568 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1569 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_104 node _T_1573 = eq(io.in.b.bits.mask, mask_1) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_105 node _T_1577 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1577 : node _T_1578 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1579 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1580 = and(_T_1578, _T_1579) node _T_1581 = or(UInt<1>(0h0), _T_1580) node _T_1582 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1583 = cvt(_T_1582) node _T_1584 = and(_T_1583, asSInt(UInt<14>(0h2000))) node _T_1585 = asSInt(_T_1584) node _T_1586 = eq(_T_1585, asSInt(UInt<1>(0h0))) node _T_1587 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1588 = cvt(_T_1587) node _T_1589 = and(_T_1588, asSInt(UInt<13>(0h1000))) node _T_1590 = asSInt(_T_1589) node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0))) node _T_1592 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1593 = cvt(_T_1592) node _T_1594 = and(_T_1593, asSInt(UInt<17>(0h10000))) node _T_1595 = asSInt(_T_1594) node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1598 = cvt(_T_1597) node _T_1599 = and(_T_1598, asSInt(UInt<15>(0h4000))) node _T_1600 = asSInt(_T_1599) node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0))) node _T_1602 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<18>(0h2f000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<17>(0h10000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<13>(0h1000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<17>(0h10000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<27>(0h4000000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1638 = cvt(_T_1637) node _T_1639 = and(_T_1638, asSInt(UInt<29>(0h10000000))) node _T_1640 = asSInt(_T_1639) node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0))) node _T_1642 = or(_T_1586, _T_1591) node _T_1643 = or(_T_1642, _T_1596) node _T_1644 = or(_T_1643, _T_1601) node _T_1645 = or(_T_1644, _T_1606) node _T_1646 = or(_T_1645, _T_1611) node _T_1647 = or(_T_1646, _T_1616) node _T_1648 = or(_T_1647, _T_1621) node _T_1649 = or(_T_1648, _T_1626) node _T_1650 = or(_T_1649, _T_1631) node _T_1651 = or(_T_1650, _T_1636) node _T_1652 = or(_T_1651, _T_1641) node _T_1653 = and(_T_1581, _T_1652) node _T_1654 = or(UInt<1>(0h0), _T_1653) node _T_1655 = and(UInt<1>(0h0), _T_1654) node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(_T_1655, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1655, UInt<1>(0h1), "") : assert_106 node _T_1659 = asUInt(reset) node _T_1660 = eq(_T_1659, UInt<1>(0h0)) when _T_1660 : node _T_1661 = eq(address_ok, UInt<1>(0h0)) when _T_1661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(legal_source, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1668 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1669 = asUInt(reset) node _T_1670 = eq(_T_1669, UInt<1>(0h0)) when _T_1670 : node _T_1671 = eq(_T_1668, UInt<1>(0h0)) when _T_1671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1668, UInt<1>(0h1), "") : assert_110 node _T_1672 = not(mask_1) node _T_1673 = and(io.in.b.bits.mask, _T_1672) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_111 node _T_1678 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1678 : node _T_1679 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1680 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1681 = and(_T_1679, _T_1680) node _T_1682 = or(UInt<1>(0h0), _T_1681) node _T_1683 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1684 = cvt(_T_1683) node _T_1685 = and(_T_1684, asSInt(UInt<14>(0h2000))) node _T_1686 = asSInt(_T_1685) node _T_1687 = eq(_T_1686, asSInt(UInt<1>(0h0))) node _T_1688 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1689 = cvt(_T_1688) node _T_1690 = and(_T_1689, asSInt(UInt<13>(0h1000))) node _T_1691 = asSInt(_T_1690) node _T_1692 = eq(_T_1691, asSInt(UInt<1>(0h0))) node _T_1693 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1694 = cvt(_T_1693) node _T_1695 = and(_T_1694, asSInt(UInt<17>(0h10000))) node _T_1696 = asSInt(_T_1695) node _T_1697 = eq(_T_1696, asSInt(UInt<1>(0h0))) node _T_1698 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1699 = cvt(_T_1698) node _T_1700 = and(_T_1699, asSInt(UInt<15>(0h4000))) node _T_1701 = asSInt(_T_1700) node _T_1702 = eq(_T_1701, asSInt(UInt<1>(0h0))) node _T_1703 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1704 = cvt(_T_1703) node _T_1705 = and(_T_1704, asSInt(UInt<13>(0h1000))) node _T_1706 = asSInt(_T_1705) node _T_1707 = eq(_T_1706, asSInt(UInt<1>(0h0))) node _T_1708 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1709 = cvt(_T_1708) node _T_1710 = and(_T_1709, asSInt(UInt<18>(0h2f000))) node _T_1711 = asSInt(_T_1710) node _T_1712 = eq(_T_1711, asSInt(UInt<1>(0h0))) node _T_1713 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1714 = cvt(_T_1713) node _T_1715 = and(_T_1714, asSInt(UInt<17>(0h10000))) node _T_1716 = asSInt(_T_1715) node _T_1717 = eq(_T_1716, asSInt(UInt<1>(0h0))) node _T_1718 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1719 = cvt(_T_1718) node _T_1720 = and(_T_1719, asSInt(UInt<13>(0h1000))) node _T_1721 = asSInt(_T_1720) node _T_1722 = eq(_T_1721, asSInt(UInt<1>(0h0))) node _T_1723 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1724 = cvt(_T_1723) node _T_1725 = and(_T_1724, asSInt(UInt<17>(0h10000))) node _T_1726 = asSInt(_T_1725) node _T_1727 = eq(_T_1726, asSInt(UInt<1>(0h0))) node _T_1728 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1729 = cvt(_T_1728) node _T_1730 = and(_T_1729, asSInt(UInt<27>(0h4000000))) node _T_1731 = asSInt(_T_1730) node _T_1732 = eq(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1734 = cvt(_T_1733) node _T_1735 = and(_T_1734, asSInt(UInt<13>(0h1000))) node _T_1736 = asSInt(_T_1735) node _T_1737 = eq(_T_1736, asSInt(UInt<1>(0h0))) node _T_1738 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1739 = cvt(_T_1738) node _T_1740 = and(_T_1739, asSInt(UInt<29>(0h10000000))) node _T_1741 = asSInt(_T_1740) node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0))) node _T_1743 = or(_T_1687, _T_1692) node _T_1744 = or(_T_1743, _T_1697) node _T_1745 = or(_T_1744, _T_1702) node _T_1746 = or(_T_1745, _T_1707) node _T_1747 = or(_T_1746, _T_1712) node _T_1748 = or(_T_1747, _T_1717) node _T_1749 = or(_T_1748, _T_1722) node _T_1750 = or(_T_1749, _T_1727) node _T_1751 = or(_T_1750, _T_1732) node _T_1752 = or(_T_1751, _T_1737) node _T_1753 = or(_T_1752, _T_1742) node _T_1754 = and(_T_1682, _T_1753) node _T_1755 = or(UInt<1>(0h0), _T_1754) node _T_1756 = and(UInt<1>(0h0), _T_1755) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_112 node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(address_ok, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(legal_source, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_116 node _T_1773 = eq(io.in.b.bits.mask, mask_1) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_117 node _T_1777 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1777 : node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1783 = cvt(_T_1782) node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000))) node _T_1785 = asSInt(_T_1784) node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0))) node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1788 = cvt(_T_1787) node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000))) node _T_1790 = asSInt(_T_1789) node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0))) node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<15>(0h4000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<13>(0h1000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1838 = cvt(_T_1837) node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000))) node _T_1840 = asSInt(_T_1839) node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0))) node _T_1842 = or(_T_1786, _T_1791) node _T_1843 = or(_T_1842, _T_1796) node _T_1844 = or(_T_1843, _T_1801) node _T_1845 = or(_T_1844, _T_1806) node _T_1846 = or(_T_1845, _T_1811) node _T_1847 = or(_T_1846, _T_1816) node _T_1848 = or(_T_1847, _T_1821) node _T_1849 = or(_T_1848, _T_1826) node _T_1850 = or(_T_1849, _T_1831) node _T_1851 = or(_T_1850, _T_1836) node _T_1852 = or(_T_1851, _T_1841) node _T_1853 = and(_T_1781, _T_1852) node _T_1854 = or(UInt<1>(0h0), _T_1853) node _T_1855 = and(UInt<1>(0h0), _T_1854) node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(_T_1855, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1855, UInt<1>(0h1), "") : assert_118 node _T_1859 = asUInt(reset) node _T_1860 = eq(_T_1859, UInt<1>(0h0)) when _T_1860 : node _T_1861 = eq(address_ok, UInt<1>(0h0)) when _T_1861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(legal_source, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1868 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_122 node _T_1872 = eq(io.in.b.bits.mask, mask_1) node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(_T_1872, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1872, UInt<1>(0h1), "") : assert_123 node _T_1876 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1876 : node _T_1877 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1878 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1879 = and(_T_1877, _T_1878) node _T_1880 = or(UInt<1>(0h0), _T_1879) node _T_1881 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1882 = cvt(_T_1881) node _T_1883 = and(_T_1882, asSInt(UInt<14>(0h2000))) node _T_1884 = asSInt(_T_1883) node _T_1885 = eq(_T_1884, asSInt(UInt<1>(0h0))) node _T_1886 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1887 = cvt(_T_1886) node _T_1888 = and(_T_1887, asSInt(UInt<13>(0h1000))) node _T_1889 = asSInt(_T_1888) node _T_1890 = eq(_T_1889, asSInt(UInt<1>(0h0))) node _T_1891 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1892 = cvt(_T_1891) node _T_1893 = and(_T_1892, asSInt(UInt<17>(0h10000))) node _T_1894 = asSInt(_T_1893) node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = xor(io.in.b.bits.address, UInt<18>(0h20000)) node _T_1897 = cvt(_T_1896) node _T_1898 = and(_T_1897, asSInt(UInt<15>(0h4000))) node _T_1899 = asSInt(_T_1898) node _T_1900 = eq(_T_1899, asSInt(UInt<1>(0h0))) node _T_1901 = xor(io.in.b.bits.address, UInt<18>(0h24000)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<13>(0h1000))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1907 = cvt(_T_1906) node _T_1908 = and(_T_1907, asSInt(UInt<18>(0h2f000))) node _T_1909 = asSInt(_T_1908) node _T_1910 = eq(_T_1909, asSInt(UInt<1>(0h0))) node _T_1911 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1912 = cvt(_T_1911) node _T_1913 = and(_T_1912, asSInt(UInt<17>(0h10000))) node _T_1914 = asSInt(_T_1913) node _T_1915 = eq(_T_1914, asSInt(UInt<1>(0h0))) node _T_1916 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1917 = cvt(_T_1916) node _T_1918 = and(_T_1917, asSInt(UInt<13>(0h1000))) node _T_1919 = asSInt(_T_1918) node _T_1920 = eq(_T_1919, asSInt(UInt<1>(0h0))) node _T_1921 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1922 = cvt(_T_1921) node _T_1923 = and(_T_1922, asSInt(UInt<17>(0h10000))) node _T_1924 = asSInt(_T_1923) node _T_1925 = eq(_T_1924, asSInt(UInt<1>(0h0))) node _T_1926 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1927 = cvt(_T_1926) node _T_1928 = and(_T_1927, asSInt(UInt<27>(0h4000000))) node _T_1929 = asSInt(_T_1928) node _T_1930 = eq(_T_1929, asSInt(UInt<1>(0h0))) node _T_1931 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1932 = cvt(_T_1931) node _T_1933 = and(_T_1932, asSInt(UInt<13>(0h1000))) node _T_1934 = asSInt(_T_1933) node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0))) node _T_1936 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1937 = cvt(_T_1936) node _T_1938 = and(_T_1937, asSInt(UInt<29>(0h10000000))) node _T_1939 = asSInt(_T_1938) node _T_1940 = eq(_T_1939, asSInt(UInt<1>(0h0))) node _T_1941 = or(_T_1885, _T_1890) node _T_1942 = or(_T_1941, _T_1895) node _T_1943 = or(_T_1942, _T_1900) node _T_1944 = or(_T_1943, _T_1905) node _T_1945 = or(_T_1944, _T_1910) node _T_1946 = or(_T_1945, _T_1915) node _T_1947 = or(_T_1946, _T_1920) node _T_1948 = or(_T_1947, _T_1925) node _T_1949 = or(_T_1948, _T_1930) node _T_1950 = or(_T_1949, _T_1935) node _T_1951 = or(_T_1950, _T_1940) node _T_1952 = and(_T_1880, _T_1951) node _T_1953 = or(UInt<1>(0h0), _T_1952) node _T_1954 = and(UInt<1>(0h0), _T_1953) node _T_1955 = asUInt(reset) node _T_1956 = eq(_T_1955, UInt<1>(0h0)) when _T_1956 : node _T_1957 = eq(_T_1954, UInt<1>(0h0)) when _T_1957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1954, UInt<1>(0h1), "") : assert_124 node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(address_ok, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(legal_source, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1964 = asUInt(reset) node _T_1965 = eq(_T_1964, UInt<1>(0h0)) when _T_1965 : node _T_1966 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1967 = eq(io.in.b.bits.mask, mask_1) node _T_1968 = asUInt(reset) node _T_1969 = eq(_T_1968, UInt<1>(0h0)) when _T_1969 : node _T_1970 = eq(_T_1967, UInt<1>(0h0)) when _T_1970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1967, UInt<1>(0h1), "") : assert_128 node _T_1971 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1972 = asUInt(reset) node _T_1973 = eq(_T_1972, UInt<1>(0h0)) when _T_1973 : node _T_1974 = eq(_T_1971, UInt<1>(0h0)) when _T_1974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1971, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1975 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1976 = asUInt(reset) node _T_1977 = eq(_T_1976, UInt<1>(0h0)) when _T_1977 : node _T_1978 = eq(_T_1975, UInt<1>(0h0)) when _T_1978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1975, UInt<1>(0h1), "") : assert_130 node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_4 connect _source_ok_WIRE_2[1], _source_ok_T_5 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<13>(0h1000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<13>(0h1000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<17>(0h10000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<18>(0h21000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<13>(0h1000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) node _address_ok_T_130 = xor(io.in.c.bits.address, UInt<18>(0h22000)) node _address_ok_T_131 = cvt(_address_ok_T_130) node _address_ok_T_132 = and(_address_ok_T_131, asSInt(UInt<13>(0h1000))) node _address_ok_T_133 = asSInt(_address_ok_T_132) node _address_ok_T_134 = eq(_address_ok_T_133, asSInt(UInt<1>(0h0))) node _address_ok_T_135 = xor(io.in.c.bits.address, UInt<18>(0h23000)) node _address_ok_T_136 = cvt(_address_ok_T_135) node _address_ok_T_137 = and(_address_ok_T_136, asSInt(UInt<13>(0h1000))) node _address_ok_T_138 = asSInt(_address_ok_T_137) node _address_ok_T_139 = eq(_address_ok_T_138, asSInt(UInt<1>(0h0))) node _address_ok_T_140 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _address_ok_T_141 = cvt(_address_ok_T_140) node _address_ok_T_142 = and(_address_ok_T_141, asSInt(UInt<13>(0h1000))) node _address_ok_T_143 = asSInt(_address_ok_T_142) node _address_ok_T_144 = eq(_address_ok_T_143, asSInt(UInt<1>(0h0))) node _address_ok_T_145 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_146 = cvt(_address_ok_T_145) node _address_ok_T_147 = and(_address_ok_T_146, asSInt(UInt<13>(0h1000))) node _address_ok_T_148 = asSInt(_address_ok_T_147) node _address_ok_T_149 = eq(_address_ok_T_148, asSInt(UInt<1>(0h0))) node _address_ok_T_150 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_151 = cvt(_address_ok_T_150) node _address_ok_T_152 = and(_address_ok_T_151, asSInt(UInt<13>(0h1000))) node _address_ok_T_153 = asSInt(_address_ok_T_152) node _address_ok_T_154 = eq(_address_ok_T_153, asSInt(UInt<1>(0h0))) node _address_ok_T_155 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_156 = cvt(_address_ok_T_155) node _address_ok_T_157 = and(_address_ok_T_156, asSInt(UInt<17>(0h10000))) node _address_ok_T_158 = asSInt(_address_ok_T_157) node _address_ok_T_159 = eq(_address_ok_T_158, asSInt(UInt<1>(0h0))) node _address_ok_T_160 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_161 = cvt(_address_ok_T_160) node _address_ok_T_162 = and(_address_ok_T_161, asSInt(UInt<13>(0h1000))) node _address_ok_T_163 = asSInt(_address_ok_T_162) node _address_ok_T_164 = eq(_address_ok_T_163, asSInt(UInt<1>(0h0))) node _address_ok_T_165 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_166 = cvt(_address_ok_T_165) node _address_ok_T_167 = and(_address_ok_T_166, asSInt(UInt<17>(0h10000))) node _address_ok_T_168 = asSInt(_address_ok_T_167) node _address_ok_T_169 = eq(_address_ok_T_168, asSInt(UInt<1>(0h0))) node _address_ok_T_170 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_171 = cvt(_address_ok_T_170) node _address_ok_T_172 = and(_address_ok_T_171, asSInt(UInt<27>(0h4000000))) node _address_ok_T_173 = asSInt(_address_ok_T_172) node _address_ok_T_174 = eq(_address_ok_T_173, asSInt(UInt<1>(0h0))) node _address_ok_T_175 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_176 = cvt(_address_ok_T_175) node _address_ok_T_177 = and(_address_ok_T_176, asSInt(UInt<13>(0h1000))) node _address_ok_T_178 = asSInt(_address_ok_T_177) node _address_ok_T_179 = eq(_address_ok_T_178, asSInt(UInt<1>(0h0))) node _address_ok_T_180 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_181 = cvt(_address_ok_T_180) node _address_ok_T_182 = and(_address_ok_T_181, asSInt(UInt<29>(0h10000000))) node _address_ok_T_183 = asSInt(_address_ok_T_182) node _address_ok_T_184 = eq(_address_ok_T_183, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[17] connect _address_ok_WIRE_1[0], _address_ok_T_104 connect _address_ok_WIRE_1[1], _address_ok_T_109 connect _address_ok_WIRE_1[2], _address_ok_T_114 connect _address_ok_WIRE_1[3], _address_ok_T_119 connect _address_ok_WIRE_1[4], _address_ok_T_124 connect _address_ok_WIRE_1[5], _address_ok_T_129 connect _address_ok_WIRE_1[6], _address_ok_T_134 connect _address_ok_WIRE_1[7], _address_ok_T_139 connect _address_ok_WIRE_1[8], _address_ok_T_144 connect _address_ok_WIRE_1[9], _address_ok_T_149 connect _address_ok_WIRE_1[10], _address_ok_T_154 connect _address_ok_WIRE_1[11], _address_ok_T_159 connect _address_ok_WIRE_1[12], _address_ok_T_164 connect _address_ok_WIRE_1[13], _address_ok_T_169 connect _address_ok_WIRE_1[14], _address_ok_T_174 connect _address_ok_WIRE_1[15], _address_ok_T_179 connect _address_ok_WIRE_1[16], _address_ok_T_184 node _address_ok_T_185 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_186 = or(_address_ok_T_185, _address_ok_WIRE_1[2]) node _address_ok_T_187 = or(_address_ok_T_186, _address_ok_WIRE_1[3]) node _address_ok_T_188 = or(_address_ok_T_187, _address_ok_WIRE_1[4]) node _address_ok_T_189 = or(_address_ok_T_188, _address_ok_WIRE_1[5]) node _address_ok_T_190 = or(_address_ok_T_189, _address_ok_WIRE_1[6]) node _address_ok_T_191 = or(_address_ok_T_190, _address_ok_WIRE_1[7]) node _address_ok_T_192 = or(_address_ok_T_191, _address_ok_WIRE_1[8]) node _address_ok_T_193 = or(_address_ok_T_192, _address_ok_WIRE_1[9]) node _address_ok_T_194 = or(_address_ok_T_193, _address_ok_WIRE_1[10]) node _address_ok_T_195 = or(_address_ok_T_194, _address_ok_WIRE_1[11]) node _address_ok_T_196 = or(_address_ok_T_195, _address_ok_WIRE_1[12]) node _address_ok_T_197 = or(_address_ok_T_196, _address_ok_WIRE_1[13]) node _address_ok_T_198 = or(_address_ok_T_197, _address_ok_WIRE_1[14]) node _address_ok_T_199 = or(_address_ok_T_198, _address_ok_WIRE_1[15]) node address_ok_1 = or(_address_ok_T_199, _address_ok_WIRE_1[16]) node _T_1979 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) node _T_1981 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1982 = cvt(_T_1981) node _T_1983 = and(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = asSInt(_T_1983) node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0))) node _T_1986 = or(_T_1980, _T_1985) node _T_1987 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) node _T_1989 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<1>(0h0))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = or(_T_1988, _T_1993) node _T_1995 = and(_T_1986, _T_1994) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_131 node _T_1999 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1999 : node _T_2000 = asUInt(reset) node _T_2001 = eq(_T_2000, UInt<1>(0h0)) when _T_2001 : node _T_2002 = eq(address_ok_1, UInt<1>(0h0)) when _T_2002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(source_ok_2, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2006 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_134 node _T_2010 = asUInt(reset) node _T_2011 = eq(_T_2010, UInt<1>(0h0)) when _T_2011 : node _T_2012 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2013 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_136 node _T_2017 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_137 node _T_2021 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2021 : node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(address_ok_1, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(source_ok_2, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2028 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_140 node _T_2032 = asUInt(reset) node _T_2033 = eq(_T_2032, UInt<1>(0h0)) when _T_2033 : node _T_2034 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2035 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2036 = asUInt(reset) node _T_2037 = eq(_T_2036, UInt<1>(0h0)) when _T_2037 : node _T_2038 = eq(_T_2035, UInt<1>(0h0)) when _T_2038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2035, UInt<1>(0h1), "") : assert_142 node _T_2039 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2039 : node _T_2040 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2041 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2044 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2045 = or(_T_2043, _T_2044) node _T_2046 = and(_T_2042, _T_2045) node _T_2047 = or(UInt<1>(0h0), _T_2046) node _T_2048 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2049 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2050 = cvt(_T_2049) node _T_2051 = and(_T_2050, asSInt(UInt<14>(0h2000))) node _T_2052 = asSInt(_T_2051) node _T_2053 = eq(_T_2052, asSInt(UInt<1>(0h0))) node _T_2054 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2055 = cvt(_T_2054) node _T_2056 = and(_T_2055, asSInt(UInt<13>(0h1000))) node _T_2057 = asSInt(_T_2056) node _T_2058 = eq(_T_2057, asSInt(UInt<1>(0h0))) node _T_2059 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2060 = cvt(_T_2059) node _T_2061 = and(_T_2060, asSInt(UInt<17>(0h10000))) node _T_2062 = asSInt(_T_2061) node _T_2063 = eq(_T_2062, asSInt(UInt<1>(0h0))) node _T_2064 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2065 = cvt(_T_2064) node _T_2066 = and(_T_2065, asSInt(UInt<15>(0h4000))) node _T_2067 = asSInt(_T_2066) node _T_2068 = eq(_T_2067, asSInt(UInt<1>(0h0))) node _T_2069 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2070 = cvt(_T_2069) node _T_2071 = and(_T_2070, asSInt(UInt<13>(0h1000))) node _T_2072 = asSInt(_T_2071) node _T_2073 = eq(_T_2072, asSInt(UInt<1>(0h0))) node _T_2074 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2075 = cvt(_T_2074) node _T_2076 = and(_T_2075, asSInt(UInt<18>(0h2f000))) node _T_2077 = asSInt(_T_2076) node _T_2078 = eq(_T_2077, asSInt(UInt<1>(0h0))) node _T_2079 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2080 = cvt(_T_2079) node _T_2081 = and(_T_2080, asSInt(UInt<17>(0h10000))) node _T_2082 = asSInt(_T_2081) node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0))) node _T_2084 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2090 = cvt(_T_2089) node _T_2091 = and(_T_2090, asSInt(UInt<27>(0h4000000))) node _T_2092 = asSInt(_T_2091) node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0))) node _T_2094 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<13>(0h1000))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = or(_T_2053, _T_2058) node _T_2100 = or(_T_2099, _T_2063) node _T_2101 = or(_T_2100, _T_2068) node _T_2102 = or(_T_2101, _T_2073) node _T_2103 = or(_T_2102, _T_2078) node _T_2104 = or(_T_2103, _T_2083) node _T_2105 = or(_T_2104, _T_2088) node _T_2106 = or(_T_2105, _T_2093) node _T_2107 = or(_T_2106, _T_2098) node _T_2108 = and(_T_2048, _T_2107) node _T_2109 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2110 = or(UInt<1>(0h0), _T_2109) node _T_2111 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<17>(0h10000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2117 = cvt(_T_2116) node _T_2118 = and(_T_2117, asSInt(UInt<29>(0h10000000))) node _T_2119 = asSInt(_T_2118) node _T_2120 = eq(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = or(_T_2115, _T_2120) node _T_2122 = and(_T_2110, _T_2121) node _T_2123 = or(UInt<1>(0h0), _T_2108) node _T_2124 = or(_T_2123, _T_2122) node _T_2125 = and(_T_2047, _T_2124) node _T_2126 = asUInt(reset) node _T_2127 = eq(_T_2126, UInt<1>(0h0)) when _T_2127 : node _T_2128 = eq(_T_2125, UInt<1>(0h0)) when _T_2128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2125, UInt<1>(0h1), "") : assert_143 node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2130 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_2129 connect _WIRE_6[1], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_6[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = or(_T_2132, _T_2133) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2134 node _T_2135 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2136 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2137 = and(_T_2135, _T_2136) node _T_2138 = or(UInt<1>(0h0), _T_2137) node _T_2139 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2140 = cvt(_T_2139) node _T_2141 = and(_T_2140, asSInt(UInt<14>(0h2000))) node _T_2142 = asSInt(_T_2141) node _T_2143 = eq(_T_2142, asSInt(UInt<1>(0h0))) node _T_2144 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2145 = cvt(_T_2144) node _T_2146 = and(_T_2145, asSInt(UInt<13>(0h1000))) node _T_2147 = asSInt(_T_2146) node _T_2148 = eq(_T_2147, asSInt(UInt<1>(0h0))) node _T_2149 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2150 = cvt(_T_2149) node _T_2151 = and(_T_2150, asSInt(UInt<17>(0h10000))) node _T_2152 = asSInt(_T_2151) node _T_2153 = eq(_T_2152, asSInt(UInt<1>(0h0))) node _T_2154 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2155 = cvt(_T_2154) node _T_2156 = and(_T_2155, asSInt(UInt<15>(0h4000))) node _T_2157 = asSInt(_T_2156) node _T_2158 = eq(_T_2157, asSInt(UInt<1>(0h0))) node _T_2159 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2160 = cvt(_T_2159) node _T_2161 = and(_T_2160, asSInt(UInt<13>(0h1000))) node _T_2162 = asSInt(_T_2161) node _T_2163 = eq(_T_2162, asSInt(UInt<1>(0h0))) node _T_2164 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2165 = cvt(_T_2164) node _T_2166 = and(_T_2165, asSInt(UInt<18>(0h2f000))) node _T_2167 = asSInt(_T_2166) node _T_2168 = eq(_T_2167, asSInt(UInt<1>(0h0))) node _T_2169 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2170 = cvt(_T_2169) node _T_2171 = and(_T_2170, asSInt(UInt<17>(0h10000))) node _T_2172 = asSInt(_T_2171) node _T_2173 = eq(_T_2172, asSInt(UInt<1>(0h0))) node _T_2174 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<13>(0h1000))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2180 = cvt(_T_2179) node _T_2181 = and(_T_2180, asSInt(UInt<17>(0h10000))) node _T_2182 = asSInt(_T_2181) node _T_2183 = eq(_T_2182, asSInt(UInt<1>(0h0))) node _T_2184 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2185 = cvt(_T_2184) node _T_2186 = and(_T_2185, asSInt(UInt<27>(0h4000000))) node _T_2187 = asSInt(_T_2186) node _T_2188 = eq(_T_2187, asSInt(UInt<1>(0h0))) node _T_2189 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2190 = cvt(_T_2189) node _T_2191 = and(_T_2190, asSInt(UInt<13>(0h1000))) node _T_2192 = asSInt(_T_2191) node _T_2193 = eq(_T_2192, asSInt(UInt<1>(0h0))) node _T_2194 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2195 = cvt(_T_2194) node _T_2196 = and(_T_2195, asSInt(UInt<29>(0h10000000))) node _T_2197 = asSInt(_T_2196) node _T_2198 = eq(_T_2197, asSInt(UInt<1>(0h0))) node _T_2199 = or(_T_2143, _T_2148) node _T_2200 = or(_T_2199, _T_2153) node _T_2201 = or(_T_2200, _T_2158) node _T_2202 = or(_T_2201, _T_2163) node _T_2203 = or(_T_2202, _T_2168) node _T_2204 = or(_T_2203, _T_2173) node _T_2205 = or(_T_2204, _T_2178) node _T_2206 = or(_T_2205, _T_2183) node _T_2207 = or(_T_2206, _T_2188) node _T_2208 = or(_T_2207, _T_2193) node _T_2209 = or(_T_2208, _T_2198) node _T_2210 = and(_T_2138, _T_2209) node _T_2211 = or(UInt<1>(0h0), _T_2210) node _T_2212 = and(_WIRE_7, _T_2211) node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(_T_2212, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2212, UInt<1>(0h1), "") : assert_144 node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(source_ok_2, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2219 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_146 node _T_2223 = asUInt(reset) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) when _T_2224 : node _T_2225 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2226 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(_T_2226, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2226, UInt<1>(0h1), "") : assert_148 node _T_2230 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_149 node _T_2234 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2234 : node _T_2235 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2236 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2237 = and(_T_2235, _T_2236) node _T_2238 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2239 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2240 = or(_T_2238, _T_2239) node _T_2241 = and(_T_2237, _T_2240) node _T_2242 = or(UInt<1>(0h0), _T_2241) node _T_2243 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2244 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2245 = cvt(_T_2244) node _T_2246 = and(_T_2245, asSInt(UInt<14>(0h2000))) node _T_2247 = asSInt(_T_2246) node _T_2248 = eq(_T_2247, asSInt(UInt<1>(0h0))) node _T_2249 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2250 = cvt(_T_2249) node _T_2251 = and(_T_2250, asSInt(UInt<13>(0h1000))) node _T_2252 = asSInt(_T_2251) node _T_2253 = eq(_T_2252, asSInt(UInt<1>(0h0))) node _T_2254 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2255 = cvt(_T_2254) node _T_2256 = and(_T_2255, asSInt(UInt<17>(0h10000))) node _T_2257 = asSInt(_T_2256) node _T_2258 = eq(_T_2257, asSInt(UInt<1>(0h0))) node _T_2259 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2260 = cvt(_T_2259) node _T_2261 = and(_T_2260, asSInt(UInt<15>(0h4000))) node _T_2262 = asSInt(_T_2261) node _T_2263 = eq(_T_2262, asSInt(UInt<1>(0h0))) node _T_2264 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2265 = cvt(_T_2264) node _T_2266 = and(_T_2265, asSInt(UInt<13>(0h1000))) node _T_2267 = asSInt(_T_2266) node _T_2268 = eq(_T_2267, asSInt(UInt<1>(0h0))) node _T_2269 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2270 = cvt(_T_2269) node _T_2271 = and(_T_2270, asSInt(UInt<18>(0h2f000))) node _T_2272 = asSInt(_T_2271) node _T_2273 = eq(_T_2272, asSInt(UInt<1>(0h0))) node _T_2274 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2275 = cvt(_T_2274) node _T_2276 = and(_T_2275, asSInt(UInt<17>(0h10000))) node _T_2277 = asSInt(_T_2276) node _T_2278 = eq(_T_2277, asSInt(UInt<1>(0h0))) node _T_2279 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2280 = cvt(_T_2279) node _T_2281 = and(_T_2280, asSInt(UInt<13>(0h1000))) node _T_2282 = asSInt(_T_2281) node _T_2283 = eq(_T_2282, asSInt(UInt<1>(0h0))) node _T_2284 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2285 = cvt(_T_2284) node _T_2286 = and(_T_2285, asSInt(UInt<27>(0h4000000))) node _T_2287 = asSInt(_T_2286) node _T_2288 = eq(_T_2287, asSInt(UInt<1>(0h0))) node _T_2289 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2290 = cvt(_T_2289) node _T_2291 = and(_T_2290, asSInt(UInt<13>(0h1000))) node _T_2292 = asSInt(_T_2291) node _T_2293 = eq(_T_2292, asSInt(UInt<1>(0h0))) node _T_2294 = or(_T_2248, _T_2253) node _T_2295 = or(_T_2294, _T_2258) node _T_2296 = or(_T_2295, _T_2263) node _T_2297 = or(_T_2296, _T_2268) node _T_2298 = or(_T_2297, _T_2273) node _T_2299 = or(_T_2298, _T_2278) node _T_2300 = or(_T_2299, _T_2283) node _T_2301 = or(_T_2300, _T_2288) node _T_2302 = or(_T_2301, _T_2293) node _T_2303 = and(_T_2243, _T_2302) node _T_2304 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2305 = or(UInt<1>(0h0), _T_2304) node _T_2306 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2307 = cvt(_T_2306) node _T_2308 = and(_T_2307, asSInt(UInt<17>(0h10000))) node _T_2309 = asSInt(_T_2308) node _T_2310 = eq(_T_2309, asSInt(UInt<1>(0h0))) node _T_2311 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2312 = cvt(_T_2311) node _T_2313 = and(_T_2312, asSInt(UInt<29>(0h10000000))) node _T_2314 = asSInt(_T_2313) node _T_2315 = eq(_T_2314, asSInt(UInt<1>(0h0))) node _T_2316 = or(_T_2310, _T_2315) node _T_2317 = and(_T_2305, _T_2316) node _T_2318 = or(UInt<1>(0h0), _T_2303) node _T_2319 = or(_T_2318, _T_2317) node _T_2320 = and(_T_2242, _T_2319) node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(_T_2320, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2320, UInt<1>(0h1), "") : assert_150 node _T_2324 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2325 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2324 connect _WIRE_8[1], _T_2325 node _T_2326 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2327 = mux(_WIRE_8[0], _T_2326, UInt<1>(0h0)) node _T_2328 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2329 = or(_T_2327, _T_2328) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2329 node _T_2330 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2331 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2332 = and(_T_2330, _T_2331) node _T_2333 = or(UInt<1>(0h0), _T_2332) node _T_2334 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2335 = cvt(_T_2334) node _T_2336 = and(_T_2335, asSInt(UInt<14>(0h2000))) node _T_2337 = asSInt(_T_2336) node _T_2338 = eq(_T_2337, asSInt(UInt<1>(0h0))) node _T_2339 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2340 = cvt(_T_2339) node _T_2341 = and(_T_2340, asSInt(UInt<13>(0h1000))) node _T_2342 = asSInt(_T_2341) node _T_2343 = eq(_T_2342, asSInt(UInt<1>(0h0))) node _T_2344 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2345 = cvt(_T_2344) node _T_2346 = and(_T_2345, asSInt(UInt<17>(0h10000))) node _T_2347 = asSInt(_T_2346) node _T_2348 = eq(_T_2347, asSInt(UInt<1>(0h0))) node _T_2349 = xor(io.in.c.bits.address, UInt<18>(0h20000)) node _T_2350 = cvt(_T_2349) node _T_2351 = and(_T_2350, asSInt(UInt<15>(0h4000))) node _T_2352 = asSInt(_T_2351) node _T_2353 = eq(_T_2352, asSInt(UInt<1>(0h0))) node _T_2354 = xor(io.in.c.bits.address, UInt<18>(0h24000)) node _T_2355 = cvt(_T_2354) node _T_2356 = and(_T_2355, asSInt(UInt<13>(0h1000))) node _T_2357 = asSInt(_T_2356) node _T_2358 = eq(_T_2357, asSInt(UInt<1>(0h0))) node _T_2359 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2360 = cvt(_T_2359) node _T_2361 = and(_T_2360, asSInt(UInt<18>(0h2f000))) node _T_2362 = asSInt(_T_2361) node _T_2363 = eq(_T_2362, asSInt(UInt<1>(0h0))) node _T_2364 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2365 = cvt(_T_2364) node _T_2366 = and(_T_2365, asSInt(UInt<17>(0h10000))) node _T_2367 = asSInt(_T_2366) node _T_2368 = eq(_T_2367, asSInt(UInt<1>(0h0))) node _T_2369 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2370 = cvt(_T_2369) node _T_2371 = and(_T_2370, asSInt(UInt<13>(0h1000))) node _T_2372 = asSInt(_T_2371) node _T_2373 = eq(_T_2372, asSInt(UInt<1>(0h0))) node _T_2374 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2375 = cvt(_T_2374) node _T_2376 = and(_T_2375, asSInt(UInt<17>(0h10000))) node _T_2377 = asSInt(_T_2376) node _T_2378 = eq(_T_2377, asSInt(UInt<1>(0h0))) node _T_2379 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2380 = cvt(_T_2379) node _T_2381 = and(_T_2380, asSInt(UInt<27>(0h4000000))) node _T_2382 = asSInt(_T_2381) node _T_2383 = eq(_T_2382, asSInt(UInt<1>(0h0))) node _T_2384 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2385 = cvt(_T_2384) node _T_2386 = and(_T_2385, asSInt(UInt<13>(0h1000))) node _T_2387 = asSInt(_T_2386) node _T_2388 = eq(_T_2387, asSInt(UInt<1>(0h0))) node _T_2389 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2390 = cvt(_T_2389) node _T_2391 = and(_T_2390, asSInt(UInt<29>(0h10000000))) node _T_2392 = asSInt(_T_2391) node _T_2393 = eq(_T_2392, asSInt(UInt<1>(0h0))) node _T_2394 = or(_T_2338, _T_2343) node _T_2395 = or(_T_2394, _T_2348) node _T_2396 = or(_T_2395, _T_2353) node _T_2397 = or(_T_2396, _T_2358) node _T_2398 = or(_T_2397, _T_2363) node _T_2399 = or(_T_2398, _T_2368) node _T_2400 = or(_T_2399, _T_2373) node _T_2401 = or(_T_2400, _T_2378) node _T_2402 = or(_T_2401, _T_2383) node _T_2403 = or(_T_2402, _T_2388) node _T_2404 = or(_T_2403, _T_2393) node _T_2405 = and(_T_2333, _T_2404) node _T_2406 = or(UInt<1>(0h0), _T_2405) node _T_2407 = and(_WIRE_9, _T_2406) node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(_T_2407, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2407, UInt<1>(0h1), "") : assert_151 node _T_2411 = asUInt(reset) node _T_2412 = eq(_T_2411, UInt<1>(0h0)) when _T_2412 : node _T_2413 = eq(source_ok_2, UInt<1>(0h0)) when _T_2413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2414 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2415 = asUInt(reset) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) when _T_2416 : node _T_2417 = eq(_T_2414, UInt<1>(0h0)) when _T_2417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2414, UInt<1>(0h1), "") : assert_153 node _T_2418 = asUInt(reset) node _T_2419 = eq(_T_2418, UInt<1>(0h0)) when _T_2419 : node _T_2420 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2421 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_155 node _T_2425 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2425 : node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(address_ok_1, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2429 = asUInt(reset) node _T_2430 = eq(_T_2429, UInt<1>(0h0)) when _T_2430 : node _T_2431 = eq(source_ok_2, UInt<1>(0h0)) when _T_2431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2435 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_159 node _T_2439 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2440 = asUInt(reset) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) when _T_2441 : node _T_2442 = eq(_T_2439, UInt<1>(0h0)) when _T_2442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2439, UInt<1>(0h1), "") : assert_160 node _T_2443 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2443 : node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(address_ok_1, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(source_ok_2, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2453 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_164 node _T_2457 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2457 : node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(address_ok_1, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2461 = asUInt(reset) node _T_2462 = eq(_T_2461, UInt<1>(0h0)) when _T_2462 : node _T_2463 = eq(source_ok_2, UInt<1>(0h0)) when _T_2463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2467 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_168 node _T_2471 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2472 = asUInt(reset) node _T_2473 = eq(_T_2472, UInt<1>(0h0)) when _T_2473 : node _T_2474 = eq(_T_2471, UInt<1>(0h0)) when _T_2474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2471, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2475 = asUInt(reset) node _T_2476 = eq(_T_2475, UInt<1>(0h0)) when _T_2476 : node _T_2477 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2478 = eq(a_first, UInt<1>(0h0)) node _T_2479 = and(io.in.a.valid, _T_2478) when _T_2479 : node _T_2480 = eq(io.in.a.bits.opcode, opcode) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_171 node _T_2484 = eq(io.in.a.bits.param, param) node _T_2485 = asUInt(reset) node _T_2486 = eq(_T_2485, UInt<1>(0h0)) when _T_2486 : node _T_2487 = eq(_T_2484, UInt<1>(0h0)) when _T_2487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2484, UInt<1>(0h1), "") : assert_172 node _T_2488 = eq(io.in.a.bits.size, size) node _T_2489 = asUInt(reset) node _T_2490 = eq(_T_2489, UInt<1>(0h0)) when _T_2490 : node _T_2491 = eq(_T_2488, UInt<1>(0h0)) when _T_2491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2488, UInt<1>(0h1), "") : assert_173 node _T_2492 = eq(io.in.a.bits.source, source) node _T_2493 = asUInt(reset) node _T_2494 = eq(_T_2493, UInt<1>(0h0)) when _T_2494 : node _T_2495 = eq(_T_2492, UInt<1>(0h0)) when _T_2495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2492, UInt<1>(0h1), "") : assert_174 node _T_2496 = eq(io.in.a.bits.address, address) node _T_2497 = asUInt(reset) node _T_2498 = eq(_T_2497, UInt<1>(0h0)) when _T_2498 : node _T_2499 = eq(_T_2496, UInt<1>(0h0)) when _T_2499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2496, UInt<1>(0h1), "") : assert_175 node _T_2500 = and(io.in.a.ready, io.in.a.valid) node _T_2501 = and(_T_2500, a_first) when _T_2501 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2502 = eq(d_first, UInt<1>(0h0)) node _T_2503 = and(io.in.d.valid, _T_2502) when _T_2503 : node _T_2504 = eq(io.in.d.bits.opcode, opcode_1) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_176 node _T_2508 = eq(io.in.d.bits.param, param_1) node _T_2509 = asUInt(reset) node _T_2510 = eq(_T_2509, UInt<1>(0h0)) when _T_2510 : node _T_2511 = eq(_T_2508, UInt<1>(0h0)) when _T_2511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2508, UInt<1>(0h1), "") : assert_177 node _T_2512 = eq(io.in.d.bits.size, size_1) node _T_2513 = asUInt(reset) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) when _T_2514 : node _T_2515 = eq(_T_2512, UInt<1>(0h0)) when _T_2515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2512, UInt<1>(0h1), "") : assert_178 node _T_2516 = eq(io.in.d.bits.source, source_1) node _T_2517 = asUInt(reset) node _T_2518 = eq(_T_2517, UInt<1>(0h0)) when _T_2518 : node _T_2519 = eq(_T_2516, UInt<1>(0h0)) when _T_2519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2516, UInt<1>(0h1), "") : assert_179 node _T_2520 = eq(io.in.d.bits.sink, sink) node _T_2521 = asUInt(reset) node _T_2522 = eq(_T_2521, UInt<1>(0h0)) when _T_2522 : node _T_2523 = eq(_T_2520, UInt<1>(0h0)) when _T_2523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2520, UInt<1>(0h1), "") : assert_180 node _T_2524 = eq(io.in.d.bits.denied, denied) node _T_2525 = asUInt(reset) node _T_2526 = eq(_T_2525, UInt<1>(0h0)) when _T_2526 : node _T_2527 = eq(_T_2524, UInt<1>(0h0)) when _T_2527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2524, UInt<1>(0h1), "") : assert_181 node _T_2528 = and(io.in.d.ready, io.in.d.valid) node _T_2529 = and(_T_2528, d_first) when _T_2529 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2530 = eq(b_first, UInt<1>(0h0)) node _T_2531 = and(io.in.b.valid, _T_2530) when _T_2531 : node _T_2532 = eq(io.in.b.bits.opcode, opcode_2) node _T_2533 = asUInt(reset) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) when _T_2534 : node _T_2535 = eq(_T_2532, UInt<1>(0h0)) when _T_2535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2532, UInt<1>(0h1), "") : assert_182 node _T_2536 = eq(io.in.b.bits.param, param_2) node _T_2537 = asUInt(reset) node _T_2538 = eq(_T_2537, UInt<1>(0h0)) when _T_2538 : node _T_2539 = eq(_T_2536, UInt<1>(0h0)) when _T_2539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2536, UInt<1>(0h1), "") : assert_183 node _T_2540 = eq(io.in.b.bits.size, size_2) node _T_2541 = asUInt(reset) node _T_2542 = eq(_T_2541, UInt<1>(0h0)) when _T_2542 : node _T_2543 = eq(_T_2540, UInt<1>(0h0)) when _T_2543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2540, UInt<1>(0h1), "") : assert_184 node _T_2544 = eq(io.in.b.bits.source, source_2) node _T_2545 = asUInt(reset) node _T_2546 = eq(_T_2545, UInt<1>(0h0)) when _T_2546 : node _T_2547 = eq(_T_2544, UInt<1>(0h0)) when _T_2547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2544, UInt<1>(0h1), "") : assert_185 node _T_2548 = eq(io.in.b.bits.address, address_1) node _T_2549 = asUInt(reset) node _T_2550 = eq(_T_2549, UInt<1>(0h0)) when _T_2550 : node _T_2551 = eq(_T_2548, UInt<1>(0h0)) when _T_2551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2548, UInt<1>(0h1), "") : assert_186 node _T_2552 = and(io.in.b.ready, io.in.b.valid) node _T_2553 = and(_T_2552, b_first) when _T_2553 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2554 = eq(c_first, UInt<1>(0h0)) node _T_2555 = and(io.in.c.valid, _T_2554) when _T_2555 : node _T_2556 = eq(io.in.c.bits.opcode, opcode_3) node _T_2557 = asUInt(reset) node _T_2558 = eq(_T_2557, UInt<1>(0h0)) when _T_2558 : node _T_2559 = eq(_T_2556, UInt<1>(0h0)) when _T_2559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2556, UInt<1>(0h1), "") : assert_187 node _T_2560 = eq(io.in.c.bits.param, param_3) node _T_2561 = asUInt(reset) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) when _T_2562 : node _T_2563 = eq(_T_2560, UInt<1>(0h0)) when _T_2563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2560, UInt<1>(0h1), "") : assert_188 node _T_2564 = eq(io.in.c.bits.size, size_3) node _T_2565 = asUInt(reset) node _T_2566 = eq(_T_2565, UInt<1>(0h0)) when _T_2566 : node _T_2567 = eq(_T_2564, UInt<1>(0h0)) when _T_2567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2564, UInt<1>(0h1), "") : assert_189 node _T_2568 = eq(io.in.c.bits.source, source_3) node _T_2569 = asUInt(reset) node _T_2570 = eq(_T_2569, UInt<1>(0h0)) when _T_2570 : node _T_2571 = eq(_T_2568, UInt<1>(0h0)) when _T_2571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2568, UInt<1>(0h1), "") : assert_190 node _T_2572 = eq(io.in.c.bits.address, address_2) node _T_2573 = asUInt(reset) node _T_2574 = eq(_T_2573, UInt<1>(0h0)) when _T_2574 : node _T_2575 = eq(_T_2572, UInt<1>(0h0)) when _T_2575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2572, UInt<1>(0h1), "") : assert_191 node _T_2576 = and(io.in.c.ready, io.in.c.valid) node _T_2577 = and(_T_2576, c_first) when _T_2577 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2578 = and(io.in.a.valid, a_first_1) node _T_2579 = and(_T_2578, UInt<1>(0h1)) when _T_2579 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2580 = and(io.in.a.ready, io.in.a.valid) node _T_2581 = and(_T_2580, a_first_1) node _T_2582 = and(_T_2581, UInt<1>(0h1)) when _T_2582 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2583 = dshr(inflight, io.in.a.bits.source) node _T_2584 = bits(_T_2583, 0, 0) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) node _T_2586 = asUInt(reset) node _T_2587 = eq(_T_2586, UInt<1>(0h0)) when _T_2587 : node _T_2588 = eq(_T_2585, UInt<1>(0h0)) when _T_2588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2585, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2589 = and(io.in.d.valid, d_first_1) node _T_2590 = and(_T_2589, UInt<1>(0h1)) node _T_2591 = eq(d_release_ack, UInt<1>(0h0)) node _T_2592 = and(_T_2590, _T_2591) when _T_2592 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2593 = and(io.in.d.ready, io.in.d.valid) node _T_2594 = and(_T_2593, d_first_1) node _T_2595 = and(_T_2594, UInt<1>(0h1)) node _T_2596 = eq(d_release_ack, UInt<1>(0h0)) node _T_2597 = and(_T_2595, _T_2596) when _T_2597 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2598 = and(io.in.d.valid, d_first_1) node _T_2599 = and(_T_2598, UInt<1>(0h1)) node _T_2600 = eq(d_release_ack, UInt<1>(0h0)) node _T_2601 = and(_T_2599, _T_2600) when _T_2601 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2602 = dshr(inflight, io.in.d.bits.source) node _T_2603 = bits(_T_2602, 0, 0) node _T_2604 = or(_T_2603, same_cycle_resp) node _T_2605 = asUInt(reset) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) when _T_2606 : node _T_2607 = eq(_T_2604, UInt<1>(0h0)) when _T_2607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2604, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2608 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2609 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2610 = or(_T_2608, _T_2609) node _T_2611 = asUInt(reset) node _T_2612 = eq(_T_2611, UInt<1>(0h0)) when _T_2612 : node _T_2613 = eq(_T_2610, UInt<1>(0h0)) when _T_2613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2610, UInt<1>(0h1), "") : assert_194 node _T_2614 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2615 = asUInt(reset) node _T_2616 = eq(_T_2615, UInt<1>(0h0)) when _T_2616 : node _T_2617 = eq(_T_2614, UInt<1>(0h0)) when _T_2617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2614, UInt<1>(0h1), "") : assert_195 else : node _T_2618 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2619 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2620 = or(_T_2618, _T_2619) node _T_2621 = asUInt(reset) node _T_2622 = eq(_T_2621, UInt<1>(0h0)) when _T_2622 : node _T_2623 = eq(_T_2620, UInt<1>(0h0)) when _T_2623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2620, UInt<1>(0h1), "") : assert_196 node _T_2624 = eq(io.in.d.bits.size, a_size_lookup) node _T_2625 = asUInt(reset) node _T_2626 = eq(_T_2625, UInt<1>(0h0)) when _T_2626 : node _T_2627 = eq(_T_2624, UInt<1>(0h0)) when _T_2627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2624, UInt<1>(0h1), "") : assert_197 node _T_2628 = and(io.in.d.valid, d_first_1) node _T_2629 = and(_T_2628, a_first_1) node _T_2630 = and(_T_2629, io.in.a.valid) node _T_2631 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2632 = and(_T_2630, _T_2631) node _T_2633 = eq(d_release_ack, UInt<1>(0h0)) node _T_2634 = and(_T_2632, _T_2633) when _T_2634 : node _T_2635 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2636 = or(_T_2635, io.in.a.ready) node _T_2637 = asUInt(reset) node _T_2638 = eq(_T_2637, UInt<1>(0h0)) when _T_2638 : node _T_2639 = eq(_T_2636, UInt<1>(0h0)) when _T_2639 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2636, UInt<1>(0h1), "") : assert_198 node _T_2640 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2641 = orr(a_set_wo_ready) node _T_2642 = eq(_T_2641, UInt<1>(0h0)) node _T_2643 = or(_T_2640, _T_2642) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_16 node _T_2647 = orr(inflight) node _T_2648 = eq(_T_2647, UInt<1>(0h0)) node _T_2649 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2650 = or(_T_2648, _T_2649) node _T_2651 = lt(watchdog, plusarg_reader.out) node _T_2652 = or(_T_2650, _T_2651) node _T_2653 = asUInt(reset) node _T_2654 = eq(_T_2653, UInt<1>(0h0)) when _T_2654 : node _T_2655 = eq(_T_2652, UInt<1>(0h0)) when _T_2655 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2652, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2656 = and(io.in.a.ready, io.in.a.valid) node _T_2657 = and(io.in.d.ready, io.in.d.valid) node _T_2658 = or(_T_2656, _T_2657) when _T_2658 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2659 = and(io.in.c.valid, c_first_1) node _T_2660 = bits(io.in.c.bits.opcode, 2, 2) node _T_2661 = bits(io.in.c.bits.opcode, 1, 1) node _T_2662 = and(_T_2660, _T_2661) node _T_2663 = and(_T_2659, _T_2662) when _T_2663 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2664 = and(io.in.c.ready, io.in.c.valid) node _T_2665 = and(_T_2664, c_first_1) node _T_2666 = bits(io.in.c.bits.opcode, 2, 2) node _T_2667 = bits(io.in.c.bits.opcode, 1, 1) node _T_2668 = and(_T_2666, _T_2667) node _T_2669 = and(_T_2665, _T_2668) when _T_2669 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2670 = dshr(inflight_1, io.in.c.bits.source) node _T_2671 = bits(_T_2670, 0, 0) node _T_2672 = eq(_T_2671, UInt<1>(0h0)) node _T_2673 = asUInt(reset) node _T_2674 = eq(_T_2673, UInt<1>(0h0)) when _T_2674 : node _T_2675 = eq(_T_2672, UInt<1>(0h0)) when _T_2675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2672, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2676 = and(io.in.d.valid, d_first_2) node _T_2677 = and(_T_2676, UInt<1>(0h1)) node _T_2678 = and(_T_2677, d_release_ack_1) when _T_2678 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2679 = and(io.in.d.ready, io.in.d.valid) node _T_2680 = and(_T_2679, d_first_2) node _T_2681 = and(_T_2680, UInt<1>(0h1)) node _T_2682 = and(_T_2681, d_release_ack_1) when _T_2682 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2683 = and(io.in.d.valid, d_first_2) node _T_2684 = and(_T_2683, UInt<1>(0h1)) node _T_2685 = and(_T_2684, d_release_ack_1) when _T_2685 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2686 = dshr(inflight_1, io.in.d.bits.source) node _T_2687 = bits(_T_2686, 0, 0) node _T_2688 = or(_T_2687, same_cycle_resp_1) node _T_2689 = asUInt(reset) node _T_2690 = eq(_T_2689, UInt<1>(0h0)) when _T_2690 : node _T_2691 = eq(_T_2688, UInt<1>(0h0)) when _T_2691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2688, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2692 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2693 = asUInt(reset) node _T_2694 = eq(_T_2693, UInt<1>(0h0)) when _T_2694 : node _T_2695 = eq(_T_2692, UInt<1>(0h0)) when _T_2695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2692, UInt<1>(0h1), "") : assert_203 else : node _T_2696 = eq(io.in.d.bits.size, c_size_lookup) node _T_2697 = asUInt(reset) node _T_2698 = eq(_T_2697, UInt<1>(0h0)) when _T_2698 : node _T_2699 = eq(_T_2696, UInt<1>(0h0)) when _T_2699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2696, UInt<1>(0h1), "") : assert_204 node _T_2700 = and(io.in.d.valid, d_first_2) node _T_2701 = and(_T_2700, c_first_1) node _T_2702 = and(_T_2701, io.in.c.valid) node _T_2703 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2704 = and(_T_2702, _T_2703) node _T_2705 = and(_T_2704, d_release_ack_1) node _T_2706 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2707 = and(_T_2705, _T_2706) when _T_2707 : node _T_2708 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2709 = or(_T_2708, io.in.c.ready) node _T_2710 = asUInt(reset) node _T_2711 = eq(_T_2710, UInt<1>(0h0)) when _T_2711 : node _T_2712 = eq(_T_2709, UInt<1>(0h0)) when _T_2712 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2709, UInt<1>(0h1), "") : assert_205 node _T_2713 = orr(c_set_wo_ready) when _T_2713 : node _T_2714 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2715 = asUInt(reset) node _T_2716 = eq(_T_2715, UInt<1>(0h0)) when _T_2716 : node _T_2717 = eq(_T_2714, UInt<1>(0h0)) when _T_2717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2714, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_17 node _T_2718 = orr(inflight_1) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) node _T_2720 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2721 = or(_T_2719, _T_2720) node _T_2722 = lt(watchdog_1, plusarg_reader_1.out) node _T_2723 = or(_T_2721, _T_2722) node _T_2724 = asUInt(reset) node _T_2725 = eq(_T_2724, UInt<1>(0h0)) when _T_2725 : node _T_2726 = eq(_T_2723, UInt<1>(0h0)) when _T_2726 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2723, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2727 = and(io.in.c.ready, io.in.c.valid) node _T_2728 = and(io.in.d.ready, io.in.d.valid) node _T_2729 = or(_T_2727, _T_2728) when _T_2729 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2730 = and(io.in.d.ready, io.in.d.valid) node _T_2731 = and(_T_2730, d_first_3) node _T_2732 = bits(io.in.d.bits.opcode, 2, 2) node _T_2733 = bits(io.in.d.bits.opcode, 1, 1) node _T_2734 = eq(_T_2733, UInt<1>(0h0)) node _T_2735 = and(_T_2732, _T_2734) node _T_2736 = and(_T_2731, _T_2735) when _T_2736 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2737 = dshr(inflight_2, io.in.d.bits.sink) node _T_2738 = bits(_T_2737, 0, 0) node _T_2739 = eq(_T_2738, UInt<1>(0h0)) node _T_2740 = asUInt(reset) node _T_2741 = eq(_T_2740, UInt<1>(0h0)) when _T_2741 : node _T_2742 = eq(_T_2739, UInt<1>(0h0)) when _T_2742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2739, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2743 = and(io.in.e.ready, io.in.e.valid) node _T_2744 = and(_T_2743, UInt<1>(0h1)) node _T_2745 = and(_T_2744, UInt<1>(0h1)) when _T_2745 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2746 = or(d_set, inflight_2) node _T_2747 = dshr(_T_2746, io.in.e.bits.sink) node _T_2748 = bits(_T_2747, 0, 0) node _T_2749 = asUInt(reset) node _T_2750 = eq(_T_2749, UInt<1>(0h0)) when _T_2750 : node _T_2751 = eq(_T_2748, UInt<1>(0h0)) when _T_2751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:49:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2748, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_8( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [17:0] _GEN_2 = io_in_b_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:18], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [17:0] _GEN_3 = io_in_b_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:18], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [20:0] _GEN_4 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:21], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [25:0] _GEN_5 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:26], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire [25:0] _GEN_6 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_60 = {io_in_b_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46] wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40] wire [27:0] _GEN_7 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_65 = {io_in_b_bits_address_0[31:28], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_66 = {1'h0, _address_ok_T_65}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_67 = _address_ok_T_66 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_68 = _address_ok_T_67; // @[Parameters.scala:137:46] wire _address_ok_T_69 = _address_ok_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_13 = _address_ok_T_69; // @[Parameters.scala:612:40] wire [27:0] _GEN_8 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = {io_in_b_bits_address_0[31:28], _GEN_8}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_14 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [28:0] _GEN_9 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_75 = {io_in_b_bits_address_0[31:29], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_15 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_80 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_16 = _address_ok_T_84; // @[Parameters.scala:612:40] wire _address_ok_T_85 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_86 = _address_ok_T_85 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_87 = _address_ok_T_86 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_88 = _address_ok_T_87 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_89 = _address_ok_T_88 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_90 = _address_ok_T_89 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_91 = _address_ok_T_90 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_92 = _address_ok_T_91 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_93 = _address_ok_T_92 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_94 = _address_ok_T_93 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_95 = _address_ok_T_94 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_96 = _address_ok_T_95 | _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_97 = _address_ok_T_96 | _address_ok_WIRE_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_98 = _address_ok_T_97 | _address_ok_WIRE_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_99 = _address_ok_T_98 | _address_ok_WIRE_15; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_99 | _address_ok_WIRE_16; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_10 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_10; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_10; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_11 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_11; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_11; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_11; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [13:0] _GEN_12 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:14], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [16:0] _GEN_13 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:17], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [17:0] _GEN_14 = io_in_c_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:18], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_129; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_130 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_131 = {1'h0, _address_ok_T_130}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_132 = _address_ok_T_131 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_133 = _address_ok_T_132; // @[Parameters.scala:137:46] wire _address_ok_T_134 = _address_ok_T_133 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_134; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_135 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_136 = {1'h0, _address_ok_T_135}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_137 = _address_ok_T_136 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_138 = _address_ok_T_137; // @[Parameters.scala:137:46] wire _address_ok_T_139 = _address_ok_T_138 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_139; // @[Parameters.scala:612:40] wire [17:0] _GEN_15 = io_in_c_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_140 = {io_in_c_bits_address_0[31:18], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_141 = {1'h0, _address_ok_T_140}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_142 = _address_ok_T_141 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_143 = _address_ok_T_142; // @[Parameters.scala:137:46] wire _address_ok_T_144 = _address_ok_T_143 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_144; // @[Parameters.scala:612:40] wire [20:0] _GEN_16 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_145 = {io_in_c_bits_address_0[31:21], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_146 = {1'h0, _address_ok_T_145}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_147 = _address_ok_T_146 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_148 = _address_ok_T_147; // @[Parameters.scala:137:46] wire _address_ok_T_149 = _address_ok_T_148 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_149; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_150 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_151 = {1'h0, _address_ok_T_150}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_152 = _address_ok_T_151 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_153 = _address_ok_T_152; // @[Parameters.scala:137:46] wire _address_ok_T_154 = _address_ok_T_153 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_154; // @[Parameters.scala:612:40] wire [25:0] _GEN_17 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_155 = {io_in_c_bits_address_0[31:26], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_156 = {1'h0, _address_ok_T_155}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_157 = _address_ok_T_156 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_158 = _address_ok_T_157; // @[Parameters.scala:137:46] wire _address_ok_T_159 = _address_ok_T_158 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_159; // @[Parameters.scala:612:40] wire [25:0] _GEN_18 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_160 = {io_in_c_bits_address_0[31:26], _GEN_18}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_161 = {1'h0, _address_ok_T_160}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_162 = _address_ok_T_161 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_163 = _address_ok_T_162; // @[Parameters.scala:137:46] wire _address_ok_T_164 = _address_ok_T_163 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_12 = _address_ok_T_164; // @[Parameters.scala:612:40] wire [27:0] _GEN_19 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_165 = {io_in_c_bits_address_0[31:28], _GEN_19}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_166 = {1'h0, _address_ok_T_165}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_167 = _address_ok_T_166 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_168 = _address_ok_T_167; // @[Parameters.scala:137:46] wire _address_ok_T_169 = _address_ok_T_168 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_13 = _address_ok_T_169; // @[Parameters.scala:612:40] wire [27:0] _GEN_20 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_170 = {io_in_c_bits_address_0[31:28], _GEN_20}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_171 = {1'h0, _address_ok_T_170}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_172 = _address_ok_T_171 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_173 = _address_ok_T_172; // @[Parameters.scala:137:46] wire _address_ok_T_174 = _address_ok_T_173 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_14 = _address_ok_T_174; // @[Parameters.scala:612:40] wire [28:0] _GEN_21 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_175 = {io_in_c_bits_address_0[31:29], _GEN_21}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_176 = {1'h0, _address_ok_T_175}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_177 = _address_ok_T_176 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_178 = _address_ok_T_177; // @[Parameters.scala:137:46] wire _address_ok_T_179 = _address_ok_T_178 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_15 = _address_ok_T_179; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_180 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_181 = {1'h0, _address_ok_T_180}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_182 = _address_ok_T_181 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_183 = _address_ok_T_182; // @[Parameters.scala:137:46] wire _address_ok_T_184 = _address_ok_T_183 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_16 = _address_ok_T_184; // @[Parameters.scala:612:40] wire _address_ok_T_185 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_186 = _address_ok_T_185 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_187 = _address_ok_T_186 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_188 = _address_ok_T_187 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_189 = _address_ok_T_188 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_190 = _address_ok_T_189 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_191 = _address_ok_T_190 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_192 = _address_ok_T_191 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_193 = _address_ok_T_192 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_194 = _address_ok_T_193 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_195 = _address_ok_T_194 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_196 = _address_ok_T_195 | _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_197 = _address_ok_T_196 | _address_ok_WIRE_1_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_198 = _address_ok_T_197 | _address_ok_WIRE_1_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_199 = _address_ok_T_198 | _address_ok_WIRE_1_15; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_199 | _address_ok_WIRE_1_16; // @[Parameters.scala:612:40, :636:64] wire _T_2656 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2656; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2656; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2730 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2730; // @[Decoupled.scala:51:35] wire [26:0] _GEN_22 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_22; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_22; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2727 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2727; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2727; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_23 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_23; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_23; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_23; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_23; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_24 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_24; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_24; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_24; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_24; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_25 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_26 = 2'h1 << _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_26; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2582 = _T_2656 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2582 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2582 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2582 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2582 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2582 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_27 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_27; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_27; // @[Monitor.scala:673:46, :783:46] wire _T_2628 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_28 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_29 = 2'h1 << _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_29; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2628 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2597 = _T_2730 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2597 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2597 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2597 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_30 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_31 = 2'h1 << _GEN_30; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_31; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_31; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2669 = _T_2727 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2669 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2669 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2669 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2669 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2669 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2700 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2700 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2682 = _T_2730 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2682 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2682 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2682 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2736 = _T_2730 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_32 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_32; // @[OneHot.scala:58:35] assign d_set = _T_2736 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2745 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_33 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_33; // @[OneHot.scala:58:35] assign e_clr = _T_2745 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_246 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_246( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_131 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_131( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_81 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_81( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_167 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_299 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_167( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_299 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_73 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_86 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_73( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_86 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_296 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_40 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_296( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_40 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_33 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_66 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_67 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_202 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_202( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_100 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_100( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_debug : input clock : Clock input reset : Reset output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fragmenter of TLFragmenter_Debug connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect fragmenter.auto.anon_in, tlOut connect tlIn, auto.tl_in connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready

module TLInterconnectCoupler_cbus_to_debug( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_Debug fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip bypass : UInt<1>, pending : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_99 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) connect in_reset, UInt<1>(0h0) reg bypass_reg : UInt<1>, clock node bypass = mux(in_reset, io.bypass, bypass_reg) regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) node _T = and(nodeIn.a.ready, nodeIn.a.valid) node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node a_first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node a_last = or(_r_last_T, _r_last_T_1) node r_3 = and(a_last, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(a_first, r_beats1, r_counter1) connect r_counter, _r_counter_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) node r_counter1_1 = tail(_r_counter1_T_1, 1) node b_first = eq(r_counter_1, UInt<1>(0h0)) node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) node b_last = or(_r_last_T_2, _r_last_T_3) node r_3_1 = and(b_last, _T_1) node _r_count_T_1 = not(r_counter1_1) node r_4_1 = and(r_beats1_1, _r_count_T_1) when _T_1 : node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) connect r_counter_1, _r_counter_T_1 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) node r_counter1_2 = tail(_r_counter1_T_2, 1) node c_first = eq(r_counter_2, UInt<1>(0h0)) node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) node c_last = or(_r_last_T_4, _r_last_T_5) node r_3_2 = and(c_last, _T_2) node _r_count_T_2 = not(r_counter1_2) node r_4_2 = and(r_beats1_2, _r_count_T_2) when _T_2 : node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) connect r_counter_2, _r_counter_T_2 node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) node r_counter1_3 = tail(_r_counter1_T_3, 1) node d_first = eq(r_counter_3, UInt<1>(0h0)) node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) node d_last = or(_r_last_T_6, _r_last_T_7) node r_3_3 = and(d_last, _T_3) node _r_count_T_3 = not(r_counter1_3) node r_4_3 = and(r_beats1_3, _r_count_T_3) when _T_3 : node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) connect r_counter_3, _r_counter_T_3 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) node r_counter1_4 = tail(_r_counter1_T_4, 1) node e_first = eq(r_counter_4, UInt<1>(0h0)) node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node e_last = or(_r_last_T_8, _r_last_T_9) node r_3_4 = and(e_last, _T_4) node _r_count_T_4 = not(r_counter1_4) node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) when _T_4 : node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) connect r_counter_4, _r_counter_T_4 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.mask, UInt<4>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<2>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) node c_request = and(_T_5, _T_6) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_8 = eq(_T_7, UInt<1>(0h0)) node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_10 = eq(_T_9, UInt<1>(0h0)) node c_response = or(_T_8, _T_10) node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) node _T_13 = eq(_T_12, UInt<1>(0h0)) node d_request = and(_T_11, _T_13) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_14.bits.sink, UInt<1>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_inc_T_1 = and(_a_inc_T, a_first) node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_inc_WIRE.bits.data, UInt<32>(0h0) connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) connect _b_inc_WIRE.bits.address, UInt<9>(0h0) connect _b_inc_WIRE.bits.source, UInt<1>(0h0) connect _b_inc_WIRE.bits.size, UInt<2>(0h0) connect _b_inc_WIRE.bits.param, UInt<2>(0h0) connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _b_inc_WIRE.valid, UInt<1>(0h0) connect _b_inc_WIRE.ready, UInt<1>(0h0) wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) node _b_inc_T_1 = and(_b_inc_T, b_first) node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_inc_WIRE.bits.data, UInt<32>(0h0) connect _c_inc_WIRE.bits.address, UInt<9>(0h0) connect _c_inc_WIRE.bits.source, UInt<1>(0h0) connect _c_inc_WIRE.bits.size, UInt<2>(0h0) connect _c_inc_WIRE.bits.param, UInt<3>(0h0) connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _c_inc_WIRE.valid, UInt<1>(0h0) connect _c_inc_WIRE.ready, UInt<1>(0h0) wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) node _c_inc_T_1 = and(_c_inc_T, c_first) node c_inc = and(_c_inc_T_1, c_request) node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_inc_T_1 = and(_d_inc_T, d_first) node d_inc = and(_d_inc_T_1, d_request) wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) connect _e_inc_WIRE.valid, UInt<1>(0h0) connect _e_inc_WIRE.ready, UInt<1>(0h0) wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) node _e_inc_T_1 = and(_e_inc_T, e_first) node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) node inc = cat(a_inc, d_inc) node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_dec_T_1 = and(_a_dec_T, a_last) node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_dec_WIRE.bits.data, UInt<32>(0h0) connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) connect _b_dec_WIRE.bits.address, UInt<9>(0h0) connect _b_dec_WIRE.bits.source, UInt<1>(0h0) connect _b_dec_WIRE.bits.size, UInt<2>(0h0) connect _b_dec_WIRE.bits.param, UInt<2>(0h0) connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _b_dec_WIRE.valid, UInt<1>(0h0) connect _b_dec_WIRE.ready, UInt<1>(0h0) wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) node _b_dec_T_1 = and(_b_dec_T, b_last) node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_dec_WIRE.bits.data, UInt<32>(0h0) connect _c_dec_WIRE.bits.address, UInt<9>(0h0) connect _c_dec_WIRE.bits.source, UInt<1>(0h0) connect _c_dec_WIRE.bits.size, UInt<2>(0h0) connect _c_dec_WIRE.bits.param, UInt<3>(0h0) connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _c_dec_WIRE.valid, UInt<1>(0h0) connect _c_dec_WIRE.ready, UInt<1>(0h0) wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) node _c_dec_T_1 = and(_c_dec_T, c_last) node c_dec = and(_c_dec_T_1, c_response) node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_dec_T_1 = and(_d_dec_T, d_last) node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) connect _e_dec_WIRE.valid, UInt<1>(0h0) connect _e_dec_WIRE.ready, UInt<1>(0h0) wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) node _e_dec_T_1 = and(_e_dec_T, e_last) node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) node dec = cat(a_dec, d_dec) node _next_flight_T = bits(inc, 0, 0) node _next_flight_T_1 = bits(inc, 1, 1) node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) node _next_flight_T_4 = add(flight, _next_flight_T_3) node _next_flight_T_5 = tail(_next_flight_T_4, 1) node _next_flight_T_6 = bits(dec, 0, 0) node _next_flight_T_7 = bits(dec, 1, 1) node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) node next_flight = tail(_next_flight_T_10, 1) connect flight, next_flight node _io_pending_T = gt(flight, UInt<1>(0h0)) connect io.pending, _io_pending_T node _T_14 = eq(next_flight, UInt<1>(0h0)) node _T_15 = or(in_reset, _T_14) when _T_15 : connect bypass_reg, io.bypass node _stall_T = neq(bypass, io.bypass) node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) node stall_counter1 = tail(_stall_counter1_T, 1) node stall_first = eq(stall_counter, UInt<1>(0h0)) node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) node stall_last = or(_stall_last_T, _stall_last_T_1) node stall_done = and(stall_last, _stall_T_1) node _stall_count_T = not(stall_counter1) node stall_count = and(stall_beats1, _stall_count_T) when _stall_T_1 : node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) connect stall_counter, _stall_counter_T node stall = and(_stall_T, stall_first) node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) connect nodeIn.a.ready, _nodeIn_a_ready_T_2 connect nodeOut.a.bits, nodeIn.a.bits connect x1_nodeOut.a.bits, nodeIn.a.bits node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) connect nodeOut.d.ready, _nodeOut_d_ready_T node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) connect nodeIn.d.valid, _nodeIn_d_valid_T wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out, nodeIn.d.bits connect nodeIn_d_bits_out, nodeOut.d.bits wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out_1, nodeIn.d.bits connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.mask, UInt<4>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.ready, UInt<1>(0h1) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.address, UInt<128>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<2>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.valid, UInt<1>(0h0) wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_28.bits.sink, UInt<1>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<9>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<2>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<9>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<2>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready connect _WIRE_33.valid, UInt<1>(0h0) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_34.bits.sink, UInt<1>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) extmodule plusarg_reader_201 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_202 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = |flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_99 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AXI4IdIndexer : input clock : Clock input reset : Reset output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}, last : UInt<1>}}}} wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<3>}}, last : UInt<1>}}} invalidate nodeOut.r.bits.last invalidate nodeOut.r.bits.echo.tl_state.source invalidate nodeOut.r.bits.echo.tl_state.size invalidate nodeOut.r.bits.resp invalidate nodeOut.r.bits.data invalidate nodeOut.r.bits.id invalidate nodeOut.r.valid invalidate nodeOut.r.ready invalidate nodeOut.ar.bits.echo.tl_state.source invalidate nodeOut.ar.bits.echo.tl_state.size invalidate nodeOut.ar.bits.qos invalidate nodeOut.ar.bits.prot invalidate nodeOut.ar.bits.cache invalidate nodeOut.ar.bits.lock invalidate nodeOut.ar.bits.burst invalidate nodeOut.ar.bits.size invalidate nodeOut.ar.bits.len invalidate nodeOut.ar.bits.addr invalidate nodeOut.ar.bits.id invalidate nodeOut.ar.valid invalidate nodeOut.ar.ready invalidate nodeOut.b.bits.echo.tl_state.source invalidate nodeOut.b.bits.echo.tl_state.size invalidate nodeOut.b.bits.resp invalidate nodeOut.b.bits.id invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.w.bits.last invalidate nodeOut.w.bits.strb invalidate nodeOut.w.bits.data invalidate nodeOut.w.valid invalidate nodeOut.w.ready invalidate nodeOut.aw.bits.echo.tl_state.source invalidate nodeOut.aw.bits.echo.tl_state.size invalidate nodeOut.aw.bits.qos invalidate nodeOut.aw.bits.prot invalidate nodeOut.aw.bits.cache invalidate nodeOut.aw.bits.lock invalidate nodeOut.aw.bits.burst invalidate nodeOut.aw.bits.size invalidate nodeOut.aw.bits.len invalidate nodeOut.aw.bits.addr invalidate nodeOut.aw.bits.id invalidate nodeOut.aw.valid invalidate nodeOut.aw.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut.ar.bits.echo.tl_state.source, nodeIn.ar.bits.echo.tl_state.source connect nodeOut.ar.bits.echo.tl_state.size, nodeIn.ar.bits.echo.tl_state.size connect nodeOut.ar.bits.qos, nodeIn.ar.bits.qos connect nodeOut.ar.bits.prot, nodeIn.ar.bits.prot connect nodeOut.ar.bits.cache, nodeIn.ar.bits.cache connect nodeOut.ar.bits.lock, nodeIn.ar.bits.lock connect nodeOut.ar.bits.burst, nodeIn.ar.bits.burst connect nodeOut.ar.bits.size, nodeIn.ar.bits.size connect nodeOut.ar.bits.len, nodeIn.ar.bits.len connect nodeOut.ar.bits.addr, nodeIn.ar.bits.addr connect nodeOut.ar.bits.id, nodeIn.ar.bits.id connect nodeOut.ar.valid, nodeIn.ar.valid connect nodeIn.ar.ready, nodeOut.ar.ready connect nodeOut.aw.bits.echo.tl_state.source, nodeIn.aw.bits.echo.tl_state.source connect nodeOut.aw.bits.echo.tl_state.size, nodeIn.aw.bits.echo.tl_state.size connect nodeOut.aw.bits.qos, nodeIn.aw.bits.qos connect nodeOut.aw.bits.prot, nodeIn.aw.bits.prot connect nodeOut.aw.bits.cache, nodeIn.aw.bits.cache connect nodeOut.aw.bits.lock, nodeIn.aw.bits.lock connect nodeOut.aw.bits.burst, nodeIn.aw.bits.burst connect nodeOut.aw.bits.size, nodeIn.aw.bits.size connect nodeOut.aw.bits.len, nodeIn.aw.bits.len connect nodeOut.aw.bits.addr, nodeIn.aw.bits.addr connect nodeOut.aw.bits.id, nodeIn.aw.bits.id connect nodeOut.aw.valid, nodeIn.aw.valid connect nodeIn.aw.ready, nodeOut.aw.ready connect nodeOut.w.bits.last, nodeIn.w.bits.last connect nodeOut.w.bits.strb, nodeIn.w.bits.strb connect nodeOut.w.bits.data, nodeIn.w.bits.data connect nodeOut.w.valid, nodeIn.w.valid connect nodeIn.w.ready, nodeOut.w.ready connect nodeIn.b.bits.echo.tl_state.source, nodeOut.b.bits.echo.tl_state.source connect nodeIn.b.bits.echo.tl_state.size, nodeOut.b.bits.echo.tl_state.size connect nodeIn.b.bits.resp, nodeOut.b.bits.resp connect nodeIn.b.bits.id, nodeOut.b.bits.id connect nodeIn.b.valid, nodeOut.b.valid connect nodeOut.b.ready, nodeIn.b.ready connect nodeIn.r.bits.last, nodeOut.r.bits.last connect nodeIn.r.bits.echo.tl_state.source, nodeOut.r.bits.echo.tl_state.source connect nodeIn.r.bits.echo.tl_state.size, nodeOut.r.bits.echo.tl_state.size connect nodeIn.r.bits.resp, nodeOut.r.bits.resp connect nodeIn.r.bits.data, nodeOut.r.bits.data connect nodeIn.r.bits.id, nodeOut.r.bits.id connect nodeIn.r.valid, nodeOut.r.valid connect nodeOut.r.ready, nodeIn.r.ready extmodule plusarg_reader_66 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_67 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module AXI4IdIndexer( // @[IdIndexer.scala:63:9] input clock, // @[IdIndexer.scala:63:9] input reset, // @[IdIndexer.scala:63:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[IdIndexer.scala:63:9] wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[IdIndexer.scala:63:9] wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_aw_bits_echo_tl_state_size_0 = auto_in_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_aw_bits_echo_tl_state_source_0 = auto_in_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_in_w_valid_0 = auto_in_w_valid; // @[IdIndexer.scala:63:9] wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[IdIndexer.scala:63:9] wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[IdIndexer.scala:63:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[IdIndexer.scala:63:9] wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[IdIndexer.scala:63:9] wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[IdIndexer.scala:63:9] wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[IdIndexer.scala:63:9] wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_ar_bits_echo_tl_state_size_0 = auto_in_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_ar_bits_echo_tl_state_source_0 = auto_in_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_in_r_ready_0 = auto_in_r_ready; // @[IdIndexer.scala:63:9] wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[IdIndexer.scala:63:9] wire auto_out_w_ready_0 = auto_out_w_ready; // @[IdIndexer.scala:63:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_b_bits_echo_tl_state_size_0 = auto_out_b_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_b_bits_echo_tl_state_source_0 = auto_out_b_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[IdIndexer.scala:63:9] wire auto_out_r_valid_0 = auto_out_r_valid; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[IdIndexer.scala:63:9] wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_r_bits_echo_tl_state_size_0 = auto_out_r_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_r_bits_echo_tl_state_source_0 = auto_out_r_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[IdIndexer.scala:63:9] wire nodeIn_aw_ready; // @[MixedNode.scala:551:17] wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[IdIndexer.scala:63:9] wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeIn_w_ready; // @[MixedNode.scala:551:17] wire nodeIn_w_valid = auto_in_w_valid_0; // @[IdIndexer.scala:63:9] wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[IdIndexer.scala:63:9] wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[IdIndexer.scala:63:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[IdIndexer.scala:63:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_ar_ready; // @[MixedNode.scala:551:17] wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[IdIndexer.scala:63:9] wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeIn_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeIn_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeIn_r_ready = auto_in_r_ready_0; // @[IdIndexer.scala:63:9] wire nodeIn_r_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_r_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17] wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_aw_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_w_ready = auto_out_w_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_w_valid; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17] wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeOut_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[IdIndexer.scala:63:9] wire nodeOut_ar_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17] wire nodeOut_r_ready; // @[MixedNode.scala:542:17] wire nodeOut_r_valid = auto_out_r_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[IdIndexer.scala:63:9] wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[IdIndexer.scala:63:9] wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[IdIndexer.scala:63:9] wire [3:0] nodeOut_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] nodeOut_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_in_aw_ready_0; // @[IdIndexer.scala:63:9] wire auto_in_w_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_b_bits_id_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_b_bits_resp_0; // @[IdIndexer.scala:63:9] wire auto_in_b_valid_0; // @[IdIndexer.scala:63:9] wire auto_in_ar_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_in_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_in_r_bits_id_0; // @[IdIndexer.scala:63:9] wire [63:0] auto_in_r_bits_data_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_in_r_bits_resp_0; // @[IdIndexer.scala:63:9] wire auto_in_r_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_in_r_valid_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] auto_out_aw_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_aw_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_aw_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_aw_bits_burst_0; // @[IdIndexer.scala:63:9] wire auto_out_aw_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_aw_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_aw_bits_qos_0; // @[IdIndexer.scala:63:9] wire auto_out_aw_valid_0; // @[IdIndexer.scala:63:9] wire [63:0] auto_out_w_bits_data_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_w_bits_strb_0; // @[IdIndexer.scala:63:9] wire auto_out_w_bits_last_0; // @[IdIndexer.scala:63:9] wire auto_out_w_valid_0; // @[IdIndexer.scala:63:9] wire auto_out_b_ready_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_id_0; // @[IdIndexer.scala:63:9] wire [31:0] auto_out_ar_bits_addr_0; // @[IdIndexer.scala:63:9] wire [7:0] auto_out_ar_bits_len_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_ar_bits_size_0; // @[IdIndexer.scala:63:9] wire [1:0] auto_out_ar_bits_burst_0; // @[IdIndexer.scala:63:9] wire auto_out_ar_bits_lock_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_cache_0; // @[IdIndexer.scala:63:9] wire [2:0] auto_out_ar_bits_prot_0; // @[IdIndexer.scala:63:9] wire [3:0] auto_out_ar_bits_qos_0; // @[IdIndexer.scala:63:9] wire auto_out_ar_valid_0; // @[IdIndexer.scala:63:9] wire auto_out_r_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[IdIndexer.scala:63:9] assign nodeOut_aw_valid = nodeIn_aw_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_addr = nodeIn_aw_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_len = nodeIn_aw_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_size = nodeIn_aw_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_burst = nodeIn_aw_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_lock = nodeIn_aw_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_cache = nodeIn_aw_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_prot = nodeIn_aw_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_qos = nodeIn_aw_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_echo_tl_state_size = nodeIn_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_echo_tl_state_source = nodeIn_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign auto_in_w_ready_0 = nodeIn_w_ready; // @[IdIndexer.scala:63:9] assign nodeOut_w_valid = nodeIn_w_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_data = nodeIn_w_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_strb = nodeIn_w_bits_strb; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_last = nodeIn_w_bits_last; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_size_0 = nodeIn_b_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_source_0 = nodeIn_b_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[IdIndexer.scala:63:9] assign nodeOut_ar_valid = nodeIn_ar_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_addr = nodeIn_ar_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_len = nodeIn_ar_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_size = nodeIn_ar_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_burst = nodeIn_ar_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_lock = nodeIn_ar_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_cache = nodeIn_ar_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_prot = nodeIn_ar_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_qos = nodeIn_ar_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_echo_tl_state_size = nodeIn_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_echo_tl_state_source = nodeIn_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_r_valid_0 = nodeIn_r_valid; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_size_0 = nodeIn_r_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_source_0 = nodeIn_r_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[IdIndexer.scala:63:9] assign nodeIn_aw_ready = nodeOut_aw_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_size_0 = nodeOut_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_source_0 = nodeOut_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign nodeIn_w_ready = nodeOut_w_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_w_valid_0 = nodeOut_w_valid; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[IdIndexer.scala:63:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[IdIndexer.scala:63:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_resp = nodeOut_b_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_echo_tl_state_size = nodeOut_b_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_echo_tl_state_source = nodeOut_b_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_ar_ready = nodeOut_ar_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_size_0 = nodeOut_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_source_0 = nodeOut_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_out_r_ready_0 = nodeOut_r_ready; // @[IdIndexer.scala:63:9] assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_echo_tl_state_size = nodeOut_r_bits_echo_tl_state_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_echo_tl_state_source = nodeOut_r_bits_echo_tl_state_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_last = nodeOut_r_bits_last; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_id = {1'h0, nodeIn_ar_bits_id}; // @[IdIndexer.scala:69:43] assign nodeOut_aw_bits_id = {1'h0, nodeIn_aw_bits_id}; // @[IdIndexer.scala:69:43, :72:43] assign nodeIn_b_bits_id = nodeOut_b_bits_id[2:0]; // @[IdIndexer.scala:78:43] assign nodeIn_r_bits_id = nodeOut_r_bits_id[2:0]; // @[IdIndexer.scala:81:43] assign auto_in_aw_ready = auto_in_aw_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_w_ready = auto_in_w_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_id = auto_in_b_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_resp = auto_in_b_bits_resp_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_size = auto_in_b_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_source = auto_in_b_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_in_ar_ready = auto_in_ar_ready_0; // @[IdIndexer.scala:63:9] assign auto_in_r_valid = auto_in_r_valid_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_id = auto_in_r_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_data = auto_in_r_bits_data_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_resp = auto_in_r_bits_resp_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_size = auto_in_r_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_source = auto_in_r_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_last = auto_in_r_bits_last_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_valid = auto_out_aw_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_id = auto_out_aw_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_addr = auto_out_aw_bits_addr_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_len = auto_out_aw_bits_len_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_size = auto_out_aw_bits_size_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_burst = auto_out_aw_bits_burst_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_lock = auto_out_aw_bits_lock_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_cache = auto_out_aw_bits_cache_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_prot = auto_out_aw_bits_prot_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_qos = auto_out_aw_bits_qos_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_size = auto_out_aw_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_source = auto_out_aw_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_out_w_valid = auto_out_w_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_data = auto_out_w_bits_data_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_strb = auto_out_w_bits_strb_0; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_last = auto_out_w_bits_last_0; // @[IdIndexer.scala:63:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_valid = auto_out_ar_valid_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_id = auto_out_ar_bits_id_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_addr = auto_out_ar_bits_addr_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_len = auto_out_ar_bits_len_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_size = auto_out_ar_bits_size_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_burst = auto_out_ar_bits_burst_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_lock = auto_out_ar_bits_lock_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_cache = auto_out_ar_bits_cache_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_prot = auto_out_ar_bits_prot_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_qos = auto_out_ar_bits_qos_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_size = auto_out_ar_bits_echo_tl_state_size_0; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_source = auto_out_ar_bits_echo_tl_state_source_0; // @[IdIndexer.scala:63:9] assign auto_out_r_ready = auto_out_r_ready_0; // @[IdIndexer.scala:63:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_73 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_73 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_73( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_73 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_29 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_29( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_acd_router_7ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, routers_egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_7 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0 connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1 connect auto.routers_egress_nodes_out.flit.bits, routers.auto.egress_nodes_out.flit.bits connect auto.routers_egress_nodes_out.flit.valid, routers.auto.egress_nodes_out.flit.valid connect routers.auto.egress_nodes_out.flit.ready, auto.routers_egress_nodes_out.flit.ready connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset

module TLSplitACDxBENoC_acd_router_7ClockSinkDomain( // @[ClockDomain.scala:14:9] output [1:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_7 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4), .auto_egress_nodes_out_flit_ready (auto_routers_egress_nodes_out_flit_ready), .auto_egress_nodes_out_flit_valid (auto_routers_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (auto_routers_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (auto_routers_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (auto_routers_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid), .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head), .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail), .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload), .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return), .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_288 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_288( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_50 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node adjustedSig = shl(io.in.sig, 25) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _common_expOut_T = bits(sAdjustedExp, 8, 0) node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0)) node _common_expOut_T_2 = tail(_common_expOut_T_1, 1) connect common_expOut, _common_expOut_T_2 node _common_fractOut_T = bits(adjustedSig, 25, 3) node _common_fractOut_T_1 = bits(adjustedSig, 24, 2) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) connect common_underflow, UInt<1>(0h0) connect common_inexact, UInt<1>(0h0) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_50(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_7 node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h4)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_28 = cvt(_T_27) node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = asSInt(_T_29) node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) node _T_32 = or(_T_26, _T_31) node _T_33 = and(_T_16, _T_24) node _T_34 = and(_T_33, _T_32) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_34, UInt<1>(0h1), "") : assert_1 node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_38 : node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_41 = and(_T_39, _T_40) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_42 = shr(io.in.a.bits.source, 3) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = leq(UInt<1>(0h0), uncommonBits_1) node _T_45 = and(_T_43, _T_44) node _T_46 = leq(uncommonBits_1, UInt<3>(0h4)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_49 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_50 = or(_T_47, _T_48) node _T_51 = or(_T_50, _T_49) node _T_52 = and(_T_41, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_59, _T_64) node _T_101 = or(_T_100, _T_69) node _T_102 = or(_T_101, _T_74) node _T_103 = or(_T_102, _T_79) node _T_104 = or(_T_103, _T_84) node _T_105 = or(_T_104, _T_89) node _T_106 = or(_T_105, _T_94) node _T_107 = or(_T_106, _T_99) node _T_108 = and(_T_54, _T_107) node _T_109 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_110 = or(UInt<1>(0h0), _T_109) node _T_111 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<29>(0h10000000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = or(_T_115, _T_120) node _T_122 = and(_T_110, _T_121) node _T_123 = or(UInt<1>(0h0), _T_108) node _T_124 = or(_T_123, _T_122) node _T_125 = and(_T_53, _T_124) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_125, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_129 = shr(io.in.a.bits.source, 3) node _T_130 = eq(_T_129, UInt<1>(0h0)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_2) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_2, UInt<3>(0h4)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_136 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_134 connect _WIRE[1], _T_135 connect _WIRE[2], _T_136 node _T_137 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_138 = mux(_WIRE[0], _T_137, UInt<1>(0h0)) node _T_139 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_141 = or(_T_138, _T_139) node _T_142 = or(_T_141, _T_140) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_142 node _T_143 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_144 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_145 = and(_T_143, _T_144) node _T_146 = or(UInt<1>(0h0), _T_145) node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<14>(0h2000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<18>(0h2f000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<13>(0h1000))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_178 = cvt(_T_177) node _T_179 = and(_T_178, asSInt(UInt<17>(0h10000))) node _T_180 = asSInt(_T_179) node _T_181 = eq(_T_180, asSInt(UInt<1>(0h0))) node _T_182 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<27>(0h4000000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_188 = cvt(_T_187) node _T_189 = and(_T_188, asSInt(UInt<13>(0h1000))) node _T_190 = asSInt(_T_189) node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0))) node _T_192 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_193 = cvt(_T_192) node _T_194 = and(_T_193, asSInt(UInt<13>(0h1000))) node _T_195 = asSInt(_T_194) node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<29>(0h10000000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = or(_T_151, _T_156) node _T_203 = or(_T_202, _T_161) node _T_204 = or(_T_203, _T_166) node _T_205 = or(_T_204, _T_171) node _T_206 = or(_T_205, _T_176) node _T_207 = or(_T_206, _T_181) node _T_208 = or(_T_207, _T_186) node _T_209 = or(_T_208, _T_191) node _T_210 = or(_T_209, _T_196) node _T_211 = or(_T_210, _T_201) node _T_212 = and(_T_146, _T_211) node _T_213 = or(UInt<1>(0h0), _T_212) node _T_214 = and(_WIRE_1, _T_213) node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_T_214, UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_214, UInt<1>(0h1), "") : assert_3 node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(source_ok, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_221 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_221, UInt<1>(0h1), "") : assert_5 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_228 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_228, UInt<1>(0h1), "") : assert_7 node _T_232 = not(io.in.a.bits.mask) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_233, UInt<1>(0h1), "") : assert_8 node _T_237 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(_T_237, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_237, UInt<1>(0h1), "") : assert_9 node _T_241 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_241 : node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_244 = and(_T_242, _T_243) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_245 = shr(io.in.a.bits.source, 3) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_3) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_3, UInt<3>(0h4)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_252 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_253 = or(_T_250, _T_251) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_244, _T_254) node _T_256 = or(UInt<1>(0h0), _T_255) node _T_257 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<14>(0h2000))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<13>(0h1000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<17>(0h10000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<18>(0h2f000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<17>(0h10000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<27>(0h4000000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<13>(0h1000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<13>(0h1000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_262, _T_267) node _T_304 = or(_T_303, _T_272) node _T_305 = or(_T_304, _T_277) node _T_306 = or(_T_305, _T_282) node _T_307 = or(_T_306, _T_287) node _T_308 = or(_T_307, _T_292) node _T_309 = or(_T_308, _T_297) node _T_310 = or(_T_309, _T_302) node _T_311 = and(_T_257, _T_310) node _T_312 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<17>(0h10000))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<29>(0h10000000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = or(_T_318, _T_323) node _T_325 = and(_T_313, _T_324) node _T_326 = or(UInt<1>(0h0), _T_311) node _T_327 = or(_T_326, _T_325) node _T_328 = and(_T_256, _T_327) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_328, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_332 = shr(io.in.a.bits.source, 3) node _T_333 = eq(_T_332, UInt<1>(0h0)) node _T_334 = leq(UInt<1>(0h0), uncommonBits_4) node _T_335 = and(_T_333, _T_334) node _T_336 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_339 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_337 connect _WIRE_2[1], _T_338 connect _WIRE_2[2], _T_339 node _T_340 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_341 = mux(_WIRE_2[0], _T_340, UInt<1>(0h0)) node _T_342 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_343 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_344 = or(_T_341, _T_342) node _T_345 = or(_T_344, _T_343) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_345 node _T_346 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_347 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_348 = and(_T_346, _T_347) node _T_349 = or(UInt<1>(0h0), _T_348) node _T_350 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<14>(0h2000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<17>(0h10000))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_366 = cvt(_T_365) node _T_367 = and(_T_366, asSInt(UInt<18>(0h2f000))) node _T_368 = asSInt(_T_367) node _T_369 = eq(_T_368, asSInt(UInt<1>(0h0))) node _T_370 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_371 = cvt(_T_370) node _T_372 = and(_T_371, asSInt(UInt<17>(0h10000))) node _T_373 = asSInt(_T_372) node _T_374 = eq(_T_373, asSInt(UInt<1>(0h0))) node _T_375 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<13>(0h1000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<17>(0h10000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_386 = cvt(_T_385) node _T_387 = and(_T_386, asSInt(UInt<27>(0h4000000))) node _T_388 = asSInt(_T_387) node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0))) node _T_390 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_391 = cvt(_T_390) node _T_392 = and(_T_391, asSInt(UInt<13>(0h1000))) node _T_393 = asSInt(_T_392) node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0))) node _T_395 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<13>(0h1000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<29>(0h10000000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = or(_T_354, _T_359) node _T_406 = or(_T_405, _T_364) node _T_407 = or(_T_406, _T_369) node _T_408 = or(_T_407, _T_374) node _T_409 = or(_T_408, _T_379) node _T_410 = or(_T_409, _T_384) node _T_411 = or(_T_410, _T_389) node _T_412 = or(_T_411, _T_394) node _T_413 = or(_T_412, _T_399) node _T_414 = or(_T_413, _T_404) node _T_415 = and(_T_349, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = and(_WIRE_3, _T_416) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_417, UInt<1>(0h1), "") : assert_11 node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(source_ok, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_424 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_424, UInt<1>(0h1), "") : assert_13 node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(is_aligned, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_431 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_431, UInt<1>(0h1), "") : assert_15 node _T_435 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_435, UInt<1>(0h1), "") : assert_16 node _T_439 = not(io.in.a.bits.mask) node _T_440 = eq(_T_439, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_440, UInt<1>(0h1), "") : assert_17 node _T_444 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_444, UInt<1>(0h1), "") : assert_18 node _T_448 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_448 : node _T_449 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_450 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_452 = shr(io.in.a.bits.source, 3) node _T_453 = eq(_T_452, UInt<1>(0h0)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_5) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_459 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_460 = or(_T_457, _T_458) node _T_461 = or(_T_460, _T_459) node _T_462 = and(_T_451, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_479 = and(_T_477, _T_478) node _T_480 = or(UInt<1>(0h0), _T_479) node _T_481 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_482 = cvt(_T_481) node _T_483 = and(_T_482, asSInt(UInt<14>(0h2000))) node _T_484 = asSInt(_T_483) node _T_485 = eq(_T_484, asSInt(UInt<1>(0h0))) node _T_486 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_487 = cvt(_T_486) node _T_488 = and(_T_487, asSInt(UInt<17>(0h10000))) node _T_489 = asSInt(_T_488) node _T_490 = eq(_T_489, asSInt(UInt<1>(0h0))) node _T_491 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_492 = cvt(_T_491) node _T_493 = and(_T_492, asSInt(UInt<18>(0h2f000))) node _T_494 = asSInt(_T_493) node _T_495 = eq(_T_494, asSInt(UInt<1>(0h0))) node _T_496 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<17>(0h10000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_502 = cvt(_T_501) node _T_503 = and(_T_502, asSInt(UInt<13>(0h1000))) node _T_504 = asSInt(_T_503) node _T_505 = eq(_T_504, asSInt(UInt<1>(0h0))) node _T_506 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<17>(0h10000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<27>(0h4000000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<29>(0h10000000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = or(_T_485, _T_490) node _T_532 = or(_T_531, _T_495) node _T_533 = or(_T_532, _T_500) node _T_534 = or(_T_533, _T_505) node _T_535 = or(_T_534, _T_510) node _T_536 = or(_T_535, _T_515) node _T_537 = or(_T_536, _T_520) node _T_538 = or(_T_537, _T_525) node _T_539 = or(_T_538, _T_530) node _T_540 = and(_T_480, _T_539) node _T_541 = or(UInt<1>(0h0), _T_476) node _T_542 = or(_T_541, _T_540) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_542, UInt<1>(0h1), "") : assert_20 node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(source_ok, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(is_aligned, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_552 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_552, UInt<1>(0h1), "") : assert_23 node _T_556 = eq(io.in.a.bits.mask, mask) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_556, UInt<1>(0h1), "") : assert_24 node _T_560 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_560, UInt<1>(0h1), "") : assert_25 node _T_564 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_564 : node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_567 = and(_T_565, _T_566) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_568 = shr(io.in.a.bits.source, 3) node _T_569 = eq(_T_568, UInt<1>(0h0)) node _T_570 = leq(UInt<1>(0h0), uncommonBits_6) node _T_571 = and(_T_569, _T_570) node _T_572 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_573 = and(_T_571, _T_572) node _T_574 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_575 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_576 = or(_T_573, _T_574) node _T_577 = or(_T_576, _T_575) node _T_578 = and(_T_567, _T_577) node _T_579 = or(UInt<1>(0h0), _T_578) node _T_580 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_581 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_582 = and(_T_580, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<13>(0h1000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = and(_T_583, _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<14>(0h2000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<18>(0h2f000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<17>(0h10000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<13>(0h1000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<27>(0h4000000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<13>(0h1000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<13>(0h1000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<29>(0h10000000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = or(_T_598, _T_603) node _T_640 = or(_T_639, _T_608) node _T_641 = or(_T_640, _T_613) node _T_642 = or(_T_641, _T_618) node _T_643 = or(_T_642, _T_623) node _T_644 = or(_T_643, _T_628) node _T_645 = or(_T_644, _T_633) node _T_646 = or(_T_645, _T_638) node _T_647 = and(_T_593, _T_646) node _T_648 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_649 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_650 = cvt(_T_649) node _T_651 = and(_T_650, asSInt(UInt<17>(0h10000))) node _T_652 = asSInt(_T_651) node _T_653 = eq(_T_652, asSInt(UInt<1>(0h0))) node _T_654 = and(_T_648, _T_653) node _T_655 = or(UInt<1>(0h0), _T_589) node _T_656 = or(_T_655, _T_647) node _T_657 = or(_T_656, _T_654) node _T_658 = and(_T_579, _T_657) node _T_659 = asUInt(reset) node _T_660 = eq(_T_659, UInt<1>(0h0)) when _T_660 : node _T_661 = eq(_T_658, UInt<1>(0h0)) when _T_661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_658, UInt<1>(0h1), "") : assert_26 node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(source_ok, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_665 = asUInt(reset) node _T_666 = eq(_T_665, UInt<1>(0h0)) when _T_666 : node _T_667 = eq(is_aligned, UInt<1>(0h0)) when _T_667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_668 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_668, UInt<1>(0h1), "") : assert_29 node _T_672 = eq(io.in.a.bits.mask, mask) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_672, UInt<1>(0h1), "") : assert_30 node _T_676 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_676 : node _T_677 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_678 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_679 = and(_T_677, _T_678) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_680 = shr(io.in.a.bits.source, 3) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = leq(UInt<1>(0h0), uncommonBits_7) node _T_683 = and(_T_681, _T_682) node _T_684 = leq(uncommonBits_7, UInt<3>(0h4)) node _T_685 = and(_T_683, _T_684) node _T_686 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_687 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_688 = or(_T_685, _T_686) node _T_689 = or(_T_688, _T_687) node _T_690 = and(_T_679, _T_689) node _T_691 = or(UInt<1>(0h0), _T_690) node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_693 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_694 = and(_T_692, _T_693) node _T_695 = or(UInt<1>(0h0), _T_694) node _T_696 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<13>(0h1000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = and(_T_695, _T_700) node _T_702 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_703 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_704 = and(_T_702, _T_703) node _T_705 = or(UInt<1>(0h0), _T_704) node _T_706 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<14>(0h2000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<18>(0h2f000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<13>(0h1000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<27>(0h4000000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<13>(0h1000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<29>(0h10000000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = or(_T_710, _T_715) node _T_752 = or(_T_751, _T_720) node _T_753 = or(_T_752, _T_725) node _T_754 = or(_T_753, _T_730) node _T_755 = or(_T_754, _T_735) node _T_756 = or(_T_755, _T_740) node _T_757 = or(_T_756, _T_745) node _T_758 = or(_T_757, _T_750) node _T_759 = and(_T_705, _T_758) node _T_760 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_761 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<17>(0h10000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = and(_T_760, _T_765) node _T_767 = or(UInt<1>(0h0), _T_701) node _T_768 = or(_T_767, _T_759) node _T_769 = or(_T_768, _T_766) node _T_770 = and(_T_691, _T_769) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_770, UInt<1>(0h1), "") : assert_31 node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(source_ok, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(is_aligned, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_780 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_780, UInt<1>(0h1), "") : assert_34 node _T_784 = not(mask) node _T_785 = and(io.in.a.bits.mask, _T_784) node _T_786 = eq(_T_785, UInt<1>(0h0)) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_786, UInt<1>(0h1), "") : assert_35 node _T_790 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_790 : node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_793 = and(_T_791, _T_792) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_794 = shr(io.in.a.bits.source, 3) node _T_795 = eq(_T_794, UInt<1>(0h0)) node _T_796 = leq(UInt<1>(0h0), uncommonBits_8) node _T_797 = and(_T_795, _T_796) node _T_798 = leq(uncommonBits_8, UInt<3>(0h4)) node _T_799 = and(_T_797, _T_798) node _T_800 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_801 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_802 = or(_T_799, _T_800) node _T_803 = or(_T_802, _T_801) node _T_804 = and(_T_793, _T_803) node _T_805 = or(UInt<1>(0h0), _T_804) node _T_806 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_807 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_808 = and(_T_806, _T_807) node _T_809 = or(UInt<1>(0h0), _T_808) node _T_810 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<14>(0h2000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<18>(0h2f000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<17>(0h10000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<27>(0h4000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<13>(0h1000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = or(_T_814, _T_819) node _T_851 = or(_T_850, _T_824) node _T_852 = or(_T_851, _T_829) node _T_853 = or(_T_852, _T_834) node _T_854 = or(_T_853, _T_839) node _T_855 = or(_T_854, _T_844) node _T_856 = or(_T_855, _T_849) node _T_857 = and(_T_809, _T_856) node _T_858 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = and(_T_858, _T_863) node _T_865 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_866 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_867 = and(_T_865, _T_866) node _T_868 = or(UInt<1>(0h0), _T_867) node _T_869 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<29>(0h10000000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = or(_T_873, _T_878) node _T_880 = and(_T_868, _T_879) node _T_881 = or(UInt<1>(0h0), _T_857) node _T_882 = or(_T_881, _T_864) node _T_883 = or(_T_882, _T_880) node _T_884 = and(_T_805, _T_883) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_884, UInt<1>(0h1), "") : assert_36 node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(source_ok, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(is_aligned, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_894 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_894, UInt<1>(0h1), "") : assert_39 node _T_898 = eq(io.in.a.bits.mask, mask) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_898, UInt<1>(0h1), "") : assert_40 node _T_902 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_902 : node _T_903 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_904 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_905 = and(_T_903, _T_904) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_906 = shr(io.in.a.bits.source, 3) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = leq(UInt<1>(0h0), uncommonBits_9) node _T_909 = and(_T_907, _T_908) node _T_910 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_913 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_914 = or(_T_911, _T_912) node _T_915 = or(_T_914, _T_913) node _T_916 = and(_T_905, _T_915) node _T_917 = or(UInt<1>(0h0), _T_916) node _T_918 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_919 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_920 = and(_T_918, _T_919) node _T_921 = or(UInt<1>(0h0), _T_920) node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<13>(0h1000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_953 = cvt(_T_952) node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000))) node _T_955 = asSInt(_T_954) node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0))) node _T_957 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_958 = cvt(_T_957) node _T_959 = and(_T_958, asSInt(UInt<13>(0h1000))) node _T_960 = asSInt(_T_959) node _T_961 = eq(_T_960, asSInt(UInt<1>(0h0))) node _T_962 = or(_T_926, _T_931) node _T_963 = or(_T_962, _T_936) node _T_964 = or(_T_963, _T_941) node _T_965 = or(_T_964, _T_946) node _T_966 = or(_T_965, _T_951) node _T_967 = or(_T_966, _T_956) node _T_968 = or(_T_967, _T_961) node _T_969 = and(_T_921, _T_968) node _T_970 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_971 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_972 = cvt(_T_971) node _T_973 = and(_T_972, asSInt(UInt<17>(0h10000))) node _T_974 = asSInt(_T_973) node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0))) node _T_976 = and(_T_970, _T_975) node _T_977 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_978 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_979 = and(_T_977, _T_978) node _T_980 = or(UInt<1>(0h0), _T_979) node _T_981 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_982 = cvt(_T_981) node _T_983 = and(_T_982, asSInt(UInt<17>(0h10000))) node _T_984 = asSInt(_T_983) node _T_985 = eq(_T_984, asSInt(UInt<1>(0h0))) node _T_986 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_987 = cvt(_T_986) node _T_988 = and(_T_987, asSInt(UInt<29>(0h10000000))) node _T_989 = asSInt(_T_988) node _T_990 = eq(_T_989, asSInt(UInt<1>(0h0))) node _T_991 = or(_T_985, _T_990) node _T_992 = and(_T_980, _T_991) node _T_993 = or(UInt<1>(0h0), _T_969) node _T_994 = or(_T_993, _T_976) node _T_995 = or(_T_994, _T_992) node _T_996 = and(_T_917, _T_995) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_996, UInt<1>(0h1), "") : assert_41 node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(source_ok, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(is_aligned, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1006 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_44 node _T_1010 = eq(io.in.a.bits.mask, mask) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_45 node _T_1014 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1014 : node _T_1015 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1016 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1017 = and(_T_1015, _T_1016) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_1018 = shr(io.in.a.bits.source, 3) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) node _T_1020 = leq(UInt<1>(0h0), uncommonBits_10) node _T_1021 = and(_T_1019, _T_1020) node _T_1022 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_1025 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_1026 = or(_T_1023, _T_1024) node _T_1027 = or(_T_1026, _T_1025) node _T_1028 = and(_T_1017, _T_1027) node _T_1029 = or(UInt<1>(0h0), _T_1028) node _T_1030 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1031 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1032 = and(_T_1030, _T_1031) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1035 = cvt(_T_1034) node _T_1036 = and(_T_1035, asSInt(UInt<13>(0h1000))) node _T_1037 = asSInt(_T_1036) node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0))) node _T_1039 = and(_T_1033, _T_1038) node _T_1040 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1041 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1042 = cvt(_T_1041) node _T_1043 = and(_T_1042, asSInt(UInt<14>(0h2000))) node _T_1044 = asSInt(_T_1043) node _T_1045 = eq(_T_1044, asSInt(UInt<1>(0h0))) node _T_1046 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1047 = cvt(_T_1046) node _T_1048 = and(_T_1047, asSInt(UInt<17>(0h10000))) node _T_1049 = asSInt(_T_1048) node _T_1050 = eq(_T_1049, asSInt(UInt<1>(0h0))) node _T_1051 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<18>(0h2f000))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<17>(0h10000))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1062 = cvt(_T_1061) node _T_1063 = and(_T_1062, asSInt(UInt<13>(0h1000))) node _T_1064 = asSInt(_T_1063) node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0))) node _T_1066 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1067 = cvt(_T_1066) node _T_1068 = and(_T_1067, asSInt(UInt<27>(0h4000000))) node _T_1069 = asSInt(_T_1068) node _T_1070 = eq(_T_1069, asSInt(UInt<1>(0h0))) node _T_1071 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_1072 = cvt(_T_1071) node _T_1073 = and(_T_1072, asSInt(UInt<13>(0h1000))) node _T_1074 = asSInt(_T_1073) node _T_1075 = eq(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1077 = cvt(_T_1076) node _T_1078 = and(_T_1077, asSInt(UInt<13>(0h1000))) node _T_1079 = asSInt(_T_1078) node _T_1080 = eq(_T_1079, asSInt(UInt<1>(0h0))) node _T_1081 = or(_T_1045, _T_1050) node _T_1082 = or(_T_1081, _T_1055) node _T_1083 = or(_T_1082, _T_1060) node _T_1084 = or(_T_1083, _T_1065) node _T_1085 = or(_T_1084, _T_1070) node _T_1086 = or(_T_1085, _T_1075) node _T_1087 = or(_T_1086, _T_1080) node _T_1088 = and(_T_1040, _T_1087) node _T_1089 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1090 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1091 = and(_T_1089, _T_1090) node _T_1092 = or(UInt<1>(0h0), _T_1091) node _T_1093 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1094 = cvt(_T_1093) node _T_1095 = and(_T_1094, asSInt(UInt<17>(0h10000))) node _T_1096 = asSInt(_T_1095) node _T_1097 = eq(_T_1096, asSInt(UInt<1>(0h0))) node _T_1098 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1099 = cvt(_T_1098) node _T_1100 = and(_T_1099, asSInt(UInt<29>(0h10000000))) node _T_1101 = asSInt(_T_1100) node _T_1102 = eq(_T_1101, asSInt(UInt<1>(0h0))) node _T_1103 = or(_T_1097, _T_1102) node _T_1104 = and(_T_1092, _T_1103) node _T_1105 = or(UInt<1>(0h0), _T_1039) node _T_1106 = or(_T_1105, _T_1088) node _T_1107 = or(_T_1106, _T_1104) node _T_1108 = and(_T_1029, _T_1107) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_46 node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(source_ok, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(is_aligned, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1118 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_49 node _T_1122 = eq(io.in.a.bits.mask, mask) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_50 node _T_1126 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1130 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_9 = shr(io.in.d.bits.source, 3) node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0)) node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<3>(0h4)) node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13) node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<3>(0h5)) node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_14 connect _source_ok_WIRE_1[1], _source_ok_T_15 connect _source_ok_WIRE_1[2], _source_ok_T_16 node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1134 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1134 : node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(source_ok_1, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1138 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_54 node _T_1142 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_55 node _T_1146 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_56 node _T_1150 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_57 node _T_1154 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1154 : node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(source_ok_1, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(sink_ok, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1161 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_60 node _T_1165 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_61 node _T_1169 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_62 node _T_1173 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_63 node _T_1177 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1178 = or(UInt<1>(0h1), _T_1177) node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(_T_1178, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1178, UInt<1>(0h1), "") : assert_64 node _T_1182 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1182 : node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(source_ok_1, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(sink_ok, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1189 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_67 node _T_1193 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_68 node _T_1197 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_69 node _T_1201 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.d.bits.corrupt) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_70 node _T_1206 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1207 = or(UInt<1>(0h1), _T_1206) node _T_1208 = asUInt(reset) node _T_1209 = eq(_T_1208, UInt<1>(0h0)) when _T_1209 : node _T_1210 = eq(_T_1207, UInt<1>(0h0)) when _T_1210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1207, UInt<1>(0h1), "") : assert_71 node _T_1211 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1211 : node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(source_ok_1, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1215 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_73 node _T_1219 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_74 node _T_1223 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1224 = or(UInt<1>(0h1), _T_1223) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_75 node _T_1228 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1228 : node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(source_ok_1, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1232 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_77 node _T_1236 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.d.bits.corrupt) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_78 node _T_1241 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1242 = or(UInt<1>(0h1), _T_1241) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_79 node _T_1246 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1246 : node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(source_ok_1, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1250 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_81 node _T_1254 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_82 node _T_1258 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1259 = or(UInt<1>(0h1), _T_1258) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1263 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_1267 = shr(io.in.b.bits.source, 3) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) node _T_1269 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_1272 = and(_T_1270, _T_1271) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1275 = cvt(_T_1274) node _T_1276 = and(_T_1275, asSInt(UInt<1>(0h0))) node _T_1277 = asSInt(_T_1276) node _T_1278 = eq(_T_1277, asSInt(UInt<1>(0h0))) node _T_1279 = or(_T_1273, _T_1278) node _T_1280 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) node _T_1282 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = or(_T_1281, _T_1286) node _T_1288 = eq(io.in.b.bits.source, UInt<4>(0h8)) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) node _T_1290 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<1>(0h0))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = or(_T_1289, _T_1294) node _T_1296 = and(_T_1279, _T_1287) node _T_1297 = and(_T_1296, _T_1295) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<13>(0h1000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_61 = cvt(_address_ok_T_60) node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<29>(0h10000000))) node _address_ok_T_63 = asSInt(_address_ok_T_62) node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[13] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 connect _address_ok_WIRE[12], _address_ok_T_64 node _address_ok_T_65 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[2]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[3]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[4]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[5]) node _address_ok_T_70 = or(_address_ok_T_69, _address_ok_WIRE[6]) node _address_ok_T_71 = or(_address_ok_T_70, _address_ok_WIRE[7]) node _address_ok_T_72 = or(_address_ok_T_71, _address_ok_WIRE[8]) node _address_ok_T_73 = or(_address_ok_T_72, _address_ok_WIRE[9]) node _address_ok_T_74 = or(_address_ok_T_73, _address_ok_WIRE[10]) node _address_ok_T_75 = or(_address_ok_T_74, _address_ok_WIRE[11]) node address_ok = or(_address_ok_T_75, _address_ok_WIRE[12]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_7 node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<3>(0h5), UInt<1>(0h0)) node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) wire _legal_source_WIRE_1 : UInt<4> connect _legal_source_WIRE_1, _legal_source_T_12 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1301 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1301 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_1302 = shr(io.in.b.bits.source, 3) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) node _T_1304 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = leq(uncommonBits_12, UInt<3>(0h4)) node _T_1307 = and(_T_1305, _T_1306) node _T_1308 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1309 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1307 connect _WIRE_4[1], _T_1308 connect _WIRE_4[2], _T_1309 node _T_1310 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1311 = mux(_WIRE_4[0], _T_1310, UInt<1>(0h0)) node _T_1312 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1313 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1314 = or(_T_1311, _T_1312) node _T_1315 = or(_T_1314, _T_1313) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1315 node _T_1316 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1317 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1318 = and(_T_1316, _T_1317) node _T_1319 = or(UInt<1>(0h0), _T_1318) node _T_1320 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1321 = cvt(_T_1320) node _T_1322 = and(_T_1321, asSInt(UInt<14>(0h2000))) node _T_1323 = asSInt(_T_1322) node _T_1324 = eq(_T_1323, asSInt(UInt<1>(0h0))) node _T_1325 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1326 = cvt(_T_1325) node _T_1327 = and(_T_1326, asSInt(UInt<13>(0h1000))) node _T_1328 = asSInt(_T_1327) node _T_1329 = eq(_T_1328, asSInt(UInt<1>(0h0))) node _T_1330 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1331 = cvt(_T_1330) node _T_1332 = and(_T_1331, asSInt(UInt<17>(0h10000))) node _T_1333 = asSInt(_T_1332) node _T_1334 = eq(_T_1333, asSInt(UInt<1>(0h0))) node _T_1335 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1336 = cvt(_T_1335) node _T_1337 = and(_T_1336, asSInt(UInt<18>(0h2f000))) node _T_1338 = asSInt(_T_1337) node _T_1339 = eq(_T_1338, asSInt(UInt<1>(0h0))) node _T_1340 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1341 = cvt(_T_1340) node _T_1342 = and(_T_1341, asSInt(UInt<17>(0h10000))) node _T_1343 = asSInt(_T_1342) node _T_1344 = eq(_T_1343, asSInt(UInt<1>(0h0))) node _T_1345 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1346 = cvt(_T_1345) node _T_1347 = and(_T_1346, asSInt(UInt<13>(0h1000))) node _T_1348 = asSInt(_T_1347) node _T_1349 = eq(_T_1348, asSInt(UInt<1>(0h0))) node _T_1350 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1351 = cvt(_T_1350) node _T_1352 = and(_T_1351, asSInt(UInt<17>(0h10000))) node _T_1353 = asSInt(_T_1352) node _T_1354 = eq(_T_1353, asSInt(UInt<1>(0h0))) node _T_1355 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1356 = cvt(_T_1355) node _T_1357 = and(_T_1356, asSInt(UInt<27>(0h4000000))) node _T_1358 = asSInt(_T_1357) node _T_1359 = eq(_T_1358, asSInt(UInt<1>(0h0))) node _T_1360 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1361 = cvt(_T_1360) node _T_1362 = and(_T_1361, asSInt(UInt<13>(0h1000))) node _T_1363 = asSInt(_T_1362) node _T_1364 = eq(_T_1363, asSInt(UInt<1>(0h0))) node _T_1365 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1366 = cvt(_T_1365) node _T_1367 = and(_T_1366, asSInt(UInt<13>(0h1000))) node _T_1368 = asSInt(_T_1367) node _T_1369 = eq(_T_1368, asSInt(UInt<1>(0h0))) node _T_1370 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1371 = cvt(_T_1370) node _T_1372 = and(_T_1371, asSInt(UInt<29>(0h10000000))) node _T_1373 = asSInt(_T_1372) node _T_1374 = eq(_T_1373, asSInt(UInt<1>(0h0))) node _T_1375 = or(_T_1324, _T_1329) node _T_1376 = or(_T_1375, _T_1334) node _T_1377 = or(_T_1376, _T_1339) node _T_1378 = or(_T_1377, _T_1344) node _T_1379 = or(_T_1378, _T_1349) node _T_1380 = or(_T_1379, _T_1354) node _T_1381 = or(_T_1380, _T_1359) node _T_1382 = or(_T_1381, _T_1364) node _T_1383 = or(_T_1382, _T_1369) node _T_1384 = or(_T_1383, _T_1374) node _T_1385 = and(_T_1319, _T_1384) node _T_1386 = or(UInt<1>(0h0), _T_1385) node _T_1387 = and(_WIRE_5, _T_1386) node _T_1388 = asUInt(reset) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) when _T_1389 : node _T_1390 = eq(_T_1387, UInt<1>(0h0)) when _T_1390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1387, UInt<1>(0h1), "") : assert_86 node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(address_ok, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(legal_source, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1400 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_90 node _T_1404 = eq(io.in.b.bits.mask, mask_1) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_91 node _T_1408 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1409 = asUInt(reset) node _T_1410 = eq(_T_1409, UInt<1>(0h0)) when _T_1410 : node _T_1411 = eq(_T_1408, UInt<1>(0h0)) when _T_1411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1408, UInt<1>(0h1), "") : assert_92 node _T_1412 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1412 : node _T_1413 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1414 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1415 = and(_T_1413, _T_1414) node _T_1416 = or(UInt<1>(0h0), _T_1415) node _T_1417 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1418 = cvt(_T_1417) node _T_1419 = and(_T_1418, asSInt(UInt<14>(0h2000))) node _T_1420 = asSInt(_T_1419) node _T_1421 = eq(_T_1420, asSInt(UInt<1>(0h0))) node _T_1422 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1423 = cvt(_T_1422) node _T_1424 = and(_T_1423, asSInt(UInt<13>(0h1000))) node _T_1425 = asSInt(_T_1424) node _T_1426 = eq(_T_1425, asSInt(UInt<1>(0h0))) node _T_1427 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1428 = cvt(_T_1427) node _T_1429 = and(_T_1428, asSInt(UInt<17>(0h10000))) node _T_1430 = asSInt(_T_1429) node _T_1431 = eq(_T_1430, asSInt(UInt<1>(0h0))) node _T_1432 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1433 = cvt(_T_1432) node _T_1434 = and(_T_1433, asSInt(UInt<18>(0h2f000))) node _T_1435 = asSInt(_T_1434) node _T_1436 = eq(_T_1435, asSInt(UInt<1>(0h0))) node _T_1437 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1438 = cvt(_T_1437) node _T_1439 = and(_T_1438, asSInt(UInt<17>(0h10000))) node _T_1440 = asSInt(_T_1439) node _T_1441 = eq(_T_1440, asSInt(UInt<1>(0h0))) node _T_1442 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1443 = cvt(_T_1442) node _T_1444 = and(_T_1443, asSInt(UInt<13>(0h1000))) node _T_1445 = asSInt(_T_1444) node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) node _T_1447 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1448 = cvt(_T_1447) node _T_1449 = and(_T_1448, asSInt(UInt<17>(0h10000))) node _T_1450 = asSInt(_T_1449) node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) node _T_1452 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1453 = cvt(_T_1452) node _T_1454 = and(_T_1453, asSInt(UInt<27>(0h4000000))) node _T_1455 = asSInt(_T_1454) node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) node _T_1457 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<13>(0h1000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<29>(0h10000000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = or(_T_1421, _T_1426) node _T_1473 = or(_T_1472, _T_1431) node _T_1474 = or(_T_1473, _T_1436) node _T_1475 = or(_T_1474, _T_1441) node _T_1476 = or(_T_1475, _T_1446) node _T_1477 = or(_T_1476, _T_1451) node _T_1478 = or(_T_1477, _T_1456) node _T_1479 = or(_T_1478, _T_1461) node _T_1480 = or(_T_1479, _T_1466) node _T_1481 = or(_T_1480, _T_1471) node _T_1482 = and(_T_1416, _T_1481) node _T_1483 = or(UInt<1>(0h0), _T_1482) node _T_1484 = and(UInt<1>(0h0), _T_1483) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_93 node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(address_ok, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(legal_source, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1497 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1498 = asUInt(reset) node _T_1499 = eq(_T_1498, UInt<1>(0h0)) when _T_1499 : node _T_1500 = eq(_T_1497, UInt<1>(0h0)) when _T_1500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1497, UInt<1>(0h1), "") : assert_97 node _T_1501 = eq(io.in.b.bits.mask, mask_1) node _T_1502 = asUInt(reset) node _T_1503 = eq(_T_1502, UInt<1>(0h0)) when _T_1503 : node _T_1504 = eq(_T_1501, UInt<1>(0h0)) when _T_1504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1501, UInt<1>(0h1), "") : assert_98 node _T_1505 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1506 = asUInt(reset) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) when _T_1507 : node _T_1508 = eq(_T_1505, UInt<1>(0h0)) when _T_1508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1505, UInt<1>(0h1), "") : assert_99 node _T_1509 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1509 : node _T_1510 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1511 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1512 = and(_T_1510, _T_1511) node _T_1513 = or(UInt<1>(0h0), _T_1512) node _T_1514 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1515 = cvt(_T_1514) node _T_1516 = and(_T_1515, asSInt(UInt<14>(0h2000))) node _T_1517 = asSInt(_T_1516) node _T_1518 = eq(_T_1517, asSInt(UInt<1>(0h0))) node _T_1519 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1520 = cvt(_T_1519) node _T_1521 = and(_T_1520, asSInt(UInt<13>(0h1000))) node _T_1522 = asSInt(_T_1521) node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1525 = cvt(_T_1524) node _T_1526 = and(_T_1525, asSInt(UInt<17>(0h10000))) node _T_1527 = asSInt(_T_1526) node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0))) node _T_1529 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1530 = cvt(_T_1529) node _T_1531 = and(_T_1530, asSInt(UInt<18>(0h2f000))) node _T_1532 = asSInt(_T_1531) node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) node _T_1534 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<17>(0h10000))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1540 = cvt(_T_1539) node _T_1541 = and(_T_1540, asSInt(UInt<13>(0h1000))) node _T_1542 = asSInt(_T_1541) node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) node _T_1544 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<17>(0h10000))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1550 = cvt(_T_1549) node _T_1551 = and(_T_1550, asSInt(UInt<27>(0h4000000))) node _T_1552 = asSInt(_T_1551) node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) node _T_1554 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<13>(0h1000))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<13>(0h1000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1565 = cvt(_T_1564) node _T_1566 = and(_T_1565, asSInt(UInt<29>(0h10000000))) node _T_1567 = asSInt(_T_1566) node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) node _T_1569 = or(_T_1518, _T_1523) node _T_1570 = or(_T_1569, _T_1528) node _T_1571 = or(_T_1570, _T_1533) node _T_1572 = or(_T_1571, _T_1538) node _T_1573 = or(_T_1572, _T_1543) node _T_1574 = or(_T_1573, _T_1548) node _T_1575 = or(_T_1574, _T_1553) node _T_1576 = or(_T_1575, _T_1558) node _T_1577 = or(_T_1576, _T_1563) node _T_1578 = or(_T_1577, _T_1568) node _T_1579 = and(_T_1513, _T_1578) node _T_1580 = or(UInt<1>(0h0), _T_1579) node _T_1581 = and(UInt<1>(0h0), _T_1580) node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(_T_1581, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1581, UInt<1>(0h1), "") : assert_100 node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(address_ok, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(legal_source, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1594 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(_T_1594, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1594, UInt<1>(0h1), "") : assert_104 node _T_1598 = eq(io.in.b.bits.mask, mask_1) node _T_1599 = asUInt(reset) node _T_1600 = eq(_T_1599, UInt<1>(0h0)) when _T_1600 : node _T_1601 = eq(_T_1598, UInt<1>(0h0)) when _T_1601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1598, UInt<1>(0h1), "") : assert_105 node _T_1602 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1602 : node _T_1603 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1604 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = or(UInt<1>(0h0), _T_1605) node _T_1607 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<14>(0h2000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<18>(0h2f000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<17>(0h10000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1638 = cvt(_T_1637) node _T_1639 = and(_T_1638, asSInt(UInt<17>(0h10000))) node _T_1640 = asSInt(_T_1639) node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0))) node _T_1642 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1643 = cvt(_T_1642) node _T_1644 = and(_T_1643, asSInt(UInt<27>(0h4000000))) node _T_1645 = asSInt(_T_1644) node _T_1646 = eq(_T_1645, asSInt(UInt<1>(0h0))) node _T_1647 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1648 = cvt(_T_1647) node _T_1649 = and(_T_1648, asSInt(UInt<13>(0h1000))) node _T_1650 = asSInt(_T_1649) node _T_1651 = eq(_T_1650, asSInt(UInt<1>(0h0))) node _T_1652 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1653 = cvt(_T_1652) node _T_1654 = and(_T_1653, asSInt(UInt<13>(0h1000))) node _T_1655 = asSInt(_T_1654) node _T_1656 = eq(_T_1655, asSInt(UInt<1>(0h0))) node _T_1657 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1658 = cvt(_T_1657) node _T_1659 = and(_T_1658, asSInt(UInt<29>(0h10000000))) node _T_1660 = asSInt(_T_1659) node _T_1661 = eq(_T_1660, asSInt(UInt<1>(0h0))) node _T_1662 = or(_T_1611, _T_1616) node _T_1663 = or(_T_1662, _T_1621) node _T_1664 = or(_T_1663, _T_1626) node _T_1665 = or(_T_1664, _T_1631) node _T_1666 = or(_T_1665, _T_1636) node _T_1667 = or(_T_1666, _T_1641) node _T_1668 = or(_T_1667, _T_1646) node _T_1669 = or(_T_1668, _T_1651) node _T_1670 = or(_T_1669, _T_1656) node _T_1671 = or(_T_1670, _T_1661) node _T_1672 = and(_T_1606, _T_1671) node _T_1673 = or(UInt<1>(0h0), _T_1672) node _T_1674 = and(UInt<1>(0h0), _T_1673) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_106 node _T_1678 = asUInt(reset) node _T_1679 = eq(_T_1678, UInt<1>(0h0)) when _T_1679 : node _T_1680 = eq(address_ok, UInt<1>(0h0)) when _T_1680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1681 = asUInt(reset) node _T_1682 = eq(_T_1681, UInt<1>(0h0)) when _T_1682 : node _T_1683 = eq(legal_source, UInt<1>(0h0)) when _T_1683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1687 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_110 node _T_1691 = not(mask_1) node _T_1692 = and(io.in.b.bits.mask, _T_1691) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) node _T_1694 = asUInt(reset) node _T_1695 = eq(_T_1694, UInt<1>(0h0)) when _T_1695 : node _T_1696 = eq(_T_1693, UInt<1>(0h0)) when _T_1696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1693, UInt<1>(0h1), "") : assert_111 node _T_1697 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1697 : node _T_1698 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1699 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1700 = and(_T_1698, _T_1699) node _T_1701 = or(UInt<1>(0h0), _T_1700) node _T_1702 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1703 = cvt(_T_1702) node _T_1704 = and(_T_1703, asSInt(UInt<14>(0h2000))) node _T_1705 = asSInt(_T_1704) node _T_1706 = eq(_T_1705, asSInt(UInt<1>(0h0))) node _T_1707 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1708 = cvt(_T_1707) node _T_1709 = and(_T_1708, asSInt(UInt<13>(0h1000))) node _T_1710 = asSInt(_T_1709) node _T_1711 = eq(_T_1710, asSInt(UInt<1>(0h0))) node _T_1712 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1713 = cvt(_T_1712) node _T_1714 = and(_T_1713, asSInt(UInt<17>(0h10000))) node _T_1715 = asSInt(_T_1714) node _T_1716 = eq(_T_1715, asSInt(UInt<1>(0h0))) node _T_1717 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1718 = cvt(_T_1717) node _T_1719 = and(_T_1718, asSInt(UInt<18>(0h2f000))) node _T_1720 = asSInt(_T_1719) node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0))) node _T_1722 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<17>(0h10000))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<13>(0h1000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<17>(0h10000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<27>(0h4000000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<13>(0h1000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<29>(0h10000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = or(_T_1706, _T_1711) node _T_1758 = or(_T_1757, _T_1716) node _T_1759 = or(_T_1758, _T_1721) node _T_1760 = or(_T_1759, _T_1726) node _T_1761 = or(_T_1760, _T_1731) node _T_1762 = or(_T_1761, _T_1736) node _T_1763 = or(_T_1762, _T_1741) node _T_1764 = or(_T_1763, _T_1746) node _T_1765 = or(_T_1764, _T_1751) node _T_1766 = or(_T_1765, _T_1756) node _T_1767 = and(_T_1701, _T_1766) node _T_1768 = or(UInt<1>(0h0), _T_1767) node _T_1769 = and(UInt<1>(0h0), _T_1768) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_112 node _T_1773 = asUInt(reset) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) when _T_1774 : node _T_1775 = eq(address_ok, UInt<1>(0h0)) when _T_1775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(legal_source, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1782 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_116 node _T_1786 = eq(io.in.b.bits.mask, mask_1) node _T_1787 = asUInt(reset) node _T_1788 = eq(_T_1787, UInt<1>(0h0)) when _T_1788 : node _T_1789 = eq(_T_1786, UInt<1>(0h0)) when _T_1789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1786, UInt<1>(0h1), "") : assert_117 node _T_1790 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1790 : node _T_1791 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1792 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = or(UInt<1>(0h0), _T_1793) node _T_1795 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1796 = cvt(_T_1795) node _T_1797 = and(_T_1796, asSInt(UInt<14>(0h2000))) node _T_1798 = asSInt(_T_1797) node _T_1799 = eq(_T_1798, asSInt(UInt<1>(0h0))) node _T_1800 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1801 = cvt(_T_1800) node _T_1802 = and(_T_1801, asSInt(UInt<13>(0h1000))) node _T_1803 = asSInt(_T_1802) node _T_1804 = eq(_T_1803, asSInt(UInt<1>(0h0))) node _T_1805 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<17>(0h10000))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1811 = cvt(_T_1810) node _T_1812 = and(_T_1811, asSInt(UInt<18>(0h2f000))) node _T_1813 = asSInt(_T_1812) node _T_1814 = eq(_T_1813, asSInt(UInt<1>(0h0))) node _T_1815 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1816 = cvt(_T_1815) node _T_1817 = and(_T_1816, asSInt(UInt<17>(0h10000))) node _T_1818 = asSInt(_T_1817) node _T_1819 = eq(_T_1818, asSInt(UInt<1>(0h0))) node _T_1820 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1821 = cvt(_T_1820) node _T_1822 = and(_T_1821, asSInt(UInt<13>(0h1000))) node _T_1823 = asSInt(_T_1822) node _T_1824 = eq(_T_1823, asSInt(UInt<1>(0h0))) node _T_1825 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1826 = cvt(_T_1825) node _T_1827 = and(_T_1826, asSInt(UInt<17>(0h10000))) node _T_1828 = asSInt(_T_1827) node _T_1829 = eq(_T_1828, asSInt(UInt<1>(0h0))) node _T_1830 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1831 = cvt(_T_1830) node _T_1832 = and(_T_1831, asSInt(UInt<27>(0h4000000))) node _T_1833 = asSInt(_T_1832) node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1836 = cvt(_T_1835) node _T_1837 = and(_T_1836, asSInt(UInt<13>(0h1000))) node _T_1838 = asSInt(_T_1837) node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0))) node _T_1840 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<13>(0h1000))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1846 = cvt(_T_1845) node _T_1847 = and(_T_1846, asSInt(UInt<29>(0h10000000))) node _T_1848 = asSInt(_T_1847) node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0))) node _T_1850 = or(_T_1799, _T_1804) node _T_1851 = or(_T_1850, _T_1809) node _T_1852 = or(_T_1851, _T_1814) node _T_1853 = or(_T_1852, _T_1819) node _T_1854 = or(_T_1853, _T_1824) node _T_1855 = or(_T_1854, _T_1829) node _T_1856 = or(_T_1855, _T_1834) node _T_1857 = or(_T_1856, _T_1839) node _T_1858 = or(_T_1857, _T_1844) node _T_1859 = or(_T_1858, _T_1849) node _T_1860 = and(_T_1794, _T_1859) node _T_1861 = or(UInt<1>(0h0), _T_1860) node _T_1862 = and(UInt<1>(0h0), _T_1861) node _T_1863 = asUInt(reset) node _T_1864 = eq(_T_1863, UInt<1>(0h0)) when _T_1864 : node _T_1865 = eq(_T_1862, UInt<1>(0h0)) when _T_1865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1862, UInt<1>(0h1), "") : assert_118 node _T_1866 = asUInt(reset) node _T_1867 = eq(_T_1866, UInt<1>(0h0)) when _T_1867 : node _T_1868 = eq(address_ok, UInt<1>(0h0)) when _T_1868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(legal_source, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1872 = asUInt(reset) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) when _T_1873 : node _T_1874 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1875 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(_T_1875, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1875, UInt<1>(0h1), "") : assert_122 node _T_1879 = eq(io.in.b.bits.mask, mask_1) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_123 node _T_1883 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1883 : node _T_1884 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1885 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1886 = and(_T_1884, _T_1885) node _T_1887 = or(UInt<1>(0h0), _T_1886) node _T_1888 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1889 = cvt(_T_1888) node _T_1890 = and(_T_1889, asSInt(UInt<14>(0h2000))) node _T_1891 = asSInt(_T_1890) node _T_1892 = eq(_T_1891, asSInt(UInt<1>(0h0))) node _T_1893 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1894 = cvt(_T_1893) node _T_1895 = and(_T_1894, asSInt(UInt<13>(0h1000))) node _T_1896 = asSInt(_T_1895) node _T_1897 = eq(_T_1896, asSInt(UInt<1>(0h0))) node _T_1898 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1899 = cvt(_T_1898) node _T_1900 = and(_T_1899, asSInt(UInt<17>(0h10000))) node _T_1901 = asSInt(_T_1900) node _T_1902 = eq(_T_1901, asSInt(UInt<1>(0h0))) node _T_1903 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1904 = cvt(_T_1903) node _T_1905 = and(_T_1904, asSInt(UInt<18>(0h2f000))) node _T_1906 = asSInt(_T_1905) node _T_1907 = eq(_T_1906, asSInt(UInt<1>(0h0))) node _T_1908 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<17>(0h10000))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1914 = cvt(_T_1913) node _T_1915 = and(_T_1914, asSInt(UInt<13>(0h1000))) node _T_1916 = asSInt(_T_1915) node _T_1917 = eq(_T_1916, asSInt(UInt<1>(0h0))) node _T_1918 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1919 = cvt(_T_1918) node _T_1920 = and(_T_1919, asSInt(UInt<17>(0h10000))) node _T_1921 = asSInt(_T_1920) node _T_1922 = eq(_T_1921, asSInt(UInt<1>(0h0))) node _T_1923 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1924 = cvt(_T_1923) node _T_1925 = and(_T_1924, asSInt(UInt<27>(0h4000000))) node _T_1926 = asSInt(_T_1925) node _T_1927 = eq(_T_1926, asSInt(UInt<1>(0h0))) node _T_1928 = xor(io.in.b.bits.address, UInt<29>(0h10016000)) node _T_1929 = cvt(_T_1928) node _T_1930 = and(_T_1929, asSInt(UInt<13>(0h1000))) node _T_1931 = asSInt(_T_1930) node _T_1932 = eq(_T_1931, asSInt(UInt<1>(0h0))) node _T_1933 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1934 = cvt(_T_1933) node _T_1935 = and(_T_1934, asSInt(UInt<13>(0h1000))) node _T_1936 = asSInt(_T_1935) node _T_1937 = eq(_T_1936, asSInt(UInt<1>(0h0))) node _T_1938 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1939 = cvt(_T_1938) node _T_1940 = and(_T_1939, asSInt(UInt<29>(0h10000000))) node _T_1941 = asSInt(_T_1940) node _T_1942 = eq(_T_1941, asSInt(UInt<1>(0h0))) node _T_1943 = or(_T_1892, _T_1897) node _T_1944 = or(_T_1943, _T_1902) node _T_1945 = or(_T_1944, _T_1907) node _T_1946 = or(_T_1945, _T_1912) node _T_1947 = or(_T_1946, _T_1917) node _T_1948 = or(_T_1947, _T_1922) node _T_1949 = or(_T_1948, _T_1927) node _T_1950 = or(_T_1949, _T_1932) node _T_1951 = or(_T_1950, _T_1937) node _T_1952 = or(_T_1951, _T_1942) node _T_1953 = and(_T_1887, _T_1952) node _T_1954 = or(UInt<1>(0h0), _T_1953) node _T_1955 = and(UInt<1>(0h0), _T_1954) node _T_1956 = asUInt(reset) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) when _T_1957 : node _T_1958 = eq(_T_1955, UInt<1>(0h0)) when _T_1958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1955, UInt<1>(0h1), "") : assert_124 node _T_1959 = asUInt(reset) node _T_1960 = eq(_T_1959, UInt<1>(0h0)) when _T_1960 : node _T_1961 = eq(address_ok, UInt<1>(0h0)) when _T_1961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1962 = asUInt(reset) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) when _T_1963 : node _T_1964 = eq(legal_source, UInt<1>(0h0)) when _T_1964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1965 = asUInt(reset) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) when _T_1966 : node _T_1967 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1968 = eq(io.in.b.bits.mask, mask_1) node _T_1969 = asUInt(reset) node _T_1970 = eq(_T_1969, UInt<1>(0h0)) when _T_1970 : node _T_1971 = eq(_T_1968, UInt<1>(0h0)) when _T_1971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1968, UInt<1>(0h1), "") : assert_128 node _T_1972 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(_T_1972, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1972, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1976 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_18 = shr(io.in.c.bits.source, 3) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<3>(0h4)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_23 connect _source_ok_WIRE_2[1], _source_ok_T_24 connect _source_ok_WIRE_2[2], _source_ok_T_25 node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_76 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_77 = cvt(_address_ok_T_76) node _address_ok_T_78 = and(_address_ok_T_77, asSInt(UInt<13>(0h1000))) node _address_ok_T_79 = asSInt(_address_ok_T_78) node _address_ok_T_80 = eq(_address_ok_T_79, asSInt(UInt<1>(0h0))) node _address_ok_T_81 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_82 = cvt(_address_ok_T_81) node _address_ok_T_83 = and(_address_ok_T_82, asSInt(UInt<13>(0h1000))) node _address_ok_T_84 = asSInt(_address_ok_T_83) node _address_ok_T_85 = eq(_address_ok_T_84, asSInt(UInt<1>(0h0))) node _address_ok_T_86 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_87 = cvt(_address_ok_T_86) node _address_ok_T_88 = and(_address_ok_T_87, asSInt(UInt<13>(0h1000))) node _address_ok_T_89 = asSInt(_address_ok_T_88) node _address_ok_T_90 = eq(_address_ok_T_89, asSInt(UInt<1>(0h0))) node _address_ok_T_91 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_92 = cvt(_address_ok_T_91) node _address_ok_T_93 = and(_address_ok_T_92, asSInt(UInt<17>(0h10000))) node _address_ok_T_94 = asSInt(_address_ok_T_93) node _address_ok_T_95 = eq(_address_ok_T_94, asSInt(UInt<1>(0h0))) node _address_ok_T_96 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_97 = cvt(_address_ok_T_96) node _address_ok_T_98 = and(_address_ok_T_97, asSInt(UInt<13>(0h1000))) node _address_ok_T_99 = asSInt(_address_ok_T_98) node _address_ok_T_100 = eq(_address_ok_T_99, asSInt(UInt<1>(0h0))) node _address_ok_T_101 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_102 = cvt(_address_ok_T_101) node _address_ok_T_103 = and(_address_ok_T_102, asSInt(UInt<13>(0h1000))) node _address_ok_T_104 = asSInt(_address_ok_T_103) node _address_ok_T_105 = eq(_address_ok_T_104, asSInt(UInt<1>(0h0))) node _address_ok_T_106 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_107 = cvt(_address_ok_T_106) node _address_ok_T_108 = and(_address_ok_T_107, asSInt(UInt<17>(0h10000))) node _address_ok_T_109 = asSInt(_address_ok_T_108) node _address_ok_T_110 = eq(_address_ok_T_109, asSInt(UInt<1>(0h0))) node _address_ok_T_111 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_112 = cvt(_address_ok_T_111) node _address_ok_T_113 = and(_address_ok_T_112, asSInt(UInt<13>(0h1000))) node _address_ok_T_114 = asSInt(_address_ok_T_113) node _address_ok_T_115 = eq(_address_ok_T_114, asSInt(UInt<1>(0h0))) node _address_ok_T_116 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_117 = cvt(_address_ok_T_116) node _address_ok_T_118 = and(_address_ok_T_117, asSInt(UInt<17>(0h10000))) node _address_ok_T_119 = asSInt(_address_ok_T_118) node _address_ok_T_120 = eq(_address_ok_T_119, asSInt(UInt<1>(0h0))) node _address_ok_T_121 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_122 = cvt(_address_ok_T_121) node _address_ok_T_123 = and(_address_ok_T_122, asSInt(UInt<27>(0h4000000))) node _address_ok_T_124 = asSInt(_address_ok_T_123) node _address_ok_T_125 = eq(_address_ok_T_124, asSInt(UInt<1>(0h0))) node _address_ok_T_126 = xor(io.in.c.bits.address, UInt<29>(0h10016000)) node _address_ok_T_127 = cvt(_address_ok_T_126) node _address_ok_T_128 = and(_address_ok_T_127, asSInt(UInt<13>(0h1000))) node _address_ok_T_129 = asSInt(_address_ok_T_128) node _address_ok_T_130 = eq(_address_ok_T_129, asSInt(UInt<1>(0h0))) node _address_ok_T_131 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_132 = cvt(_address_ok_T_131) node _address_ok_T_133 = and(_address_ok_T_132, asSInt(UInt<13>(0h1000))) node _address_ok_T_134 = asSInt(_address_ok_T_133) node _address_ok_T_135 = eq(_address_ok_T_134, asSInt(UInt<1>(0h0))) node _address_ok_T_136 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_137 = cvt(_address_ok_T_136) node _address_ok_T_138 = and(_address_ok_T_137, asSInt(UInt<29>(0h10000000))) node _address_ok_T_139 = asSInt(_address_ok_T_138) node _address_ok_T_140 = eq(_address_ok_T_139, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[13] connect _address_ok_WIRE_1[0], _address_ok_T_80 connect _address_ok_WIRE_1[1], _address_ok_T_85 connect _address_ok_WIRE_1[2], _address_ok_T_90 connect _address_ok_WIRE_1[3], _address_ok_T_95 connect _address_ok_WIRE_1[4], _address_ok_T_100 connect _address_ok_WIRE_1[5], _address_ok_T_105 connect _address_ok_WIRE_1[6], _address_ok_T_110 connect _address_ok_WIRE_1[7], _address_ok_T_115 connect _address_ok_WIRE_1[8], _address_ok_T_120 connect _address_ok_WIRE_1[9], _address_ok_T_125 connect _address_ok_WIRE_1[10], _address_ok_T_130 connect _address_ok_WIRE_1[11], _address_ok_T_135 connect _address_ok_WIRE_1[12], _address_ok_T_140 node _address_ok_T_141 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_142 = or(_address_ok_T_141, _address_ok_WIRE_1[2]) node _address_ok_T_143 = or(_address_ok_T_142, _address_ok_WIRE_1[3]) node _address_ok_T_144 = or(_address_ok_T_143, _address_ok_WIRE_1[4]) node _address_ok_T_145 = or(_address_ok_T_144, _address_ok_WIRE_1[5]) node _address_ok_T_146 = or(_address_ok_T_145, _address_ok_WIRE_1[6]) node _address_ok_T_147 = or(_address_ok_T_146, _address_ok_WIRE_1[7]) node _address_ok_T_148 = or(_address_ok_T_147, _address_ok_WIRE_1[8]) node _address_ok_T_149 = or(_address_ok_T_148, _address_ok_WIRE_1[9]) node _address_ok_T_150 = or(_address_ok_T_149, _address_ok_WIRE_1[10]) node _address_ok_T_151 = or(_address_ok_T_150, _address_ok_WIRE_1[11]) node address_ok_1 = or(_address_ok_T_151, _address_ok_WIRE_1[12]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_1980 = shr(io.in.c.bits.source, 3) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) node _T_1982 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1983 = and(_T_1981, _T_1982) node _T_1984 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_1985 = and(_T_1983, _T_1984) node _T_1986 = eq(_T_1985, UInt<1>(0h0)) node _T_1987 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1988 = cvt(_T_1987) node _T_1989 = and(_T_1988, asSInt(UInt<1>(0h0))) node _T_1990 = asSInt(_T_1989) node _T_1991 = eq(_T_1990, asSInt(UInt<1>(0h0))) node _T_1992 = or(_T_1986, _T_1991) node _T_1993 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1994 = eq(_T_1993, UInt<1>(0h0)) node _T_1995 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1996 = cvt(_T_1995) node _T_1997 = and(_T_1996, asSInt(UInt<1>(0h0))) node _T_1998 = asSInt(_T_1997) node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0))) node _T_2000 = or(_T_1994, _T_1999) node _T_2001 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) node _T_2003 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2004 = cvt(_T_2003) node _T_2005 = and(_T_2004, asSInt(UInt<1>(0h0))) node _T_2006 = asSInt(_T_2005) node _T_2007 = eq(_T_2006, asSInt(UInt<1>(0h0))) node _T_2008 = or(_T_2002, _T_2007) node _T_2009 = and(_T_1992, _T_2000) node _T_2010 = and(_T_2009, _T_2008) node _T_2011 = asUInt(reset) node _T_2012 = eq(_T_2011, UInt<1>(0h0)) when _T_2012 : node _T_2013 = eq(_T_2010, UInt<1>(0h0)) when _T_2013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_2010, UInt<1>(0h1), "") : assert_131 node _T_2014 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_2014 : node _T_2015 = asUInt(reset) node _T_2016 = eq(_T_2015, UInt<1>(0h0)) when _T_2016 : node _T_2017 = eq(address_ok_1, UInt<1>(0h0)) when _T_2017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(source_ok_2, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2021 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(_T_2021, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2021, UInt<1>(0h1), "") : assert_134 node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2028 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_136 node _T_2032 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2033 = asUInt(reset) node _T_2034 = eq(_T_2033, UInt<1>(0h0)) when _T_2034 : node _T_2035 = eq(_T_2032, UInt<1>(0h0)) when _T_2035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2032, UInt<1>(0h1), "") : assert_137 node _T_2036 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2036 : node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(address_ok_1, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2040 = asUInt(reset) node _T_2041 = eq(_T_2040, UInt<1>(0h0)) when _T_2041 : node _T_2042 = eq(source_ok_2, UInt<1>(0h0)) when _T_2042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2043 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2044 = asUInt(reset) node _T_2045 = eq(_T_2044, UInt<1>(0h0)) when _T_2045 : node _T_2046 = eq(_T_2043, UInt<1>(0h0)) when _T_2046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2043, UInt<1>(0h1), "") : assert_140 node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2050 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_142 node _T_2054 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2054 : node _T_2055 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2056 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2057 = and(_T_2055, _T_2056) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_2058 = shr(io.in.c.bits.source, 3) node _T_2059 = eq(_T_2058, UInt<1>(0h0)) node _T_2060 = leq(UInt<1>(0h0), uncommonBits_14) node _T_2061 = and(_T_2059, _T_2060) node _T_2062 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_2063 = and(_T_2061, _T_2062) node _T_2064 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2065 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2066 = or(_T_2063, _T_2064) node _T_2067 = or(_T_2066, _T_2065) node _T_2068 = and(_T_2057, _T_2067) node _T_2069 = or(UInt<1>(0h0), _T_2068) node _T_2070 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2071 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2072 = cvt(_T_2071) node _T_2073 = and(_T_2072, asSInt(UInt<14>(0h2000))) node _T_2074 = asSInt(_T_2073) node _T_2075 = eq(_T_2074, asSInt(UInt<1>(0h0))) node _T_2076 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2077 = cvt(_T_2076) node _T_2078 = and(_T_2077, asSInt(UInt<13>(0h1000))) node _T_2079 = asSInt(_T_2078) node _T_2080 = eq(_T_2079, asSInt(UInt<1>(0h0))) node _T_2081 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2082 = cvt(_T_2081) node _T_2083 = and(_T_2082, asSInt(UInt<17>(0h10000))) node _T_2084 = asSInt(_T_2083) node _T_2085 = eq(_T_2084, asSInt(UInt<1>(0h0))) node _T_2086 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2087 = cvt(_T_2086) node _T_2088 = and(_T_2087, asSInt(UInt<18>(0h2f000))) node _T_2089 = asSInt(_T_2088) node _T_2090 = eq(_T_2089, asSInt(UInt<1>(0h0))) node _T_2091 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2092 = cvt(_T_2091) node _T_2093 = and(_T_2092, asSInt(UInt<17>(0h10000))) node _T_2094 = asSInt(_T_2093) node _T_2095 = eq(_T_2094, asSInt(UInt<1>(0h0))) node _T_2096 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2097 = cvt(_T_2096) node _T_2098 = and(_T_2097, asSInt(UInt<13>(0h1000))) node _T_2099 = asSInt(_T_2098) node _T_2100 = eq(_T_2099, asSInt(UInt<1>(0h0))) node _T_2101 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2102 = cvt(_T_2101) node _T_2103 = and(_T_2102, asSInt(UInt<27>(0h4000000))) node _T_2104 = asSInt(_T_2103) node _T_2105 = eq(_T_2104, asSInt(UInt<1>(0h0))) node _T_2106 = xor(io.in.c.bits.address, UInt<29>(0h10016000)) node _T_2107 = cvt(_T_2106) node _T_2108 = and(_T_2107, asSInt(UInt<13>(0h1000))) node _T_2109 = asSInt(_T_2108) node _T_2110 = eq(_T_2109, asSInt(UInt<1>(0h0))) node _T_2111 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<13>(0h1000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = or(_T_2075, _T_2080) node _T_2117 = or(_T_2116, _T_2085) node _T_2118 = or(_T_2117, _T_2090) node _T_2119 = or(_T_2118, _T_2095) node _T_2120 = or(_T_2119, _T_2100) node _T_2121 = or(_T_2120, _T_2105) node _T_2122 = or(_T_2121, _T_2110) node _T_2123 = or(_T_2122, _T_2115) node _T_2124 = and(_T_2070, _T_2123) node _T_2125 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2126 = or(UInt<1>(0h0), _T_2125) node _T_2127 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2128 = cvt(_T_2127) node _T_2129 = and(_T_2128, asSInt(UInt<17>(0h10000))) node _T_2130 = asSInt(_T_2129) node _T_2131 = eq(_T_2130, asSInt(UInt<1>(0h0))) node _T_2132 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2133 = cvt(_T_2132) node _T_2134 = and(_T_2133, asSInt(UInt<29>(0h10000000))) node _T_2135 = asSInt(_T_2134) node _T_2136 = eq(_T_2135, asSInt(UInt<1>(0h0))) node _T_2137 = or(_T_2131, _T_2136) node _T_2138 = and(_T_2126, _T_2137) node _T_2139 = or(UInt<1>(0h0), _T_2124) node _T_2140 = or(_T_2139, _T_2138) node _T_2141 = and(_T_2069, _T_2140) node _T_2142 = asUInt(reset) node _T_2143 = eq(_T_2142, UInt<1>(0h0)) when _T_2143 : node _T_2144 = eq(_T_2141, UInt<1>(0h0)) when _T_2144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2141, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 2, 0) node _T_2145 = shr(io.in.c.bits.source, 3) node _T_2146 = eq(_T_2145, UInt<1>(0h0)) node _T_2147 = leq(UInt<1>(0h0), uncommonBits_15) node _T_2148 = and(_T_2146, _T_2147) node _T_2149 = leq(uncommonBits_15, UInt<3>(0h4)) node _T_2150 = and(_T_2148, _T_2149) node _T_2151 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2152 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2150 connect _WIRE_6[1], _T_2151 connect _WIRE_6[2], _T_2152 node _T_2153 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2154 = mux(_WIRE_6[0], _T_2153, UInt<1>(0h0)) node _T_2155 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2156 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2157 = or(_T_2154, _T_2155) node _T_2158 = or(_T_2157, _T_2156) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2158 node _T_2159 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2160 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2161 = and(_T_2159, _T_2160) node _T_2162 = or(UInt<1>(0h0), _T_2161) node _T_2163 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2164 = cvt(_T_2163) node _T_2165 = and(_T_2164, asSInt(UInt<14>(0h2000))) node _T_2166 = asSInt(_T_2165) node _T_2167 = eq(_T_2166, asSInt(UInt<1>(0h0))) node _T_2168 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2169 = cvt(_T_2168) node _T_2170 = and(_T_2169, asSInt(UInt<13>(0h1000))) node _T_2171 = asSInt(_T_2170) node _T_2172 = eq(_T_2171, asSInt(UInt<1>(0h0))) node _T_2173 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2174 = cvt(_T_2173) node _T_2175 = and(_T_2174, asSInt(UInt<17>(0h10000))) node _T_2176 = asSInt(_T_2175) node _T_2177 = eq(_T_2176, asSInt(UInt<1>(0h0))) node _T_2178 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2179 = cvt(_T_2178) node _T_2180 = and(_T_2179, asSInt(UInt<18>(0h2f000))) node _T_2181 = asSInt(_T_2180) node _T_2182 = eq(_T_2181, asSInt(UInt<1>(0h0))) node _T_2183 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2184 = cvt(_T_2183) node _T_2185 = and(_T_2184, asSInt(UInt<17>(0h10000))) node _T_2186 = asSInt(_T_2185) node _T_2187 = eq(_T_2186, asSInt(UInt<1>(0h0))) node _T_2188 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2189 = cvt(_T_2188) node _T_2190 = and(_T_2189, asSInt(UInt<13>(0h1000))) node _T_2191 = asSInt(_T_2190) node _T_2192 = eq(_T_2191, asSInt(UInt<1>(0h0))) node _T_2193 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2194 = cvt(_T_2193) node _T_2195 = and(_T_2194, asSInt(UInt<17>(0h10000))) node _T_2196 = asSInt(_T_2195) node _T_2197 = eq(_T_2196, asSInt(UInt<1>(0h0))) node _T_2198 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2199 = cvt(_T_2198) node _T_2200 = and(_T_2199, asSInt(UInt<27>(0h4000000))) node _T_2201 = asSInt(_T_2200) node _T_2202 = eq(_T_2201, asSInt(UInt<1>(0h0))) node _T_2203 = xor(io.in.c.bits.address, UInt<29>(0h10016000)) node _T_2204 = cvt(_T_2203) node _T_2205 = and(_T_2204, asSInt(UInt<13>(0h1000))) node _T_2206 = asSInt(_T_2205) node _T_2207 = eq(_T_2206, asSInt(UInt<1>(0h0))) node _T_2208 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2209 = cvt(_T_2208) node _T_2210 = and(_T_2209, asSInt(UInt<13>(0h1000))) node _T_2211 = asSInt(_T_2210) node _T_2212 = eq(_T_2211, asSInt(UInt<1>(0h0))) node _T_2213 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2214 = cvt(_T_2213) node _T_2215 = and(_T_2214, asSInt(UInt<29>(0h10000000))) node _T_2216 = asSInt(_T_2215) node _T_2217 = eq(_T_2216, asSInt(UInt<1>(0h0))) node _T_2218 = or(_T_2167, _T_2172) node _T_2219 = or(_T_2218, _T_2177) node _T_2220 = or(_T_2219, _T_2182) node _T_2221 = or(_T_2220, _T_2187) node _T_2222 = or(_T_2221, _T_2192) node _T_2223 = or(_T_2222, _T_2197) node _T_2224 = or(_T_2223, _T_2202) node _T_2225 = or(_T_2224, _T_2207) node _T_2226 = or(_T_2225, _T_2212) node _T_2227 = or(_T_2226, _T_2217) node _T_2228 = and(_T_2162, _T_2227) node _T_2229 = or(UInt<1>(0h0), _T_2228) node _T_2230 = and(_WIRE_7, _T_2229) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_144 node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(source_ok_2, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2237 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_146 node _T_2241 = asUInt(reset) node _T_2242 = eq(_T_2241, UInt<1>(0h0)) when _T_2242 : node _T_2243 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2244 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(_T_2244, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2244, UInt<1>(0h1), "") : assert_148 node _T_2248 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_149 node _T_2252 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2252 : node _T_2253 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2254 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2255 = and(_T_2253, _T_2254) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_2256 = shr(io.in.c.bits.source, 3) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) node _T_2258 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2259 = and(_T_2257, _T_2258) node _T_2260 = leq(uncommonBits_16, UInt<3>(0h4)) node _T_2261 = and(_T_2259, _T_2260) node _T_2262 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2263 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2264 = or(_T_2261, _T_2262) node _T_2265 = or(_T_2264, _T_2263) node _T_2266 = and(_T_2255, _T_2265) node _T_2267 = or(UInt<1>(0h0), _T_2266) node _T_2268 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2269 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2270 = cvt(_T_2269) node _T_2271 = and(_T_2270, asSInt(UInt<14>(0h2000))) node _T_2272 = asSInt(_T_2271) node _T_2273 = eq(_T_2272, asSInt(UInt<1>(0h0))) node _T_2274 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2275 = cvt(_T_2274) node _T_2276 = and(_T_2275, asSInt(UInt<13>(0h1000))) node _T_2277 = asSInt(_T_2276) node _T_2278 = eq(_T_2277, asSInt(UInt<1>(0h0))) node _T_2279 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2280 = cvt(_T_2279) node _T_2281 = and(_T_2280, asSInt(UInt<17>(0h10000))) node _T_2282 = asSInt(_T_2281) node _T_2283 = eq(_T_2282, asSInt(UInt<1>(0h0))) node _T_2284 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2285 = cvt(_T_2284) node _T_2286 = and(_T_2285, asSInt(UInt<18>(0h2f000))) node _T_2287 = asSInt(_T_2286) node _T_2288 = eq(_T_2287, asSInt(UInt<1>(0h0))) node _T_2289 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2290 = cvt(_T_2289) node _T_2291 = and(_T_2290, asSInt(UInt<17>(0h10000))) node _T_2292 = asSInt(_T_2291) node _T_2293 = eq(_T_2292, asSInt(UInt<1>(0h0))) node _T_2294 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2295 = cvt(_T_2294) node _T_2296 = and(_T_2295, asSInt(UInt<13>(0h1000))) node _T_2297 = asSInt(_T_2296) node _T_2298 = eq(_T_2297, asSInt(UInt<1>(0h0))) node _T_2299 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2300 = cvt(_T_2299) node _T_2301 = and(_T_2300, asSInt(UInt<27>(0h4000000))) node _T_2302 = asSInt(_T_2301) node _T_2303 = eq(_T_2302, asSInt(UInt<1>(0h0))) node _T_2304 = xor(io.in.c.bits.address, UInt<29>(0h10016000)) node _T_2305 = cvt(_T_2304) node _T_2306 = and(_T_2305, asSInt(UInt<13>(0h1000))) node _T_2307 = asSInt(_T_2306) node _T_2308 = eq(_T_2307, asSInt(UInt<1>(0h0))) node _T_2309 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2310 = cvt(_T_2309) node _T_2311 = and(_T_2310, asSInt(UInt<13>(0h1000))) node _T_2312 = asSInt(_T_2311) node _T_2313 = eq(_T_2312, asSInt(UInt<1>(0h0))) node _T_2314 = or(_T_2273, _T_2278) node _T_2315 = or(_T_2314, _T_2283) node _T_2316 = or(_T_2315, _T_2288) node _T_2317 = or(_T_2316, _T_2293) node _T_2318 = or(_T_2317, _T_2298) node _T_2319 = or(_T_2318, _T_2303) node _T_2320 = or(_T_2319, _T_2308) node _T_2321 = or(_T_2320, _T_2313) node _T_2322 = and(_T_2268, _T_2321) node _T_2323 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2324 = or(UInt<1>(0h0), _T_2323) node _T_2325 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2326 = cvt(_T_2325) node _T_2327 = and(_T_2326, asSInt(UInt<17>(0h10000))) node _T_2328 = asSInt(_T_2327) node _T_2329 = eq(_T_2328, asSInt(UInt<1>(0h0))) node _T_2330 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2331 = cvt(_T_2330) node _T_2332 = and(_T_2331, asSInt(UInt<29>(0h10000000))) node _T_2333 = asSInt(_T_2332) node _T_2334 = eq(_T_2333, asSInt(UInt<1>(0h0))) node _T_2335 = or(_T_2329, _T_2334) node _T_2336 = and(_T_2324, _T_2335) node _T_2337 = or(UInt<1>(0h0), _T_2322) node _T_2338 = or(_T_2337, _T_2336) node _T_2339 = and(_T_2267, _T_2338) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_2343 = shr(io.in.c.bits.source, 3) node _T_2344 = eq(_T_2343, UInt<1>(0h0)) node _T_2345 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2346 = and(_T_2344, _T_2345) node _T_2347 = leq(uncommonBits_17, UInt<3>(0h4)) node _T_2348 = and(_T_2346, _T_2347) node _T_2349 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2350 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2348 connect _WIRE_8[1], _T_2349 connect _WIRE_8[2], _T_2350 node _T_2351 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2352 = mux(_WIRE_8[0], _T_2351, UInt<1>(0h0)) node _T_2353 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2354 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2355 = or(_T_2352, _T_2353) node _T_2356 = or(_T_2355, _T_2354) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2356 node _T_2357 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2358 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2359 = and(_T_2357, _T_2358) node _T_2360 = or(UInt<1>(0h0), _T_2359) node _T_2361 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2362 = cvt(_T_2361) node _T_2363 = and(_T_2362, asSInt(UInt<14>(0h2000))) node _T_2364 = asSInt(_T_2363) node _T_2365 = eq(_T_2364, asSInt(UInt<1>(0h0))) node _T_2366 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2367 = cvt(_T_2366) node _T_2368 = and(_T_2367, asSInt(UInt<13>(0h1000))) node _T_2369 = asSInt(_T_2368) node _T_2370 = eq(_T_2369, asSInt(UInt<1>(0h0))) node _T_2371 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2372 = cvt(_T_2371) node _T_2373 = and(_T_2372, asSInt(UInt<17>(0h10000))) node _T_2374 = asSInt(_T_2373) node _T_2375 = eq(_T_2374, asSInt(UInt<1>(0h0))) node _T_2376 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2377 = cvt(_T_2376) node _T_2378 = and(_T_2377, asSInt(UInt<18>(0h2f000))) node _T_2379 = asSInt(_T_2378) node _T_2380 = eq(_T_2379, asSInt(UInt<1>(0h0))) node _T_2381 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2382 = cvt(_T_2381) node _T_2383 = and(_T_2382, asSInt(UInt<17>(0h10000))) node _T_2384 = asSInt(_T_2383) node _T_2385 = eq(_T_2384, asSInt(UInt<1>(0h0))) node _T_2386 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2387 = cvt(_T_2386) node _T_2388 = and(_T_2387, asSInt(UInt<13>(0h1000))) node _T_2389 = asSInt(_T_2388) node _T_2390 = eq(_T_2389, asSInt(UInt<1>(0h0))) node _T_2391 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2392 = cvt(_T_2391) node _T_2393 = and(_T_2392, asSInt(UInt<17>(0h10000))) node _T_2394 = asSInt(_T_2393) node _T_2395 = eq(_T_2394, asSInt(UInt<1>(0h0))) node _T_2396 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2397 = cvt(_T_2396) node _T_2398 = and(_T_2397, asSInt(UInt<27>(0h4000000))) node _T_2399 = asSInt(_T_2398) node _T_2400 = eq(_T_2399, asSInt(UInt<1>(0h0))) node _T_2401 = xor(io.in.c.bits.address, UInt<29>(0h10016000)) node _T_2402 = cvt(_T_2401) node _T_2403 = and(_T_2402, asSInt(UInt<13>(0h1000))) node _T_2404 = asSInt(_T_2403) node _T_2405 = eq(_T_2404, asSInt(UInt<1>(0h0))) node _T_2406 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2407 = cvt(_T_2406) node _T_2408 = and(_T_2407, asSInt(UInt<13>(0h1000))) node _T_2409 = asSInt(_T_2408) node _T_2410 = eq(_T_2409, asSInt(UInt<1>(0h0))) node _T_2411 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2412 = cvt(_T_2411) node _T_2413 = and(_T_2412, asSInt(UInt<29>(0h10000000))) node _T_2414 = asSInt(_T_2413) node _T_2415 = eq(_T_2414, asSInt(UInt<1>(0h0))) node _T_2416 = or(_T_2365, _T_2370) node _T_2417 = or(_T_2416, _T_2375) node _T_2418 = or(_T_2417, _T_2380) node _T_2419 = or(_T_2418, _T_2385) node _T_2420 = or(_T_2419, _T_2390) node _T_2421 = or(_T_2420, _T_2395) node _T_2422 = or(_T_2421, _T_2400) node _T_2423 = or(_T_2422, _T_2405) node _T_2424 = or(_T_2423, _T_2410) node _T_2425 = or(_T_2424, _T_2415) node _T_2426 = and(_T_2360, _T_2425) node _T_2427 = or(UInt<1>(0h0), _T_2426) node _T_2428 = and(_WIRE_9, _T_2427) node _T_2429 = asUInt(reset) node _T_2430 = eq(_T_2429, UInt<1>(0h0)) when _T_2430 : node _T_2431 = eq(_T_2428, UInt<1>(0h0)) when _T_2431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2428, UInt<1>(0h1), "") : assert_151 node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(source_ok_2, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2435 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_153 node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2442 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2443 = asUInt(reset) node _T_2444 = eq(_T_2443, UInt<1>(0h0)) when _T_2444 : node _T_2445 = eq(_T_2442, UInt<1>(0h0)) when _T_2445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2442, UInt<1>(0h1), "") : assert_155 node _T_2446 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2446 : node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(address_ok_1, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(source_ok_2, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2453 = asUInt(reset) node _T_2454 = eq(_T_2453, UInt<1>(0h0)) when _T_2454 : node _T_2455 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2456 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2457 = asUInt(reset) node _T_2458 = eq(_T_2457, UInt<1>(0h0)) when _T_2458 : node _T_2459 = eq(_T_2456, UInt<1>(0h0)) when _T_2459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2456, UInt<1>(0h1), "") : assert_159 node _T_2460 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2461 = asUInt(reset) node _T_2462 = eq(_T_2461, UInt<1>(0h0)) when _T_2462 : node _T_2463 = eq(_T_2460, UInt<1>(0h0)) when _T_2463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2460, UInt<1>(0h1), "") : assert_160 node _T_2464 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2464 : node _T_2465 = asUInt(reset) node _T_2466 = eq(_T_2465, UInt<1>(0h0)) when _T_2466 : node _T_2467 = eq(address_ok_1, UInt<1>(0h0)) when _T_2467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(source_ok_2, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2471 = asUInt(reset) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) when _T_2472 : node _T_2473 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2474 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2475 = asUInt(reset) node _T_2476 = eq(_T_2475, UInt<1>(0h0)) when _T_2476 : node _T_2477 = eq(_T_2474, UInt<1>(0h0)) when _T_2477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2474, UInt<1>(0h1), "") : assert_164 node _T_2478 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2478 : node _T_2479 = asUInt(reset) node _T_2480 = eq(_T_2479, UInt<1>(0h0)) when _T_2480 : node _T_2481 = eq(address_ok_1, UInt<1>(0h0)) when _T_2481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(source_ok_2, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2485 = asUInt(reset) node _T_2486 = eq(_T_2485, UInt<1>(0h0)) when _T_2486 : node _T_2487 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2488 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2489 = asUInt(reset) node _T_2490 = eq(_T_2489, UInt<1>(0h0)) when _T_2490 : node _T_2491 = eq(_T_2488, UInt<1>(0h0)) when _T_2491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2488, UInt<1>(0h1), "") : assert_168 node _T_2492 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2493 = asUInt(reset) node _T_2494 = eq(_T_2493, UInt<1>(0h0)) when _T_2494 : node _T_2495 = eq(_T_2492, UInt<1>(0h0)) when _T_2495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2492, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<5>(0h10)) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2499 = eq(a_first, UInt<1>(0h0)) node _T_2500 = and(io.in.a.valid, _T_2499) when _T_2500 : node _T_2501 = eq(io.in.a.bits.opcode, opcode) node _T_2502 = asUInt(reset) node _T_2503 = eq(_T_2502, UInt<1>(0h0)) when _T_2503 : node _T_2504 = eq(_T_2501, UInt<1>(0h0)) when _T_2504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2501, UInt<1>(0h1), "") : assert_171 node _T_2505 = eq(io.in.a.bits.param, param) node _T_2506 = asUInt(reset) node _T_2507 = eq(_T_2506, UInt<1>(0h0)) when _T_2507 : node _T_2508 = eq(_T_2505, UInt<1>(0h0)) when _T_2508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2505, UInt<1>(0h1), "") : assert_172 node _T_2509 = eq(io.in.a.bits.size, size) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_173 node _T_2513 = eq(io.in.a.bits.source, source) node _T_2514 = asUInt(reset) node _T_2515 = eq(_T_2514, UInt<1>(0h0)) when _T_2515 : node _T_2516 = eq(_T_2513, UInt<1>(0h0)) when _T_2516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2513, UInt<1>(0h1), "") : assert_174 node _T_2517 = eq(io.in.a.bits.address, address) node _T_2518 = asUInt(reset) node _T_2519 = eq(_T_2518, UInt<1>(0h0)) when _T_2519 : node _T_2520 = eq(_T_2517, UInt<1>(0h0)) when _T_2520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2517, UInt<1>(0h1), "") : assert_175 node _T_2521 = and(io.in.a.ready, io.in.a.valid) node _T_2522 = and(_T_2521, a_first) when _T_2522 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2523 = eq(d_first, UInt<1>(0h0)) node _T_2524 = and(io.in.d.valid, _T_2523) when _T_2524 : node _T_2525 = eq(io.in.d.bits.opcode, opcode_1) node _T_2526 = asUInt(reset) node _T_2527 = eq(_T_2526, UInt<1>(0h0)) when _T_2527 : node _T_2528 = eq(_T_2525, UInt<1>(0h0)) when _T_2528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2525, UInt<1>(0h1), "") : assert_176 node _T_2529 = eq(io.in.d.bits.param, param_1) node _T_2530 = asUInt(reset) node _T_2531 = eq(_T_2530, UInt<1>(0h0)) when _T_2531 : node _T_2532 = eq(_T_2529, UInt<1>(0h0)) when _T_2532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2529, UInt<1>(0h1), "") : assert_177 node _T_2533 = eq(io.in.d.bits.size, size_1) node _T_2534 = asUInt(reset) node _T_2535 = eq(_T_2534, UInt<1>(0h0)) when _T_2535 : node _T_2536 = eq(_T_2533, UInt<1>(0h0)) when _T_2536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2533, UInt<1>(0h1), "") : assert_178 node _T_2537 = eq(io.in.d.bits.source, source_1) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_179 node _T_2541 = eq(io.in.d.bits.sink, sink) node _T_2542 = asUInt(reset) node _T_2543 = eq(_T_2542, UInt<1>(0h0)) when _T_2543 : node _T_2544 = eq(_T_2541, UInt<1>(0h0)) when _T_2544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2541, UInt<1>(0h1), "") : assert_180 node _T_2545 = eq(io.in.d.bits.denied, denied) node _T_2546 = asUInt(reset) node _T_2547 = eq(_T_2546, UInt<1>(0h0)) when _T_2547 : node _T_2548 = eq(_T_2545, UInt<1>(0h0)) when _T_2548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2545, UInt<1>(0h1), "") : assert_181 node _T_2549 = and(io.in.d.ready, io.in.d.valid) node _T_2550 = and(_T_2549, d_first) when _T_2550 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2551 = eq(b_first, UInt<1>(0h0)) node _T_2552 = and(io.in.b.valid, _T_2551) when _T_2552 : node _T_2553 = eq(io.in.b.bits.opcode, opcode_2) node _T_2554 = asUInt(reset) node _T_2555 = eq(_T_2554, UInt<1>(0h0)) when _T_2555 : node _T_2556 = eq(_T_2553, UInt<1>(0h0)) when _T_2556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2553, UInt<1>(0h1), "") : assert_182 node _T_2557 = eq(io.in.b.bits.param, param_2) node _T_2558 = asUInt(reset) node _T_2559 = eq(_T_2558, UInt<1>(0h0)) when _T_2559 : node _T_2560 = eq(_T_2557, UInt<1>(0h0)) when _T_2560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2557, UInt<1>(0h1), "") : assert_183 node _T_2561 = eq(io.in.b.bits.size, size_2) node _T_2562 = asUInt(reset) node _T_2563 = eq(_T_2562, UInt<1>(0h0)) when _T_2563 : node _T_2564 = eq(_T_2561, UInt<1>(0h0)) when _T_2564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2561, UInt<1>(0h1), "") : assert_184 node _T_2565 = eq(io.in.b.bits.source, source_2) node _T_2566 = asUInt(reset) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) when _T_2567 : node _T_2568 = eq(_T_2565, UInt<1>(0h0)) when _T_2568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2565, UInt<1>(0h1), "") : assert_185 node _T_2569 = eq(io.in.b.bits.address, address_1) node _T_2570 = asUInt(reset) node _T_2571 = eq(_T_2570, UInt<1>(0h0)) when _T_2571 : node _T_2572 = eq(_T_2569, UInt<1>(0h0)) when _T_2572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2569, UInt<1>(0h1), "") : assert_186 node _T_2573 = and(io.in.b.ready, io.in.b.valid) node _T_2574 = and(_T_2573, b_first) when _T_2574 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2575 = eq(c_first, UInt<1>(0h0)) node _T_2576 = and(io.in.c.valid, _T_2575) when _T_2576 : node _T_2577 = eq(io.in.c.bits.opcode, opcode_3) node _T_2578 = asUInt(reset) node _T_2579 = eq(_T_2578, UInt<1>(0h0)) when _T_2579 : node _T_2580 = eq(_T_2577, UInt<1>(0h0)) when _T_2580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2577, UInt<1>(0h1), "") : assert_187 node _T_2581 = eq(io.in.c.bits.param, param_3) node _T_2582 = asUInt(reset) node _T_2583 = eq(_T_2582, UInt<1>(0h0)) when _T_2583 : node _T_2584 = eq(_T_2581, UInt<1>(0h0)) when _T_2584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2581, UInt<1>(0h1), "") : assert_188 node _T_2585 = eq(io.in.c.bits.size, size_3) node _T_2586 = asUInt(reset) node _T_2587 = eq(_T_2586, UInt<1>(0h0)) when _T_2587 : node _T_2588 = eq(_T_2585, UInt<1>(0h0)) when _T_2588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2585, UInt<1>(0h1), "") : assert_189 node _T_2589 = eq(io.in.c.bits.source, source_3) node _T_2590 = asUInt(reset) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) when _T_2591 : node _T_2592 = eq(_T_2589, UInt<1>(0h0)) when _T_2592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2589, UInt<1>(0h1), "") : assert_190 node _T_2593 = eq(io.in.c.bits.address, address_2) node _T_2594 = asUInt(reset) node _T_2595 = eq(_T_2594, UInt<1>(0h0)) when _T_2595 : node _T_2596 = eq(_T_2593, UInt<1>(0h0)) when _T_2596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2593, UInt<1>(0h1), "") : assert_191 node _T_2597 = and(io.in.c.ready, io.in.c.valid) node _T_2598 = and(_T_2597, c_first) when _T_2598 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes : UInt<72>, clock, reset, UInt<72>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<9> connect a_set, UInt<9>(0h0) wire a_set_wo_ready : UInt<9> connect a_set_wo_ready, UInt<9>(0h0) wire a_opcodes_set : UInt<36> connect a_opcodes_set, UInt<36>(0h0) wire a_sizes_set : UInt<72> connect a_sizes_set, UInt<72>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2599 = and(io.in.a.valid, a_first_1) node _T_2600 = and(_T_2599, UInt<1>(0h1)) when _T_2600 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2601 = and(io.in.a.ready, io.in.a.valid) node _T_2602 = and(_T_2601, a_first_1) node _T_2603 = and(_T_2602, UInt<1>(0h1)) when _T_2603 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2604 = dshr(inflight, io.in.a.bits.source) node _T_2605 = bits(_T_2604, 0, 0) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) node _T_2607 = asUInt(reset) node _T_2608 = eq(_T_2607, UInt<1>(0h0)) when _T_2608 : node _T_2609 = eq(_T_2606, UInt<1>(0h0)) when _T_2609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2606, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<9> connect d_clr, UInt<9>(0h0) wire d_clr_wo_ready : UInt<9> connect d_clr_wo_ready, UInt<9>(0h0) wire d_opcodes_clr : UInt<36> connect d_opcodes_clr, UInt<36>(0h0) wire d_sizes_clr : UInt<72> connect d_sizes_clr, UInt<72>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2610 = and(io.in.d.valid, d_first_1) node _T_2611 = and(_T_2610, UInt<1>(0h1)) node _T_2612 = eq(d_release_ack, UInt<1>(0h0)) node _T_2613 = and(_T_2611, _T_2612) when _T_2613 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2614 = and(io.in.d.ready, io.in.d.valid) node _T_2615 = and(_T_2614, d_first_1) node _T_2616 = and(_T_2615, UInt<1>(0h1)) node _T_2617 = eq(d_release_ack, UInt<1>(0h0)) node _T_2618 = and(_T_2616, _T_2617) when _T_2618 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2619 = and(io.in.d.valid, d_first_1) node _T_2620 = and(_T_2619, UInt<1>(0h1)) node _T_2621 = eq(d_release_ack, UInt<1>(0h0)) node _T_2622 = and(_T_2620, _T_2621) when _T_2622 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2623 = dshr(inflight, io.in.d.bits.source) node _T_2624 = bits(_T_2623, 0, 0) node _T_2625 = or(_T_2624, same_cycle_resp) node _T_2626 = asUInt(reset) node _T_2627 = eq(_T_2626, UInt<1>(0h0)) when _T_2627 : node _T_2628 = eq(_T_2625, UInt<1>(0h0)) when _T_2628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2625, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2629 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2630 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2631 = or(_T_2629, _T_2630) node _T_2632 = asUInt(reset) node _T_2633 = eq(_T_2632, UInt<1>(0h0)) when _T_2633 : node _T_2634 = eq(_T_2631, UInt<1>(0h0)) when _T_2634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2631, UInt<1>(0h1), "") : assert_194 node _T_2635 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2636 = asUInt(reset) node _T_2637 = eq(_T_2636, UInt<1>(0h0)) when _T_2637 : node _T_2638 = eq(_T_2635, UInt<1>(0h0)) when _T_2638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2635, UInt<1>(0h1), "") : assert_195 else : node _T_2639 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2640 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2641 = or(_T_2639, _T_2640) node _T_2642 = asUInt(reset) node _T_2643 = eq(_T_2642, UInt<1>(0h0)) when _T_2643 : node _T_2644 = eq(_T_2641, UInt<1>(0h0)) when _T_2644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2641, UInt<1>(0h1), "") : assert_196 node _T_2645 = eq(io.in.d.bits.size, a_size_lookup) node _T_2646 = asUInt(reset) node _T_2647 = eq(_T_2646, UInt<1>(0h0)) when _T_2647 : node _T_2648 = eq(_T_2645, UInt<1>(0h0)) when _T_2648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2645, UInt<1>(0h1), "") : assert_197 node _T_2649 = and(io.in.d.valid, d_first_1) node _T_2650 = and(_T_2649, a_first_1) node _T_2651 = and(_T_2650, io.in.a.valid) node _T_2652 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2653 = and(_T_2651, _T_2652) node _T_2654 = eq(d_release_ack, UInt<1>(0h0)) node _T_2655 = and(_T_2653, _T_2654) when _T_2655 : node _T_2656 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2657 = or(_T_2656, io.in.a.ready) node _T_2658 = asUInt(reset) node _T_2659 = eq(_T_2658, UInt<1>(0h0)) when _T_2659 : node _T_2660 = eq(_T_2657, UInt<1>(0h0)) when _T_2660 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2657, UInt<1>(0h1), "") : assert_198 node _T_2661 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2662 = orr(a_set_wo_ready) node _T_2663 = eq(_T_2662, UInt<1>(0h0)) node _T_2664 = or(_T_2661, _T_2663) node _T_2665 = asUInt(reset) node _T_2666 = eq(_T_2665, UInt<1>(0h0)) when _T_2666 : node _T_2667 = eq(_T_2664, UInt<1>(0h0)) when _T_2667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2664, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_2 node _T_2668 = orr(inflight) node _T_2669 = eq(_T_2668, UInt<1>(0h0)) node _T_2670 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2671 = or(_T_2669, _T_2670) node _T_2672 = lt(watchdog, plusarg_reader.out) node _T_2673 = or(_T_2671, _T_2672) node _T_2674 = asUInt(reset) node _T_2675 = eq(_T_2674, UInt<1>(0h0)) when _T_2675 : node _T_2676 = eq(_T_2673, UInt<1>(0h0)) when _T_2676 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2673, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2677 = and(io.in.a.ready, io.in.a.valid) node _T_2678 = and(io.in.d.ready, io.in.d.valid) node _T_2679 = or(_T_2677, _T_2678) when _T_2679 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes_1 : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes_1 : UInt<72>, clock, reset, UInt<72>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<9> connect c_set, UInt<9>(0h0) wire c_set_wo_ready : UInt<9> connect c_set_wo_ready, UInt<9>(0h0) wire c_opcodes_set : UInt<36> connect c_opcodes_set, UInt<36>(0h0) wire c_sizes_set : UInt<72> connect c_sizes_set, UInt<72>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2680 = and(io.in.c.valid, c_first_1) node _T_2681 = bits(io.in.c.bits.opcode, 2, 2) node _T_2682 = bits(io.in.c.bits.opcode, 1, 1) node _T_2683 = and(_T_2681, _T_2682) node _T_2684 = and(_T_2680, _T_2683) when _T_2684 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2685 = and(io.in.c.ready, io.in.c.valid) node _T_2686 = and(_T_2685, c_first_1) node _T_2687 = bits(io.in.c.bits.opcode, 2, 2) node _T_2688 = bits(io.in.c.bits.opcode, 1, 1) node _T_2689 = and(_T_2687, _T_2688) node _T_2690 = and(_T_2686, _T_2689) when _T_2690 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2691 = dshr(inflight_1, io.in.c.bits.source) node _T_2692 = bits(_T_2691, 0, 0) node _T_2693 = eq(_T_2692, UInt<1>(0h0)) node _T_2694 = asUInt(reset) node _T_2695 = eq(_T_2694, UInt<1>(0h0)) when _T_2695 : node _T_2696 = eq(_T_2693, UInt<1>(0h0)) when _T_2696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2693, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<9> connect d_clr_1, UInt<9>(0h0) wire d_clr_wo_ready_1 : UInt<9> connect d_clr_wo_ready_1, UInt<9>(0h0) wire d_opcodes_clr_1 : UInt<36> connect d_opcodes_clr_1, UInt<36>(0h0) wire d_sizes_clr_1 : UInt<72> connect d_sizes_clr_1, UInt<72>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2697 = and(io.in.d.valid, d_first_2) node _T_2698 = and(_T_2697, UInt<1>(0h1)) node _T_2699 = and(_T_2698, d_release_ack_1) when _T_2699 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2700 = and(io.in.d.ready, io.in.d.valid) node _T_2701 = and(_T_2700, d_first_2) node _T_2702 = and(_T_2701, UInt<1>(0h1)) node _T_2703 = and(_T_2702, d_release_ack_1) when _T_2703 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2704 = and(io.in.d.valid, d_first_2) node _T_2705 = and(_T_2704, UInt<1>(0h1)) node _T_2706 = and(_T_2705, d_release_ack_1) when _T_2706 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2707 = dshr(inflight_1, io.in.d.bits.source) node _T_2708 = bits(_T_2707, 0, 0) node _T_2709 = or(_T_2708, same_cycle_resp_1) node _T_2710 = asUInt(reset) node _T_2711 = eq(_T_2710, UInt<1>(0h0)) when _T_2711 : node _T_2712 = eq(_T_2709, UInt<1>(0h0)) when _T_2712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2709, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2713 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2714 = asUInt(reset) node _T_2715 = eq(_T_2714, UInt<1>(0h0)) when _T_2715 : node _T_2716 = eq(_T_2713, UInt<1>(0h0)) when _T_2716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2713, UInt<1>(0h1), "") : assert_203 else : node _T_2717 = eq(io.in.d.bits.size, c_size_lookup) node _T_2718 = asUInt(reset) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) when _T_2719 : node _T_2720 = eq(_T_2717, UInt<1>(0h0)) when _T_2720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2717, UInt<1>(0h1), "") : assert_204 node _T_2721 = and(io.in.d.valid, d_first_2) node _T_2722 = and(_T_2721, c_first_1) node _T_2723 = and(_T_2722, io.in.c.valid) node _T_2724 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2725 = and(_T_2723, _T_2724) node _T_2726 = and(_T_2725, d_release_ack_1) node _T_2727 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2728 = and(_T_2726, _T_2727) when _T_2728 : node _T_2729 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2730 = or(_T_2729, io.in.c.ready) node _T_2731 = asUInt(reset) node _T_2732 = eq(_T_2731, UInt<1>(0h0)) when _T_2732 : node _T_2733 = eq(_T_2730, UInt<1>(0h0)) when _T_2733 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2730, UInt<1>(0h1), "") : assert_205 node _T_2734 = orr(c_set_wo_ready) when _T_2734 : node _T_2735 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2736 = asUInt(reset) node _T_2737 = eq(_T_2736, UInt<1>(0h0)) when _T_2737 : node _T_2738 = eq(_T_2735, UInt<1>(0h0)) when _T_2738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2735, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_3 node _T_2739 = orr(inflight_1) node _T_2740 = eq(_T_2739, UInt<1>(0h0)) node _T_2741 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2742 = or(_T_2740, _T_2741) node _T_2743 = lt(watchdog_1, plusarg_reader_1.out) node _T_2744 = or(_T_2742, _T_2743) node _T_2745 = asUInt(reset) node _T_2746 = eq(_T_2745, UInt<1>(0h0)) when _T_2746 : node _T_2747 = eq(_T_2744, UInt<1>(0h0)) when _T_2747 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2744, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2748 = and(io.in.c.ready, io.in.c.valid) node _T_2749 = and(io.in.d.ready, io.in.d.valid) node _T_2750 = or(_T_2748, _T_2749) when _T_2750 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<16>, clock, reset, UInt<16>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<16> connect d_set, UInt<16>(0h0) node _T_2751 = and(io.in.d.ready, io.in.d.valid) node _T_2752 = and(_T_2751, d_first_3) node _T_2753 = bits(io.in.d.bits.opcode, 2, 2) node _T_2754 = bits(io.in.d.bits.opcode, 1, 1) node _T_2755 = eq(_T_2754, UInt<1>(0h0)) node _T_2756 = and(_T_2753, _T_2755) node _T_2757 = and(_T_2752, _T_2756) when _T_2757 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2758 = dshr(inflight_2, io.in.d.bits.sink) node _T_2759 = bits(_T_2758, 0, 0) node _T_2760 = eq(_T_2759, UInt<1>(0h0)) node _T_2761 = asUInt(reset) node _T_2762 = eq(_T_2761, UInt<1>(0h0)) when _T_2762 : node _T_2763 = eq(_T_2760, UInt<1>(0h0)) when _T_2763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2760, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<16> connect e_clr, UInt<16>(0h0) node _T_2764 = and(io.in.e.ready, io.in.e.valid) node _T_2765 = and(_T_2764, UInt<1>(0h1)) node _T_2766 = and(_T_2765, UInt<1>(0h1)) when _T_2766 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2767 = or(d_set, inflight_2) node _T_2768 = dshr(_T_2767, io.in.e.bits.sink) node _T_2769 = bits(_T_2768, 0, 0) node _T_2770 = asUInt(reset) node _T_2771 = eq(_T_2770, UInt<1>(0h0)) when _T_2771 : node _T_2772 = eq(_T_2769, UInt<1>(0h0)) when _T_2772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2769, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_source = 4'h0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = 4'h0; // @[Parameters.scala:52:29] wire [3:0] _legal_source_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29] wire [3:0] _legal_source_T_10 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_12 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_WIRE_1 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _uncommonBits_T_12 = 4'h0; // @[Parameters.scala:52:29] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_7 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] uncommonBits_11 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _legal_source_T_9 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_11 = 3'h0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_12 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] b_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_76 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = io_in_a_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31] wire _source_ok_T_8 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_8 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_2 = _uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_3 = _uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_8 = _uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_9 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_10 = ~_source_ok_T_9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_13 = source_ok_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_14 = _source_ok_T_12 & _source_ok_T_13; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31] wire _source_ok_T_15 = io_in_d_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31] wire _source_ok_T_16 = io_in_d_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31] wire _source_ok_T_17 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_17 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10016000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [28:0] _GEN_8 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:29], _GEN_8}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_60 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46] wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40] wire _address_ok_T_65 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_70 = _address_ok_T_69 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_71 = _address_ok_T_70 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_72 = _address_ok_T_71 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_73 = _address_ok_T_72 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_74 = _address_ok_T_73 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_75 = _address_ok_T_74 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_75 | _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = io_in_c_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_2 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = io_in_c_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_c_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_26 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_77 = {1'h0, _address_ok_T_76}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_78 = _address_ok_T_77 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_79 = _address_ok_T_78; // @[Parameters.scala:137:46] wire _address_ok_T_80 = _address_ok_T_79 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_80; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_81 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_82 = {1'h0, _address_ok_T_81}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_83 = _address_ok_T_82 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_84 = _address_ok_T_83; // @[Parameters.scala:137:46] wire _address_ok_T_85 = _address_ok_T_84 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_85; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_86 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_87 = {1'h0, _address_ok_T_86}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_88 = _address_ok_T_87 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_89 = _address_ok_T_88; // @[Parameters.scala:137:46] wire _address_ok_T_90 = _address_ok_T_89 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_90; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_91 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_92 = {1'h0, _address_ok_T_91}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_93 = _address_ok_T_92 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_94 = _address_ok_T_93; // @[Parameters.scala:137:46] wire _address_ok_T_95 = _address_ok_T_94 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_95; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_96 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_97 = {1'h0, _address_ok_T_96}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_98 = _address_ok_T_97 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_99 = _address_ok_T_98; // @[Parameters.scala:137:46] wire _address_ok_T_100 = _address_ok_T_99 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_100; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_101 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_102 = {1'h0, _address_ok_T_101}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_103 = _address_ok_T_102 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_104 = _address_ok_T_103; // @[Parameters.scala:137:46] wire _address_ok_T_105 = _address_ok_T_104 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_105; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_106 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_107 = {1'h0, _address_ok_T_106}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_108 = _address_ok_T_107 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_109 = _address_ok_T_108; // @[Parameters.scala:137:46] wire _address_ok_T_110 = _address_ok_T_109 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_110; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_111 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_112 = {1'h0, _address_ok_T_111}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_113 = _address_ok_T_112 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_114 = _address_ok_T_113; // @[Parameters.scala:137:46] wire _address_ok_T_115 = _address_ok_T_114 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_115; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_116 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_117 = {1'h0, _address_ok_T_116}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_118 = _address_ok_T_117 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_119 = _address_ok_T_118; // @[Parameters.scala:137:46] wire _address_ok_T_120 = _address_ok_T_119 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_120; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_121 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_122 = {1'h0, _address_ok_T_121}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_123 = _address_ok_T_122 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_124 = _address_ok_T_123; // @[Parameters.scala:137:46] wire _address_ok_T_125 = _address_ok_T_124 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_125; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10016000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_126 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_127 = {1'h0, _address_ok_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_128 = _address_ok_T_127 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_129 = _address_ok_T_128; // @[Parameters.scala:137:46] wire _address_ok_T_130 = _address_ok_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_130; // @[Parameters.scala:612:40] wire [28:0] _GEN_18 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_131 = {io_in_c_bits_address_0[31:29], _GEN_18}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_132 = {1'h0, _address_ok_T_131}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_133 = _address_ok_T_132 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_134 = _address_ok_T_133; // @[Parameters.scala:137:46] wire _address_ok_T_135 = _address_ok_T_134 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_135; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_136 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_137 = {1'h0, _address_ok_T_136}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_138 = _address_ok_T_137 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_139 = _address_ok_T_138; // @[Parameters.scala:137:46] wire _address_ok_T_140 = _address_ok_T_139 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_12 = _address_ok_T_140; // @[Parameters.scala:612:40] wire _address_ok_T_141 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_142 = _address_ok_T_141 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_143 = _address_ok_T_142 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_144 = _address_ok_T_143 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_145 = _address_ok_T_144 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_146 = _address_ok_T_145 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_147 = _address_ok_T_146 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_148 = _address_ok_T_147 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_149 = _address_ok_T_148 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_150 = _address_ok_T_149 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_151 = _address_ok_T_150 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_151 | _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_15 = _uncommonBits_T_15[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire _T_2677 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2677; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2677; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2751 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2751; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2751; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2751; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2751; // @[Decoupled.scala:51:35] wire [26:0] _GEN_19 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_19; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_19; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_19; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_19; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2748 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2748; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2748; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [8:0] inflight; // @[Monitor.scala:614:27] reg [35:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [71:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] a_set; // @[Monitor.scala:626:34] wire [8:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [35:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [71:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_20 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_20; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_20; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_20; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_20; // @[Monitor.scala:637:69, :790:101] wire [35:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [35:0] _a_opcode_lookup_T_6 = {32'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [35:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_21 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_21; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_21; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_21; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_21; // @[Monitor.scala:641:65, :791:99] wire [71:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [71:0] _a_size_lookup_T_6 = {64'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [71:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[71:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_22 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2603 = _T_2677 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2603 ? _a_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2603 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2603 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2603 ? _a_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2603 ? _a_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8:0] d_clr; // @[Monitor.scala:664:34] wire [8:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [35:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [71:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2649 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_24 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_24; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_24; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_24; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2649 & ~d_release_ack ? _d_clr_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2618 = _T_2751 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2618 ? _d_clr_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2618 ? _d_opcodes_clr_T_5[35:0] : 36'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2618 ? _d_sizes_clr_T_5[71:0] : 72'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [35:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [35:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [35:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [71:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [71:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [71:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8:0] inflight_1; // @[Monitor.scala:726:35] reg [35:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [71:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] c_set; // @[Monitor.scala:738:34] wire [8:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [35:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [71:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [35:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [35:0] _c_opcode_lookup_T_6 = {32'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [35:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [71:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [71:0] _c_size_lookup_T_6 = {64'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [71:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[71:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_25 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_25; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2690 = _T_2748 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2690 ? _c_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2690 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2690 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2690 ? _c_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2690 ? _c_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [8:0] d_clr_1; // @[Monitor.scala:774:34] wire [8:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [35:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [71:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2721 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2721 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2703 = _T_2751 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2703 ? _d_clr_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2703 ? _d_opcodes_clr_T_11[35:0] : 36'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2703 ? _d_sizes_clr_T_11[71:0] : 72'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [8:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [8:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [35:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [35:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [35:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [71:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [71:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [71:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2757 = _T_2751 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_26 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_26; // @[OneHot.scala:58:35] assign d_set = _T_2757 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire [15:0] _GEN_27 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_27; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_106 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_213 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_214 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_106( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_192 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_192( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_21 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_21( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip bypass : UInt<1>, pending : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_52 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) connect in_reset, UInt<1>(0h0) reg bypass_reg : UInt<1>, clock node bypass = mux(in_reset, io.bypass, bypass_reg) regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) node _T = and(nodeIn.a.ready, nodeIn.a.valid) node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node a_first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node a_last = or(_r_last_T, _r_last_T_1) node r_3 = and(a_last, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(a_first, r_beats1, r_counter1) connect r_counter, _r_counter_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) node r_counter1_1 = tail(_r_counter1_T_1, 1) node b_first = eq(r_counter_1, UInt<1>(0h0)) node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) node b_last = or(_r_last_T_2, _r_last_T_3) node r_3_1 = and(b_last, _T_1) node _r_count_T_1 = not(r_counter1_1) node r_4_1 = and(r_beats1_1, _r_count_T_1) when _T_1 : node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) connect r_counter_1, _r_counter_T_1 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) node r_counter1_2 = tail(_r_counter1_T_2, 1) node c_first = eq(r_counter_2, UInt<1>(0h0)) node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) node c_last = or(_r_last_T_4, _r_last_T_5) node r_3_2 = and(c_last, _T_2) node _r_count_T_2 = not(r_counter1_2) node r_4_2 = and(r_beats1_2, _r_count_T_2) when _T_2 : node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) connect r_counter_2, _r_counter_T_2 node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) node r_counter1_3 = tail(_r_counter1_T_3, 1) node d_first = eq(r_counter_3, UInt<1>(0h0)) node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) node d_last = or(_r_last_T_6, _r_last_T_7) node r_3_3 = and(d_last, _T_3) node _r_count_T_3 = not(r_counter1_3) node r_4_3 = and(r_beats1_3, _r_count_T_3) when _T_3 : node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) connect r_counter_3, _r_counter_T_3 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) node r_counter1_4 = tail(_r_counter1_T_4, 1) node e_first = eq(r_counter_4, UInt<1>(0h0)) node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node e_last = or(_r_last_T_8, _r_last_T_9) node r_3_4 = and(e_last, _T_4) node _r_count_T_4 = not(r_counter1_4) node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) when _T_4 : node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) connect r_counter_4, _r_counter_T_4 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.mask, UInt<4>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<2>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) node c_request = and(_T_5, _T_6) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_8 = eq(_T_7, UInt<1>(0h0)) node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_10 = eq(_T_9, UInt<1>(0h0)) node c_response = or(_T_8, _T_10) node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) node _T_13 = eq(_T_12, UInt<1>(0h0)) node d_request = and(_T_11, _T_13) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_14.bits.sink, UInt<1>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_inc_T_1 = and(_a_inc_T, a_first) node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_inc_WIRE.bits.data, UInt<32>(0h0) connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) connect _b_inc_WIRE.bits.address, UInt<9>(0h0) connect _b_inc_WIRE.bits.source, UInt<1>(0h0) connect _b_inc_WIRE.bits.size, UInt<2>(0h0) connect _b_inc_WIRE.bits.param, UInt<2>(0h0) connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _b_inc_WIRE.valid, UInt<1>(0h0) connect _b_inc_WIRE.ready, UInt<1>(0h0) wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) node _b_inc_T_1 = and(_b_inc_T, b_first) node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_inc_WIRE.bits.data, UInt<32>(0h0) connect _c_inc_WIRE.bits.address, UInt<9>(0h0) connect _c_inc_WIRE.bits.source, UInt<1>(0h0) connect _c_inc_WIRE.bits.size, UInt<2>(0h0) connect _c_inc_WIRE.bits.param, UInt<3>(0h0) connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _c_inc_WIRE.valid, UInt<1>(0h0) connect _c_inc_WIRE.ready, UInt<1>(0h0) wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) node _c_inc_T_1 = and(_c_inc_T, c_first) node c_inc = and(_c_inc_T_1, c_request) node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_inc_T_1 = and(_d_inc_T, d_first) node d_inc = and(_d_inc_T_1, d_request) wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) connect _e_inc_WIRE.valid, UInt<1>(0h0) connect _e_inc_WIRE.ready, UInt<1>(0h0) wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) node _e_inc_T_1 = and(_e_inc_T, e_first) node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) node inc = cat(a_inc, d_inc) node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_dec_T_1 = and(_a_dec_T, a_last) node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_dec_WIRE.bits.data, UInt<32>(0h0) connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) connect _b_dec_WIRE.bits.address, UInt<9>(0h0) connect _b_dec_WIRE.bits.source, UInt<1>(0h0) connect _b_dec_WIRE.bits.size, UInt<2>(0h0) connect _b_dec_WIRE.bits.param, UInt<2>(0h0) connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _b_dec_WIRE.valid, UInt<1>(0h0) connect _b_dec_WIRE.ready, UInt<1>(0h0) wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) node _b_dec_T_1 = and(_b_dec_T, b_last) node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_dec_WIRE.bits.data, UInt<32>(0h0) connect _c_dec_WIRE.bits.address, UInt<9>(0h0) connect _c_dec_WIRE.bits.source, UInt<1>(0h0) connect _c_dec_WIRE.bits.size, UInt<2>(0h0) connect _c_dec_WIRE.bits.param, UInt<3>(0h0) connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _c_dec_WIRE.valid, UInt<1>(0h0) connect _c_dec_WIRE.ready, UInt<1>(0h0) wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) node _c_dec_T_1 = and(_c_dec_T, c_last) node c_dec = and(_c_dec_T_1, c_response) node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_dec_T_1 = and(_d_dec_T, d_last) node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) connect _e_dec_WIRE.valid, UInt<1>(0h0) connect _e_dec_WIRE.ready, UInt<1>(0h0) wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) node _e_dec_T_1 = and(_e_dec_T, e_last) node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) node dec = cat(a_dec, d_dec) node _next_flight_T = bits(inc, 0, 0) node _next_flight_T_1 = bits(inc, 1, 1) node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) node _next_flight_T_4 = add(flight, _next_flight_T_3) node _next_flight_T_5 = tail(_next_flight_T_4, 1) node _next_flight_T_6 = bits(dec, 0, 0) node _next_flight_T_7 = bits(dec, 1, 1) node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) node next_flight = tail(_next_flight_T_10, 1) connect flight, next_flight node _io_pending_T = gt(flight, UInt<1>(0h0)) connect io.pending, _io_pending_T node _T_14 = eq(next_flight, UInt<1>(0h0)) node _T_15 = or(in_reset, _T_14) when _T_15 : connect bypass_reg, io.bypass node _stall_T = neq(bypass, io.bypass) node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) node stall_counter1 = tail(_stall_counter1_T, 1) node stall_first = eq(stall_counter, UInt<1>(0h0)) node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) node stall_last = or(_stall_last_T, _stall_last_T_1) node stall_done = and(stall_last, _stall_T_1) node _stall_count_T = not(stall_counter1) node stall_count = and(stall_beats1, _stall_count_T) when _stall_T_1 : node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) connect stall_counter, _stall_counter_T node stall = and(_stall_T, stall_first) node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) connect nodeIn.a.ready, _nodeIn_a_ready_T_2 connect nodeOut.a.bits, nodeIn.a.bits connect x1_nodeOut.a.bits, nodeIn.a.bits node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) connect nodeOut.d.ready, _nodeOut_d_ready_T node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) connect nodeIn.d.valid, _nodeIn_d_valid_T wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out, nodeIn.d.bits connect nodeIn_d_bits_out, nodeOut.d.bits wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out_1, nodeIn.d.bits connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.mask, UInt<4>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.ready, UInt<1>(0h1) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.address, UInt<128>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<2>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.valid, UInt<1>(0h0) wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_28.bits.sink, UInt<1>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<9>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<2>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<9>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<2>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready connect _WIRE_33.valid, UInt<1>(0h0) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_34.bits.sink, UInt<1>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) extmodule plusarg_reader_107 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_108 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = |flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_52 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_22 : input clock : Clock input reset : Reset output io : { req : { flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}}, resp : { `1` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, `0` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<13> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_andMatrixInput_6) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_6_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_3, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_4_5, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_orMatrixOutputs_hi = cat(decoded_andMatrixOutputs_5_2, decoded_andMatrixOutputs_3_2) node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_2 = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 1, 0) node _decoded_T_1 = bits(_decoded_T, 0, 0) node _decoded_T_2 = bits(_decoded_T, 1, 1) node _decoded_T_3 = cat(_decoded_T_1, _decoded_T_2) node _decoded_T_4 = bits(decoded_plaOutput, 3, 2) node _decoded_T_5 = bits(_decoded_T_4, 0, 0) node _decoded_T_6 = bits(_decoded_T_4, 1, 1) node _decoded_T_7 = cat(_decoded_T_5, _decoded_T_6) node decoded = cat(_decoded_T_3, _decoded_T_7) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T connect io.resp.`0`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<13> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_8, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_5_6, decoded_andMatrixOutputs_andMatrixInput_6_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T_4 = orr(decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_lo_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs_1, 3, 3) node decoded_invMatrixOutputs_lo_1 = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_1 = cat(_decoded_invMatrixOutputs_T_7, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_8 = bits(decoded_plaOutput_1, 1, 0) node _decoded_T_9 = bits(_decoded_T_8, 0, 0) node _decoded_T_10 = bits(_decoded_T_8, 1, 1) node _decoded_T_11 = cat(_decoded_T_9, _decoded_T_10) node _decoded_T_12 = bits(decoded_plaOutput_1, 3, 2) node _decoded_T_13 = bits(_decoded_T_12, 0, 0) node _decoded_T_14 = bits(_decoded_T_12, 1, 1) node _decoded_T_15 = cat(_decoded_T_13, _decoded_T_14) node decoded_1 = cat(_decoded_T_11, _decoded_T_15) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T connect io.resp.`1`.vc_sel.`1`[0], UInt<1>(0h0) extmodule plusarg_reader_40 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20

module RouteComputer_22( // @[RouteComputer.scala:29:7] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1 // @[RouteComputer.scala:40:14] ); wire [11:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id[0], io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_3 = ~(io_req_1_bits_flow_egress_node[3]); // @[pla.scala:78:21] assign io_resp_0_vc_sel_0_0 = |{&{decoded_invInputs[0], io_req_0_bits_flow_egress_node[0], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[5], decoded_invInputs[9], decoded_invInputs[10]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_1 = |{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_src_virt_id[0]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[0], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_src_virt_id[0]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_src_virt_id[0]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<29>(0h10000000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<29>(0h10000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<29>(0h10000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<29>(0h10000000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<29>(0h10000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<29>(0h10000000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<29>(0h10000000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<29>(0h10000000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<29>(0h10000000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h1), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h1), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h1), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h1), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h1), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_32 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_33 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_87 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_104 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_87( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_104 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RVCExpander_6 : input clock : Clock input reset : Reset output io : { flip in : UInt<32>, out : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>, ill : UInt<1>} node _io_rvc_T = bits(io.in, 1, 0) node _io_rvc_T_1 = neq(_io_rvc_T, UInt<2>(0h3)) connect io.rvc, _io_rvc_T_1 node _io_out_s_opc_T = bits(io.in, 12, 5) node _io_out_s_opc_T_1 = orr(_io_out_s_opc_T) node io_out_s_opc = mux(_io_out_s_opc_T_1, UInt<7>(0h13), UInt<7>(0h1f)) node _io_out_s_T = bits(io.in, 10, 7) node _io_out_s_T_1 = bits(io.in, 12, 11) node _io_out_s_T_2 = bits(io.in, 5, 5) node _io_out_s_T_3 = bits(io.in, 6, 6) node io_out_s_lo = cat(_io_out_s_T_3, UInt<2>(0h0)) node io_out_s_hi_hi = cat(_io_out_s_T, _io_out_s_T_1) node io_out_s_hi = cat(io_out_s_hi_hi, _io_out_s_T_2) node _io_out_s_T_4 = cat(io_out_s_hi, io_out_s_lo) node _io_out_s_T_5 = bits(io.in, 4, 2) node _io_out_s_T_6 = cat(UInt<2>(0h1), _io_out_s_T_5) node io_out_s_lo_1 = cat(_io_out_s_T_6, io_out_s_opc) node io_out_s_hi_hi_1 = cat(_io_out_s_T_4, UInt<5>(0h2)) node io_out_s_hi_1 = cat(io_out_s_hi_hi_1, UInt<3>(0h0)) node _io_out_s_T_7 = cat(io_out_s_hi_1, io_out_s_lo_1) node _io_out_s_T_8 = bits(io.in, 4, 2) node _io_out_s_T_9 = cat(UInt<2>(0h1), _io_out_s_T_8) node _io_out_s_T_10 = bits(io.in, 4, 2) node _io_out_s_T_11 = cat(UInt<2>(0h1), _io_out_s_T_10) node _io_out_s_T_12 = bits(io.in, 31, 27) wire io_out_s_0 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_0.bits, _io_out_s_T_7 connect io_out_s_0.rd, _io_out_s_T_9 connect io_out_s_0.rs1, UInt<5>(0h2) connect io_out_s_0.rs2, _io_out_s_T_11 connect io_out_s_0.rs3, _io_out_s_T_12 node _io_out_s_T_13 = bits(io.in, 6, 5) node _io_out_s_T_14 = bits(io.in, 12, 10) node io_out_s_hi_2 = cat(_io_out_s_T_13, _io_out_s_T_14) node _io_out_s_T_15 = cat(io_out_s_hi_2, UInt<3>(0h0)) node _io_out_s_T_16 = bits(io.in, 9, 7) node _io_out_s_T_17 = cat(UInt<2>(0h1), _io_out_s_T_16) node _io_out_s_T_18 = bits(io.in, 4, 2) node _io_out_s_T_19 = cat(UInt<2>(0h1), _io_out_s_T_18) node io_out_s_lo_2 = cat(_io_out_s_T_19, UInt<7>(0h7)) node io_out_s_hi_hi_2 = cat(_io_out_s_T_15, _io_out_s_T_17) node io_out_s_hi_3 = cat(io_out_s_hi_hi_2, UInt<3>(0h3)) node _io_out_s_T_20 = cat(io_out_s_hi_3, io_out_s_lo_2) node _io_out_s_T_21 = bits(io.in, 4, 2) node _io_out_s_T_22 = cat(UInt<2>(0h1), _io_out_s_T_21) node _io_out_s_T_23 = bits(io.in, 9, 7) node _io_out_s_T_24 = cat(UInt<2>(0h1), _io_out_s_T_23) node _io_out_s_T_25 = bits(io.in, 4, 2) node _io_out_s_T_26 = cat(UInt<2>(0h1), _io_out_s_T_25) node _io_out_s_T_27 = bits(io.in, 31, 27) wire io_out_s_1 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_1.bits, _io_out_s_T_20 connect io_out_s_1.rd, _io_out_s_T_22 connect io_out_s_1.rs1, _io_out_s_T_24 connect io_out_s_1.rs2, _io_out_s_T_26 connect io_out_s_1.rs3, _io_out_s_T_27 node _io_out_s_T_28 = bits(io.in, 5, 5) node _io_out_s_T_29 = bits(io.in, 12, 10) node _io_out_s_T_30 = bits(io.in, 6, 6) node io_out_s_lo_3 = cat(_io_out_s_T_30, UInt<2>(0h0)) node io_out_s_hi_4 = cat(_io_out_s_T_28, _io_out_s_T_29) node _io_out_s_T_31 = cat(io_out_s_hi_4, io_out_s_lo_3) node _io_out_s_T_32 = bits(io.in, 9, 7) node _io_out_s_T_33 = cat(UInt<2>(0h1), _io_out_s_T_32) node _io_out_s_T_34 = bits(io.in, 4, 2) node _io_out_s_T_35 = cat(UInt<2>(0h1), _io_out_s_T_34) node io_out_s_lo_4 = cat(_io_out_s_T_35, UInt<7>(0h3)) node io_out_s_hi_hi_3 = cat(_io_out_s_T_31, _io_out_s_T_33) node io_out_s_hi_5 = cat(io_out_s_hi_hi_3, UInt<3>(0h2)) node _io_out_s_T_36 = cat(io_out_s_hi_5, io_out_s_lo_4) node _io_out_s_T_37 = bits(io.in, 4, 2) node _io_out_s_T_38 = cat(UInt<2>(0h1), _io_out_s_T_37) node _io_out_s_T_39 = bits(io.in, 9, 7) node _io_out_s_T_40 = cat(UInt<2>(0h1), _io_out_s_T_39) node _io_out_s_T_41 = bits(io.in, 4, 2) node _io_out_s_T_42 = cat(UInt<2>(0h1), _io_out_s_T_41) node _io_out_s_T_43 = bits(io.in, 31, 27) wire io_out_s_2 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_2.bits, _io_out_s_T_36 connect io_out_s_2.rd, _io_out_s_T_38 connect io_out_s_2.rs1, _io_out_s_T_40 connect io_out_s_2.rs2, _io_out_s_T_42 connect io_out_s_2.rs3, _io_out_s_T_43 node _io_out_s_T_44 = bits(io.in, 6, 5) node _io_out_s_T_45 = bits(io.in, 12, 10) node io_out_s_hi_6 = cat(_io_out_s_T_44, _io_out_s_T_45) node _io_out_s_T_46 = cat(io_out_s_hi_6, UInt<3>(0h0)) node _io_out_s_T_47 = bits(io.in, 9, 7) node _io_out_s_T_48 = cat(UInt<2>(0h1), _io_out_s_T_47) node _io_out_s_T_49 = bits(io.in, 4, 2) node _io_out_s_T_50 = cat(UInt<2>(0h1), _io_out_s_T_49) node io_out_s_lo_5 = cat(_io_out_s_T_50, UInt<7>(0h3)) node io_out_s_hi_hi_4 = cat(_io_out_s_T_46, _io_out_s_T_48) node io_out_s_hi_7 = cat(io_out_s_hi_hi_4, UInt<3>(0h3)) node _io_out_s_T_51 = cat(io_out_s_hi_7, io_out_s_lo_5) node _io_out_s_T_52 = bits(io.in, 4, 2) node _io_out_s_T_53 = cat(UInt<2>(0h1), _io_out_s_T_52) node _io_out_s_T_54 = bits(io.in, 9, 7) node _io_out_s_T_55 = cat(UInt<2>(0h1), _io_out_s_T_54) node _io_out_s_T_56 = bits(io.in, 4, 2) node _io_out_s_T_57 = cat(UInt<2>(0h1), _io_out_s_T_56) node _io_out_s_T_58 = bits(io.in, 31, 27) wire io_out_s_3 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_3.bits, _io_out_s_T_51 connect io_out_s_3.rd, _io_out_s_T_53 connect io_out_s_3.rs1, _io_out_s_T_55 connect io_out_s_3.rs2, _io_out_s_T_57 connect io_out_s_3.rs3, _io_out_s_T_58 node _io_out_s_T_59 = bits(io.in, 5, 5) node _io_out_s_T_60 = bits(io.in, 12, 10) node _io_out_s_T_61 = bits(io.in, 6, 6) node io_out_s_lo_6 = cat(_io_out_s_T_61, UInt<2>(0h0)) node io_out_s_hi_8 = cat(_io_out_s_T_59, _io_out_s_T_60) node _io_out_s_T_62 = cat(io_out_s_hi_8, io_out_s_lo_6) node _io_out_s_T_63 = shr(_io_out_s_T_62, 5) node _io_out_s_T_64 = bits(io.in, 4, 2) node _io_out_s_T_65 = cat(UInt<2>(0h1), _io_out_s_T_64) node _io_out_s_T_66 = bits(io.in, 9, 7) node _io_out_s_T_67 = cat(UInt<2>(0h1), _io_out_s_T_66) node _io_out_s_T_68 = bits(io.in, 5, 5) node _io_out_s_T_69 = bits(io.in, 12, 10) node _io_out_s_T_70 = bits(io.in, 6, 6) node io_out_s_lo_7 = cat(_io_out_s_T_70, UInt<2>(0h0)) node io_out_s_hi_9 = cat(_io_out_s_T_68, _io_out_s_T_69) node _io_out_s_T_71 = cat(io_out_s_hi_9, io_out_s_lo_7) node _io_out_s_T_72 = bits(_io_out_s_T_71, 4, 0) node io_out_s_lo_hi = cat(UInt<3>(0h2), _io_out_s_T_72) node io_out_s_lo_8 = cat(io_out_s_lo_hi, UInt<7>(0h3f)) node io_out_s_hi_hi_5 = cat(_io_out_s_T_63, _io_out_s_T_65) node io_out_s_hi_10 = cat(io_out_s_hi_hi_5, _io_out_s_T_67) node _io_out_s_T_73 = cat(io_out_s_hi_10, io_out_s_lo_8) node _io_out_s_T_74 = bits(io.in, 4, 2) node _io_out_s_T_75 = cat(UInt<2>(0h1), _io_out_s_T_74) node _io_out_s_T_76 = bits(io.in, 9, 7) node _io_out_s_T_77 = cat(UInt<2>(0h1), _io_out_s_T_76) node _io_out_s_T_78 = bits(io.in, 4, 2) node _io_out_s_T_79 = cat(UInt<2>(0h1), _io_out_s_T_78) node _io_out_s_T_80 = bits(io.in, 31, 27) wire io_out_s_4 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_4.bits, _io_out_s_T_73 connect io_out_s_4.rd, _io_out_s_T_75 connect io_out_s_4.rs1, _io_out_s_T_77 connect io_out_s_4.rs2, _io_out_s_T_79 connect io_out_s_4.rs3, _io_out_s_T_80 node _io_out_s_T_81 = bits(io.in, 6, 5) node _io_out_s_T_82 = bits(io.in, 12, 10) node io_out_s_hi_11 = cat(_io_out_s_T_81, _io_out_s_T_82) node _io_out_s_T_83 = cat(io_out_s_hi_11, UInt<3>(0h0)) node _io_out_s_T_84 = shr(_io_out_s_T_83, 5) node _io_out_s_T_85 = bits(io.in, 4, 2) node _io_out_s_T_86 = cat(UInt<2>(0h1), _io_out_s_T_85) node _io_out_s_T_87 = bits(io.in, 9, 7) node _io_out_s_T_88 = cat(UInt<2>(0h1), _io_out_s_T_87) node _io_out_s_T_89 = bits(io.in, 6, 5) node _io_out_s_T_90 = bits(io.in, 12, 10) node io_out_s_hi_12 = cat(_io_out_s_T_89, _io_out_s_T_90) node _io_out_s_T_91 = cat(io_out_s_hi_12, UInt<3>(0h0)) node _io_out_s_T_92 = bits(_io_out_s_T_91, 4, 0) node io_out_s_lo_hi_1 = cat(UInt<3>(0h3), _io_out_s_T_92) node io_out_s_lo_9 = cat(io_out_s_lo_hi_1, UInt<7>(0h27)) node io_out_s_hi_hi_6 = cat(_io_out_s_T_84, _io_out_s_T_86) node io_out_s_hi_13 = cat(io_out_s_hi_hi_6, _io_out_s_T_88) node _io_out_s_T_93 = cat(io_out_s_hi_13, io_out_s_lo_9) node _io_out_s_T_94 = bits(io.in, 4, 2) node _io_out_s_T_95 = cat(UInt<2>(0h1), _io_out_s_T_94) node _io_out_s_T_96 = bits(io.in, 9, 7) node _io_out_s_T_97 = cat(UInt<2>(0h1), _io_out_s_T_96) node _io_out_s_T_98 = bits(io.in, 4, 2) node _io_out_s_T_99 = cat(UInt<2>(0h1), _io_out_s_T_98) node _io_out_s_T_100 = bits(io.in, 31, 27) wire io_out_s_5 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_5.bits, _io_out_s_T_93 connect io_out_s_5.rd, _io_out_s_T_95 connect io_out_s_5.rs1, _io_out_s_T_97 connect io_out_s_5.rs2, _io_out_s_T_99 connect io_out_s_5.rs3, _io_out_s_T_100 node _io_out_s_T_101 = bits(io.in, 5, 5) node _io_out_s_T_102 = bits(io.in, 12, 10) node _io_out_s_T_103 = bits(io.in, 6, 6) node io_out_s_lo_10 = cat(_io_out_s_T_103, UInt<2>(0h0)) node io_out_s_hi_14 = cat(_io_out_s_T_101, _io_out_s_T_102) node _io_out_s_T_104 = cat(io_out_s_hi_14, io_out_s_lo_10) node _io_out_s_T_105 = shr(_io_out_s_T_104, 5) node _io_out_s_T_106 = bits(io.in, 4, 2) node _io_out_s_T_107 = cat(UInt<2>(0h1), _io_out_s_T_106) node _io_out_s_T_108 = bits(io.in, 9, 7) node _io_out_s_T_109 = cat(UInt<2>(0h1), _io_out_s_T_108) node _io_out_s_T_110 = bits(io.in, 5, 5) node _io_out_s_T_111 = bits(io.in, 12, 10) node _io_out_s_T_112 = bits(io.in, 6, 6) node io_out_s_lo_11 = cat(_io_out_s_T_112, UInt<2>(0h0)) node io_out_s_hi_15 = cat(_io_out_s_T_110, _io_out_s_T_111) node _io_out_s_T_113 = cat(io_out_s_hi_15, io_out_s_lo_11) node _io_out_s_T_114 = bits(_io_out_s_T_113, 4, 0) node io_out_s_lo_hi_2 = cat(UInt<3>(0h2), _io_out_s_T_114) node io_out_s_lo_12 = cat(io_out_s_lo_hi_2, UInt<7>(0h23)) node io_out_s_hi_hi_7 = cat(_io_out_s_T_105, _io_out_s_T_107) node io_out_s_hi_16 = cat(io_out_s_hi_hi_7, _io_out_s_T_109) node _io_out_s_T_115 = cat(io_out_s_hi_16, io_out_s_lo_12) node _io_out_s_T_116 = bits(io.in, 4, 2) node _io_out_s_T_117 = cat(UInt<2>(0h1), _io_out_s_T_116) node _io_out_s_T_118 = bits(io.in, 9, 7) node _io_out_s_T_119 = cat(UInt<2>(0h1), _io_out_s_T_118) node _io_out_s_T_120 = bits(io.in, 4, 2) node _io_out_s_T_121 = cat(UInt<2>(0h1), _io_out_s_T_120) node _io_out_s_T_122 = bits(io.in, 31, 27) wire io_out_s_6 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_6.bits, _io_out_s_T_115 connect io_out_s_6.rd, _io_out_s_T_117 connect io_out_s_6.rs1, _io_out_s_T_119 connect io_out_s_6.rs2, _io_out_s_T_121 connect io_out_s_6.rs3, _io_out_s_T_122 node _io_out_s_T_123 = bits(io.in, 6, 5) node _io_out_s_T_124 = bits(io.in, 12, 10) node io_out_s_hi_17 = cat(_io_out_s_T_123, _io_out_s_T_124) node _io_out_s_T_125 = cat(io_out_s_hi_17, UInt<3>(0h0)) node _io_out_s_T_126 = shr(_io_out_s_T_125, 5) node _io_out_s_T_127 = bits(io.in, 4, 2) node _io_out_s_T_128 = cat(UInt<2>(0h1), _io_out_s_T_127) node _io_out_s_T_129 = bits(io.in, 9, 7) node _io_out_s_T_130 = cat(UInt<2>(0h1), _io_out_s_T_129) node _io_out_s_T_131 = bits(io.in, 6, 5) node _io_out_s_T_132 = bits(io.in, 12, 10) node io_out_s_hi_18 = cat(_io_out_s_T_131, _io_out_s_T_132) node _io_out_s_T_133 = cat(io_out_s_hi_18, UInt<3>(0h0)) node _io_out_s_T_134 = bits(_io_out_s_T_133, 4, 0) node io_out_s_lo_hi_3 = cat(UInt<3>(0h3), _io_out_s_T_134) node io_out_s_lo_13 = cat(io_out_s_lo_hi_3, UInt<7>(0h23)) node io_out_s_hi_hi_8 = cat(_io_out_s_T_126, _io_out_s_T_128) node io_out_s_hi_19 = cat(io_out_s_hi_hi_8, _io_out_s_T_130) node _io_out_s_T_135 = cat(io_out_s_hi_19, io_out_s_lo_13) node _io_out_s_T_136 = bits(io.in, 4, 2) node _io_out_s_T_137 = cat(UInt<2>(0h1), _io_out_s_T_136) node _io_out_s_T_138 = bits(io.in, 9, 7) node _io_out_s_T_139 = cat(UInt<2>(0h1), _io_out_s_T_138) node _io_out_s_T_140 = bits(io.in, 4, 2) node _io_out_s_T_141 = cat(UInt<2>(0h1), _io_out_s_T_140) node _io_out_s_T_142 = bits(io.in, 31, 27) wire io_out_s_7 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_7.bits, _io_out_s_T_135 connect io_out_s_7.rd, _io_out_s_T_137 connect io_out_s_7.rs1, _io_out_s_T_139 connect io_out_s_7.rs2, _io_out_s_T_141 connect io_out_s_7.rs3, _io_out_s_T_142 node _io_out_s_T_143 = bits(io.in, 12, 12) node _io_out_s_T_144 = mux(_io_out_s_T_143, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_145 = bits(io.in, 6, 2) node _io_out_s_T_146 = cat(_io_out_s_T_144, _io_out_s_T_145) node _io_out_s_T_147 = bits(io.in, 11, 7) node _io_out_s_T_148 = bits(io.in, 11, 7) node io_out_s_lo_14 = cat(_io_out_s_T_148, UInt<7>(0h13)) node io_out_s_hi_hi_9 = cat(_io_out_s_T_146, _io_out_s_T_147) node io_out_s_hi_20 = cat(io_out_s_hi_hi_9, UInt<3>(0h0)) node _io_out_s_T_149 = cat(io_out_s_hi_20, io_out_s_lo_14) node _io_out_s_T_150 = bits(io.in, 11, 7) node _io_out_s_T_151 = bits(io.in, 11, 7) node _io_out_s_T_152 = bits(io.in, 4, 2) node _io_out_s_T_153 = cat(UInt<2>(0h1), _io_out_s_T_152) node _io_out_s_T_154 = bits(io.in, 31, 27) wire io_out_s_8 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_8.bits, _io_out_s_T_149 connect io_out_s_8.rd, _io_out_s_T_150 connect io_out_s_8.rs1, _io_out_s_T_151 connect io_out_s_8.rs2, _io_out_s_T_153 connect io_out_s_8.rs3, _io_out_s_T_154 node _io_out_s_opc_T_2 = bits(io.in, 11, 7) node _io_out_s_opc_T_3 = orr(_io_out_s_opc_T_2) node io_out_s_opc_1 = mux(_io_out_s_opc_T_3, UInt<7>(0h1b), UInt<7>(0h1f)) node _io_out_s_T_155 = bits(io.in, 12, 12) node _io_out_s_T_156 = mux(_io_out_s_T_155, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_157 = bits(io.in, 6, 2) node _io_out_s_T_158 = cat(_io_out_s_T_156, _io_out_s_T_157) node _io_out_s_T_159 = bits(io.in, 11, 7) node _io_out_s_T_160 = bits(io.in, 11, 7) node io_out_s_lo_15 = cat(_io_out_s_T_160, io_out_s_opc_1) node io_out_s_hi_hi_10 = cat(_io_out_s_T_158, _io_out_s_T_159) node io_out_s_hi_21 = cat(io_out_s_hi_hi_10, UInt<3>(0h0)) node _io_out_s_T_161 = cat(io_out_s_hi_21, io_out_s_lo_15) node _io_out_s_T_162 = bits(io.in, 11, 7) node _io_out_s_T_163 = bits(io.in, 11, 7) node _io_out_s_T_164 = bits(io.in, 4, 2) node _io_out_s_T_165 = cat(UInt<2>(0h1), _io_out_s_T_164) node _io_out_s_T_166 = bits(io.in, 31, 27) wire io_out_s_9 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_9.bits, _io_out_s_T_161 connect io_out_s_9.rd, _io_out_s_T_162 connect io_out_s_9.rs1, _io_out_s_T_163 connect io_out_s_9.rs2, _io_out_s_T_165 connect io_out_s_9.rs3, _io_out_s_T_166 node _io_out_s_T_167 = bits(io.in, 12, 12) node _io_out_s_T_168 = mux(_io_out_s_T_167, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_169 = bits(io.in, 6, 2) node _io_out_s_T_170 = cat(_io_out_s_T_168, _io_out_s_T_169) node _io_out_s_T_171 = bits(io.in, 11, 7) node io_out_s_lo_16 = cat(_io_out_s_T_171, UInt<7>(0h13)) node io_out_s_hi_hi_11 = cat(_io_out_s_T_170, UInt<5>(0h0)) node io_out_s_hi_22 = cat(io_out_s_hi_hi_11, UInt<3>(0h0)) node _io_out_s_T_172 = cat(io_out_s_hi_22, io_out_s_lo_16) node _io_out_s_T_173 = bits(io.in, 11, 7) node _io_out_s_T_174 = bits(io.in, 4, 2) node _io_out_s_T_175 = cat(UInt<2>(0h1), _io_out_s_T_174) node _io_out_s_T_176 = bits(io.in, 31, 27) wire io_out_s_10 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_10.bits, _io_out_s_T_172 connect io_out_s_10.rd, _io_out_s_T_173 connect io_out_s_10.rs1, UInt<5>(0h0) connect io_out_s_10.rs2, _io_out_s_T_175 connect io_out_s_10.rs3, _io_out_s_T_176 node _io_out_s_opc_T_4 = bits(io.in, 12, 12) node _io_out_s_opc_T_5 = mux(_io_out_s_opc_T_4, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_opc_T_6 = bits(io.in, 6, 2) node _io_out_s_opc_T_7 = cat(_io_out_s_opc_T_5, _io_out_s_opc_T_6) node _io_out_s_opc_T_8 = orr(_io_out_s_opc_T_7) node io_out_s_opc_2 = mux(_io_out_s_opc_T_8, UInt<7>(0h37), UInt<7>(0h3f)) node _io_out_s_me_T = bits(io.in, 12, 12) node _io_out_s_me_T_1 = mux(_io_out_s_me_T, UInt<15>(0h7fff), UInt<15>(0h0)) node _io_out_s_me_T_2 = bits(io.in, 6, 2) node io_out_s_me_hi = cat(_io_out_s_me_T_1, _io_out_s_me_T_2) node _io_out_s_me_T_3 = cat(io_out_s_me_hi, UInt<12>(0h0)) node _io_out_s_me_T_4 = bits(_io_out_s_me_T_3, 31, 12) node _io_out_s_me_T_5 = bits(io.in, 11, 7) node io_out_s_me_hi_1 = cat(_io_out_s_me_T_4, _io_out_s_me_T_5) node _io_out_s_me_T_6 = cat(io_out_s_me_hi_1, io_out_s_opc_2) node _io_out_s_me_T_7 = bits(io.in, 11, 7) node _io_out_s_me_T_8 = bits(io.in, 11, 7) node _io_out_s_me_T_9 = bits(io.in, 4, 2) node _io_out_s_me_T_10 = cat(UInt<2>(0h1), _io_out_s_me_T_9) node _io_out_s_me_T_11 = bits(io.in, 31, 27) wire io_out_s_me : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_me.bits, _io_out_s_me_T_6 connect io_out_s_me.rd, _io_out_s_me_T_7 connect io_out_s_me.rs1, _io_out_s_me_T_8 connect io_out_s_me.rs2, _io_out_s_me_T_10 connect io_out_s_me.rs3, _io_out_s_me_T_11 node _io_out_s_T_177 = bits(io.in, 11, 7) node _io_out_s_T_178 = eq(_io_out_s_T_177, UInt<5>(0h0)) node _io_out_s_T_179 = bits(io.in, 11, 7) node _io_out_s_T_180 = eq(_io_out_s_T_179, UInt<5>(0h2)) node _io_out_s_T_181 = or(_io_out_s_T_178, _io_out_s_T_180) node _io_out_s_opc_T_9 = bits(io.in, 12, 12) node _io_out_s_opc_T_10 = mux(_io_out_s_opc_T_9, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_opc_T_11 = bits(io.in, 6, 2) node _io_out_s_opc_T_12 = cat(_io_out_s_opc_T_10, _io_out_s_opc_T_11) node _io_out_s_opc_T_13 = orr(_io_out_s_opc_T_12) node io_out_s_opc_3 = mux(_io_out_s_opc_T_13, UInt<7>(0h13), UInt<7>(0h1f)) node _io_out_s_T_182 = bits(io.in, 12, 12) node _io_out_s_T_183 = mux(_io_out_s_T_182, UInt<3>(0h7), UInt<3>(0h0)) node _io_out_s_T_184 = bits(io.in, 4, 3) node _io_out_s_T_185 = bits(io.in, 5, 5) node _io_out_s_T_186 = bits(io.in, 2, 2) node _io_out_s_T_187 = bits(io.in, 6, 6) node io_out_s_lo_hi_4 = cat(_io_out_s_T_186, _io_out_s_T_187) node io_out_s_lo_17 = cat(io_out_s_lo_hi_4, UInt<4>(0h0)) node io_out_s_hi_hi_12 = cat(_io_out_s_T_183, _io_out_s_T_184) node io_out_s_hi_23 = cat(io_out_s_hi_hi_12, _io_out_s_T_185) node _io_out_s_T_188 = cat(io_out_s_hi_23, io_out_s_lo_17) node _io_out_s_T_189 = bits(io.in, 11, 7) node _io_out_s_T_190 = bits(io.in, 11, 7) node io_out_s_lo_18 = cat(_io_out_s_T_190, io_out_s_opc_3) node io_out_s_hi_hi_13 = cat(_io_out_s_T_188, _io_out_s_T_189) node io_out_s_hi_24 = cat(io_out_s_hi_hi_13, UInt<3>(0h0)) node _io_out_s_T_191 = cat(io_out_s_hi_24, io_out_s_lo_18) node _io_out_s_T_192 = bits(io.in, 11, 7) node _io_out_s_T_193 = bits(io.in, 11, 7) node _io_out_s_T_194 = bits(io.in, 4, 2) node _io_out_s_T_195 = cat(UInt<2>(0h1), _io_out_s_T_194) node _io_out_s_T_196 = bits(io.in, 31, 27) wire io_out_s_res : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_res.bits, _io_out_s_T_191 connect io_out_s_res.rd, _io_out_s_T_192 connect io_out_s_res.rs1, _io_out_s_T_193 connect io_out_s_res.rs2, _io_out_s_T_195 connect io_out_s_res.rs3, _io_out_s_T_196 node io_out_s_11 = mux(_io_out_s_T_181, io_out_s_res, io_out_s_me) node _io_out_s_T_197 = bits(io.in, 12, 12) node _io_out_s_T_198 = bits(io.in, 6, 2) node _io_out_s_T_199 = cat(_io_out_s_T_197, _io_out_s_T_198) node _io_out_s_T_200 = bits(io.in, 9, 7) node _io_out_s_T_201 = cat(UInt<2>(0h1), _io_out_s_T_200) node _io_out_s_T_202 = bits(io.in, 9, 7) node _io_out_s_T_203 = cat(UInt<2>(0h1), _io_out_s_T_202) node io_out_s_lo_19 = cat(_io_out_s_T_203, UInt<7>(0h13)) node io_out_s_hi_hi_14 = cat(_io_out_s_T_199, _io_out_s_T_201) node io_out_s_hi_25 = cat(io_out_s_hi_hi_14, UInt<3>(0h5)) node _io_out_s_T_204 = cat(io_out_s_hi_25, io_out_s_lo_19) node _io_out_s_T_205 = bits(io.in, 12, 12) node _io_out_s_T_206 = bits(io.in, 6, 2) node _io_out_s_T_207 = cat(_io_out_s_T_205, _io_out_s_T_206) node _io_out_s_T_208 = bits(io.in, 9, 7) node _io_out_s_T_209 = cat(UInt<2>(0h1), _io_out_s_T_208) node _io_out_s_T_210 = bits(io.in, 9, 7) node _io_out_s_T_211 = cat(UInt<2>(0h1), _io_out_s_T_210) node io_out_s_lo_20 = cat(_io_out_s_T_211, UInt<7>(0h13)) node io_out_s_hi_hi_15 = cat(_io_out_s_T_207, _io_out_s_T_209) node io_out_s_hi_26 = cat(io_out_s_hi_hi_15, UInt<3>(0h5)) node _io_out_s_T_212 = cat(io_out_s_hi_26, io_out_s_lo_20) node _io_out_s_T_213 = or(_io_out_s_T_212, UInt<31>(0h40000000)) node _io_out_s_T_214 = bits(io.in, 12, 12) node _io_out_s_T_215 = mux(_io_out_s_T_214, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_216 = bits(io.in, 6, 2) node _io_out_s_T_217 = cat(_io_out_s_T_215, _io_out_s_T_216) node _io_out_s_T_218 = bits(io.in, 9, 7) node _io_out_s_T_219 = cat(UInt<2>(0h1), _io_out_s_T_218) node _io_out_s_T_220 = bits(io.in, 9, 7) node _io_out_s_T_221 = cat(UInt<2>(0h1), _io_out_s_T_220) node io_out_s_lo_21 = cat(_io_out_s_T_221, UInt<7>(0h13)) node io_out_s_hi_hi_16 = cat(_io_out_s_T_217, _io_out_s_T_219) node io_out_s_hi_27 = cat(io_out_s_hi_hi_16, UInt<3>(0h7)) node _io_out_s_T_222 = cat(io_out_s_hi_27, io_out_s_lo_21) node _io_out_s_funct_T = bits(io.in, 12, 12) node _io_out_s_funct_T_1 = bits(io.in, 6, 5) node _io_out_s_funct_T_2 = cat(_io_out_s_funct_T, _io_out_s_funct_T_1) node _io_out_s_funct_T_3 = eq(_io_out_s_funct_T_2, UInt<1>(0h1)) node _io_out_s_funct_T_4 = mux(_io_out_s_funct_T_3, UInt<3>(0h4), UInt<1>(0h0)) node _io_out_s_funct_T_5 = eq(_io_out_s_funct_T_2, UInt<2>(0h2)) node _io_out_s_funct_T_6 = mux(_io_out_s_funct_T_5, UInt<3>(0h6), _io_out_s_funct_T_4) node _io_out_s_funct_T_7 = eq(_io_out_s_funct_T_2, UInt<2>(0h3)) node _io_out_s_funct_T_8 = mux(_io_out_s_funct_T_7, UInt<3>(0h7), _io_out_s_funct_T_6) node _io_out_s_funct_T_9 = eq(_io_out_s_funct_T_2, UInt<3>(0h4)) node _io_out_s_funct_T_10 = mux(_io_out_s_funct_T_9, UInt<1>(0h0), _io_out_s_funct_T_8) node _io_out_s_funct_T_11 = eq(_io_out_s_funct_T_2, UInt<3>(0h5)) node _io_out_s_funct_T_12 = mux(_io_out_s_funct_T_11, UInt<1>(0h0), _io_out_s_funct_T_10) node _io_out_s_funct_T_13 = eq(_io_out_s_funct_T_2, UInt<3>(0h6)) node _io_out_s_funct_T_14 = mux(_io_out_s_funct_T_13, UInt<2>(0h2), _io_out_s_funct_T_12) node _io_out_s_funct_T_15 = eq(_io_out_s_funct_T_2, UInt<3>(0h7)) node io_out_s_funct = mux(_io_out_s_funct_T_15, UInt<2>(0h3), _io_out_s_funct_T_14) node _io_out_s_sub_T = bits(io.in, 6, 5) node _io_out_s_sub_T_1 = eq(_io_out_s_sub_T, UInt<1>(0h0)) node io_out_s_sub = mux(_io_out_s_sub_T_1, UInt<31>(0h40000000), UInt<1>(0h0)) node _io_out_s_opc_T_14 = bits(io.in, 12, 12) node io_out_s_opc_4 = mux(_io_out_s_opc_T_14, UInt<7>(0h3b), UInt<7>(0h33)) node _io_out_s_T_223 = bits(io.in, 4, 2) node _io_out_s_T_224 = cat(UInt<2>(0h1), _io_out_s_T_223) node _io_out_s_T_225 = bits(io.in, 9, 7) node _io_out_s_T_226 = cat(UInt<2>(0h1), _io_out_s_T_225) node _io_out_s_T_227 = bits(io.in, 9, 7) node _io_out_s_T_228 = cat(UInt<2>(0h1), _io_out_s_T_227) node io_out_s_lo_22 = cat(_io_out_s_T_228, io_out_s_opc_4) node io_out_s_hi_hi_17 = cat(_io_out_s_T_224, _io_out_s_T_226) node io_out_s_hi_28 = cat(io_out_s_hi_hi_17, io_out_s_funct) node _io_out_s_T_229 = cat(io_out_s_hi_28, io_out_s_lo_22) node _io_out_s_T_230 = or(_io_out_s_T_229, io_out_s_sub) node _io_out_s_T_231 = bits(io.in, 11, 10) node _io_out_s_T_232 = eq(_io_out_s_T_231, UInt<1>(0h1)) node _io_out_s_T_233 = mux(_io_out_s_T_232, _io_out_s_T_213, _io_out_s_T_204) node _io_out_s_T_234 = eq(_io_out_s_T_231, UInt<2>(0h2)) node _io_out_s_T_235 = mux(_io_out_s_T_234, _io_out_s_T_222, _io_out_s_T_233) node _io_out_s_T_236 = eq(_io_out_s_T_231, UInt<2>(0h3)) node _io_out_s_T_237 = mux(_io_out_s_T_236, _io_out_s_T_230, _io_out_s_T_235) node _io_out_s_T_238 = bits(io.in, 9, 7) node _io_out_s_T_239 = cat(UInt<2>(0h1), _io_out_s_T_238) node _io_out_s_T_240 = bits(io.in, 9, 7) node _io_out_s_T_241 = cat(UInt<2>(0h1), _io_out_s_T_240) node _io_out_s_T_242 = bits(io.in, 4, 2) node _io_out_s_T_243 = cat(UInt<2>(0h1), _io_out_s_T_242) node _io_out_s_T_244 = bits(io.in, 31, 27) wire io_out_s_12 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_12.bits, _io_out_s_T_237 connect io_out_s_12.rd, _io_out_s_T_239 connect io_out_s_12.rs1, _io_out_s_T_241 connect io_out_s_12.rs2, _io_out_s_T_243 connect io_out_s_12.rs3, _io_out_s_T_244 node _io_out_s_T_245 = bits(io.in, 12, 12) node _io_out_s_T_246 = mux(_io_out_s_T_245, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_247 = bits(io.in, 8, 8) node _io_out_s_T_248 = bits(io.in, 10, 9) node _io_out_s_T_249 = bits(io.in, 6, 6) node _io_out_s_T_250 = bits(io.in, 7, 7) node _io_out_s_T_251 = bits(io.in, 2, 2) node _io_out_s_T_252 = bits(io.in, 11, 11) node _io_out_s_T_253 = bits(io.in, 5, 3) node io_out_s_lo_lo = cat(_io_out_s_T_253, UInt<1>(0h0)) node io_out_s_lo_hi_5 = cat(_io_out_s_T_251, _io_out_s_T_252) node io_out_s_lo_23 = cat(io_out_s_lo_hi_5, io_out_s_lo_lo) node io_out_s_hi_lo = cat(_io_out_s_T_249, _io_out_s_T_250) node io_out_s_hi_hi_hi = cat(_io_out_s_T_246, _io_out_s_T_247) node io_out_s_hi_hi_18 = cat(io_out_s_hi_hi_hi, _io_out_s_T_248) node io_out_s_hi_29 = cat(io_out_s_hi_hi_18, io_out_s_hi_lo) node _io_out_s_T_254 = cat(io_out_s_hi_29, io_out_s_lo_23) node _io_out_s_T_255 = bits(_io_out_s_T_254, 20, 20) node _io_out_s_T_256 = bits(io.in, 12, 12) node _io_out_s_T_257 = mux(_io_out_s_T_256, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_258 = bits(io.in, 8, 8) node _io_out_s_T_259 = bits(io.in, 10, 9) node _io_out_s_T_260 = bits(io.in, 6, 6) node _io_out_s_T_261 = bits(io.in, 7, 7) node _io_out_s_T_262 = bits(io.in, 2, 2) node _io_out_s_T_263 = bits(io.in, 11, 11) node _io_out_s_T_264 = bits(io.in, 5, 3) node io_out_s_lo_lo_1 = cat(_io_out_s_T_264, UInt<1>(0h0)) node io_out_s_lo_hi_6 = cat(_io_out_s_T_262, _io_out_s_T_263) node io_out_s_lo_24 = cat(io_out_s_lo_hi_6, io_out_s_lo_lo_1) node io_out_s_hi_lo_1 = cat(_io_out_s_T_260, _io_out_s_T_261) node io_out_s_hi_hi_hi_1 = cat(_io_out_s_T_257, _io_out_s_T_258) node io_out_s_hi_hi_19 = cat(io_out_s_hi_hi_hi_1, _io_out_s_T_259) node io_out_s_hi_30 = cat(io_out_s_hi_hi_19, io_out_s_hi_lo_1) node _io_out_s_T_265 = cat(io_out_s_hi_30, io_out_s_lo_24) node _io_out_s_T_266 = bits(_io_out_s_T_265, 10, 1) node _io_out_s_T_267 = bits(io.in, 12, 12) node _io_out_s_T_268 = mux(_io_out_s_T_267, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_269 = bits(io.in, 8, 8) node _io_out_s_T_270 = bits(io.in, 10, 9) node _io_out_s_T_271 = bits(io.in, 6, 6) node _io_out_s_T_272 = bits(io.in, 7, 7) node _io_out_s_T_273 = bits(io.in, 2, 2) node _io_out_s_T_274 = bits(io.in, 11, 11) node _io_out_s_T_275 = bits(io.in, 5, 3) node io_out_s_lo_lo_2 = cat(_io_out_s_T_275, UInt<1>(0h0)) node io_out_s_lo_hi_7 = cat(_io_out_s_T_273, _io_out_s_T_274) node io_out_s_lo_25 = cat(io_out_s_lo_hi_7, io_out_s_lo_lo_2) node io_out_s_hi_lo_2 = cat(_io_out_s_T_271, _io_out_s_T_272) node io_out_s_hi_hi_hi_2 = cat(_io_out_s_T_268, _io_out_s_T_269) node io_out_s_hi_hi_20 = cat(io_out_s_hi_hi_hi_2, _io_out_s_T_270) node io_out_s_hi_31 = cat(io_out_s_hi_hi_20, io_out_s_hi_lo_2) node _io_out_s_T_276 = cat(io_out_s_hi_31, io_out_s_lo_25) node _io_out_s_T_277 = bits(_io_out_s_T_276, 11, 11) node _io_out_s_T_278 = bits(io.in, 12, 12) node _io_out_s_T_279 = mux(_io_out_s_T_278, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_280 = bits(io.in, 8, 8) node _io_out_s_T_281 = bits(io.in, 10, 9) node _io_out_s_T_282 = bits(io.in, 6, 6) node _io_out_s_T_283 = bits(io.in, 7, 7) node _io_out_s_T_284 = bits(io.in, 2, 2) node _io_out_s_T_285 = bits(io.in, 11, 11) node _io_out_s_T_286 = bits(io.in, 5, 3) node io_out_s_lo_lo_3 = cat(_io_out_s_T_286, UInt<1>(0h0)) node io_out_s_lo_hi_8 = cat(_io_out_s_T_284, _io_out_s_T_285) node io_out_s_lo_26 = cat(io_out_s_lo_hi_8, io_out_s_lo_lo_3) node io_out_s_hi_lo_3 = cat(_io_out_s_T_282, _io_out_s_T_283) node io_out_s_hi_hi_hi_3 = cat(_io_out_s_T_279, _io_out_s_T_280) node io_out_s_hi_hi_21 = cat(io_out_s_hi_hi_hi_3, _io_out_s_T_281) node io_out_s_hi_32 = cat(io_out_s_hi_hi_21, io_out_s_hi_lo_3) node _io_out_s_T_287 = cat(io_out_s_hi_32, io_out_s_lo_26) node _io_out_s_T_288 = bits(_io_out_s_T_287, 19, 12) node io_out_s_lo_hi_9 = cat(_io_out_s_T_288, UInt<5>(0h0)) node io_out_s_lo_27 = cat(io_out_s_lo_hi_9, UInt<7>(0h6f)) node io_out_s_hi_hi_22 = cat(_io_out_s_T_255, _io_out_s_T_266) node io_out_s_hi_33 = cat(io_out_s_hi_hi_22, _io_out_s_T_277) node _io_out_s_T_289 = cat(io_out_s_hi_33, io_out_s_lo_27) node _io_out_s_T_290 = bits(io.in, 9, 7) node _io_out_s_T_291 = cat(UInt<2>(0h1), _io_out_s_T_290) node _io_out_s_T_292 = bits(io.in, 4, 2) node _io_out_s_T_293 = cat(UInt<2>(0h1), _io_out_s_T_292) node _io_out_s_T_294 = bits(io.in, 31, 27) wire io_out_s_13 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_13.bits, _io_out_s_T_289 connect io_out_s_13.rd, UInt<5>(0h0) connect io_out_s_13.rs1, _io_out_s_T_291 connect io_out_s_13.rs2, _io_out_s_T_293 connect io_out_s_13.rs3, _io_out_s_T_294 node _io_out_s_T_295 = bits(io.in, 12, 12) node _io_out_s_T_296 = mux(_io_out_s_T_295, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_297 = bits(io.in, 6, 5) node _io_out_s_T_298 = bits(io.in, 2, 2) node _io_out_s_T_299 = bits(io.in, 11, 10) node _io_out_s_T_300 = bits(io.in, 4, 3) node io_out_s_lo_hi_10 = cat(_io_out_s_T_299, _io_out_s_T_300) node io_out_s_lo_28 = cat(io_out_s_lo_hi_10, UInt<1>(0h0)) node io_out_s_hi_hi_23 = cat(_io_out_s_T_296, _io_out_s_T_297) node io_out_s_hi_34 = cat(io_out_s_hi_hi_23, _io_out_s_T_298) node _io_out_s_T_301 = cat(io_out_s_hi_34, io_out_s_lo_28) node _io_out_s_T_302 = bits(_io_out_s_T_301, 12, 12) node _io_out_s_T_303 = bits(io.in, 12, 12) node _io_out_s_T_304 = mux(_io_out_s_T_303, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_305 = bits(io.in, 6, 5) node _io_out_s_T_306 = bits(io.in, 2, 2) node _io_out_s_T_307 = bits(io.in, 11, 10) node _io_out_s_T_308 = bits(io.in, 4, 3) node io_out_s_lo_hi_11 = cat(_io_out_s_T_307, _io_out_s_T_308) node io_out_s_lo_29 = cat(io_out_s_lo_hi_11, UInt<1>(0h0)) node io_out_s_hi_hi_24 = cat(_io_out_s_T_304, _io_out_s_T_305) node io_out_s_hi_35 = cat(io_out_s_hi_hi_24, _io_out_s_T_306) node _io_out_s_T_309 = cat(io_out_s_hi_35, io_out_s_lo_29) node _io_out_s_T_310 = bits(_io_out_s_T_309, 10, 5) node _io_out_s_T_311 = bits(io.in, 9, 7) node _io_out_s_T_312 = cat(UInt<2>(0h1), _io_out_s_T_311) node _io_out_s_T_313 = bits(io.in, 12, 12) node _io_out_s_T_314 = mux(_io_out_s_T_313, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_315 = bits(io.in, 6, 5) node _io_out_s_T_316 = bits(io.in, 2, 2) node _io_out_s_T_317 = bits(io.in, 11, 10) node _io_out_s_T_318 = bits(io.in, 4, 3) node io_out_s_lo_hi_12 = cat(_io_out_s_T_317, _io_out_s_T_318) node io_out_s_lo_30 = cat(io_out_s_lo_hi_12, UInt<1>(0h0)) node io_out_s_hi_hi_25 = cat(_io_out_s_T_314, _io_out_s_T_315) node io_out_s_hi_36 = cat(io_out_s_hi_hi_25, _io_out_s_T_316) node _io_out_s_T_319 = cat(io_out_s_hi_36, io_out_s_lo_30) node _io_out_s_T_320 = bits(_io_out_s_T_319, 4, 1) node _io_out_s_T_321 = bits(io.in, 12, 12) node _io_out_s_T_322 = mux(_io_out_s_T_321, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_323 = bits(io.in, 6, 5) node _io_out_s_T_324 = bits(io.in, 2, 2) node _io_out_s_T_325 = bits(io.in, 11, 10) node _io_out_s_T_326 = bits(io.in, 4, 3) node io_out_s_lo_hi_13 = cat(_io_out_s_T_325, _io_out_s_T_326) node io_out_s_lo_31 = cat(io_out_s_lo_hi_13, UInt<1>(0h0)) node io_out_s_hi_hi_26 = cat(_io_out_s_T_322, _io_out_s_T_323) node io_out_s_hi_37 = cat(io_out_s_hi_hi_26, _io_out_s_T_324) node _io_out_s_T_327 = cat(io_out_s_hi_37, io_out_s_lo_31) node _io_out_s_T_328 = bits(_io_out_s_T_327, 11, 11) node io_out_s_lo_lo_4 = cat(_io_out_s_T_328, UInt<7>(0h63)) node io_out_s_lo_hi_14 = cat(UInt<3>(0h0), _io_out_s_T_320) node io_out_s_lo_32 = cat(io_out_s_lo_hi_14, io_out_s_lo_lo_4) node io_out_s_hi_lo_4 = cat(UInt<5>(0h0), _io_out_s_T_312) node io_out_s_hi_hi_27 = cat(_io_out_s_T_302, _io_out_s_T_310) node io_out_s_hi_38 = cat(io_out_s_hi_hi_27, io_out_s_hi_lo_4) node _io_out_s_T_329 = cat(io_out_s_hi_38, io_out_s_lo_32) node _io_out_s_T_330 = bits(io.in, 9, 7) node _io_out_s_T_331 = cat(UInt<2>(0h1), _io_out_s_T_330) node _io_out_s_T_332 = bits(io.in, 9, 7) node _io_out_s_T_333 = cat(UInt<2>(0h1), _io_out_s_T_332) node _io_out_s_T_334 = bits(io.in, 31, 27) wire io_out_s_14 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_14.bits, _io_out_s_T_329 connect io_out_s_14.rd, _io_out_s_T_331 connect io_out_s_14.rs1, _io_out_s_T_333 connect io_out_s_14.rs2, UInt<5>(0h0) connect io_out_s_14.rs3, _io_out_s_T_334 node _io_out_s_T_335 = bits(io.in, 12, 12) node _io_out_s_T_336 = mux(_io_out_s_T_335, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_337 = bits(io.in, 6, 5) node _io_out_s_T_338 = bits(io.in, 2, 2) node _io_out_s_T_339 = bits(io.in, 11, 10) node _io_out_s_T_340 = bits(io.in, 4, 3) node io_out_s_lo_hi_15 = cat(_io_out_s_T_339, _io_out_s_T_340) node io_out_s_lo_33 = cat(io_out_s_lo_hi_15, UInt<1>(0h0)) node io_out_s_hi_hi_28 = cat(_io_out_s_T_336, _io_out_s_T_337) node io_out_s_hi_39 = cat(io_out_s_hi_hi_28, _io_out_s_T_338) node _io_out_s_T_341 = cat(io_out_s_hi_39, io_out_s_lo_33) node _io_out_s_T_342 = bits(_io_out_s_T_341, 12, 12) node _io_out_s_T_343 = bits(io.in, 12, 12) node _io_out_s_T_344 = mux(_io_out_s_T_343, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_345 = bits(io.in, 6, 5) node _io_out_s_T_346 = bits(io.in, 2, 2) node _io_out_s_T_347 = bits(io.in, 11, 10) node _io_out_s_T_348 = bits(io.in, 4, 3) node io_out_s_lo_hi_16 = cat(_io_out_s_T_347, _io_out_s_T_348) node io_out_s_lo_34 = cat(io_out_s_lo_hi_16, UInt<1>(0h0)) node io_out_s_hi_hi_29 = cat(_io_out_s_T_344, _io_out_s_T_345) node io_out_s_hi_40 = cat(io_out_s_hi_hi_29, _io_out_s_T_346) node _io_out_s_T_349 = cat(io_out_s_hi_40, io_out_s_lo_34) node _io_out_s_T_350 = bits(_io_out_s_T_349, 10, 5) node _io_out_s_T_351 = bits(io.in, 9, 7) node _io_out_s_T_352 = cat(UInt<2>(0h1), _io_out_s_T_351) node _io_out_s_T_353 = bits(io.in, 12, 12) node _io_out_s_T_354 = mux(_io_out_s_T_353, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_355 = bits(io.in, 6, 5) node _io_out_s_T_356 = bits(io.in, 2, 2) node _io_out_s_T_357 = bits(io.in, 11, 10) node _io_out_s_T_358 = bits(io.in, 4, 3) node io_out_s_lo_hi_17 = cat(_io_out_s_T_357, _io_out_s_T_358) node io_out_s_lo_35 = cat(io_out_s_lo_hi_17, UInt<1>(0h0)) node io_out_s_hi_hi_30 = cat(_io_out_s_T_354, _io_out_s_T_355) node io_out_s_hi_41 = cat(io_out_s_hi_hi_30, _io_out_s_T_356) node _io_out_s_T_359 = cat(io_out_s_hi_41, io_out_s_lo_35) node _io_out_s_T_360 = bits(_io_out_s_T_359, 4, 1) node _io_out_s_T_361 = bits(io.in, 12, 12) node _io_out_s_T_362 = mux(_io_out_s_T_361, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_363 = bits(io.in, 6, 5) node _io_out_s_T_364 = bits(io.in, 2, 2) node _io_out_s_T_365 = bits(io.in, 11, 10) node _io_out_s_T_366 = bits(io.in, 4, 3) node io_out_s_lo_hi_18 = cat(_io_out_s_T_365, _io_out_s_T_366) node io_out_s_lo_36 = cat(io_out_s_lo_hi_18, UInt<1>(0h0)) node io_out_s_hi_hi_31 = cat(_io_out_s_T_362, _io_out_s_T_363) node io_out_s_hi_42 = cat(io_out_s_hi_hi_31, _io_out_s_T_364) node _io_out_s_T_367 = cat(io_out_s_hi_42, io_out_s_lo_36) node _io_out_s_T_368 = bits(_io_out_s_T_367, 11, 11) node io_out_s_lo_lo_5 = cat(_io_out_s_T_368, UInt<7>(0h63)) node io_out_s_lo_hi_19 = cat(UInt<3>(0h1), _io_out_s_T_360) node io_out_s_lo_37 = cat(io_out_s_lo_hi_19, io_out_s_lo_lo_5) node io_out_s_hi_lo_5 = cat(UInt<5>(0h0), _io_out_s_T_352) node io_out_s_hi_hi_32 = cat(_io_out_s_T_342, _io_out_s_T_350) node io_out_s_hi_43 = cat(io_out_s_hi_hi_32, io_out_s_hi_lo_5) node _io_out_s_T_369 = cat(io_out_s_hi_43, io_out_s_lo_37) node _io_out_s_T_370 = bits(io.in, 9, 7) node _io_out_s_T_371 = cat(UInt<2>(0h1), _io_out_s_T_370) node _io_out_s_T_372 = bits(io.in, 31, 27) wire io_out_s_15 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_15.bits, _io_out_s_T_369 connect io_out_s_15.rd, UInt<5>(0h0) connect io_out_s_15.rs1, _io_out_s_T_371 connect io_out_s_15.rs2, UInt<5>(0h0) connect io_out_s_15.rs3, _io_out_s_T_372 node _io_out_s_load_opc_T = bits(io.in, 11, 7) node _io_out_s_load_opc_T_1 = orr(_io_out_s_load_opc_T) node io_out_s_load_opc = mux(_io_out_s_load_opc_T_1, UInt<7>(0h3), UInt<7>(0h1f)) node _io_out_s_T_373 = bits(io.in, 12, 12) node _io_out_s_T_374 = bits(io.in, 6, 2) node _io_out_s_T_375 = cat(_io_out_s_T_373, _io_out_s_T_374) node _io_out_s_T_376 = bits(io.in, 11, 7) node _io_out_s_T_377 = bits(io.in, 11, 7) node io_out_s_lo_38 = cat(_io_out_s_T_377, UInt<7>(0h13)) node io_out_s_hi_hi_33 = cat(_io_out_s_T_375, _io_out_s_T_376) node io_out_s_hi_44 = cat(io_out_s_hi_hi_33, UInt<3>(0h1)) node _io_out_s_T_378 = cat(io_out_s_hi_44, io_out_s_lo_38) node _io_out_s_T_379 = bits(io.in, 11, 7) node _io_out_s_T_380 = bits(io.in, 11, 7) node _io_out_s_T_381 = bits(io.in, 6, 2) node _io_out_s_T_382 = bits(io.in, 31, 27) wire io_out_s_16 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_16.bits, _io_out_s_T_378 connect io_out_s_16.rd, _io_out_s_T_379 connect io_out_s_16.rs1, _io_out_s_T_380 connect io_out_s_16.rs2, _io_out_s_T_381 connect io_out_s_16.rs3, _io_out_s_T_382 node _io_out_s_T_383 = bits(io.in, 4, 2) node _io_out_s_T_384 = bits(io.in, 12, 12) node _io_out_s_T_385 = bits(io.in, 6, 5) node io_out_s_lo_39 = cat(_io_out_s_T_385, UInt<3>(0h0)) node io_out_s_hi_45 = cat(_io_out_s_T_383, _io_out_s_T_384) node _io_out_s_T_386 = cat(io_out_s_hi_45, io_out_s_lo_39) node _io_out_s_T_387 = bits(io.in, 11, 7) node io_out_s_lo_40 = cat(_io_out_s_T_387, UInt<7>(0h7)) node io_out_s_hi_hi_34 = cat(_io_out_s_T_386, UInt<5>(0h2)) node io_out_s_hi_46 = cat(io_out_s_hi_hi_34, UInt<3>(0h3)) node _io_out_s_T_388 = cat(io_out_s_hi_46, io_out_s_lo_40) node _io_out_s_T_389 = bits(io.in, 11, 7) node _io_out_s_T_390 = bits(io.in, 6, 2) node _io_out_s_T_391 = bits(io.in, 31, 27) wire io_out_s_17 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_17.bits, _io_out_s_T_388 connect io_out_s_17.rd, _io_out_s_T_389 connect io_out_s_17.rs1, UInt<5>(0h2) connect io_out_s_17.rs2, _io_out_s_T_390 connect io_out_s_17.rs3, _io_out_s_T_391 node _io_out_s_T_392 = bits(io.in, 3, 2) node _io_out_s_T_393 = bits(io.in, 12, 12) node _io_out_s_T_394 = bits(io.in, 6, 4) node io_out_s_lo_41 = cat(_io_out_s_T_394, UInt<2>(0h0)) node io_out_s_hi_47 = cat(_io_out_s_T_392, _io_out_s_T_393) node _io_out_s_T_395 = cat(io_out_s_hi_47, io_out_s_lo_41) node _io_out_s_T_396 = bits(io.in, 11, 7) node io_out_s_lo_42 = cat(_io_out_s_T_396, io_out_s_load_opc) node io_out_s_hi_hi_35 = cat(_io_out_s_T_395, UInt<5>(0h2)) node io_out_s_hi_48 = cat(io_out_s_hi_hi_35, UInt<3>(0h2)) node _io_out_s_T_397 = cat(io_out_s_hi_48, io_out_s_lo_42) node _io_out_s_T_398 = bits(io.in, 11, 7) node _io_out_s_T_399 = bits(io.in, 6, 2) node _io_out_s_T_400 = bits(io.in, 31, 27) wire io_out_s_18 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_18.bits, _io_out_s_T_397 connect io_out_s_18.rd, _io_out_s_T_398 connect io_out_s_18.rs1, UInt<5>(0h2) connect io_out_s_18.rs2, _io_out_s_T_399 connect io_out_s_18.rs3, _io_out_s_T_400 node _io_out_s_T_401 = bits(io.in, 4, 2) node _io_out_s_T_402 = bits(io.in, 12, 12) node _io_out_s_T_403 = bits(io.in, 6, 5) node io_out_s_lo_43 = cat(_io_out_s_T_403, UInt<3>(0h0)) node io_out_s_hi_49 = cat(_io_out_s_T_401, _io_out_s_T_402) node _io_out_s_T_404 = cat(io_out_s_hi_49, io_out_s_lo_43) node _io_out_s_T_405 = bits(io.in, 11, 7) node io_out_s_lo_44 = cat(_io_out_s_T_405, io_out_s_load_opc) node io_out_s_hi_hi_36 = cat(_io_out_s_T_404, UInt<5>(0h2)) node io_out_s_hi_50 = cat(io_out_s_hi_hi_36, UInt<3>(0h3)) node _io_out_s_T_406 = cat(io_out_s_hi_50, io_out_s_lo_44) node _io_out_s_T_407 = bits(io.in, 11, 7) node _io_out_s_T_408 = bits(io.in, 6, 2) node _io_out_s_T_409 = bits(io.in, 31, 27) wire io_out_s_19 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_19.bits, _io_out_s_T_406 connect io_out_s_19.rd, _io_out_s_T_407 connect io_out_s_19.rs1, UInt<5>(0h2) connect io_out_s_19.rs2, _io_out_s_T_408 connect io_out_s_19.rs3, _io_out_s_T_409 node _io_out_s_mv_T = bits(io.in, 6, 2) node _io_out_s_mv_T_1 = bits(io.in, 11, 7) node io_out_s_mv_lo = cat(_io_out_s_mv_T_1, UInt<7>(0h33)) node io_out_s_mv_hi_hi = cat(_io_out_s_mv_T, UInt<5>(0h0)) node io_out_s_mv_hi = cat(io_out_s_mv_hi_hi, UInt<3>(0h0)) node _io_out_s_mv_T_2 = cat(io_out_s_mv_hi, io_out_s_mv_lo) node _io_out_s_mv_T_3 = bits(io.in, 11, 7) node _io_out_s_mv_T_4 = bits(io.in, 6, 2) node _io_out_s_mv_T_5 = bits(io.in, 31, 27) wire io_out_s_mv : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_mv.bits, _io_out_s_mv_T_2 connect io_out_s_mv.rd, _io_out_s_mv_T_3 connect io_out_s_mv.rs1, UInt<5>(0h0) connect io_out_s_mv.rs2, _io_out_s_mv_T_4 connect io_out_s_mv.rs3, _io_out_s_mv_T_5 node _io_out_s_add_T = bits(io.in, 6, 2) node _io_out_s_add_T_1 = bits(io.in, 11, 7) node _io_out_s_add_T_2 = bits(io.in, 11, 7) node io_out_s_add_lo = cat(_io_out_s_add_T_2, UInt<7>(0h33)) node io_out_s_add_hi_hi = cat(_io_out_s_add_T, _io_out_s_add_T_1) node io_out_s_add_hi = cat(io_out_s_add_hi_hi, UInt<3>(0h0)) node _io_out_s_add_T_3 = cat(io_out_s_add_hi, io_out_s_add_lo) node _io_out_s_add_T_4 = bits(io.in, 11, 7) node _io_out_s_add_T_5 = bits(io.in, 11, 7) node _io_out_s_add_T_6 = bits(io.in, 6, 2) node _io_out_s_add_T_7 = bits(io.in, 31, 27) wire io_out_s_add : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_add.bits, _io_out_s_add_T_3 connect io_out_s_add.rd, _io_out_s_add_T_4 connect io_out_s_add.rs1, _io_out_s_add_T_5 connect io_out_s_add.rs2, _io_out_s_add_T_6 connect io_out_s_add.rs3, _io_out_s_add_T_7 node _io_out_s_jr_T = bits(io.in, 6, 2) node _io_out_s_jr_T_1 = bits(io.in, 11, 7) node io_out_s_jr_lo = cat(UInt<5>(0h0), UInt<7>(0h67)) node io_out_s_jr_hi_hi = cat(_io_out_s_jr_T, _io_out_s_jr_T_1) node io_out_s_jr_hi = cat(io_out_s_jr_hi_hi, UInt<3>(0h0)) node io_out_s_jr = cat(io_out_s_jr_hi, io_out_s_jr_lo) node _io_out_s_reserved_T = shr(io_out_s_jr, 7) node io_out_s_reserved = cat(_io_out_s_reserved_T, UInt<7>(0h1f)) node _io_out_s_jr_reserved_T = bits(io.in, 11, 7) node _io_out_s_jr_reserved_T_1 = orr(_io_out_s_jr_reserved_T) node _io_out_s_jr_reserved_T_2 = mux(_io_out_s_jr_reserved_T_1, io_out_s_jr, io_out_s_reserved) node _io_out_s_jr_reserved_T_3 = bits(io.in, 11, 7) node _io_out_s_jr_reserved_T_4 = bits(io.in, 6, 2) node _io_out_s_jr_reserved_T_5 = bits(io.in, 31, 27) wire io_out_s_jr_reserved : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_jr_reserved.bits, _io_out_s_jr_reserved_T_2 connect io_out_s_jr_reserved.rd, UInt<5>(0h0) connect io_out_s_jr_reserved.rs1, _io_out_s_jr_reserved_T_3 connect io_out_s_jr_reserved.rs2, _io_out_s_jr_reserved_T_4 connect io_out_s_jr_reserved.rs3, _io_out_s_jr_reserved_T_5 node _io_out_s_jr_mv_T = bits(io.in, 6, 2) node _io_out_s_jr_mv_T_1 = orr(_io_out_s_jr_mv_T) node io_out_s_jr_mv = mux(_io_out_s_jr_mv_T_1, io_out_s_mv, io_out_s_jr_reserved) node _io_out_s_jalr_T = bits(io.in, 6, 2) node _io_out_s_jalr_T_1 = bits(io.in, 11, 7) node io_out_s_jalr_lo = cat(UInt<5>(0h1), UInt<7>(0h67)) node io_out_s_jalr_hi_hi = cat(_io_out_s_jalr_T, _io_out_s_jalr_T_1) node io_out_s_jalr_hi = cat(io_out_s_jalr_hi_hi, UInt<3>(0h0)) node io_out_s_jalr = cat(io_out_s_jalr_hi, io_out_s_jalr_lo) node _io_out_s_ebreak_T = shr(io_out_s_jr, 7) node _io_out_s_ebreak_T_1 = cat(_io_out_s_ebreak_T, UInt<7>(0h73)) node io_out_s_ebreak = or(_io_out_s_ebreak_T_1, UInt<21>(0h100000)) node _io_out_s_jalr_ebreak_T = bits(io.in, 11, 7) node _io_out_s_jalr_ebreak_T_1 = orr(_io_out_s_jalr_ebreak_T) node _io_out_s_jalr_ebreak_T_2 = mux(_io_out_s_jalr_ebreak_T_1, io_out_s_jalr, io_out_s_ebreak) node _io_out_s_jalr_ebreak_T_3 = bits(io.in, 11, 7) node _io_out_s_jalr_ebreak_T_4 = bits(io.in, 6, 2) node _io_out_s_jalr_ebreak_T_5 = bits(io.in, 31, 27) wire io_out_s_jalr_ebreak : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_jalr_ebreak.bits, _io_out_s_jalr_ebreak_T_2 connect io_out_s_jalr_ebreak.rd, UInt<5>(0h1) connect io_out_s_jalr_ebreak.rs1, _io_out_s_jalr_ebreak_T_3 connect io_out_s_jalr_ebreak.rs2, _io_out_s_jalr_ebreak_T_4 connect io_out_s_jalr_ebreak.rs3, _io_out_s_jalr_ebreak_T_5 node _io_out_s_jalr_add_T = bits(io.in, 6, 2) node _io_out_s_jalr_add_T_1 = orr(_io_out_s_jalr_add_T) node io_out_s_jalr_add = mux(_io_out_s_jalr_add_T_1, io_out_s_add, io_out_s_jalr_ebreak) node _io_out_s_T_410 = bits(io.in, 12, 12) node io_out_s_20 = mux(_io_out_s_T_410, io_out_s_jalr_add, io_out_s_jr_mv) node _io_out_s_T_411 = bits(io.in, 9, 7) node _io_out_s_T_412 = bits(io.in, 12, 10) node io_out_s_hi_51 = cat(_io_out_s_T_411, _io_out_s_T_412) node _io_out_s_T_413 = cat(io_out_s_hi_51, UInt<3>(0h0)) node _io_out_s_T_414 = shr(_io_out_s_T_413, 5) node _io_out_s_T_415 = bits(io.in, 6, 2) node _io_out_s_T_416 = bits(io.in, 9, 7) node _io_out_s_T_417 = bits(io.in, 12, 10) node io_out_s_hi_52 = cat(_io_out_s_T_416, _io_out_s_T_417) node _io_out_s_T_418 = cat(io_out_s_hi_52, UInt<3>(0h0)) node _io_out_s_T_419 = bits(_io_out_s_T_418, 4, 0) node io_out_s_lo_hi_20 = cat(UInt<3>(0h3), _io_out_s_T_419) node io_out_s_lo_45 = cat(io_out_s_lo_hi_20, UInt<7>(0h27)) node io_out_s_hi_hi_37 = cat(_io_out_s_T_414, _io_out_s_T_415) node io_out_s_hi_53 = cat(io_out_s_hi_hi_37, UInt<5>(0h2)) node _io_out_s_T_420 = cat(io_out_s_hi_53, io_out_s_lo_45) node _io_out_s_T_421 = bits(io.in, 11, 7) node _io_out_s_T_422 = bits(io.in, 6, 2) node _io_out_s_T_423 = bits(io.in, 31, 27) wire io_out_s_21 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_21.bits, _io_out_s_T_420 connect io_out_s_21.rd, _io_out_s_T_421 connect io_out_s_21.rs1, UInt<5>(0h2) connect io_out_s_21.rs2, _io_out_s_T_422 connect io_out_s_21.rs3, _io_out_s_T_423 node _io_out_s_T_424 = bits(io.in, 8, 7) node _io_out_s_T_425 = bits(io.in, 12, 9) node io_out_s_hi_54 = cat(_io_out_s_T_424, _io_out_s_T_425) node _io_out_s_T_426 = cat(io_out_s_hi_54, UInt<2>(0h0)) node _io_out_s_T_427 = shr(_io_out_s_T_426, 5) node _io_out_s_T_428 = bits(io.in, 6, 2) node _io_out_s_T_429 = bits(io.in, 8, 7) node _io_out_s_T_430 = bits(io.in, 12, 9) node io_out_s_hi_55 = cat(_io_out_s_T_429, _io_out_s_T_430) node _io_out_s_T_431 = cat(io_out_s_hi_55, UInt<2>(0h0)) node _io_out_s_T_432 = bits(_io_out_s_T_431, 4, 0) node io_out_s_lo_hi_21 = cat(UInt<3>(0h2), _io_out_s_T_432) node io_out_s_lo_46 = cat(io_out_s_lo_hi_21, UInt<7>(0h23)) node io_out_s_hi_hi_38 = cat(_io_out_s_T_427, _io_out_s_T_428) node io_out_s_hi_56 = cat(io_out_s_hi_hi_38, UInt<5>(0h2)) node _io_out_s_T_433 = cat(io_out_s_hi_56, io_out_s_lo_46) node _io_out_s_T_434 = bits(io.in, 11, 7) node _io_out_s_T_435 = bits(io.in, 6, 2) node _io_out_s_T_436 = bits(io.in, 31, 27) wire io_out_s_22 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_22.bits, _io_out_s_T_433 connect io_out_s_22.rd, _io_out_s_T_434 connect io_out_s_22.rs1, UInt<5>(0h2) connect io_out_s_22.rs2, _io_out_s_T_435 connect io_out_s_22.rs3, _io_out_s_T_436 node _io_out_s_T_437 = bits(io.in, 9, 7) node _io_out_s_T_438 = bits(io.in, 12, 10) node io_out_s_hi_57 = cat(_io_out_s_T_437, _io_out_s_T_438) node _io_out_s_T_439 = cat(io_out_s_hi_57, UInt<3>(0h0)) node _io_out_s_T_440 = shr(_io_out_s_T_439, 5) node _io_out_s_T_441 = bits(io.in, 6, 2) node _io_out_s_T_442 = bits(io.in, 9, 7) node _io_out_s_T_443 = bits(io.in, 12, 10) node io_out_s_hi_58 = cat(_io_out_s_T_442, _io_out_s_T_443) node _io_out_s_T_444 = cat(io_out_s_hi_58, UInt<3>(0h0)) node _io_out_s_T_445 = bits(_io_out_s_T_444, 4, 0) node io_out_s_lo_hi_22 = cat(UInt<3>(0h3), _io_out_s_T_445) node io_out_s_lo_47 = cat(io_out_s_lo_hi_22, UInt<7>(0h23)) node io_out_s_hi_hi_39 = cat(_io_out_s_T_440, _io_out_s_T_441) node io_out_s_hi_59 = cat(io_out_s_hi_hi_39, UInt<5>(0h2)) node _io_out_s_T_446 = cat(io_out_s_hi_59, io_out_s_lo_47) node _io_out_s_T_447 = bits(io.in, 11, 7) node _io_out_s_T_448 = bits(io.in, 6, 2) node _io_out_s_T_449 = bits(io.in, 31, 27) wire io_out_s_23 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_23.bits, _io_out_s_T_446 connect io_out_s_23.rd, _io_out_s_T_447 connect io_out_s_23.rs1, UInt<5>(0h2) connect io_out_s_23.rs2, _io_out_s_T_448 connect io_out_s_23.rs3, _io_out_s_T_449 node _io_out_s_T_450 = bits(io.in, 11, 7) node _io_out_s_T_451 = bits(io.in, 19, 15) node _io_out_s_T_452 = bits(io.in, 24, 20) node _io_out_s_T_453 = bits(io.in, 31, 27) wire io_out_s_24 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_24.bits, io.in connect io_out_s_24.rd, _io_out_s_T_450 connect io_out_s_24.rs1, _io_out_s_T_451 connect io_out_s_24.rs2, _io_out_s_T_452 connect io_out_s_24.rs3, _io_out_s_T_453 node _io_out_s_T_454 = bits(io.in, 11, 7) node _io_out_s_T_455 = bits(io.in, 19, 15) node _io_out_s_T_456 = bits(io.in, 24, 20) node _io_out_s_T_457 = bits(io.in, 31, 27) wire io_out_s_25 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_25.bits, io.in connect io_out_s_25.rd, _io_out_s_T_454 connect io_out_s_25.rs1, _io_out_s_T_455 connect io_out_s_25.rs2, _io_out_s_T_456 connect io_out_s_25.rs3, _io_out_s_T_457 node _io_out_s_T_458 = bits(io.in, 11, 7) node _io_out_s_T_459 = bits(io.in, 19, 15) node _io_out_s_T_460 = bits(io.in, 24, 20) node _io_out_s_T_461 = bits(io.in, 31, 27) wire io_out_s_26 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_26.bits, io.in connect io_out_s_26.rd, _io_out_s_T_458 connect io_out_s_26.rs1, _io_out_s_T_459 connect io_out_s_26.rs2, _io_out_s_T_460 connect io_out_s_26.rs3, _io_out_s_T_461 node _io_out_s_T_462 = bits(io.in, 11, 7) node _io_out_s_T_463 = bits(io.in, 19, 15) node _io_out_s_T_464 = bits(io.in, 24, 20) node _io_out_s_T_465 = bits(io.in, 31, 27) wire io_out_s_27 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_27.bits, io.in connect io_out_s_27.rd, _io_out_s_T_462 connect io_out_s_27.rs1, _io_out_s_T_463 connect io_out_s_27.rs2, _io_out_s_T_464 connect io_out_s_27.rs3, _io_out_s_T_465 node _io_out_s_T_466 = bits(io.in, 11, 7) node _io_out_s_T_467 = bits(io.in, 19, 15) node _io_out_s_T_468 = bits(io.in, 24, 20) node _io_out_s_T_469 = bits(io.in, 31, 27) wire io_out_s_28 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_28.bits, io.in connect io_out_s_28.rd, _io_out_s_T_466 connect io_out_s_28.rs1, _io_out_s_T_467 connect io_out_s_28.rs2, _io_out_s_T_468 connect io_out_s_28.rs3, _io_out_s_T_469 node _io_out_s_T_470 = bits(io.in, 11, 7) node _io_out_s_T_471 = bits(io.in, 19, 15) node _io_out_s_T_472 = bits(io.in, 24, 20) node _io_out_s_T_473 = bits(io.in, 31, 27) wire io_out_s_29 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_29.bits, io.in connect io_out_s_29.rd, _io_out_s_T_470 connect io_out_s_29.rs1, _io_out_s_T_471 connect io_out_s_29.rs2, _io_out_s_T_472 connect io_out_s_29.rs3, _io_out_s_T_473 node _io_out_s_T_474 = bits(io.in, 11, 7) node _io_out_s_T_475 = bits(io.in, 19, 15) node _io_out_s_T_476 = bits(io.in, 24, 20) node _io_out_s_T_477 = bits(io.in, 31, 27) wire io_out_s_30 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_30.bits, io.in connect io_out_s_30.rd, _io_out_s_T_474 connect io_out_s_30.rs1, _io_out_s_T_475 connect io_out_s_30.rs2, _io_out_s_T_476 connect io_out_s_30.rs3, _io_out_s_T_477 node _io_out_s_T_478 = bits(io.in, 11, 7) node _io_out_s_T_479 = bits(io.in, 19, 15) node _io_out_s_T_480 = bits(io.in, 24, 20) node _io_out_s_T_481 = bits(io.in, 31, 27) wire io_out_s_31 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_31.bits, io.in connect io_out_s_31.rd, _io_out_s_T_478 connect io_out_s_31.rs1, _io_out_s_T_479 connect io_out_s_31.rs2, _io_out_s_T_480 connect io_out_s_31.rs3, _io_out_s_T_481 node _io_out_T = bits(io.in, 1, 0) node _io_out_T_1 = bits(io.in, 15, 13) node _io_out_T_2 = cat(_io_out_T, _io_out_T_1) node _io_out_T_3 = eq(_io_out_T_2, UInt<1>(0h1)) node _io_out_T_4 = mux(_io_out_T_3, io_out_s_1, io_out_s_0) node _io_out_T_5 = eq(_io_out_T_2, UInt<2>(0h2)) node _io_out_T_6 = mux(_io_out_T_5, io_out_s_2, _io_out_T_4) node _io_out_T_7 = eq(_io_out_T_2, UInt<2>(0h3)) node _io_out_T_8 = mux(_io_out_T_7, io_out_s_3, _io_out_T_6) node _io_out_T_9 = eq(_io_out_T_2, UInt<3>(0h4)) node _io_out_T_10 = mux(_io_out_T_9, io_out_s_4, _io_out_T_8) node _io_out_T_11 = eq(_io_out_T_2, UInt<3>(0h5)) node _io_out_T_12 = mux(_io_out_T_11, io_out_s_5, _io_out_T_10) node _io_out_T_13 = eq(_io_out_T_2, UInt<3>(0h6)) node _io_out_T_14 = mux(_io_out_T_13, io_out_s_6, _io_out_T_12) node _io_out_T_15 = eq(_io_out_T_2, UInt<3>(0h7)) node _io_out_T_16 = mux(_io_out_T_15, io_out_s_7, _io_out_T_14) node _io_out_T_17 = eq(_io_out_T_2, UInt<4>(0h8)) node _io_out_T_18 = mux(_io_out_T_17, io_out_s_8, _io_out_T_16) node _io_out_T_19 = eq(_io_out_T_2, UInt<4>(0h9)) node _io_out_T_20 = mux(_io_out_T_19, io_out_s_9, _io_out_T_18) node _io_out_T_21 = eq(_io_out_T_2, UInt<4>(0ha)) node _io_out_T_22 = mux(_io_out_T_21, io_out_s_10, _io_out_T_20) node _io_out_T_23 = eq(_io_out_T_2, UInt<4>(0hb)) node _io_out_T_24 = mux(_io_out_T_23, io_out_s_11, _io_out_T_22) node _io_out_T_25 = eq(_io_out_T_2, UInt<4>(0hc)) node _io_out_T_26 = mux(_io_out_T_25, io_out_s_12, _io_out_T_24) node _io_out_T_27 = eq(_io_out_T_2, UInt<4>(0hd)) node _io_out_T_28 = mux(_io_out_T_27, io_out_s_13, _io_out_T_26) node _io_out_T_29 = eq(_io_out_T_2, UInt<4>(0he)) node _io_out_T_30 = mux(_io_out_T_29, io_out_s_14, _io_out_T_28) node _io_out_T_31 = eq(_io_out_T_2, UInt<4>(0hf)) node _io_out_T_32 = mux(_io_out_T_31, io_out_s_15, _io_out_T_30) node _io_out_T_33 = eq(_io_out_T_2, UInt<5>(0h10)) node _io_out_T_34 = mux(_io_out_T_33, io_out_s_16, _io_out_T_32) node _io_out_T_35 = eq(_io_out_T_2, UInt<5>(0h11)) node _io_out_T_36 = mux(_io_out_T_35, io_out_s_17, _io_out_T_34) node _io_out_T_37 = eq(_io_out_T_2, UInt<5>(0h12)) node _io_out_T_38 = mux(_io_out_T_37, io_out_s_18, _io_out_T_36) node _io_out_T_39 = eq(_io_out_T_2, UInt<5>(0h13)) node _io_out_T_40 = mux(_io_out_T_39, io_out_s_19, _io_out_T_38) node _io_out_T_41 = eq(_io_out_T_2, UInt<5>(0h14)) node _io_out_T_42 = mux(_io_out_T_41, io_out_s_20, _io_out_T_40) node _io_out_T_43 = eq(_io_out_T_2, UInt<5>(0h15)) node _io_out_T_44 = mux(_io_out_T_43, io_out_s_21, _io_out_T_42) node _io_out_T_45 = eq(_io_out_T_2, UInt<5>(0h16)) node _io_out_T_46 = mux(_io_out_T_45, io_out_s_22, _io_out_T_44) node _io_out_T_47 = eq(_io_out_T_2, UInt<5>(0h17)) node _io_out_T_48 = mux(_io_out_T_47, io_out_s_23, _io_out_T_46) node _io_out_T_49 = eq(_io_out_T_2, UInt<5>(0h18)) node _io_out_T_50 = mux(_io_out_T_49, io_out_s_24, _io_out_T_48) node _io_out_T_51 = eq(_io_out_T_2, UInt<5>(0h19)) node _io_out_T_52 = mux(_io_out_T_51, io_out_s_25, _io_out_T_50) node _io_out_T_53 = eq(_io_out_T_2, UInt<5>(0h1a)) node _io_out_T_54 = mux(_io_out_T_53, io_out_s_26, _io_out_T_52) node _io_out_T_55 = eq(_io_out_T_2, UInt<5>(0h1b)) node _io_out_T_56 = mux(_io_out_T_55, io_out_s_27, _io_out_T_54) node _io_out_T_57 = eq(_io_out_T_2, UInt<5>(0h1c)) node _io_out_T_58 = mux(_io_out_T_57, io_out_s_28, _io_out_T_56) node _io_out_T_59 = eq(_io_out_T_2, UInt<5>(0h1d)) node _io_out_T_60 = mux(_io_out_T_59, io_out_s_29, _io_out_T_58) node _io_out_T_61 = eq(_io_out_T_2, UInt<5>(0h1e)) node _io_out_T_62 = mux(_io_out_T_61, io_out_s_30, _io_out_T_60) node _io_out_T_63 = eq(_io_out_T_2, UInt<5>(0h1f)) node _io_out_T_64 = mux(_io_out_T_63, io_out_s_31, _io_out_T_62) connect io.out, _io_out_T_64 node _io_ill_s_T = bits(io.in, 12, 2) node _io_ill_s_T_1 = orr(_io_ill_s_T) node io_ill_s_0 = eq(_io_ill_s_T_1, UInt<1>(0h0)) node _io_ill_s_T_2 = bits(io.in, 11, 7) node io_ill_s_9 = eq(_io_ill_s_T_2, UInt<1>(0h0)) node _io_ill_s_T_3 = bits(io.in, 12, 12) node _io_ill_s_T_4 = bits(io.in, 6, 2) node _io_ill_s_T_5 = orr(_io_ill_s_T_4) node _io_ill_s_T_6 = or(_io_ill_s_T_3, _io_ill_s_T_5) node io_ill_s_11 = eq(_io_ill_s_T_6, UInt<1>(0h0)) node _io_ill_s_T_7 = bits(io.in, 12, 10) node _io_ill_s_T_8 = andr(_io_ill_s_T_7) node _io_ill_s_T_9 = bits(io.in, 6, 6) node _io_ill_s_T_10 = eq(_io_ill_s_T_9, UInt<1>(0h1)) node io_ill_s_12 = and(_io_ill_s_T_8, _io_ill_s_T_10) node _io_ill_s_T_11 = bits(io.in, 11, 7) node io_ill_s_18 = eq(_io_ill_s_T_11, UInt<1>(0h0)) node _io_ill_s_T_12 = bits(io.in, 11, 7) node io_ill_s_19 = eq(_io_ill_s_T_12, UInt<1>(0h0)) node _io_ill_s_T_13 = bits(io.in, 12, 2) node _io_ill_s_T_14 = orr(_io_ill_s_T_13) node io_ill_s_20 = eq(_io_ill_s_T_14, UInt<1>(0h0)) node _io_ill_T = bits(io.in, 1, 0) node _io_ill_T_1 = bits(io.in, 15, 13) node _io_ill_T_2 = cat(_io_ill_T, _io_ill_T_1) node _io_ill_T_3 = eq(_io_ill_T_2, UInt<1>(0h1)) node _io_ill_T_4 = mux(_io_ill_T_3, UInt<1>(0h0), io_ill_s_0) node _io_ill_T_5 = eq(_io_ill_T_2, UInt<2>(0h2)) node _io_ill_T_6 = mux(_io_ill_T_5, UInt<1>(0h0), _io_ill_T_4) node _io_ill_T_7 = eq(_io_ill_T_2, UInt<2>(0h3)) node _io_ill_T_8 = mux(_io_ill_T_7, UInt<1>(0h0), _io_ill_T_6) node _io_ill_T_9 = eq(_io_ill_T_2, UInt<3>(0h4)) node _io_ill_T_10 = mux(_io_ill_T_9, UInt<1>(0h1), _io_ill_T_8) node _io_ill_T_11 = eq(_io_ill_T_2, UInt<3>(0h5)) node _io_ill_T_12 = mux(_io_ill_T_11, UInt<1>(0h0), _io_ill_T_10) node _io_ill_T_13 = eq(_io_ill_T_2, UInt<3>(0h6)) node _io_ill_T_14 = mux(_io_ill_T_13, UInt<1>(0h0), _io_ill_T_12) node _io_ill_T_15 = eq(_io_ill_T_2, UInt<3>(0h7)) node _io_ill_T_16 = mux(_io_ill_T_15, UInt<1>(0h0), _io_ill_T_14) node _io_ill_T_17 = eq(_io_ill_T_2, UInt<4>(0h8)) node _io_ill_T_18 = mux(_io_ill_T_17, UInt<1>(0h0), _io_ill_T_16) node _io_ill_T_19 = eq(_io_ill_T_2, UInt<4>(0h9)) node _io_ill_T_20 = mux(_io_ill_T_19, io_ill_s_9, _io_ill_T_18) node _io_ill_T_21 = eq(_io_ill_T_2, UInt<4>(0ha)) node _io_ill_T_22 = mux(_io_ill_T_21, UInt<1>(0h0), _io_ill_T_20) node _io_ill_T_23 = eq(_io_ill_T_2, UInt<4>(0hb)) node _io_ill_T_24 = mux(_io_ill_T_23, io_ill_s_11, _io_ill_T_22) node _io_ill_T_25 = eq(_io_ill_T_2, UInt<4>(0hc)) node _io_ill_T_26 = mux(_io_ill_T_25, io_ill_s_12, _io_ill_T_24) node _io_ill_T_27 = eq(_io_ill_T_2, UInt<4>(0hd)) node _io_ill_T_28 = mux(_io_ill_T_27, UInt<1>(0h0), _io_ill_T_26) node _io_ill_T_29 = eq(_io_ill_T_2, UInt<4>(0he)) node _io_ill_T_30 = mux(_io_ill_T_29, UInt<1>(0h0), _io_ill_T_28) node _io_ill_T_31 = eq(_io_ill_T_2, UInt<4>(0hf)) node _io_ill_T_32 = mux(_io_ill_T_31, UInt<1>(0h0), _io_ill_T_30) node _io_ill_T_33 = eq(_io_ill_T_2, UInt<5>(0h10)) node _io_ill_T_34 = mux(_io_ill_T_33, UInt<1>(0h0), _io_ill_T_32) node _io_ill_T_35 = eq(_io_ill_T_2, UInt<5>(0h11)) node _io_ill_T_36 = mux(_io_ill_T_35, UInt<1>(0h0), _io_ill_T_34) node _io_ill_T_37 = eq(_io_ill_T_2, UInt<5>(0h12)) node _io_ill_T_38 = mux(_io_ill_T_37, io_ill_s_18, _io_ill_T_36) node _io_ill_T_39 = eq(_io_ill_T_2, UInt<5>(0h13)) node _io_ill_T_40 = mux(_io_ill_T_39, io_ill_s_19, _io_ill_T_38) node _io_ill_T_41 = eq(_io_ill_T_2, UInt<5>(0h14)) node _io_ill_T_42 = mux(_io_ill_T_41, io_ill_s_20, _io_ill_T_40) node _io_ill_T_43 = eq(_io_ill_T_2, UInt<5>(0h15)) node _io_ill_T_44 = mux(_io_ill_T_43, UInt<1>(0h0), _io_ill_T_42) node _io_ill_T_45 = eq(_io_ill_T_2, UInt<5>(0h16)) node _io_ill_T_46 = mux(_io_ill_T_45, UInt<1>(0h0), _io_ill_T_44) node _io_ill_T_47 = eq(_io_ill_T_2, UInt<5>(0h17)) node _io_ill_T_48 = mux(_io_ill_T_47, UInt<1>(0h0), _io_ill_T_46) node _io_ill_T_49 = eq(_io_ill_T_2, UInt<5>(0h18)) node _io_ill_T_50 = mux(_io_ill_T_49, UInt<1>(0h0), _io_ill_T_48) node _io_ill_T_51 = eq(_io_ill_T_2, UInt<5>(0h19)) node _io_ill_T_52 = mux(_io_ill_T_51, UInt<1>(0h0), _io_ill_T_50) node _io_ill_T_53 = eq(_io_ill_T_2, UInt<5>(0h1a)) node _io_ill_T_54 = mux(_io_ill_T_53, UInt<1>(0h0), _io_ill_T_52) node _io_ill_T_55 = eq(_io_ill_T_2, UInt<5>(0h1b)) node _io_ill_T_56 = mux(_io_ill_T_55, UInt<1>(0h0), _io_ill_T_54) node _io_ill_T_57 = eq(_io_ill_T_2, UInt<5>(0h1c)) node _io_ill_T_58 = mux(_io_ill_T_57, UInt<1>(0h0), _io_ill_T_56) node _io_ill_T_59 = eq(_io_ill_T_2, UInt<5>(0h1d)) node _io_ill_T_60 = mux(_io_ill_T_59, UInt<1>(0h0), _io_ill_T_58) node _io_ill_T_61 = eq(_io_ill_T_2, UInt<5>(0h1e)) node _io_ill_T_62 = mux(_io_ill_T_61, UInt<1>(0h0), _io_ill_T_60) node _io_ill_T_63 = eq(_io_ill_T_2, UInt<5>(0h1f)) node _io_ill_T_64 = mux(_io_ill_T_63, UInt<1>(0h0), _io_ill_T_62) connect io.ill, _io_ill_T_64

module RVCExpander_6( // @[RVC.scala:190:7] input clock, // @[RVC.scala:190:7] input reset, // @[RVC.scala:190:7] input [31:0] io_in, // @[RVC.scala:191:14] output [31:0] io_out_bits, // @[RVC.scala:191:14] output io_rvc // @[RVC.scala:191:14] ); wire [31:0] io_in_0 = io_in; // @[RVC.scala:190:7] wire [11:0] io_out_s_jr_lo = 12'h67; // @[RVC.scala:135:19] wire [4:0] io_out_s_10_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_13_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_14_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_mv_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_jr_reserved_rd = 5'h0; // @[RVC.scala:21:19] wire [11:0] io_out_s_jalr_lo = 12'hE7; // @[RVC.scala:139:21] wire [4:0] io_out_s_jalr_ebreak_rd = 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_17_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_18_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_19_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_21_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_22_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_23_rs1 = 5'h2; // @[package.scala:39:86] wire [31:0] io_out_s_24_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_25_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_26_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_27_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_28_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_29_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_30_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_31_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] _io_out_T_64_bits; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rd; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs1; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs2; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs3; // @[package.scala:39:76] wire _io_rvc_T_1; // @[RVC.scala:199:26] wire _io_ill_T_64; // @[package.scala:39:76] wire [31:0] io_out_bits_0; // @[RVC.scala:190:7] wire [4:0] io_out_rd; // @[RVC.scala:190:7] wire [4:0] io_out_rs1; // @[RVC.scala:190:7] wire [4:0] io_out_rs2; // @[RVC.scala:190:7] wire [4:0] io_out_rs3; // @[RVC.scala:190:7] wire io_rvc_0; // @[RVC.scala:190:7] wire io_ill; // @[RVC.scala:190:7] wire [1:0] _io_rvc_T = io_in_0[1:0]; // @[RVC.scala:190:7, :199:20] wire [1:0] _io_out_T = io_in_0[1:0]; // @[RVC.scala:154:12, :190:7, :199:20] wire [1:0] _io_ill_T = io_in_0[1:0]; // @[RVC.scala:186:12, :190:7, :199:20] assign _io_rvc_T_1 = _io_rvc_T != 2'h3; // @[RVC.scala:199:{20,26}] assign io_rvc_0 = _io_rvc_T_1; // @[RVC.scala:190:7, :199:26] wire [7:0] _io_out_s_opc_T = io_in_0[12:5]; // @[RVC.scala:53:22, :190:7] wire _io_out_s_opc_T_1 = |_io_out_s_opc_T; // @[RVC.scala:53:{22,29}] wire [6:0] io_out_s_opc = _io_out_s_opc_T_1 ? 7'h13 : 7'h1F; // @[RVC.scala:53:{20,29}] wire [3:0] _io_out_s_T = io_in_0[10:7]; // @[RVC.scala:34:26, :190:7] wire [1:0] _io_out_s_T_1 = io_in_0[12:11]; // @[RVC.scala:34:35, :190:7] wire _io_out_s_T_2 = io_in_0[5]; // @[RVC.scala:34:45, :190:7] wire _io_out_s_T_28 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_59 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_68 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_101 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_110 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_185 = io_in_0[5]; // @[RVC.scala:34:45, :42:50, :190:7] wire _io_out_s_T_3 = io_in_0[6]; // @[RVC.scala:34:51, :190:7] wire _io_out_s_T_30 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_61 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_70 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_103 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_112 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_187 = io_in_0[6]; // @[RVC.scala:34:51, :42:62, :190:7] wire _io_out_s_T_249 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_260 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_271 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_282 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_ill_s_T_9 = io_in_0[6]; // @[RVC.scala:34:51, :169:69, :190:7] wire [2:0] io_out_s_lo = {_io_out_s_T_3, 2'h0}; // @[RVC.scala:34:{24,51}] wire [5:0] io_out_s_hi_hi = {_io_out_s_T, _io_out_s_T_1}; // @[RVC.scala:34:{24,26,35}] wire [6:0] io_out_s_hi = {io_out_s_hi_hi, _io_out_s_T_2}; // @[RVC.scala:34:{24,45}] wire [9:0] _io_out_s_T_4 = {io_out_s_hi, io_out_s_lo}; // @[RVC.scala:34:24] wire [2:0] _io_out_s_T_5 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_8 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_10 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_18 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_21 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_25 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_34 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_37 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_41 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_49 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_52 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_56 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_64 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_74 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_78 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_85 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_94 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_98 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_106 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_116 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_120 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_127 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_136 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_140 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_152 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_164 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_174 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_me_T_9 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_194 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_223 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_242 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_292 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_383 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [2:0] _io_out_s_T_401 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [4:0] _io_out_s_T_6 = {2'h1, _io_out_s_T_5}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_1 = {_io_out_s_T_6, io_out_s_opc}; // @[RVC.scala:31:17, :53:20, :54:15] wire [14:0] io_out_s_hi_hi_1 = {_io_out_s_T_4, 5'h2}; // @[package.scala:39:86] wire [17:0] io_out_s_hi_1 = {io_out_s_hi_hi_1, 3'h0}; // @[RVC.scala:54:15] wire [29:0] _io_out_s_T_7 = {io_out_s_hi_1, io_out_s_lo_1}; // @[RVC.scala:54:15] wire [4:0] _io_out_s_T_9 = {2'h1, _io_out_s_T_8}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rd = _io_out_s_T_9; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_11 = {2'h1, _io_out_s_T_10}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs2 = _io_out_s_T_11; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_12 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_27 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_43 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_58 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_80 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_100 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_122 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_142 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_154 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_166 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_176 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_me_T_11 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_196 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_244 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_294 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_334 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_372 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_382 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_391 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_400 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_409 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_mv_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_add_T_7 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jr_reserved_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_423 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_436 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_449 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_453 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_457 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_461 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_465 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_469 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_473 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_477 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_481 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] io_out_s_0_rs3 = _io_out_s_T_12; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_0_bits; // @[RVC.scala:21:19] assign io_out_s_0_bits = {2'h0, _io_out_s_T_7}; // @[RVC.scala:21:19, :22:14, :54:15] wire [1:0] _io_out_s_T_13 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_44 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_81 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_89 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_123 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_131 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_funct_T_1 = io_in_0[6:5]; // @[RVC.scala:36:20, :102:77, :190:7] wire [1:0] _io_out_s_sub_T = io_in_0[6:5]; // @[RVC.scala:36:20, :103:24, :190:7] wire [1:0] _io_out_s_T_297 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_305 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_315 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_323 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_337 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_345 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_355 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_363 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_385 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [1:0] _io_out_s_T_403 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [2:0] _io_out_s_T_14 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_29 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_45 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_60 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_69 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_82 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_90 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_102 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_111 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_124 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_132 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_412 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_417 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_438 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_443 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_ill_s_T_7 = io_in_0[12:10]; // @[RVC.scala:36:28, :169:22, :190:7] wire [4:0] io_out_s_hi_2 = {_io_out_s_T_13, _io_out_s_T_14}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_15 = {io_out_s_hi_2, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_16 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_23 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_32 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_39 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_47 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_54 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_66 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_76 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_87 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_96 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_108 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_118 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_129 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_138 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_200 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_202 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_208 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_210 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_218 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_220 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_225 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_227 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_238 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_240 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_290 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_311 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_330 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_332 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_351 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_370 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_411 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_416 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_437 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_442 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [4:0] _io_out_s_T_17 = {2'h1, _io_out_s_T_16}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_19 = {2'h1, _io_out_s_T_18}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_2 = {_io_out_s_T_19, 7'h7}; // @[RVC.scala:31:17, :58:23] wire [12:0] io_out_s_hi_hi_2 = {_io_out_s_T_15, _io_out_s_T_17}; // @[RVC.scala:30:17, :36:18, :58:23] wire [15:0] io_out_s_hi_3 = {io_out_s_hi_hi_2, 3'h3}; // @[RVC.scala:58:23] wire [27:0] _io_out_s_T_20 = {io_out_s_hi_3, io_out_s_lo_2}; // @[RVC.scala:58:23] wire [4:0] _io_out_s_T_22 = {2'h1, _io_out_s_T_21}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rd = _io_out_s_T_22; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_24 = {2'h1, _io_out_s_T_23}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs1 = _io_out_s_T_24; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_26 = {2'h1, _io_out_s_T_25}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs2 = _io_out_s_T_26; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_1_rs3 = _io_out_s_T_27; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_1_bits; // @[RVC.scala:21:19] assign io_out_s_1_bits = {4'h0, _io_out_s_T_20}; // @[RVC.scala:21:19, :22:14, :58:23] wire [2:0] io_out_s_lo_3 = {_io_out_s_T_30, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_4 = {_io_out_s_T_28, _io_out_s_T_29}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_31 = {io_out_s_hi_4, io_out_s_lo_3}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_33 = {2'h1, _io_out_s_T_32}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_35 = {2'h1, _io_out_s_T_34}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_4 = {_io_out_s_T_35, 7'h3}; // @[RVC.scala:31:17, :57:22] wire [11:0] io_out_s_hi_hi_3 = {_io_out_s_T_31, _io_out_s_T_33}; // @[RVC.scala:30:17, :35:18, :57:22] wire [14:0] io_out_s_hi_5 = {io_out_s_hi_hi_3, 3'h2}; // @[package.scala:39:86] wire [26:0] _io_out_s_T_36 = {io_out_s_hi_5, io_out_s_lo_4}; // @[RVC.scala:57:22] wire [4:0] _io_out_s_T_38 = {2'h1, _io_out_s_T_37}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rd = _io_out_s_T_38; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_40 = {2'h1, _io_out_s_T_39}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs1 = _io_out_s_T_40; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_42 = {2'h1, _io_out_s_T_41}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs2 = _io_out_s_T_42; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_2_rs3 = _io_out_s_T_43; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_2_bits; // @[RVC.scala:21:19] assign io_out_s_2_bits = {5'h0, _io_out_s_T_36}; // @[RVC.scala:21:19, :22:14, :57:22] wire [4:0] io_out_s_hi_6 = {_io_out_s_T_44, _io_out_s_T_45}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_46 = {io_out_s_hi_6, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_48 = {2'h1, _io_out_s_T_47}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_50 = {2'h1, _io_out_s_T_49}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_5 = {_io_out_s_T_50, 7'h3}; // @[RVC.scala:31:17, :56:22] wire [12:0] io_out_s_hi_hi_4 = {_io_out_s_T_46, _io_out_s_T_48}; // @[RVC.scala:30:17, :36:18, :56:22] wire [15:0] io_out_s_hi_7 = {io_out_s_hi_hi_4, 3'h3}; // @[RVC.scala:56:22] wire [27:0] _io_out_s_T_51 = {io_out_s_hi_7, io_out_s_lo_5}; // @[RVC.scala:56:22] wire [4:0] _io_out_s_T_53 = {2'h1, _io_out_s_T_52}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rd = _io_out_s_T_53; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_55 = {2'h1, _io_out_s_T_54}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs1 = _io_out_s_T_55; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_57 = {2'h1, _io_out_s_T_56}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs2 = _io_out_s_T_57; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_3_rs3 = _io_out_s_T_58; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_3_bits; // @[RVC.scala:21:19] assign io_out_s_3_bits = {4'h0, _io_out_s_T_51}; // @[RVC.scala:21:19, :22:14, :56:22] wire [2:0] io_out_s_lo_6 = {_io_out_s_T_61, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_8 = {_io_out_s_T_59, _io_out_s_T_60}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_62 = {io_out_s_hi_8, io_out_s_lo_6}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_63 = _io_out_s_T_62[6:5]; // @[RVC.scala:35:18, :63:32] wire [4:0] _io_out_s_T_65 = {2'h1, _io_out_s_T_64}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_67 = {2'h1, _io_out_s_T_66}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_7 = {_io_out_s_T_70, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_9 = {_io_out_s_T_68, _io_out_s_T_69}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_71 = {io_out_s_hi_9, io_out_s_lo_7}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_72 = _io_out_s_T_71[4:0]; // @[RVC.scala:35:18, :63:65] wire [7:0] io_out_s_lo_hi = {3'h2, _io_out_s_T_72}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_8 = {io_out_s_lo_hi, 7'h3F}; // @[RVC.scala:63:25] wire [6:0] io_out_s_hi_hi_5 = {_io_out_s_T_63, _io_out_s_T_65}; // @[RVC.scala:31:17, :63:{25,32}] wire [11:0] io_out_s_hi_10 = {io_out_s_hi_hi_5, _io_out_s_T_67}; // @[RVC.scala:30:17, :63:25] wire [26:0] _io_out_s_T_73 = {io_out_s_hi_10, io_out_s_lo_8}; // @[RVC.scala:63:25] wire [4:0] _io_out_s_T_75 = {2'h1, _io_out_s_T_74}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rd = _io_out_s_T_75; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_77 = {2'h1, _io_out_s_T_76}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs1 = _io_out_s_T_77; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_79 = {2'h1, _io_out_s_T_78}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs2 = _io_out_s_T_79; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_4_rs3 = _io_out_s_T_80; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_4_bits; // @[RVC.scala:21:19] assign io_out_s_4_bits = {5'h0, _io_out_s_T_73}; // @[RVC.scala:21:19, :22:14, :63:25] wire [4:0] io_out_s_hi_11 = {_io_out_s_T_81, _io_out_s_T_82}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_83 = {io_out_s_hi_11, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_84 = _io_out_s_T_83[7:5]; // @[RVC.scala:36:18, :66:30] wire [4:0] _io_out_s_T_86 = {2'h1, _io_out_s_T_85}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_88 = {2'h1, _io_out_s_T_87}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_12 = {_io_out_s_T_89, _io_out_s_T_90}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_91 = {io_out_s_hi_12, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_92 = _io_out_s_T_91[4:0]; // @[RVC.scala:36:18, :66:63] wire [7:0] io_out_s_lo_hi_1 = {3'h3, _io_out_s_T_92}; // @[RVC.scala:66:{23,63}] wire [14:0] io_out_s_lo_9 = {io_out_s_lo_hi_1, 7'h27}; // @[RVC.scala:66:23] wire [7:0] io_out_s_hi_hi_6 = {_io_out_s_T_84, _io_out_s_T_86}; // @[RVC.scala:31:17, :66:{23,30}] wire [12:0] io_out_s_hi_13 = {io_out_s_hi_hi_6, _io_out_s_T_88}; // @[RVC.scala:30:17, :66:23] wire [27:0] _io_out_s_T_93 = {io_out_s_hi_13, io_out_s_lo_9}; // @[RVC.scala:66:23] wire [4:0] _io_out_s_T_95 = {2'h1, _io_out_s_T_94}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rd = _io_out_s_T_95; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_97 = {2'h1, _io_out_s_T_96}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs1 = _io_out_s_T_97; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_99 = {2'h1, _io_out_s_T_98}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs2 = _io_out_s_T_99; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_5_rs3 = _io_out_s_T_100; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_5_bits; // @[RVC.scala:21:19] assign io_out_s_5_bits = {4'h0, _io_out_s_T_93}; // @[RVC.scala:21:19, :22:14, :66:23] wire [2:0] io_out_s_lo_10 = {_io_out_s_T_103, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_14 = {_io_out_s_T_101, _io_out_s_T_102}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_104 = {io_out_s_hi_14, io_out_s_lo_10}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_105 = _io_out_s_T_104[6:5]; // @[RVC.scala:35:18, :65:29] wire [4:0] _io_out_s_T_107 = {2'h1, _io_out_s_T_106}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_109 = {2'h1, _io_out_s_T_108}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_11 = {_io_out_s_T_112, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_15 = {_io_out_s_T_110, _io_out_s_T_111}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_113 = {io_out_s_hi_15, io_out_s_lo_11}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_114 = _io_out_s_T_113[4:0]; // @[RVC.scala:35:18, :65:62] wire [7:0] io_out_s_lo_hi_2 = {3'h2, _io_out_s_T_114}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_12 = {io_out_s_lo_hi_2, 7'h23}; // @[RVC.scala:65:22] wire [6:0] io_out_s_hi_hi_7 = {_io_out_s_T_105, _io_out_s_T_107}; // @[RVC.scala:31:17, :65:{22,29}] wire [11:0] io_out_s_hi_16 = {io_out_s_hi_hi_7, _io_out_s_T_109}; // @[RVC.scala:30:17, :65:22] wire [26:0] _io_out_s_T_115 = {io_out_s_hi_16, io_out_s_lo_12}; // @[RVC.scala:65:22] wire [4:0] _io_out_s_T_117 = {2'h1, _io_out_s_T_116}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rd = _io_out_s_T_117; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_119 = {2'h1, _io_out_s_T_118}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs1 = _io_out_s_T_119; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_121 = {2'h1, _io_out_s_T_120}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs2 = _io_out_s_T_121; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_6_rs3 = _io_out_s_T_122; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_6_bits; // @[RVC.scala:21:19] assign io_out_s_6_bits = {5'h0, _io_out_s_T_115}; // @[RVC.scala:21:19, :22:14, :65:22] wire [4:0] io_out_s_hi_17 = {_io_out_s_T_123, _io_out_s_T_124}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_125 = {io_out_s_hi_17, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_126 = _io_out_s_T_125[7:5]; // @[RVC.scala:36:18, :64:29] wire [4:0] _io_out_s_T_128 = {2'h1, _io_out_s_T_127}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_130 = {2'h1, _io_out_s_T_129}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_18 = {_io_out_s_T_131, _io_out_s_T_132}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_133 = {io_out_s_hi_18, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_134 = _io_out_s_T_133[4:0]; // @[RVC.scala:36:18, :64:62] wire [7:0] io_out_s_lo_hi_3 = {3'h3, _io_out_s_T_134}; // @[RVC.scala:64:{22,62}] wire [14:0] io_out_s_lo_13 = {io_out_s_lo_hi_3, 7'h23}; // @[RVC.scala:64:22] wire [7:0] io_out_s_hi_hi_8 = {_io_out_s_T_126, _io_out_s_T_128}; // @[RVC.scala:31:17, :64:{22,29}] wire [12:0] io_out_s_hi_19 = {io_out_s_hi_hi_8, _io_out_s_T_130}; // @[RVC.scala:30:17, :64:22] wire [27:0] _io_out_s_T_135 = {io_out_s_hi_19, io_out_s_lo_13}; // @[RVC.scala:64:22] wire [4:0] _io_out_s_T_137 = {2'h1, _io_out_s_T_136}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rd = _io_out_s_T_137; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_139 = {2'h1, _io_out_s_T_138}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs1 = _io_out_s_T_139; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_141 = {2'h1, _io_out_s_T_140}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs2 = _io_out_s_T_141; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_7_rs3 = _io_out_s_T_142; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_7_bits; // @[RVC.scala:21:19] assign io_out_s_7_bits = {4'h0, _io_out_s_T_135}; // @[RVC.scala:21:19, :22:14, :64:22] wire _io_out_s_T_143 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_155 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_167 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_opc_T_4 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_me_T = io_in_0[12]; // @[RVC.scala:41:30, :43:30, :190:7] wire _io_out_s_opc_T_9 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_182 = io_in_0[12]; // @[RVC.scala:42:34, :43:30, :190:7] wire _io_out_s_T_197 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_205 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_214 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_funct_T = io_in_0[12]; // @[RVC.scala:43:30, :102:70, :190:7] wire _io_out_s_opc_T_14 = io_in_0[12]; // @[RVC.scala:43:30, :104:24, :190:7] wire _io_out_s_T_245 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_256 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_267 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_278 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_295 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_303 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_313 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_321 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_335 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_343 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_353 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_361 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_373 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_384 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_393 = io_in_0[12]; // @[RVC.scala:37:30, :43:30, :190:7] wire _io_out_s_T_402 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_410 = io_in_0[12]; // @[RVC.scala:43:30, :143:12, :190:7] wire _io_ill_s_T_3 = io_in_0[12]; // @[RVC.scala:43:30, :168:19, :190:7] wire [6:0] _io_out_s_T_144 = {7{_io_out_s_T_143}}; // @[RVC.scala:43:{25,30}] wire [4:0] _io_out_s_T_145 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_157 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_169 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_opc_T_6 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_me_T_2 = io_in_0[6:2]; // @[RVC.scala:41:38, :43:38, :190:7] wire [4:0] _io_out_s_opc_T_11 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_198 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_206 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_216 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_374 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_381 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_390 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_399 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_408 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T_6 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_reserved_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_415 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_422 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_428 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_435 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_441 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_448 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_ill_s_T_4 = io_in_0[6:2]; // @[RVC.scala:43:38, :168:27, :190:7] wire [11:0] _io_out_s_T_146 = {_io_out_s_T_144, _io_out_s_T_145}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_147 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_148 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_150 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_151 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_opc_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_159 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_160 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_162 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_163 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_171 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_173 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_7 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_8 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_177 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_179 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_189 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_190 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_192 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_193 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_load_opc_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_376 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_377 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_379 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_380 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_387 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_389 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_396 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_398 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_405 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_407 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_4 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_421 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_434 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_447 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_450 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_454 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_458 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_462 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_466 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_470 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_474 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_478 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_ill_s_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_11 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_12 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [11:0] io_out_s_lo_14 = {_io_out_s_T_148, 7'h13}; // @[RVC.scala:33:13, :75:24] wire [16:0] io_out_s_hi_hi_9 = {_io_out_s_T_146, _io_out_s_T_147}; // @[RVC.scala:33:13, :43:20, :75:24] wire [19:0] io_out_s_hi_20 = {io_out_s_hi_hi_9, 3'h0}; // @[RVC.scala:75:24] wire [31:0] _io_out_s_T_149 = {io_out_s_hi_20, io_out_s_lo_14}; // @[RVC.scala:75:24] wire [31:0] io_out_s_8_bits = _io_out_s_T_149; // @[RVC.scala:21:19, :75:24] wire [4:0] io_out_s_8_rd = _io_out_s_T_150; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_8_rs1 = _io_out_s_T_151; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_153 = {2'h1, _io_out_s_T_152}; // @[package.scala:39:86] wire [4:0] io_out_s_8_rs2 = _io_out_s_T_153; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_8_rs3 = _io_out_s_T_154; // @[RVC.scala:20:101, :21:19] wire _io_out_s_opc_T_3 = |_io_out_s_opc_T_2; // @[RVC.scala:33:13, :77:24] wire [6:0] io_out_s_opc_1 = {4'h3, ~_io_out_s_opc_T_3, 2'h3}; // @[RVC.scala:77:{20,24}] wire [6:0] _io_out_s_T_156 = {7{_io_out_s_T_155}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_158 = {_io_out_s_T_156, _io_out_s_T_157}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_15 = {_io_out_s_T_160, io_out_s_opc_1}; // @[RVC.scala:33:13, :77:20, :78:15] wire [16:0] io_out_s_hi_hi_10 = {_io_out_s_T_158, _io_out_s_T_159}; // @[RVC.scala:33:13, :43:20, :78:15] wire [19:0] io_out_s_hi_21 = {io_out_s_hi_hi_10, 3'h0}; // @[RVC.scala:78:15] wire [31:0] _io_out_s_T_161 = {io_out_s_hi_21, io_out_s_lo_15}; // @[RVC.scala:78:15] wire [31:0] io_out_s_9_bits = _io_out_s_T_161; // @[RVC.scala:21:19, :78:15] wire [4:0] io_out_s_9_rd = _io_out_s_T_162; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_9_rs1 = _io_out_s_T_163; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_165 = {2'h1, _io_out_s_T_164}; // @[package.scala:39:86] wire [4:0] io_out_s_9_rs2 = _io_out_s_T_165; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_9_rs3 = _io_out_s_T_166; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_T_168 = {7{_io_out_s_T_167}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_170 = {_io_out_s_T_168, _io_out_s_T_169}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_16 = {_io_out_s_T_171, 7'h13}; // @[RVC.scala:33:13, :84:22] wire [16:0] io_out_s_hi_hi_11 = {_io_out_s_T_170, 5'h0}; // @[RVC.scala:43:20, :84:22] wire [19:0] io_out_s_hi_22 = {io_out_s_hi_hi_11, 3'h0}; // @[RVC.scala:84:22] wire [31:0] _io_out_s_T_172 = {io_out_s_hi_22, io_out_s_lo_16}; // @[RVC.scala:84:22] wire [31:0] io_out_s_10_bits = _io_out_s_T_172; // @[RVC.scala:21:19, :84:22] wire [4:0] io_out_s_10_rd = _io_out_s_T_173; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_175 = {2'h1, _io_out_s_T_174}; // @[package.scala:39:86] wire [4:0] io_out_s_10_rs2 = _io_out_s_T_175; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_10_rs3 = _io_out_s_T_176; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_opc_T_5 = {7{_io_out_s_opc_T_4}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_7 = {_io_out_s_opc_T_5, _io_out_s_opc_T_6}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_8 = |_io_out_s_opc_T_7; // @[RVC.scala:43:20, :90:29] wire [6:0] io_out_s_opc_2 = {3'h3, ~_io_out_s_opc_T_8, 3'h7}; // @[RVC.scala:90:{20,29}] wire [14:0] _io_out_s_me_T_1 = {15{_io_out_s_me_T}}; // @[RVC.scala:41:{24,30}] wire [19:0] io_out_s_me_hi = {_io_out_s_me_T_1, _io_out_s_me_T_2}; // @[RVC.scala:41:{19,24,38}] wire [31:0] _io_out_s_me_T_3 = {io_out_s_me_hi, 12'h0}; // @[RVC.scala:41:19] wire [19:0] _io_out_s_me_T_4 = _io_out_s_me_T_3[31:12]; // @[RVC.scala:41:19, :91:31] wire [24:0] io_out_s_me_hi_1 = {_io_out_s_me_T_4, _io_out_s_me_T_5}; // @[RVC.scala:33:13, :91:{24,31}] wire [31:0] _io_out_s_me_T_6 = {io_out_s_me_hi_1, io_out_s_opc_2}; // @[RVC.scala:90:20, :91:24] wire [31:0] io_out_s_me_bits = _io_out_s_me_T_6; // @[RVC.scala:21:19, :91:24] wire [4:0] io_out_s_me_rd = _io_out_s_me_T_7; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_me_rs1 = _io_out_s_me_T_8; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_me_T_10 = {2'h1, _io_out_s_me_T_9}; // @[package.scala:39:86] wire [4:0] io_out_s_me_rs2 = _io_out_s_me_T_10; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_me_rs3 = _io_out_s_me_T_11; // @[RVC.scala:20:101, :21:19] wire _io_out_s_T_178 = _io_out_s_T_177 == 5'h0; // @[RVC.scala:33:13, :92:14] wire _io_out_s_T_180 = _io_out_s_T_179 == 5'h2; // @[package.scala:39:86] wire _io_out_s_T_181 = _io_out_s_T_178 | _io_out_s_T_180; // @[RVC.scala:92:{14,21,27}] wire [6:0] _io_out_s_opc_T_10 = {7{_io_out_s_opc_T_9}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_12 = {_io_out_s_opc_T_10, _io_out_s_opc_T_11}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_13 = |_io_out_s_opc_T_12; // @[RVC.scala:43:20, :86:29] wire [6:0] io_out_s_opc_3 = _io_out_s_opc_T_13 ? 7'h13 : 7'h1F; // @[RVC.scala:86:{20,29}] wire [2:0] _io_out_s_T_183 = {3{_io_out_s_T_182}}; // @[RVC.scala:42:{29,34}] wire [1:0] _io_out_s_T_184 = io_in_0[4:3]; // @[RVC.scala:42:42, :190:7] wire [1:0] _io_out_s_T_300 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_308 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_318 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_326 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_340 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_348 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_358 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_366 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire _io_out_s_T_186 = io_in_0[2]; // @[RVC.scala:42:56, :190:7] wire _io_out_s_T_251 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_262 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_273 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_284 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_298 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_306 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_316 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_324 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_338 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_346 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_356 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_364 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire [1:0] io_out_s_lo_hi_4 = {_io_out_s_T_186, _io_out_s_T_187}; // @[RVC.scala:42:{24,56,62}] wire [5:0] io_out_s_lo_17 = {io_out_s_lo_hi_4, 4'h0}; // @[RVC.scala:42:24] wire [4:0] io_out_s_hi_hi_12 = {_io_out_s_T_183, _io_out_s_T_184}; // @[RVC.scala:42:{24,29,42}] wire [5:0] io_out_s_hi_23 = {io_out_s_hi_hi_12, _io_out_s_T_185}; // @[RVC.scala:42:{24,50}] wire [11:0] _io_out_s_T_188 = {io_out_s_hi_23, io_out_s_lo_17}; // @[RVC.scala:42:24] wire [11:0] io_out_s_lo_18 = {_io_out_s_T_190, io_out_s_opc_3}; // @[RVC.scala:33:13, :86:20, :87:15] wire [16:0] io_out_s_hi_hi_13 = {_io_out_s_T_188, _io_out_s_T_189}; // @[RVC.scala:33:13, :42:24, :87:15] wire [19:0] io_out_s_hi_24 = {io_out_s_hi_hi_13, 3'h0}; // @[RVC.scala:87:15] wire [31:0] _io_out_s_T_191 = {io_out_s_hi_24, io_out_s_lo_18}; // @[RVC.scala:87:15] wire [31:0] io_out_s_res_bits = _io_out_s_T_191; // @[RVC.scala:21:19, :87:15] wire [4:0] io_out_s_res_rd = _io_out_s_T_192; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_res_rs1 = _io_out_s_T_193; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_195 = {2'h1, _io_out_s_T_194}; // @[package.scala:39:86] wire [4:0] io_out_s_res_rs2 = _io_out_s_T_195; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_res_rs3 = _io_out_s_T_196; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_11_bits = _io_out_s_T_181 ? io_out_s_res_bits : io_out_s_me_bits; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rd = _io_out_s_T_181 ? io_out_s_res_rd : io_out_s_me_rd; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs1 = _io_out_s_T_181 ? io_out_s_res_rs1 : io_out_s_me_rs1; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs2 = _io_out_s_T_181 ? io_out_s_res_rs2 : io_out_s_me_rs2; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs3 = _io_out_s_T_181 ? io_out_s_res_rs3 : io_out_s_me_rs3; // @[RVC.scala:21:19, :92:{10,21}] wire [5:0] _io_out_s_T_199 = {_io_out_s_T_197, _io_out_s_T_198}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_201 = {2'h1, _io_out_s_T_200}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_203 = {2'h1, _io_out_s_T_202}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_19 = {_io_out_s_T_203, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_14 = {_io_out_s_T_199, _io_out_s_T_201}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_25 = {io_out_s_hi_hi_14, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_204 = {io_out_s_hi_25, io_out_s_lo_19}; // @[RVC.scala:98:21] wire [5:0] _io_out_s_T_207 = {_io_out_s_T_205, _io_out_s_T_206}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_209 = {2'h1, _io_out_s_T_208}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_211 = {2'h1, _io_out_s_T_210}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_20 = {_io_out_s_T_211, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_15 = {_io_out_s_T_207, _io_out_s_T_209}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_26 = {io_out_s_hi_hi_15, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_212 = {io_out_s_hi_26, io_out_s_lo_20}; // @[RVC.scala:98:21] wire [30:0] _io_out_s_T_213 = {5'h10, _io_out_s_T_212}; // @[RVC.scala:98:21, :99:23] wire [6:0] _io_out_s_T_215 = {7{_io_out_s_T_214}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_217 = {_io_out_s_T_215, _io_out_s_T_216}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_219 = {2'h1, _io_out_s_T_218}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_221 = {2'h1, _io_out_s_T_220}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_21 = {_io_out_s_T_221, 7'h13}; // @[RVC.scala:30:17, :100:21] wire [16:0] io_out_s_hi_hi_16 = {_io_out_s_T_217, _io_out_s_T_219}; // @[RVC.scala:30:17, :43:20, :100:21] wire [19:0] io_out_s_hi_27 = {io_out_s_hi_hi_16, 3'h7}; // @[RVC.scala:100:21] wire [31:0] _io_out_s_T_222 = {io_out_s_hi_27, io_out_s_lo_21}; // @[RVC.scala:100:21] wire [2:0] _io_out_s_funct_T_2 = {_io_out_s_funct_T, _io_out_s_funct_T_1}; // @[RVC.scala:102:{68,70,77}] wire _io_out_s_funct_T_3 = _io_out_s_funct_T_2 == 3'h1; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_3, 2'h0}; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_5 = _io_out_s_funct_T_2 == 3'h2; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_6 = _io_out_s_funct_T_5 ? 3'h6 : _io_out_s_funct_T_4; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_7 = _io_out_s_funct_T_2 == 3'h3; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_8 = _io_out_s_funct_T_7 ? 3'h7 : _io_out_s_funct_T_6; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_9 = _io_out_s_funct_T_2 == 3'h4; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_10 = _io_out_s_funct_T_9 ? 3'h0 : _io_out_s_funct_T_8; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_11 = _io_out_s_funct_T_2 == 3'h5; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_12 = _io_out_s_funct_T_11 ? 3'h0 : _io_out_s_funct_T_10; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_13 = _io_out_s_funct_T_2 == 3'h6; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_14 = _io_out_s_funct_T_13 ? 3'h2 : _io_out_s_funct_T_12; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_15 = &_io_out_s_funct_T_2; // @[package.scala:39:86] wire [2:0] io_out_s_funct = _io_out_s_funct_T_15 ? 3'h3 : _io_out_s_funct_T_14; // @[package.scala:39:{76,86}] wire _io_out_s_sub_T_1 = _io_out_s_sub_T == 2'h0; // @[RVC.scala:103:{24,30}] wire [30:0] io_out_s_sub = {_io_out_s_sub_T_1, 30'h0}; // @[RVC.scala:103:{22,30}] wire [6:0] io_out_s_opc_4 = {3'h3, _io_out_s_opc_T_14, 3'h3}; // @[RVC.scala:104:{22,24}] wire [4:0] _io_out_s_T_224 = {2'h1, _io_out_s_T_223}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_226 = {2'h1, _io_out_s_T_225}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_228 = {2'h1, _io_out_s_T_227}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_22 = {_io_out_s_T_228, io_out_s_opc_4}; // @[RVC.scala:30:17, :104:22, :105:12] wire [9:0] io_out_s_hi_hi_17 = {_io_out_s_T_224, _io_out_s_T_226}; // @[RVC.scala:30:17, :31:17, :105:12] wire [12:0] io_out_s_hi_28 = {io_out_s_hi_hi_17, io_out_s_funct}; // @[package.scala:39:76] wire [24:0] _io_out_s_T_229 = {io_out_s_hi_28, io_out_s_lo_22}; // @[RVC.scala:105:12] wire [30:0] _io_out_s_T_230 = {6'h0, _io_out_s_T_229} | io_out_s_sub; // @[RVC.scala:103:22, :105:{12,43}] wire [1:0] _io_out_s_T_231 = io_in_0[11:10]; // @[RVC.scala:107:42, :190:7] wire [1:0] _io_out_s_T_299 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_307 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_317 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_325 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_339 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_347 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_357 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_365 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire _io_out_s_T_232 = _io_out_s_T_231 == 2'h1; // @[package.scala:39:86] wire [30:0] _io_out_s_T_233 = _io_out_s_T_232 ? _io_out_s_T_213 : {5'h0, _io_out_s_T_204}; // @[package.scala:39:{76,86}] wire _io_out_s_T_234 = _io_out_s_T_231 == 2'h2; // @[package.scala:39:86] wire [31:0] _io_out_s_T_235 = _io_out_s_T_234 ? _io_out_s_T_222 : {1'h0, _io_out_s_T_233}; // @[package.scala:39:{76,86}] wire _io_out_s_T_236 = &_io_out_s_T_231; // @[package.scala:39:86] wire [31:0] _io_out_s_T_237 = _io_out_s_T_236 ? {1'h0, _io_out_s_T_230} : _io_out_s_T_235; // @[package.scala:39:{76,86}] wire [31:0] io_out_s_12_bits = _io_out_s_T_237; // @[package.scala:39:76] wire [4:0] _io_out_s_T_239 = {2'h1, _io_out_s_T_238}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rd = _io_out_s_T_239; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_241 = {2'h1, _io_out_s_T_240}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs1 = _io_out_s_T_241; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_243 = {2'h1, _io_out_s_T_242}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs2 = _io_out_s_T_243; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_12_rs3 = _io_out_s_T_244; // @[RVC.scala:20:101, :21:19] wire [9:0] _io_out_s_T_246 = {10{_io_out_s_T_245}}; // @[RVC.scala:44:{22,28}] wire _io_out_s_T_247 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_258 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_269 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_280 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire [1:0] _io_out_s_T_248 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_259 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_270 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_281 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire _io_out_s_T_250 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_261 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_272 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_283 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_252 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_263 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_274 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_285 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire [2:0] _io_out_s_T_253 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_264 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_275 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_286 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [3:0] io_out_s_lo_lo = {_io_out_s_T_253, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_5 = {_io_out_s_T_251, _io_out_s_T_252}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_23 = {io_out_s_lo_hi_5, io_out_s_lo_lo}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo = {_io_out_s_T_249, _io_out_s_T_250}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi = {_io_out_s_T_246, _io_out_s_T_247}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_18 = {io_out_s_hi_hi_hi, _io_out_s_T_248}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_29 = {io_out_s_hi_hi_18, io_out_s_hi_lo}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_254 = {io_out_s_hi_29, io_out_s_lo_23}; // @[RVC.scala:44:17] wire _io_out_s_T_255 = _io_out_s_T_254[20]; // @[RVC.scala:44:17, :94:26] wire [9:0] _io_out_s_T_257 = {10{_io_out_s_T_256}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_1 = {_io_out_s_T_264, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_6 = {_io_out_s_T_262, _io_out_s_T_263}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_24 = {io_out_s_lo_hi_6, io_out_s_lo_lo_1}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_1 = {_io_out_s_T_260, _io_out_s_T_261}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_1 = {_io_out_s_T_257, _io_out_s_T_258}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_19 = {io_out_s_hi_hi_hi_1, _io_out_s_T_259}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_30 = {io_out_s_hi_hi_19, io_out_s_hi_lo_1}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_265 = {io_out_s_hi_30, io_out_s_lo_24}; // @[RVC.scala:44:17] wire [9:0] _io_out_s_T_266 = _io_out_s_T_265[10:1]; // @[RVC.scala:44:17, :94:36] wire [9:0] _io_out_s_T_268 = {10{_io_out_s_T_267}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_2 = {_io_out_s_T_275, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_7 = {_io_out_s_T_273, _io_out_s_T_274}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_25 = {io_out_s_lo_hi_7, io_out_s_lo_lo_2}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_2 = {_io_out_s_T_271, _io_out_s_T_272}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_2 = {_io_out_s_T_268, _io_out_s_T_269}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_20 = {io_out_s_hi_hi_hi_2, _io_out_s_T_270}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_31 = {io_out_s_hi_hi_20, io_out_s_hi_lo_2}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_276 = {io_out_s_hi_31, io_out_s_lo_25}; // @[RVC.scala:44:17] wire _io_out_s_T_277 = _io_out_s_T_276[11]; // @[RVC.scala:44:17, :94:48] wire [9:0] _io_out_s_T_279 = {10{_io_out_s_T_278}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_3 = {_io_out_s_T_286, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_8 = {_io_out_s_T_284, _io_out_s_T_285}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_26 = {io_out_s_lo_hi_8, io_out_s_lo_lo_3}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_3 = {_io_out_s_T_282, _io_out_s_T_283}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_3 = {_io_out_s_T_279, _io_out_s_T_280}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_21 = {io_out_s_hi_hi_hi_3, _io_out_s_T_281}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_32 = {io_out_s_hi_hi_21, io_out_s_hi_lo_3}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_287 = {io_out_s_hi_32, io_out_s_lo_26}; // @[RVC.scala:44:17] wire [7:0] _io_out_s_T_288 = _io_out_s_T_287[19:12]; // @[RVC.scala:44:17, :94:58] wire [12:0] io_out_s_lo_hi_9 = {_io_out_s_T_288, 5'h0}; // @[RVC.scala:94:{21,58}] wire [19:0] io_out_s_lo_27 = {io_out_s_lo_hi_9, 7'h6F}; // @[RVC.scala:94:21] wire [10:0] io_out_s_hi_hi_22 = {_io_out_s_T_255, _io_out_s_T_266}; // @[RVC.scala:94:{21,26,36}] wire [11:0] io_out_s_hi_33 = {io_out_s_hi_hi_22, _io_out_s_T_277}; // @[RVC.scala:94:{21,48}] wire [31:0] _io_out_s_T_289 = {io_out_s_hi_33, io_out_s_lo_27}; // @[RVC.scala:94:21] wire [31:0] io_out_s_13_bits = _io_out_s_T_289; // @[RVC.scala:21:19, :94:21] wire [4:0] _io_out_s_T_291 = {2'h1, _io_out_s_T_290}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs1 = _io_out_s_T_291; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_293 = {2'h1, _io_out_s_T_292}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs2 = _io_out_s_T_293; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_13_rs3 = _io_out_s_T_294; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_296 = {5{_io_out_s_T_295}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_10 = {_io_out_s_T_299, _io_out_s_T_300}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_28 = {io_out_s_lo_hi_10, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_23 = {_io_out_s_T_296, _io_out_s_T_297}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_34 = {io_out_s_hi_hi_23, _io_out_s_T_298}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_301 = {io_out_s_hi_34, io_out_s_lo_28}; // @[RVC.scala:45:17] wire _io_out_s_T_302 = _io_out_s_T_301[12]; // @[RVC.scala:45:17, :95:29] wire [4:0] _io_out_s_T_304 = {5{_io_out_s_T_303}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_11 = {_io_out_s_T_307, _io_out_s_T_308}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_29 = {io_out_s_lo_hi_11, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_24 = {_io_out_s_T_304, _io_out_s_T_305}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_35 = {io_out_s_hi_hi_24, _io_out_s_T_306}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_309 = {io_out_s_hi_35, io_out_s_lo_29}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_310 = _io_out_s_T_309[10:5]; // @[RVC.scala:45:17, :95:39] wire [4:0] _io_out_s_T_312 = {2'h1, _io_out_s_T_311}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_314 = {5{_io_out_s_T_313}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_12 = {_io_out_s_T_317, _io_out_s_T_318}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_30 = {io_out_s_lo_hi_12, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_25 = {_io_out_s_T_314, _io_out_s_T_315}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_36 = {io_out_s_hi_hi_25, _io_out_s_T_316}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_319 = {io_out_s_hi_36, io_out_s_lo_30}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_320 = _io_out_s_T_319[4:1]; // @[RVC.scala:45:17, :95:71] wire [4:0] _io_out_s_T_322 = {5{_io_out_s_T_321}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_13 = {_io_out_s_T_325, _io_out_s_T_326}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_31 = {io_out_s_lo_hi_13, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_26 = {_io_out_s_T_322, _io_out_s_T_323}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_37 = {io_out_s_hi_hi_26, _io_out_s_T_324}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_327 = {io_out_s_hi_37, io_out_s_lo_31}; // @[RVC.scala:45:17] wire _io_out_s_T_328 = _io_out_s_T_327[11]; // @[RVC.scala:45:17, :95:82] wire [7:0] io_out_s_lo_lo_4 = {_io_out_s_T_328, 7'h63}; // @[RVC.scala:95:{24,82}] wire [6:0] io_out_s_lo_hi_14 = {3'h0, _io_out_s_T_320}; // @[RVC.scala:95:{24,71}] wire [14:0] io_out_s_lo_32 = {io_out_s_lo_hi_14, io_out_s_lo_lo_4}; // @[RVC.scala:95:24] wire [9:0] io_out_s_hi_lo_4 = {5'h0, _io_out_s_T_312}; // @[RVC.scala:30:17, :95:24] wire [6:0] io_out_s_hi_hi_27 = {_io_out_s_T_302, _io_out_s_T_310}; // @[RVC.scala:95:{24,29,39}] wire [16:0] io_out_s_hi_38 = {io_out_s_hi_hi_27, io_out_s_hi_lo_4}; // @[RVC.scala:95:24] wire [31:0] _io_out_s_T_329 = {io_out_s_hi_38, io_out_s_lo_32}; // @[RVC.scala:95:24] wire [31:0] io_out_s_14_bits = _io_out_s_T_329; // @[RVC.scala:21:19, :95:24] wire [4:0] _io_out_s_T_331 = {2'h1, _io_out_s_T_330}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rd = _io_out_s_T_331; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_333 = {2'h1, _io_out_s_T_332}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rs1 = _io_out_s_T_333; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_14_rs3 = _io_out_s_T_334; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_336 = {5{_io_out_s_T_335}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_15 = {_io_out_s_T_339, _io_out_s_T_340}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_33 = {io_out_s_lo_hi_15, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_28 = {_io_out_s_T_336, _io_out_s_T_337}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_39 = {io_out_s_hi_hi_28, _io_out_s_T_338}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_341 = {io_out_s_hi_39, io_out_s_lo_33}; // @[RVC.scala:45:17] wire _io_out_s_T_342 = _io_out_s_T_341[12]; // @[RVC.scala:45:17, :96:29] wire [4:0] _io_out_s_T_344 = {5{_io_out_s_T_343}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_16 = {_io_out_s_T_347, _io_out_s_T_348}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_34 = {io_out_s_lo_hi_16, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_29 = {_io_out_s_T_344, _io_out_s_T_345}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_40 = {io_out_s_hi_hi_29, _io_out_s_T_346}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_349 = {io_out_s_hi_40, io_out_s_lo_34}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_350 = _io_out_s_T_349[10:5]; // @[RVC.scala:45:17, :96:39] wire [4:0] _io_out_s_T_352 = {2'h1, _io_out_s_T_351}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_354 = {5{_io_out_s_T_353}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_17 = {_io_out_s_T_357, _io_out_s_T_358}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_35 = {io_out_s_lo_hi_17, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_30 = {_io_out_s_T_354, _io_out_s_T_355}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_41 = {io_out_s_hi_hi_30, _io_out_s_T_356}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_359 = {io_out_s_hi_41, io_out_s_lo_35}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_360 = _io_out_s_T_359[4:1]; // @[RVC.scala:45:17, :96:71] wire [4:0] _io_out_s_T_362 = {5{_io_out_s_T_361}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_18 = {_io_out_s_T_365, _io_out_s_T_366}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_36 = {io_out_s_lo_hi_18, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_31 = {_io_out_s_T_362, _io_out_s_T_363}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_42 = {io_out_s_hi_hi_31, _io_out_s_T_364}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_367 = {io_out_s_hi_42, io_out_s_lo_36}; // @[RVC.scala:45:17] wire _io_out_s_T_368 = _io_out_s_T_367[11]; // @[RVC.scala:45:17, :96:82] wire [7:0] io_out_s_lo_lo_5 = {_io_out_s_T_368, 7'h63}; // @[RVC.scala:96:{24,82}] wire [6:0] io_out_s_lo_hi_19 = {3'h1, _io_out_s_T_360}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_37 = {io_out_s_lo_hi_19, io_out_s_lo_lo_5}; // @[RVC.scala:96:24] wire [9:0] io_out_s_hi_lo_5 = {5'h0, _io_out_s_T_352}; // @[RVC.scala:30:17, :96:24] wire [6:0] io_out_s_hi_hi_32 = {_io_out_s_T_342, _io_out_s_T_350}; // @[RVC.scala:96:{24,29,39}] wire [16:0] io_out_s_hi_43 = {io_out_s_hi_hi_32, io_out_s_hi_lo_5}; // @[RVC.scala:96:24] wire [31:0] _io_out_s_T_369 = {io_out_s_hi_43, io_out_s_lo_37}; // @[RVC.scala:96:24] wire [31:0] io_out_s_15_bits = _io_out_s_T_369; // @[RVC.scala:21:19, :96:24] wire [4:0] _io_out_s_T_371 = {2'h1, _io_out_s_T_370}; // @[package.scala:39:86] wire [4:0] io_out_s_15_rs1 = _io_out_s_T_371; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_15_rs3 = _io_out_s_T_372; // @[RVC.scala:20:101, :21:19] wire _io_out_s_load_opc_T_1 = |_io_out_s_load_opc_T; // @[RVC.scala:33:13, :113:27] wire [6:0] io_out_s_load_opc = _io_out_s_load_opc_T_1 ? 7'h3 : 7'h1F; // @[RVC.scala:113:{23,27}] wire [5:0] _io_out_s_T_375 = {_io_out_s_T_373, _io_out_s_T_374}; // @[RVC.scala:46:{18,20,27}] wire [11:0] io_out_s_lo_38 = {_io_out_s_T_377, 7'h13}; // @[RVC.scala:33:13, :114:24] wire [10:0] io_out_s_hi_hi_33 = {_io_out_s_T_375, _io_out_s_T_376}; // @[RVC.scala:33:13, :46:18, :114:24] wire [13:0] io_out_s_hi_44 = {io_out_s_hi_hi_33, 3'h1}; // @[package.scala:39:86] wire [25:0] _io_out_s_T_378 = {io_out_s_hi_44, io_out_s_lo_38}; // @[RVC.scala:114:24] wire [4:0] io_out_s_16_rd = _io_out_s_T_379; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs1 = _io_out_s_T_380; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs2 = _io_out_s_T_381; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_16_rs3 = _io_out_s_T_382; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_16_bits; // @[RVC.scala:21:19] assign io_out_s_16_bits = {6'h0, _io_out_s_T_378}; // @[RVC.scala:21:19, :22:14, :105:43, :114:24] wire [4:0] io_out_s_lo_39 = {_io_out_s_T_385, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_45 = {_io_out_s_T_383, _io_out_s_T_384}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_386 = {io_out_s_hi_45, io_out_s_lo_39}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_40 = {_io_out_s_T_387, 7'h7}; // @[RVC.scala:33:13, :117:25] wire [13:0] io_out_s_hi_hi_34 = {_io_out_s_T_386, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_46 = {io_out_s_hi_hi_34, 3'h3}; // @[RVC.scala:117:25] wire [28:0] _io_out_s_T_388 = {io_out_s_hi_46, io_out_s_lo_40}; // @[RVC.scala:117:25] wire [4:0] io_out_s_17_rd = _io_out_s_T_389; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_17_rs2 = _io_out_s_T_390; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_17_rs3 = _io_out_s_T_391; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_17_bits; // @[RVC.scala:21:19] assign io_out_s_17_bits = {3'h0, _io_out_s_T_388}; // @[RVC.scala:21:19, :22:14, :117:25] wire [1:0] _io_out_s_T_392 = io_in_0[3:2]; // @[RVC.scala:37:22, :190:7] wire [2:0] _io_out_s_T_394 = io_in_0[6:4]; // @[RVC.scala:37:37, :190:7] wire [4:0] io_out_s_lo_41 = {_io_out_s_T_394, 2'h0}; // @[RVC.scala:37:{20,37}] wire [2:0] io_out_s_hi_47 = {_io_out_s_T_392, _io_out_s_T_393}; // @[RVC.scala:37:{20,22,30}] wire [7:0] _io_out_s_T_395 = {io_out_s_hi_47, io_out_s_lo_41}; // @[RVC.scala:37:20] wire [11:0] io_out_s_lo_42 = {_io_out_s_T_396, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :116:24] wire [12:0] io_out_s_hi_hi_35 = {_io_out_s_T_395, 5'h2}; // @[package.scala:39:86] wire [15:0] io_out_s_hi_48 = {io_out_s_hi_hi_35, 3'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_397 = {io_out_s_hi_48, io_out_s_lo_42}; // @[RVC.scala:116:24] wire [4:0] io_out_s_18_rd = _io_out_s_T_398; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_18_rs2 = _io_out_s_T_399; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_18_rs3 = _io_out_s_T_400; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_18_bits; // @[RVC.scala:21:19] assign io_out_s_18_bits = {4'h0, _io_out_s_T_397}; // @[RVC.scala:21:19, :22:14, :116:24] wire [4:0] io_out_s_lo_43 = {_io_out_s_T_403, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_49 = {_io_out_s_T_401, _io_out_s_T_402}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_404 = {io_out_s_hi_49, io_out_s_lo_43}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_44 = {_io_out_s_T_405, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :115:24] wire [13:0] io_out_s_hi_hi_36 = {_io_out_s_T_404, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_50 = {io_out_s_hi_hi_36, 3'h3}; // @[RVC.scala:115:24] wire [28:0] _io_out_s_T_406 = {io_out_s_hi_50, io_out_s_lo_44}; // @[RVC.scala:115:24] wire [4:0] io_out_s_19_rd = _io_out_s_T_407; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_19_rs2 = _io_out_s_T_408; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_19_rs3 = _io_out_s_T_409; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_19_bits; // @[RVC.scala:21:19] assign io_out_s_19_bits = {3'h0, _io_out_s_T_406}; // @[RVC.scala:21:19, :22:14, :115:24] wire [11:0] io_out_s_mv_lo = {_io_out_s_mv_T_1, 7'h33}; // @[RVC.scala:33:13, :132:22] wire [9:0] io_out_s_mv_hi_hi = {_io_out_s_mv_T, 5'h0}; // @[RVC.scala:32:14, :132:22] wire [12:0] io_out_s_mv_hi = {io_out_s_mv_hi_hi, 3'h0}; // @[RVC.scala:132:22] wire [24:0] _io_out_s_mv_T_2 = {io_out_s_mv_hi, io_out_s_mv_lo}; // @[RVC.scala:132:22] wire [4:0] io_out_s_mv_rd = _io_out_s_mv_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_mv_rs2 = _io_out_s_mv_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_mv_rs3 = _io_out_s_mv_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_mv_bits; // @[RVC.scala:21:19] assign io_out_s_mv_bits = {7'h0, _io_out_s_mv_T_2}; // @[RVC.scala:21:19, :22:14, :132:22] wire [11:0] io_out_s_add_lo = {_io_out_s_add_T_2, 7'h33}; // @[RVC.scala:33:13, :134:25] wire [9:0] io_out_s_add_hi_hi = {_io_out_s_add_T, _io_out_s_add_T_1}; // @[RVC.scala:32:14, :33:13, :134:25] wire [12:0] io_out_s_add_hi = {io_out_s_add_hi_hi, 3'h0}; // @[RVC.scala:134:25] wire [24:0] _io_out_s_add_T_3 = {io_out_s_add_hi, io_out_s_add_lo}; // @[RVC.scala:134:25] wire [4:0] io_out_s_add_rd = _io_out_s_add_T_4; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs1 = _io_out_s_add_T_5; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs2 = _io_out_s_add_T_6; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_add_rs3 = _io_out_s_add_T_7; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_add_bits; // @[RVC.scala:21:19] assign io_out_s_add_bits = {7'h0, _io_out_s_add_T_3}; // @[RVC.scala:21:19, :22:14, :134:25] wire [9:0] io_out_s_jr_hi_hi = {_io_out_s_jr_T, _io_out_s_jr_T_1}; // @[RVC.scala:32:14, :33:13, :135:19] wire [12:0] io_out_s_jr_hi = {io_out_s_jr_hi_hi, 3'h0}; // @[RVC.scala:135:19] wire [24:0] io_out_s_jr = {io_out_s_jr_hi, 12'h67}; // @[RVC.scala:135:19] wire [17:0] _io_out_s_reserved_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29] wire [17:0] _io_out_s_ebreak_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29, :140:27] wire [24:0] io_out_s_reserved = {_io_out_s_reserved_T, 7'h1F}; // @[RVC.scala:136:{25,29}] wire _io_out_s_jr_reserved_T_1 = |_io_out_s_jr_reserved_T; // @[RVC.scala:33:13, :137:37] wire [24:0] _io_out_s_jr_reserved_T_2 = _io_out_s_jr_reserved_T_1 ? io_out_s_jr : io_out_s_reserved; // @[RVC.scala:135:19, :136:25, :137:{33,37}] wire [4:0] io_out_s_jr_reserved_rs1 = _io_out_s_jr_reserved_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jr_reserved_rs2 = _io_out_s_jr_reserved_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jr_reserved_rs3 = _io_out_s_jr_reserved_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jr_reserved_bits; // @[RVC.scala:21:19] assign io_out_s_jr_reserved_bits = {7'h0, _io_out_s_jr_reserved_T_2}; // @[RVC.scala:21:19, :22:14, :137:33] wire _io_out_s_jr_mv_T_1 = |_io_out_s_jr_mv_T; // @[RVC.scala:32:14, :138:27] wire [31:0] io_out_s_jr_mv_bits = _io_out_s_jr_mv_T_1 ? io_out_s_mv_bits : io_out_s_jr_reserved_bits; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rd = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rd : 5'h0; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs1 = _io_out_s_jr_mv_T_1 ? 5'h0 : io_out_s_jr_reserved_rs1; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs2 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs2 : io_out_s_jr_reserved_rs2; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs3 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs3 : io_out_s_jr_reserved_rs3; // @[RVC.scala:21:19, :138:{22,27}] wire [9:0] io_out_s_jalr_hi_hi = {_io_out_s_jalr_T, _io_out_s_jalr_T_1}; // @[RVC.scala:32:14, :33:13, :139:21] wire [12:0] io_out_s_jalr_hi = {io_out_s_jalr_hi_hi, 3'h0}; // @[RVC.scala:139:21] wire [24:0] io_out_s_jalr = {io_out_s_jalr_hi, 12'hE7}; // @[RVC.scala:139:21] wire [24:0] _io_out_s_ebreak_T_1 = {_io_out_s_ebreak_T, 7'h73}; // @[RVC.scala:140:{23,27}] wire [24:0] io_out_s_ebreak = {_io_out_s_ebreak_T_1[24:21], _io_out_s_ebreak_T_1[20:0] | 21'h100000}; // @[RVC.scala:140:{23,46}] wire _io_out_s_jalr_ebreak_T_1 = |_io_out_s_jalr_ebreak_T; // @[RVC.scala:33:13, :141:37] wire [24:0] _io_out_s_jalr_ebreak_T_2 = _io_out_s_jalr_ebreak_T_1 ? io_out_s_jalr : io_out_s_ebreak; // @[RVC.scala:139:21, :140:46, :141:{33,37}] wire [4:0] io_out_s_jalr_ebreak_rs1 = _io_out_s_jalr_ebreak_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jalr_ebreak_rs2 = _io_out_s_jalr_ebreak_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jalr_ebreak_rs3 = _io_out_s_jalr_ebreak_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19] assign io_out_s_jalr_ebreak_bits = {7'h0, _io_out_s_jalr_ebreak_T_2}; // @[RVC.scala:21:19, :22:14, :141:33] wire _io_out_s_jalr_add_T_1 = |_io_out_s_jalr_add_T; // @[RVC.scala:32:14, :142:30] wire [31:0] io_out_s_jalr_add_bits = _io_out_s_jalr_add_T_1 ? io_out_s_add_bits : io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rd = _io_out_s_jalr_add_T_1 ? io_out_s_add_rd : 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_jalr_add_rs1 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs1 : io_out_s_jalr_ebreak_rs1; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs2 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs2 : io_out_s_jalr_ebreak_rs2; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs3 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs3 : io_out_s_jalr_ebreak_rs3; // @[RVC.scala:21:19, :142:{25,30}] wire [31:0] io_out_s_20_bits = _io_out_s_T_410 ? io_out_s_jalr_add_bits : io_out_s_jr_mv_bits; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rd = _io_out_s_T_410 ? io_out_s_jalr_add_rd : io_out_s_jr_mv_rd; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs1 = _io_out_s_T_410 ? io_out_s_jalr_add_rs1 : io_out_s_jr_mv_rs1; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs2 = _io_out_s_T_410 ? io_out_s_jalr_add_rs2 : io_out_s_jr_mv_rs2; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs3 = _io_out_s_T_410 ? io_out_s_jalr_add_rs3 : io_out_s_jr_mv_rs3; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [5:0] io_out_s_hi_51 = {_io_out_s_T_411, _io_out_s_T_412}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_413 = {io_out_s_hi_51, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_414 = _io_out_s_T_413[8:5]; // @[RVC.scala:40:20, :124:34] wire [5:0] io_out_s_hi_52 = {_io_out_s_T_416, _io_out_s_T_417}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_418 = {io_out_s_hi_52, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_419 = _io_out_s_T_418[4:0]; // @[RVC.scala:40:20, :124:66] wire [7:0] io_out_s_lo_hi_20 = {3'h3, _io_out_s_T_419}; // @[RVC.scala:124:{25,66}] wire [14:0] io_out_s_lo_45 = {io_out_s_lo_hi_20, 7'h27}; // @[RVC.scala:124:25] wire [8:0] io_out_s_hi_hi_37 = {_io_out_s_T_414, _io_out_s_T_415}; // @[RVC.scala:32:14, :124:{25,34}] wire [13:0] io_out_s_hi_53 = {io_out_s_hi_hi_37, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_420 = {io_out_s_hi_53, io_out_s_lo_45}; // @[RVC.scala:124:25] wire [4:0] io_out_s_21_rd = _io_out_s_T_421; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_21_rs2 = _io_out_s_T_422; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_21_rs3 = _io_out_s_T_423; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_21_bits; // @[RVC.scala:21:19] assign io_out_s_21_bits = {3'h0, _io_out_s_T_420}; // @[RVC.scala:21:19, :22:14, :124:25] wire [1:0] _io_out_s_T_424 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [1:0] _io_out_s_T_429 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [3:0] _io_out_s_T_425 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [3:0] _io_out_s_T_430 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [5:0] io_out_s_hi_54 = {_io_out_s_T_424, _io_out_s_T_425}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_426 = {io_out_s_hi_54, 2'h0}; // @[RVC.scala:39:20] wire [2:0] _io_out_s_T_427 = _io_out_s_T_426[7:5]; // @[RVC.scala:39:20, :123:33] wire [5:0] io_out_s_hi_55 = {_io_out_s_T_429, _io_out_s_T_430}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_431 = {io_out_s_hi_55, 2'h0}; // @[RVC.scala:39:20] wire [4:0] _io_out_s_T_432 = _io_out_s_T_431[4:0]; // @[RVC.scala:39:20, :123:65] wire [7:0] io_out_s_lo_hi_21 = {3'h2, _io_out_s_T_432}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_46 = {io_out_s_lo_hi_21, 7'h23}; // @[RVC.scala:123:24] wire [7:0] io_out_s_hi_hi_38 = {_io_out_s_T_427, _io_out_s_T_428}; // @[RVC.scala:32:14, :123:{24,33}] wire [12:0] io_out_s_hi_56 = {io_out_s_hi_hi_38, 5'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_433 = {io_out_s_hi_56, io_out_s_lo_46}; // @[RVC.scala:123:24] wire [4:0] io_out_s_22_rd = _io_out_s_T_434; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_22_rs2 = _io_out_s_T_435; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_22_rs3 = _io_out_s_T_436; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_22_bits; // @[RVC.scala:21:19] assign io_out_s_22_bits = {4'h0, _io_out_s_T_433}; // @[RVC.scala:21:19, :22:14, :123:24] wire [5:0] io_out_s_hi_57 = {_io_out_s_T_437, _io_out_s_T_438}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_439 = {io_out_s_hi_57, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_440 = _io_out_s_T_439[8:5]; // @[RVC.scala:40:20, :122:33] wire [5:0] io_out_s_hi_58 = {_io_out_s_T_442, _io_out_s_T_443}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_444 = {io_out_s_hi_58, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_445 = _io_out_s_T_444[4:0]; // @[RVC.scala:40:20, :122:65] wire [7:0] io_out_s_lo_hi_22 = {3'h3, _io_out_s_T_445}; // @[RVC.scala:122:{24,65}] wire [14:0] io_out_s_lo_47 = {io_out_s_lo_hi_22, 7'h23}; // @[RVC.scala:122:24] wire [8:0] io_out_s_hi_hi_39 = {_io_out_s_T_440, _io_out_s_T_441}; // @[RVC.scala:32:14, :122:{24,33}] wire [13:0] io_out_s_hi_59 = {io_out_s_hi_hi_39, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_446 = {io_out_s_hi_59, io_out_s_lo_47}; // @[RVC.scala:122:24] wire [4:0] io_out_s_23_rd = _io_out_s_T_447; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_23_rs2 = _io_out_s_T_448; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_23_rs3 = _io_out_s_T_449; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_23_bits; // @[RVC.scala:21:19] assign io_out_s_23_bits = {3'h0, _io_out_s_T_446}; // @[RVC.scala:21:19, :22:14, :122:24] wire [4:0] io_out_s_24_rd = _io_out_s_T_450; // @[RVC.scala:20:36, :21:19] wire [4:0] _io_out_s_T_451 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_455 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_459 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_463 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_467 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_471 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_475 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_479 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] io_out_s_24_rs1 = _io_out_s_T_451; // @[RVC.scala:20:57, :21:19] wire [4:0] _io_out_s_T_452 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_456 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_460 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_464 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_468 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_472 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_476 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_480 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] io_out_s_24_rs2 = _io_out_s_T_452; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_24_rs3 = _io_out_s_T_453; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_25_rd = _io_out_s_T_454; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_25_rs1 = _io_out_s_T_455; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_25_rs2 = _io_out_s_T_456; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_25_rs3 = _io_out_s_T_457; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_26_rd = _io_out_s_T_458; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_26_rs1 = _io_out_s_T_459; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_26_rs2 = _io_out_s_T_460; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_26_rs3 = _io_out_s_T_461; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_27_rd = _io_out_s_T_462; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_27_rs1 = _io_out_s_T_463; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_27_rs2 = _io_out_s_T_464; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_27_rs3 = _io_out_s_T_465; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_28_rd = _io_out_s_T_466; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_28_rs1 = _io_out_s_T_467; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_28_rs2 = _io_out_s_T_468; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_28_rs3 = _io_out_s_T_469; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_29_rd = _io_out_s_T_470; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_29_rs1 = _io_out_s_T_471; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_29_rs2 = _io_out_s_T_472; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_29_rs3 = _io_out_s_T_473; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_30_rd = _io_out_s_T_474; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_30_rs1 = _io_out_s_T_475; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_30_rs2 = _io_out_s_T_476; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_30_rs3 = _io_out_s_T_477; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_31_rd = _io_out_s_T_478; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_31_rs1 = _io_out_s_T_479; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_31_rs2 = _io_out_s_T_480; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_31_rs3 = _io_out_s_T_481; // @[RVC.scala:20:101, :21:19] wire [2:0] _io_out_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :190:7] wire [2:0] _io_ill_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :186:20, :190:7] wire [4:0] _io_out_T_2 = {_io_out_T, _io_out_T_1}; // @[RVC.scala:154:{10,12,20}] wire _io_out_T_3 = _io_out_T_2 == 5'h1; // @[package.scala:39:86] wire [31:0] _io_out_T_4_bits = _io_out_T_3 ? io_out_s_1_bits : io_out_s_0_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rd = _io_out_T_3 ? io_out_s_1_rd : io_out_s_0_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs1 = _io_out_T_3 ? io_out_s_1_rs1 : 5'h2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs2 = _io_out_T_3 ? io_out_s_1_rs2 : io_out_s_0_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs3 = _io_out_T_3 ? io_out_s_1_rs3 : io_out_s_0_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_5 = _io_out_T_2 == 5'h2; // @[package.scala:39:86] wire [31:0] _io_out_T_6_bits = _io_out_T_5 ? io_out_s_2_bits : _io_out_T_4_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rd = _io_out_T_5 ? io_out_s_2_rd : _io_out_T_4_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs1 = _io_out_T_5 ? io_out_s_2_rs1 : _io_out_T_4_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs2 = _io_out_T_5 ? io_out_s_2_rs2 : _io_out_T_4_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs3 = _io_out_T_5 ? io_out_s_2_rs3 : _io_out_T_4_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_7 = _io_out_T_2 == 5'h3; // @[package.scala:39:86] wire [31:0] _io_out_T_8_bits = _io_out_T_7 ? io_out_s_3_bits : _io_out_T_6_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rd = _io_out_T_7 ? io_out_s_3_rd : _io_out_T_6_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs1 = _io_out_T_7 ? io_out_s_3_rs1 : _io_out_T_6_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs2 = _io_out_T_7 ? io_out_s_3_rs2 : _io_out_T_6_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs3 = _io_out_T_7 ? io_out_s_3_rs3 : _io_out_T_6_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_9 = _io_out_T_2 == 5'h4; // @[package.scala:39:86] wire [31:0] _io_out_T_10_bits = _io_out_T_9 ? io_out_s_4_bits : _io_out_T_8_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rd = _io_out_T_9 ? io_out_s_4_rd : _io_out_T_8_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs1 = _io_out_T_9 ? io_out_s_4_rs1 : _io_out_T_8_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs2 = _io_out_T_9 ? io_out_s_4_rs2 : _io_out_T_8_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs3 = _io_out_T_9 ? io_out_s_4_rs3 : _io_out_T_8_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_11 = _io_out_T_2 == 5'h5; // @[package.scala:39:86] wire [31:0] _io_out_T_12_bits = _io_out_T_11 ? io_out_s_5_bits : _io_out_T_10_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rd = _io_out_T_11 ? io_out_s_5_rd : _io_out_T_10_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs1 = _io_out_T_11 ? io_out_s_5_rs1 : _io_out_T_10_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs2 = _io_out_T_11 ? io_out_s_5_rs2 : _io_out_T_10_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs3 = _io_out_T_11 ? io_out_s_5_rs3 : _io_out_T_10_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_13 = _io_out_T_2 == 5'h6; // @[package.scala:39:86] wire [31:0] _io_out_T_14_bits = _io_out_T_13 ? io_out_s_6_bits : _io_out_T_12_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rd = _io_out_T_13 ? io_out_s_6_rd : _io_out_T_12_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs1 = _io_out_T_13 ? io_out_s_6_rs1 : _io_out_T_12_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs2 = _io_out_T_13 ? io_out_s_6_rs2 : _io_out_T_12_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs3 = _io_out_T_13 ? io_out_s_6_rs3 : _io_out_T_12_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_15 = _io_out_T_2 == 5'h7; // @[package.scala:39:86] wire [31:0] _io_out_T_16_bits = _io_out_T_15 ? io_out_s_7_bits : _io_out_T_14_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rd = _io_out_T_15 ? io_out_s_7_rd : _io_out_T_14_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs1 = _io_out_T_15 ? io_out_s_7_rs1 : _io_out_T_14_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs2 = _io_out_T_15 ? io_out_s_7_rs2 : _io_out_T_14_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs3 = _io_out_T_15 ? io_out_s_7_rs3 : _io_out_T_14_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_17 = _io_out_T_2 == 5'h8; // @[package.scala:39:86] wire [31:0] _io_out_T_18_bits = _io_out_T_17 ? io_out_s_8_bits : _io_out_T_16_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rd = _io_out_T_17 ? io_out_s_8_rd : _io_out_T_16_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs1 = _io_out_T_17 ? io_out_s_8_rs1 : _io_out_T_16_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs2 = _io_out_T_17 ? io_out_s_8_rs2 : _io_out_T_16_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs3 = _io_out_T_17 ? io_out_s_8_rs3 : _io_out_T_16_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_19 = _io_out_T_2 == 5'h9; // @[package.scala:39:86] wire [31:0] _io_out_T_20_bits = _io_out_T_19 ? io_out_s_9_bits : _io_out_T_18_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rd = _io_out_T_19 ? io_out_s_9_rd : _io_out_T_18_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs1 = _io_out_T_19 ? io_out_s_9_rs1 : _io_out_T_18_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs2 = _io_out_T_19 ? io_out_s_9_rs2 : _io_out_T_18_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs3 = _io_out_T_19 ? io_out_s_9_rs3 : _io_out_T_18_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_21 = _io_out_T_2 == 5'hA; // @[package.scala:39:86] wire [31:0] _io_out_T_22_bits = _io_out_T_21 ? io_out_s_10_bits : _io_out_T_20_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rd = _io_out_T_21 ? io_out_s_10_rd : _io_out_T_20_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs1 = _io_out_T_21 ? 5'h0 : _io_out_T_20_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs2 = _io_out_T_21 ? io_out_s_10_rs2 : _io_out_T_20_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs3 = _io_out_T_21 ? io_out_s_10_rs3 : _io_out_T_20_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_23 = _io_out_T_2 == 5'hB; // @[package.scala:39:86] wire [31:0] _io_out_T_24_bits = _io_out_T_23 ? io_out_s_11_bits : _io_out_T_22_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rd = _io_out_T_23 ? io_out_s_11_rd : _io_out_T_22_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs1 = _io_out_T_23 ? io_out_s_11_rs1 : _io_out_T_22_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs2 = _io_out_T_23 ? io_out_s_11_rs2 : _io_out_T_22_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs3 = _io_out_T_23 ? io_out_s_11_rs3 : _io_out_T_22_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_25 = _io_out_T_2 == 5'hC; // @[package.scala:39:86] wire [31:0] _io_out_T_26_bits = _io_out_T_25 ? io_out_s_12_bits : _io_out_T_24_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rd = _io_out_T_25 ? io_out_s_12_rd : _io_out_T_24_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs1 = _io_out_T_25 ? io_out_s_12_rs1 : _io_out_T_24_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs2 = _io_out_T_25 ? io_out_s_12_rs2 : _io_out_T_24_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs3 = _io_out_T_25 ? io_out_s_12_rs3 : _io_out_T_24_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_27 = _io_out_T_2 == 5'hD; // @[package.scala:39:86] wire [31:0] _io_out_T_28_bits = _io_out_T_27 ? io_out_s_13_bits : _io_out_T_26_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rd = _io_out_T_27 ? 5'h0 : _io_out_T_26_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs1 = _io_out_T_27 ? io_out_s_13_rs1 : _io_out_T_26_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs2 = _io_out_T_27 ? io_out_s_13_rs2 : _io_out_T_26_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs3 = _io_out_T_27 ? io_out_s_13_rs3 : _io_out_T_26_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_29 = _io_out_T_2 == 5'hE; // @[package.scala:39:86] wire [31:0] _io_out_T_30_bits = _io_out_T_29 ? io_out_s_14_bits : _io_out_T_28_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rd = _io_out_T_29 ? io_out_s_14_rd : _io_out_T_28_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs1 = _io_out_T_29 ? io_out_s_14_rs1 : _io_out_T_28_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs2 = _io_out_T_29 ? 5'h0 : _io_out_T_28_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs3 = _io_out_T_29 ? io_out_s_14_rs3 : _io_out_T_28_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_31 = _io_out_T_2 == 5'hF; // @[package.scala:39:86] wire [31:0] _io_out_T_32_bits = _io_out_T_31 ? io_out_s_15_bits : _io_out_T_30_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rd = _io_out_T_31 ? 5'h0 : _io_out_T_30_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs1 = _io_out_T_31 ? io_out_s_15_rs1 : _io_out_T_30_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs2 = _io_out_T_31 ? 5'h0 : _io_out_T_30_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs3 = _io_out_T_31 ? io_out_s_15_rs3 : _io_out_T_30_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_33 = _io_out_T_2 == 5'h10; // @[package.scala:39:86] wire [31:0] _io_out_T_34_bits = _io_out_T_33 ? io_out_s_16_bits : _io_out_T_32_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rd = _io_out_T_33 ? io_out_s_16_rd : _io_out_T_32_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs1 = _io_out_T_33 ? io_out_s_16_rs1 : _io_out_T_32_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs2 = _io_out_T_33 ? io_out_s_16_rs2 : _io_out_T_32_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs3 = _io_out_T_33 ? io_out_s_16_rs3 : _io_out_T_32_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_35 = _io_out_T_2 == 5'h11; // @[package.scala:39:86] wire [31:0] _io_out_T_36_bits = _io_out_T_35 ? io_out_s_17_bits : _io_out_T_34_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rd = _io_out_T_35 ? io_out_s_17_rd : _io_out_T_34_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs1 = _io_out_T_35 ? 5'h2 : _io_out_T_34_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs2 = _io_out_T_35 ? io_out_s_17_rs2 : _io_out_T_34_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs3 = _io_out_T_35 ? io_out_s_17_rs3 : _io_out_T_34_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_37 = _io_out_T_2 == 5'h12; // @[package.scala:39:86] wire [31:0] _io_out_T_38_bits = _io_out_T_37 ? io_out_s_18_bits : _io_out_T_36_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rd = _io_out_T_37 ? io_out_s_18_rd : _io_out_T_36_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs1 = _io_out_T_37 ? 5'h2 : _io_out_T_36_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs2 = _io_out_T_37 ? io_out_s_18_rs2 : _io_out_T_36_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs3 = _io_out_T_37 ? io_out_s_18_rs3 : _io_out_T_36_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_39 = _io_out_T_2 == 5'h13; // @[package.scala:39:86] wire [31:0] _io_out_T_40_bits = _io_out_T_39 ? io_out_s_19_bits : _io_out_T_38_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rd = _io_out_T_39 ? io_out_s_19_rd : _io_out_T_38_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs1 = _io_out_T_39 ? 5'h2 : _io_out_T_38_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs2 = _io_out_T_39 ? io_out_s_19_rs2 : _io_out_T_38_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs3 = _io_out_T_39 ? io_out_s_19_rs3 : _io_out_T_38_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_41 = _io_out_T_2 == 5'h14; // @[package.scala:39:86] wire [31:0] _io_out_T_42_bits = _io_out_T_41 ? io_out_s_20_bits : _io_out_T_40_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rd = _io_out_T_41 ? io_out_s_20_rd : _io_out_T_40_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs1 = _io_out_T_41 ? io_out_s_20_rs1 : _io_out_T_40_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs2 = _io_out_T_41 ? io_out_s_20_rs2 : _io_out_T_40_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs3 = _io_out_T_41 ? io_out_s_20_rs3 : _io_out_T_40_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_43 = _io_out_T_2 == 5'h15; // @[package.scala:39:86] wire [31:0] _io_out_T_44_bits = _io_out_T_43 ? io_out_s_21_bits : _io_out_T_42_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rd = _io_out_T_43 ? io_out_s_21_rd : _io_out_T_42_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs1 = _io_out_T_43 ? 5'h2 : _io_out_T_42_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs2 = _io_out_T_43 ? io_out_s_21_rs2 : _io_out_T_42_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs3 = _io_out_T_43 ? io_out_s_21_rs3 : _io_out_T_42_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_45 = _io_out_T_2 == 5'h16; // @[package.scala:39:86] wire [31:0] _io_out_T_46_bits = _io_out_T_45 ? io_out_s_22_bits : _io_out_T_44_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rd = _io_out_T_45 ? io_out_s_22_rd : _io_out_T_44_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs1 = _io_out_T_45 ? 5'h2 : _io_out_T_44_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs2 = _io_out_T_45 ? io_out_s_22_rs2 : _io_out_T_44_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs3 = _io_out_T_45 ? io_out_s_22_rs3 : _io_out_T_44_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_47 = _io_out_T_2 == 5'h17; // @[package.scala:39:86] wire [31:0] _io_out_T_48_bits = _io_out_T_47 ? io_out_s_23_bits : _io_out_T_46_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rd = _io_out_T_47 ? io_out_s_23_rd : _io_out_T_46_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs1 = _io_out_T_47 ? 5'h2 : _io_out_T_46_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs2 = _io_out_T_47 ? io_out_s_23_rs2 : _io_out_T_46_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs3 = _io_out_T_47 ? io_out_s_23_rs3 : _io_out_T_46_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_49 = _io_out_T_2 == 5'h18; // @[package.scala:39:86] wire [31:0] _io_out_T_50_bits = _io_out_T_49 ? io_out_s_24_bits : _io_out_T_48_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rd = _io_out_T_49 ? io_out_s_24_rd : _io_out_T_48_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs1 = _io_out_T_49 ? io_out_s_24_rs1 : _io_out_T_48_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs2 = _io_out_T_49 ? io_out_s_24_rs2 : _io_out_T_48_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs3 = _io_out_T_49 ? io_out_s_24_rs3 : _io_out_T_48_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_51 = _io_out_T_2 == 5'h19; // @[package.scala:39:86] wire [31:0] _io_out_T_52_bits = _io_out_T_51 ? io_out_s_25_bits : _io_out_T_50_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rd = _io_out_T_51 ? io_out_s_25_rd : _io_out_T_50_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs1 = _io_out_T_51 ? io_out_s_25_rs1 : _io_out_T_50_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs2 = _io_out_T_51 ? io_out_s_25_rs2 : _io_out_T_50_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs3 = _io_out_T_51 ? io_out_s_25_rs3 : _io_out_T_50_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_53 = _io_out_T_2 == 5'h1A; // @[package.scala:39:86] wire [31:0] _io_out_T_54_bits = _io_out_T_53 ? io_out_s_26_bits : _io_out_T_52_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rd = _io_out_T_53 ? io_out_s_26_rd : _io_out_T_52_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs1 = _io_out_T_53 ? io_out_s_26_rs1 : _io_out_T_52_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs2 = _io_out_T_53 ? io_out_s_26_rs2 : _io_out_T_52_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs3 = _io_out_T_53 ? io_out_s_26_rs3 : _io_out_T_52_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_55 = _io_out_T_2 == 5'h1B; // @[package.scala:39:86] wire [31:0] _io_out_T_56_bits = _io_out_T_55 ? io_out_s_27_bits : _io_out_T_54_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rd = _io_out_T_55 ? io_out_s_27_rd : _io_out_T_54_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs1 = _io_out_T_55 ? io_out_s_27_rs1 : _io_out_T_54_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs2 = _io_out_T_55 ? io_out_s_27_rs2 : _io_out_T_54_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs3 = _io_out_T_55 ? io_out_s_27_rs3 : _io_out_T_54_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_57 = _io_out_T_2 == 5'h1C; // @[package.scala:39:86] wire [31:0] _io_out_T_58_bits = _io_out_T_57 ? io_out_s_28_bits : _io_out_T_56_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rd = _io_out_T_57 ? io_out_s_28_rd : _io_out_T_56_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs1 = _io_out_T_57 ? io_out_s_28_rs1 : _io_out_T_56_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs2 = _io_out_T_57 ? io_out_s_28_rs2 : _io_out_T_56_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs3 = _io_out_T_57 ? io_out_s_28_rs3 : _io_out_T_56_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_59 = _io_out_T_2 == 5'h1D; // @[package.scala:39:86] wire [31:0] _io_out_T_60_bits = _io_out_T_59 ? io_out_s_29_bits : _io_out_T_58_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rd = _io_out_T_59 ? io_out_s_29_rd : _io_out_T_58_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs1 = _io_out_T_59 ? io_out_s_29_rs1 : _io_out_T_58_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs2 = _io_out_T_59 ? io_out_s_29_rs2 : _io_out_T_58_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs3 = _io_out_T_59 ? io_out_s_29_rs3 : _io_out_T_58_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_61 = _io_out_T_2 == 5'h1E; // @[package.scala:39:86] wire [31:0] _io_out_T_62_bits = _io_out_T_61 ? io_out_s_30_bits : _io_out_T_60_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rd = _io_out_T_61 ? io_out_s_30_rd : _io_out_T_60_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs1 = _io_out_T_61 ? io_out_s_30_rs1 : _io_out_T_60_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs2 = _io_out_T_61 ? io_out_s_30_rs2 : _io_out_T_60_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs3 = _io_out_T_61 ? io_out_s_30_rs3 : _io_out_T_60_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_63 = &_io_out_T_2; // @[package.scala:39:86] assign _io_out_T_64_bits = _io_out_T_63 ? io_out_s_31_bits : _io_out_T_62_bits; // @[package.scala:39:{76,86}] assign _io_out_T_64_rd = _io_out_T_63 ? io_out_s_31_rd : _io_out_T_62_rd; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs1 = _io_out_T_63 ? io_out_s_31_rs1 : _io_out_T_62_rs1; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs2 = _io_out_T_63 ? io_out_s_31_rs2 : _io_out_T_62_rs2; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs3 = _io_out_T_63 ? io_out_s_31_rs3 : _io_out_T_62_rs3; // @[package.scala:39:{76,86}] assign io_out_bits_0 = _io_out_T_64_bits; // @[package.scala:39:76] assign io_out_rd = _io_out_T_64_rd; // @[package.scala:39:76] assign io_out_rs1 = _io_out_T_64_rs1; // @[package.scala:39:76] assign io_out_rs2 = _io_out_T_64_rs2; // @[package.scala:39:76] assign io_out_rs3 = _io_out_T_64_rs3; // @[package.scala:39:76] wire [10:0] _io_ill_s_T = io_in_0[12:2]; // @[RVC.scala:158:19, :190:7] wire [10:0] _io_ill_s_T_13 = io_in_0[12:2]; // @[RVC.scala:158:19, :177:21, :190:7] wire _io_ill_s_T_1 = |_io_ill_s_T; // @[RVC.scala:158:{19,27}] wire io_ill_s_0 = ~_io_ill_s_T_1; // @[RVC.scala:158:{16,27}] wire io_ill_s_9 = _io_ill_s_T_2 == 5'h0; // @[RVC.scala:33:13, :167:47] wire _io_ill_s_T_5 = |_io_ill_s_T_4; // @[RVC.scala:168:{27,34}] wire _io_ill_s_T_6 = _io_ill_s_T_3 | _io_ill_s_T_5; // @[RVC.scala:168:{19,24,34}] wire io_ill_s_11 = ~_io_ill_s_T_6; // @[RVC.scala:168:{16,24}] wire _io_ill_s_T_8 = &_io_ill_s_T_7; // @[RVC.scala:169:{22,31}] wire _io_ill_s_T_10 = _io_ill_s_T_9; // @[RVC.scala:169:{69,73}] wire io_ill_s_12 = _io_ill_s_T_8 & _io_ill_s_T_10; // @[RVC.scala:169:{31,36,73}] wire io_ill_s_18 = _io_ill_s_T_11 == 5'h0; // @[RVC.scala:33:13, :175:18] wire io_ill_s_19 = _io_ill_s_T_12 == 5'h0; // @[RVC.scala:33:13, :175:18] wire _io_ill_s_T_14 = |_io_ill_s_T_13; // @[RVC.scala:177:{21,29}] wire io_ill_s_20 = ~_io_ill_s_T_14; // @[RVC.scala:177:{18,29}] wire [4:0] _io_ill_T_2 = {_io_ill_T, _io_ill_T_1}; // @[RVC.scala:186:{10,12,20}] wire _io_ill_T_3 = _io_ill_T_2 == 5'h1; // @[package.scala:39:86] wire _io_ill_T_4 = ~_io_ill_T_3 & io_ill_s_0; // @[package.scala:39:{76,86}] wire _io_ill_T_5 = _io_ill_T_2 == 5'h2; // @[package.scala:39:86] wire _io_ill_T_6 = ~_io_ill_T_5 & _io_ill_T_4; // @[package.scala:39:{76,86}] wire _io_ill_T_7 = _io_ill_T_2 == 5'h3; // @[package.scala:39:86] wire _io_ill_T_8 = ~_io_ill_T_7 & _io_ill_T_6; // @[package.scala:39:{76,86}] wire _io_ill_T_9 = _io_ill_T_2 == 5'h4; // @[package.scala:39:86] wire _io_ill_T_10 = _io_ill_T_9 | _io_ill_T_8; // @[package.scala:39:{76,86}] wire _io_ill_T_11 = _io_ill_T_2 == 5'h5; // @[package.scala:39:86] wire _io_ill_T_12 = ~_io_ill_T_11 & _io_ill_T_10; // @[package.scala:39:{76,86}] wire _io_ill_T_13 = _io_ill_T_2 == 5'h6; // @[package.scala:39:86] wire _io_ill_T_14 = ~_io_ill_T_13 & _io_ill_T_12; // @[package.scala:39:{76,86}] wire _io_ill_T_15 = _io_ill_T_2 == 5'h7; // @[package.scala:39:86] wire _io_ill_T_16 = ~_io_ill_T_15 & _io_ill_T_14; // @[package.scala:39:{76,86}] wire _io_ill_T_17 = _io_ill_T_2 == 5'h8; // @[package.scala:39:86] wire _io_ill_T_18 = ~_io_ill_T_17 & _io_ill_T_16; // @[package.scala:39:{76,86}] wire _io_ill_T_19 = _io_ill_T_2 == 5'h9; // @[package.scala:39:86] wire _io_ill_T_20 = _io_ill_T_19 ? io_ill_s_9 : _io_ill_T_18; // @[package.scala:39:{76,86}] wire _io_ill_T_21 = _io_ill_T_2 == 5'hA; // @[package.scala:39:86] wire _io_ill_T_22 = ~_io_ill_T_21 & _io_ill_T_20; // @[package.scala:39:{76,86}] wire _io_ill_T_23 = _io_ill_T_2 == 5'hB; // @[package.scala:39:86] wire _io_ill_T_24 = _io_ill_T_23 ? io_ill_s_11 : _io_ill_T_22; // @[package.scala:39:{76,86}] wire _io_ill_T_25 = _io_ill_T_2 == 5'hC; // @[package.scala:39:86] wire _io_ill_T_26 = _io_ill_T_25 ? io_ill_s_12 : _io_ill_T_24; // @[package.scala:39:{76,86}] wire _io_ill_T_27 = _io_ill_T_2 == 5'hD; // @[package.scala:39:86] wire _io_ill_T_28 = ~_io_ill_T_27 & _io_ill_T_26; // @[package.scala:39:{76,86}] wire _io_ill_T_29 = _io_ill_T_2 == 5'hE; // @[package.scala:39:86] wire _io_ill_T_30 = ~_io_ill_T_29 & _io_ill_T_28; // @[package.scala:39:{76,86}] wire _io_ill_T_31 = _io_ill_T_2 == 5'hF; // @[package.scala:39:86] wire _io_ill_T_32 = ~_io_ill_T_31 & _io_ill_T_30; // @[package.scala:39:{76,86}] wire _io_ill_T_33 = _io_ill_T_2 == 5'h10; // @[package.scala:39:86] wire _io_ill_T_34 = ~_io_ill_T_33 & _io_ill_T_32; // @[package.scala:39:{76,86}] wire _io_ill_T_35 = _io_ill_T_2 == 5'h11; // @[package.scala:39:86] wire _io_ill_T_36 = ~_io_ill_T_35 & _io_ill_T_34; // @[package.scala:39:{76,86}] wire _io_ill_T_37 = _io_ill_T_2 == 5'h12; // @[package.scala:39:86] wire _io_ill_T_38 = _io_ill_T_37 ? io_ill_s_18 : _io_ill_T_36; // @[package.scala:39:{76,86}] wire _io_ill_T_39 = _io_ill_T_2 == 5'h13; // @[package.scala:39:86] wire _io_ill_T_40 = _io_ill_T_39 ? io_ill_s_19 : _io_ill_T_38; // @[package.scala:39:{76,86}] wire _io_ill_T_41 = _io_ill_T_2 == 5'h14; // @[package.scala:39:86] wire _io_ill_T_42 = _io_ill_T_41 ? io_ill_s_20 : _io_ill_T_40; // @[package.scala:39:{76,86}] wire _io_ill_T_43 = _io_ill_T_2 == 5'h15; // @[package.scala:39:86] wire _io_ill_T_44 = ~_io_ill_T_43 & _io_ill_T_42; // @[package.scala:39:{76,86}] wire _io_ill_T_45 = _io_ill_T_2 == 5'h16; // @[package.scala:39:86] wire _io_ill_T_46 = ~_io_ill_T_45 & _io_ill_T_44; // @[package.scala:39:{76,86}] wire _io_ill_T_47 = _io_ill_T_2 == 5'h17; // @[package.scala:39:86] wire _io_ill_T_48 = ~_io_ill_T_47 & _io_ill_T_46; // @[package.scala:39:{76,86}] wire _io_ill_T_49 = _io_ill_T_2 == 5'h18; // @[package.scala:39:86] wire _io_ill_T_50 = ~_io_ill_T_49 & _io_ill_T_48; // @[package.scala:39:{76,86}] wire _io_ill_T_51 = _io_ill_T_2 == 5'h19; // @[package.scala:39:86] wire _io_ill_T_52 = ~_io_ill_T_51 & _io_ill_T_50; // @[package.scala:39:{76,86}] wire _io_ill_T_53 = _io_ill_T_2 == 5'h1A; // @[package.scala:39:86] wire _io_ill_T_54 = ~_io_ill_T_53 & _io_ill_T_52; // @[package.scala:39:{76,86}] wire _io_ill_T_55 = _io_ill_T_2 == 5'h1B; // @[package.scala:39:86] wire _io_ill_T_56 = ~_io_ill_T_55 & _io_ill_T_54; // @[package.scala:39:{76,86}] wire _io_ill_T_57 = _io_ill_T_2 == 5'h1C; // @[package.scala:39:86] wire _io_ill_T_58 = ~_io_ill_T_57 & _io_ill_T_56; // @[package.scala:39:{76,86}] wire _io_ill_T_59 = _io_ill_T_2 == 5'h1D; // @[package.scala:39:86] wire _io_ill_T_60 = ~_io_ill_T_59 & _io_ill_T_58; // @[package.scala:39:{76,86}] wire _io_ill_T_61 = _io_ill_T_2 == 5'h1E; // @[package.scala:39:86] wire _io_ill_T_62 = ~_io_ill_T_61 & _io_ill_T_60; // @[package.scala:39:{76,86}] wire _io_ill_T_63 = &_io_ill_T_2; // @[package.scala:39:86] assign _io_ill_T_64 = ~_io_ill_T_63 & _io_ill_T_62; // @[package.scala:39:{76,86}] assign io_ill = _io_ill_T_64; // @[package.scala:39:76] assign io_out_bits = io_out_bits_0; // @[RVC.scala:190:7] assign io_rvc = io_rvc_0; // @[RVC.scala:190:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a26d64s9k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_7 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a26d64s9k1z2u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a26d64s9k1z2u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<9>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<9>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<9>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<9>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_16 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_17 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBuffer_a26d64s9k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_7 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s9k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s9k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulDiv_7 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { fn : UInt<5>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, full_data : UInt<128>, tag : UInt<5>}}} regreset state : UInt<3>, clock, reset, UInt<3>(0h0) reg req : { fn : UInt<5>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock reg count : UInt<7>, clock reg neg_out : UInt<1>, clock reg isHi : UInt<1>, clock reg resHi : UInt<1>, clock reg divisor : UInt<65>, clock reg remainder : UInt<130>, clock wire decoded_plaInput : UInt<3> node decoded_invInputs = not(decoded_plaInput) wire decoded : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_3_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_4_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 2, 2) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 2, 2) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_1_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_plaInput, 2, 2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_4_2) node decoded_orMatrixOutputs_lo = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded, decoded_invMatrixOutputs connect decoded_plaInput, io.req.bits.fn node _T = bits(decoded, 3, 3) node _T_1 = bits(decoded, 2, 2) node _T_2 = bits(decoded, 1, 1) node _T_3 = bits(decoded, 0, 0) node cmdMul = bits(_T, 0, 0) node cmdHi = bits(_T_1, 0, 0) node lhsSigned = bits(_T_2, 0, 0) node rhsSigned = bits(_T_3, 0, 0) node _T_4 = eq(io.req.bits.dw, UInt<1>(0h0)) node _T_5 = and(UInt<1>(0h1), _T_4) node _sign_T = bits(io.req.bits.in1, 31, 31) node _sign_T_1 = bits(io.req.bits.in1, 63, 63) node _sign_T_2 = mux(_T_5, _sign_T, _sign_T_1) node lhs_sign = and(lhsSigned, _sign_T_2) node _hi_T = mux(lhs_sign, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hi_T_1 = bits(io.req.bits.in1, 63, 32) node hi = mux(_T_5, _hi_T, _hi_T_1) node _T_6 = bits(io.req.bits.in1, 31, 0) node lhs_in = cat(hi, _T_6) node _T_7 = eq(io.req.bits.dw, UInt<1>(0h0)) node _T_8 = and(UInt<1>(0h1), _T_7) node _sign_T_3 = bits(io.req.bits.in2, 31, 31) node _sign_T_4 = bits(io.req.bits.in2, 63, 63) node _sign_T_5 = mux(_T_8, _sign_T_3, _sign_T_4) node rhs_sign = and(rhsSigned, _sign_T_5) node _hi_T_2 = mux(rhs_sign, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hi_T_3 = bits(io.req.bits.in2, 63, 32) node hi_1 = mux(_T_8, _hi_T_2, _hi_T_3) node _T_9 = bits(io.req.bits.in2, 31, 0) node rhs_in = cat(hi_1, _T_9) node _subtractor_T = bits(remainder, 128, 64) node _subtractor_T_1 = sub(_subtractor_T, divisor) node subtractor = tail(_subtractor_T_1, 1) node _result_T = bits(remainder, 128, 65) node _result_T_1 = bits(remainder, 63, 0) node result = mux(resHi, _result_T, _result_T_1) node _negated_remainder_T = sub(UInt<1>(0h0), result) node negated_remainder = tail(_negated_remainder_T, 1) node _T_10 = eq(state, UInt<3>(0h1)) when _T_10 : node _T_11 = bits(remainder, 63, 63) when _T_11 : connect remainder, negated_remainder node _T_12 = bits(divisor, 63, 63) when _T_12 : connect divisor, subtractor connect state, UInt<3>(0h3) node _T_13 = eq(state, UInt<3>(0h5)) when _T_13 : connect remainder, negated_remainder connect state, UInt<3>(0h7) connect resHi, UInt<1>(0h0) node _T_14 = eq(state, UInt<3>(0h2)) when _T_14 : node _mulReg_T = bits(remainder, 129, 65) node _mulReg_T_1 = bits(remainder, 63, 0) node mulReg = cat(_mulReg_T, _mulReg_T_1) node mplierSign = bits(remainder, 64, 64) node mplier = bits(mulReg, 63, 0) node _accum_T = bits(mulReg, 128, 64) node accum = asSInt(_accum_T) node mpcand = asSInt(divisor) node _prod_T = bits(mplier, 7, 0) node _prod_T_1 = cat(mplierSign, _prod_T) node _prod_T_2 = asSInt(_prod_T_1) node _prod_T_3 = mul(_prod_T_2, mpcand) node _prod_T_4 = add(_prod_T_3, accum) node _prod_T_5 = tail(_prod_T_4, 1) node prod = asSInt(_prod_T_5) node _nextMulReg_T = bits(mplier, 63, 8) node nextMulReg_hi = asUInt(prod) node nextMulReg = cat(nextMulReg_hi, _nextMulReg_T) node _nextMplierSign_T = eq(count, UInt<3>(0h6)) node nextMplierSign = and(_nextMplierSign_T, neg_out) node _eOutMask_T = mul(count, UInt<4>(0h8)) node _eOutMask_T_1 = bits(_eOutMask_T, 5, 0) node _eOutMask_T_2 = dshr(asSInt(UInt<65>(0h10000000000000000)), _eOutMask_T_1) node eOutMask = bits(_eOutMask_T_2, 63, 0) node _eOut_T = neq(count, UInt<3>(0h7)) node _eOut_T_1 = and(UInt<1>(0h1), _eOut_T) node _eOut_T_2 = neq(count, UInt<1>(0h0)) node _eOut_T_3 = and(_eOut_T_1, _eOut_T_2) node _eOut_T_4 = eq(isHi, UInt<1>(0h0)) node _eOut_T_5 = and(_eOut_T_3, _eOut_T_4) node _eOut_T_6 = not(eOutMask) node _eOut_T_7 = and(mplier, _eOut_T_6) node _eOut_T_8 = eq(_eOut_T_7, UInt<1>(0h0)) node eOut = and(_eOut_T_5, _eOut_T_8) node _eOutRes_T = mul(count, UInt<4>(0h8)) node _eOutRes_T_1 = sub(UInt<7>(0h40), _eOutRes_T) node _eOutRes_T_2 = tail(_eOutRes_T_1, 1) node _eOutRes_T_3 = bits(_eOutRes_T_2, 5, 0) node eOutRes = dshr(mulReg, _eOutRes_T_3) node _nextMulReg1_T = bits(nextMulReg, 128, 64) node _nextMulReg1_T_1 = mux(eOut, eOutRes, nextMulReg) node _nextMulReg1_T_2 = bits(_nextMulReg1_T_1, 63, 0) node nextMulReg1 = cat(_nextMulReg1_T, _nextMulReg1_T_2) node _remainder_T = shr(nextMulReg1, 64) node _remainder_T_1 = bits(nextMulReg1, 63, 0) node remainder_hi = cat(_remainder_T, nextMplierSign) node _remainder_T_2 = cat(remainder_hi, _remainder_T_1) connect remainder, _remainder_T_2 node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 node _T_15 = eq(count, UInt<3>(0h7)) node _T_16 = or(eOut, _T_15) when _T_16 : connect state, UInt<3>(0h6) connect resHi, isHi node _T_17 = eq(state, UInt<3>(0h3)) when _T_17 : node unrolls_less = bits(subtractor, 64, 64) node _unrolls_T = bits(remainder, 127, 64) node _unrolls_T_1 = bits(subtractor, 63, 0) node _unrolls_T_2 = mux(unrolls_less, _unrolls_T, _unrolls_T_1) node _unrolls_T_3 = bits(remainder, 63, 0) node _unrolls_T_4 = eq(unrolls_less, UInt<1>(0h0)) node unrolls_hi = cat(_unrolls_T_2, _unrolls_T_3) node unrolls_0 = cat(unrolls_hi, _unrolls_T_4) connect remainder, unrolls_0 node _T_18 = eq(count, UInt<7>(0h40)) when _T_18 : node _state_T = mux(neg_out, UInt<3>(0h5), UInt<3>(0h7)) connect state, _state_T connect resHi, isHi node _count_T_2 = add(count, UInt<1>(0h1)) node _count_T_3 = tail(_count_T_2, 1) connect count, _count_T_3 node _divby0_T = eq(count, UInt<1>(0h0)) node _divby0_T_1 = bits(subtractor, 64, 64) node _divby0_T_2 = eq(_divby0_T_1, UInt<1>(0h0)) node divby0 = and(_divby0_T, _divby0_T_2) node alignMask = not(UInt<6>(0h0)) node _divisorMSB_T = bits(divisor, 63, 0) node divisorMSB_hi = bits(_divisorMSB_T, 63, 32) node divisorMSB_lo = bits(_divisorMSB_T, 31, 0) node divisorMSB_useHi = orr(divisorMSB_hi) node divisorMSB_hi_1 = bits(divisorMSB_hi, 31, 16) node divisorMSB_lo_1 = bits(divisorMSB_hi, 15, 0) node divisorMSB_useHi_1 = orr(divisorMSB_hi_1) node divisorMSB_hi_2 = bits(divisorMSB_hi_1, 15, 8) node divisorMSB_lo_2 = bits(divisorMSB_hi_1, 7, 0) node divisorMSB_useHi_2 = orr(divisorMSB_hi_2) node divisorMSB_hi_3 = bits(divisorMSB_hi_2, 7, 4) node divisorMSB_lo_3 = bits(divisorMSB_hi_2, 3, 0) node divisorMSB_useHi_3 = orr(divisorMSB_hi_3) node _divisorMSB_T_1 = bits(divisorMSB_hi_3, 3, 3) node _divisorMSB_T_2 = bits(divisorMSB_hi_3, 2, 2) node _divisorMSB_T_3 = bits(divisorMSB_hi_3, 1, 1) node _divisorMSB_T_4 = mux(_divisorMSB_T_2, UInt<2>(0h2), _divisorMSB_T_3) node _divisorMSB_T_5 = mux(_divisorMSB_T_1, UInt<2>(0h3), _divisorMSB_T_4) node _divisorMSB_T_6 = bits(divisorMSB_lo_3, 3, 3) node _divisorMSB_T_7 = bits(divisorMSB_lo_3, 2, 2) node _divisorMSB_T_8 = bits(divisorMSB_lo_3, 1, 1) node _divisorMSB_T_9 = mux(_divisorMSB_T_7, UInt<2>(0h2), _divisorMSB_T_8) node _divisorMSB_T_10 = mux(_divisorMSB_T_6, UInt<2>(0h3), _divisorMSB_T_9) node _divisorMSB_T_11 = mux(divisorMSB_useHi_3, _divisorMSB_T_5, _divisorMSB_T_10) node _divisorMSB_T_12 = cat(divisorMSB_useHi_3, _divisorMSB_T_11) node divisorMSB_hi_4 = bits(divisorMSB_lo_2, 7, 4) node divisorMSB_lo_4 = bits(divisorMSB_lo_2, 3, 0) node divisorMSB_useHi_4 = orr(divisorMSB_hi_4) node _divisorMSB_T_13 = bits(divisorMSB_hi_4, 3, 3) node _divisorMSB_T_14 = bits(divisorMSB_hi_4, 2, 2) node _divisorMSB_T_15 = bits(divisorMSB_hi_4, 1, 1) node _divisorMSB_T_16 = mux(_divisorMSB_T_14, UInt<2>(0h2), _divisorMSB_T_15) node _divisorMSB_T_17 = mux(_divisorMSB_T_13, UInt<2>(0h3), _divisorMSB_T_16) node _divisorMSB_T_18 = bits(divisorMSB_lo_4, 3, 3) node _divisorMSB_T_19 = bits(divisorMSB_lo_4, 2, 2) node _divisorMSB_T_20 = bits(divisorMSB_lo_4, 1, 1) node _divisorMSB_T_21 = mux(_divisorMSB_T_19, UInt<2>(0h2), _divisorMSB_T_20) node _divisorMSB_T_22 = mux(_divisorMSB_T_18, UInt<2>(0h3), _divisorMSB_T_21) node _divisorMSB_T_23 = mux(divisorMSB_useHi_4, _divisorMSB_T_17, _divisorMSB_T_22) node _divisorMSB_T_24 = cat(divisorMSB_useHi_4, _divisorMSB_T_23) node _divisorMSB_T_25 = mux(divisorMSB_useHi_2, _divisorMSB_T_12, _divisorMSB_T_24) node _divisorMSB_T_26 = cat(divisorMSB_useHi_2, _divisorMSB_T_25) node divisorMSB_hi_5 = bits(divisorMSB_lo_1, 15, 8) node divisorMSB_lo_5 = bits(divisorMSB_lo_1, 7, 0) node divisorMSB_useHi_5 = orr(divisorMSB_hi_5) node divisorMSB_hi_6 = bits(divisorMSB_hi_5, 7, 4) node divisorMSB_lo_6 = bits(divisorMSB_hi_5, 3, 0) node divisorMSB_useHi_6 = orr(divisorMSB_hi_6) node _divisorMSB_T_27 = bits(divisorMSB_hi_6, 3, 3) node _divisorMSB_T_28 = bits(divisorMSB_hi_6, 2, 2) node _divisorMSB_T_29 = bits(divisorMSB_hi_6, 1, 1) node _divisorMSB_T_30 = mux(_divisorMSB_T_28, UInt<2>(0h2), _divisorMSB_T_29) node _divisorMSB_T_31 = mux(_divisorMSB_T_27, UInt<2>(0h3), _divisorMSB_T_30) node _divisorMSB_T_32 = bits(divisorMSB_lo_6, 3, 3) node _divisorMSB_T_33 = bits(divisorMSB_lo_6, 2, 2) node _divisorMSB_T_34 = bits(divisorMSB_lo_6, 1, 1) node _divisorMSB_T_35 = mux(_divisorMSB_T_33, UInt<2>(0h2), _divisorMSB_T_34) node _divisorMSB_T_36 = mux(_divisorMSB_T_32, UInt<2>(0h3), _divisorMSB_T_35) node _divisorMSB_T_37 = mux(divisorMSB_useHi_6, _divisorMSB_T_31, _divisorMSB_T_36) node _divisorMSB_T_38 = cat(divisorMSB_useHi_6, _divisorMSB_T_37) node divisorMSB_hi_7 = bits(divisorMSB_lo_5, 7, 4) node divisorMSB_lo_7 = bits(divisorMSB_lo_5, 3, 0) node divisorMSB_useHi_7 = orr(divisorMSB_hi_7) node _divisorMSB_T_39 = bits(divisorMSB_hi_7, 3, 3) node _divisorMSB_T_40 = bits(divisorMSB_hi_7, 2, 2) node _divisorMSB_T_41 = bits(divisorMSB_hi_7, 1, 1) node _divisorMSB_T_42 = mux(_divisorMSB_T_40, UInt<2>(0h2), _divisorMSB_T_41) node _divisorMSB_T_43 = mux(_divisorMSB_T_39, UInt<2>(0h3), _divisorMSB_T_42) node _divisorMSB_T_44 = bits(divisorMSB_lo_7, 3, 3) node _divisorMSB_T_45 = bits(divisorMSB_lo_7, 2, 2) node _divisorMSB_T_46 = bits(divisorMSB_lo_7, 1, 1) node _divisorMSB_T_47 = mux(_divisorMSB_T_45, UInt<2>(0h2), _divisorMSB_T_46) node _divisorMSB_T_48 = mux(_divisorMSB_T_44, UInt<2>(0h3), _divisorMSB_T_47) node _divisorMSB_T_49 = mux(divisorMSB_useHi_7, _divisorMSB_T_43, _divisorMSB_T_48) node _divisorMSB_T_50 = cat(divisorMSB_useHi_7, _divisorMSB_T_49) node _divisorMSB_T_51 = mux(divisorMSB_useHi_5, _divisorMSB_T_38, _divisorMSB_T_50) node _divisorMSB_T_52 = cat(divisorMSB_useHi_5, _divisorMSB_T_51) node _divisorMSB_T_53 = mux(divisorMSB_useHi_1, _divisorMSB_T_26, _divisorMSB_T_52) node _divisorMSB_T_54 = cat(divisorMSB_useHi_1, _divisorMSB_T_53) node divisorMSB_hi_8 = bits(divisorMSB_lo, 31, 16) node divisorMSB_lo_8 = bits(divisorMSB_lo, 15, 0) node divisorMSB_useHi_8 = orr(divisorMSB_hi_8) node divisorMSB_hi_9 = bits(divisorMSB_hi_8, 15, 8) node divisorMSB_lo_9 = bits(divisorMSB_hi_8, 7, 0) node divisorMSB_useHi_9 = orr(divisorMSB_hi_9) node divisorMSB_hi_10 = bits(divisorMSB_hi_9, 7, 4) node divisorMSB_lo_10 = bits(divisorMSB_hi_9, 3, 0) node divisorMSB_useHi_10 = orr(divisorMSB_hi_10) node _divisorMSB_T_55 = bits(divisorMSB_hi_10, 3, 3) node _divisorMSB_T_56 = bits(divisorMSB_hi_10, 2, 2) node _divisorMSB_T_57 = bits(divisorMSB_hi_10, 1, 1) node _divisorMSB_T_58 = mux(_divisorMSB_T_56, UInt<2>(0h2), _divisorMSB_T_57) node _divisorMSB_T_59 = mux(_divisorMSB_T_55, UInt<2>(0h3), _divisorMSB_T_58) node _divisorMSB_T_60 = bits(divisorMSB_lo_10, 3, 3) node _divisorMSB_T_61 = bits(divisorMSB_lo_10, 2, 2) node _divisorMSB_T_62 = bits(divisorMSB_lo_10, 1, 1) node _divisorMSB_T_63 = mux(_divisorMSB_T_61, UInt<2>(0h2), _divisorMSB_T_62) node _divisorMSB_T_64 = mux(_divisorMSB_T_60, UInt<2>(0h3), _divisorMSB_T_63) node _divisorMSB_T_65 = mux(divisorMSB_useHi_10, _divisorMSB_T_59, _divisorMSB_T_64) node _divisorMSB_T_66 = cat(divisorMSB_useHi_10, _divisorMSB_T_65) node divisorMSB_hi_11 = bits(divisorMSB_lo_9, 7, 4) node divisorMSB_lo_11 = bits(divisorMSB_lo_9, 3, 0) node divisorMSB_useHi_11 = orr(divisorMSB_hi_11) node _divisorMSB_T_67 = bits(divisorMSB_hi_11, 3, 3) node _divisorMSB_T_68 = bits(divisorMSB_hi_11, 2, 2) node _divisorMSB_T_69 = bits(divisorMSB_hi_11, 1, 1) node _divisorMSB_T_70 = mux(_divisorMSB_T_68, UInt<2>(0h2), _divisorMSB_T_69) node _divisorMSB_T_71 = mux(_divisorMSB_T_67, UInt<2>(0h3), _divisorMSB_T_70) node _divisorMSB_T_72 = bits(divisorMSB_lo_11, 3, 3) node _divisorMSB_T_73 = bits(divisorMSB_lo_11, 2, 2) node _divisorMSB_T_74 = bits(divisorMSB_lo_11, 1, 1) node _divisorMSB_T_75 = mux(_divisorMSB_T_73, UInt<2>(0h2), _divisorMSB_T_74) node _divisorMSB_T_76 = mux(_divisorMSB_T_72, UInt<2>(0h3), _divisorMSB_T_75) node _divisorMSB_T_77 = mux(divisorMSB_useHi_11, _divisorMSB_T_71, _divisorMSB_T_76) node _divisorMSB_T_78 = cat(divisorMSB_useHi_11, _divisorMSB_T_77) node _divisorMSB_T_79 = mux(divisorMSB_useHi_9, _divisorMSB_T_66, _divisorMSB_T_78) node _divisorMSB_T_80 = cat(divisorMSB_useHi_9, _divisorMSB_T_79) node divisorMSB_hi_12 = bits(divisorMSB_lo_8, 15, 8) node divisorMSB_lo_12 = bits(divisorMSB_lo_8, 7, 0) node divisorMSB_useHi_12 = orr(divisorMSB_hi_12) node divisorMSB_hi_13 = bits(divisorMSB_hi_12, 7, 4) node divisorMSB_lo_13 = bits(divisorMSB_hi_12, 3, 0) node divisorMSB_useHi_13 = orr(divisorMSB_hi_13) node _divisorMSB_T_81 = bits(divisorMSB_hi_13, 3, 3) node _divisorMSB_T_82 = bits(divisorMSB_hi_13, 2, 2) node _divisorMSB_T_83 = bits(divisorMSB_hi_13, 1, 1) node _divisorMSB_T_84 = mux(_divisorMSB_T_82, UInt<2>(0h2), _divisorMSB_T_83) node _divisorMSB_T_85 = mux(_divisorMSB_T_81, UInt<2>(0h3), _divisorMSB_T_84) node _divisorMSB_T_86 = bits(divisorMSB_lo_13, 3, 3) node _divisorMSB_T_87 = bits(divisorMSB_lo_13, 2, 2) node _divisorMSB_T_88 = bits(divisorMSB_lo_13, 1, 1) node _divisorMSB_T_89 = mux(_divisorMSB_T_87, UInt<2>(0h2), _divisorMSB_T_88) node _divisorMSB_T_90 = mux(_divisorMSB_T_86, UInt<2>(0h3), _divisorMSB_T_89) node _divisorMSB_T_91 = mux(divisorMSB_useHi_13, _divisorMSB_T_85, _divisorMSB_T_90) node _divisorMSB_T_92 = cat(divisorMSB_useHi_13, _divisorMSB_T_91) node divisorMSB_hi_14 = bits(divisorMSB_lo_12, 7, 4) node divisorMSB_lo_14 = bits(divisorMSB_lo_12, 3, 0) node divisorMSB_useHi_14 = orr(divisorMSB_hi_14) node _divisorMSB_T_93 = bits(divisorMSB_hi_14, 3, 3) node _divisorMSB_T_94 = bits(divisorMSB_hi_14, 2, 2) node _divisorMSB_T_95 = bits(divisorMSB_hi_14, 1, 1) node _divisorMSB_T_96 = mux(_divisorMSB_T_94, UInt<2>(0h2), _divisorMSB_T_95) node _divisorMSB_T_97 = mux(_divisorMSB_T_93, UInt<2>(0h3), _divisorMSB_T_96) node _divisorMSB_T_98 = bits(divisorMSB_lo_14, 3, 3) node _divisorMSB_T_99 = bits(divisorMSB_lo_14, 2, 2) node _divisorMSB_T_100 = bits(divisorMSB_lo_14, 1, 1) node _divisorMSB_T_101 = mux(_divisorMSB_T_99, UInt<2>(0h2), _divisorMSB_T_100) node _divisorMSB_T_102 = mux(_divisorMSB_T_98, UInt<2>(0h3), _divisorMSB_T_101) node _divisorMSB_T_103 = mux(divisorMSB_useHi_14, _divisorMSB_T_97, _divisorMSB_T_102) node _divisorMSB_T_104 = cat(divisorMSB_useHi_14, _divisorMSB_T_103) node _divisorMSB_T_105 = mux(divisorMSB_useHi_12, _divisorMSB_T_92, _divisorMSB_T_104) node _divisorMSB_T_106 = cat(divisorMSB_useHi_12, _divisorMSB_T_105) node _divisorMSB_T_107 = mux(divisorMSB_useHi_8, _divisorMSB_T_80, _divisorMSB_T_106) node _divisorMSB_T_108 = cat(divisorMSB_useHi_8, _divisorMSB_T_107) node _divisorMSB_T_109 = mux(divisorMSB_useHi, _divisorMSB_T_54, _divisorMSB_T_108) node _divisorMSB_T_110 = cat(divisorMSB_useHi, _divisorMSB_T_109) node divisorMSB = and(_divisorMSB_T_110, alignMask) node _dividendMSB_T = bits(remainder, 63, 0) node dividendMSB_hi = bits(_dividendMSB_T, 63, 32) node dividendMSB_lo = bits(_dividendMSB_T, 31, 0) node dividendMSB_useHi = orr(dividendMSB_hi) node dividendMSB_hi_1 = bits(dividendMSB_hi, 31, 16) node dividendMSB_lo_1 = bits(dividendMSB_hi, 15, 0) node dividendMSB_useHi_1 = orr(dividendMSB_hi_1) node dividendMSB_hi_2 = bits(dividendMSB_hi_1, 15, 8) node dividendMSB_lo_2 = bits(dividendMSB_hi_1, 7, 0) node dividendMSB_useHi_2 = orr(dividendMSB_hi_2) node dividendMSB_hi_3 = bits(dividendMSB_hi_2, 7, 4) node dividendMSB_lo_3 = bits(dividendMSB_hi_2, 3, 0) node dividendMSB_useHi_3 = orr(dividendMSB_hi_3) node _dividendMSB_T_1 = bits(dividendMSB_hi_3, 3, 3) node _dividendMSB_T_2 = bits(dividendMSB_hi_3, 2, 2) node _dividendMSB_T_3 = bits(dividendMSB_hi_3, 1, 1) node _dividendMSB_T_4 = mux(_dividendMSB_T_2, UInt<2>(0h2), _dividendMSB_T_3) node _dividendMSB_T_5 = mux(_dividendMSB_T_1, UInt<2>(0h3), _dividendMSB_T_4) node _dividendMSB_T_6 = bits(dividendMSB_lo_3, 3, 3) node _dividendMSB_T_7 = bits(dividendMSB_lo_3, 2, 2) node _dividendMSB_T_8 = bits(dividendMSB_lo_3, 1, 1) node _dividendMSB_T_9 = mux(_dividendMSB_T_7, UInt<2>(0h2), _dividendMSB_T_8) node _dividendMSB_T_10 = mux(_dividendMSB_T_6, UInt<2>(0h3), _dividendMSB_T_9) node _dividendMSB_T_11 = mux(dividendMSB_useHi_3, _dividendMSB_T_5, _dividendMSB_T_10) node _dividendMSB_T_12 = cat(dividendMSB_useHi_3, _dividendMSB_T_11) node dividendMSB_hi_4 = bits(dividendMSB_lo_2, 7, 4) node dividendMSB_lo_4 = bits(dividendMSB_lo_2, 3, 0) node dividendMSB_useHi_4 = orr(dividendMSB_hi_4) node _dividendMSB_T_13 = bits(dividendMSB_hi_4, 3, 3) node _dividendMSB_T_14 = bits(dividendMSB_hi_4, 2, 2) node _dividendMSB_T_15 = bits(dividendMSB_hi_4, 1, 1) node _dividendMSB_T_16 = mux(_dividendMSB_T_14, UInt<2>(0h2), _dividendMSB_T_15) node _dividendMSB_T_17 = mux(_dividendMSB_T_13, UInt<2>(0h3), _dividendMSB_T_16) node _dividendMSB_T_18 = bits(dividendMSB_lo_4, 3, 3) node _dividendMSB_T_19 = bits(dividendMSB_lo_4, 2, 2) node _dividendMSB_T_20 = bits(dividendMSB_lo_4, 1, 1) node _dividendMSB_T_21 = mux(_dividendMSB_T_19, UInt<2>(0h2), _dividendMSB_T_20) node _dividendMSB_T_22 = mux(_dividendMSB_T_18, UInt<2>(0h3), _dividendMSB_T_21) node _dividendMSB_T_23 = mux(dividendMSB_useHi_4, _dividendMSB_T_17, _dividendMSB_T_22) node _dividendMSB_T_24 = cat(dividendMSB_useHi_4, _dividendMSB_T_23) node _dividendMSB_T_25 = mux(dividendMSB_useHi_2, _dividendMSB_T_12, _dividendMSB_T_24) node _dividendMSB_T_26 = cat(dividendMSB_useHi_2, _dividendMSB_T_25) node dividendMSB_hi_5 = bits(dividendMSB_lo_1, 15, 8) node dividendMSB_lo_5 = bits(dividendMSB_lo_1, 7, 0) node dividendMSB_useHi_5 = orr(dividendMSB_hi_5) node dividendMSB_hi_6 = bits(dividendMSB_hi_5, 7, 4) node dividendMSB_lo_6 = bits(dividendMSB_hi_5, 3, 0) node dividendMSB_useHi_6 = orr(dividendMSB_hi_6) node _dividendMSB_T_27 = bits(dividendMSB_hi_6, 3, 3) node _dividendMSB_T_28 = bits(dividendMSB_hi_6, 2, 2) node _dividendMSB_T_29 = bits(dividendMSB_hi_6, 1, 1) node _dividendMSB_T_30 = mux(_dividendMSB_T_28, UInt<2>(0h2), _dividendMSB_T_29) node _dividendMSB_T_31 = mux(_dividendMSB_T_27, UInt<2>(0h3), _dividendMSB_T_30) node _dividendMSB_T_32 = bits(dividendMSB_lo_6, 3, 3) node _dividendMSB_T_33 = bits(dividendMSB_lo_6, 2, 2) node _dividendMSB_T_34 = bits(dividendMSB_lo_6, 1, 1) node _dividendMSB_T_35 = mux(_dividendMSB_T_33, UInt<2>(0h2), _dividendMSB_T_34) node _dividendMSB_T_36 = mux(_dividendMSB_T_32, UInt<2>(0h3), _dividendMSB_T_35) node _dividendMSB_T_37 = mux(dividendMSB_useHi_6, _dividendMSB_T_31, _dividendMSB_T_36) node _dividendMSB_T_38 = cat(dividendMSB_useHi_6, _dividendMSB_T_37) node dividendMSB_hi_7 = bits(dividendMSB_lo_5, 7, 4) node dividendMSB_lo_7 = bits(dividendMSB_lo_5, 3, 0) node dividendMSB_useHi_7 = orr(dividendMSB_hi_7) node _dividendMSB_T_39 = bits(dividendMSB_hi_7, 3, 3) node _dividendMSB_T_40 = bits(dividendMSB_hi_7, 2, 2) node _dividendMSB_T_41 = bits(dividendMSB_hi_7, 1, 1) node _dividendMSB_T_42 = mux(_dividendMSB_T_40, UInt<2>(0h2), _dividendMSB_T_41) node _dividendMSB_T_43 = mux(_dividendMSB_T_39, UInt<2>(0h3), _dividendMSB_T_42) node _dividendMSB_T_44 = bits(dividendMSB_lo_7, 3, 3) node _dividendMSB_T_45 = bits(dividendMSB_lo_7, 2, 2) node _dividendMSB_T_46 = bits(dividendMSB_lo_7, 1, 1) node _dividendMSB_T_47 = mux(_dividendMSB_T_45, UInt<2>(0h2), _dividendMSB_T_46) node _dividendMSB_T_48 = mux(_dividendMSB_T_44, UInt<2>(0h3), _dividendMSB_T_47) node _dividendMSB_T_49 = mux(dividendMSB_useHi_7, _dividendMSB_T_43, _dividendMSB_T_48) node _dividendMSB_T_50 = cat(dividendMSB_useHi_7, _dividendMSB_T_49) node _dividendMSB_T_51 = mux(dividendMSB_useHi_5, _dividendMSB_T_38, _dividendMSB_T_50) node _dividendMSB_T_52 = cat(dividendMSB_useHi_5, _dividendMSB_T_51) node _dividendMSB_T_53 = mux(dividendMSB_useHi_1, _dividendMSB_T_26, _dividendMSB_T_52) node _dividendMSB_T_54 = cat(dividendMSB_useHi_1, _dividendMSB_T_53) node dividendMSB_hi_8 = bits(dividendMSB_lo, 31, 16) node dividendMSB_lo_8 = bits(dividendMSB_lo, 15, 0) node dividendMSB_useHi_8 = orr(dividendMSB_hi_8) node dividendMSB_hi_9 = bits(dividendMSB_hi_8, 15, 8) node dividendMSB_lo_9 = bits(dividendMSB_hi_8, 7, 0) node dividendMSB_useHi_9 = orr(dividendMSB_hi_9) node dividendMSB_hi_10 = bits(dividendMSB_hi_9, 7, 4) node dividendMSB_lo_10 = bits(dividendMSB_hi_9, 3, 0) node dividendMSB_useHi_10 = orr(dividendMSB_hi_10) node _dividendMSB_T_55 = bits(dividendMSB_hi_10, 3, 3) node _dividendMSB_T_56 = bits(dividendMSB_hi_10, 2, 2) node _dividendMSB_T_57 = bits(dividendMSB_hi_10, 1, 1) node _dividendMSB_T_58 = mux(_dividendMSB_T_56, UInt<2>(0h2), _dividendMSB_T_57) node _dividendMSB_T_59 = mux(_dividendMSB_T_55, UInt<2>(0h3), _dividendMSB_T_58) node _dividendMSB_T_60 = bits(dividendMSB_lo_10, 3, 3) node _dividendMSB_T_61 = bits(dividendMSB_lo_10, 2, 2) node _dividendMSB_T_62 = bits(dividendMSB_lo_10, 1, 1) node _dividendMSB_T_63 = mux(_dividendMSB_T_61, UInt<2>(0h2), _dividendMSB_T_62) node _dividendMSB_T_64 = mux(_dividendMSB_T_60, UInt<2>(0h3), _dividendMSB_T_63) node _dividendMSB_T_65 = mux(dividendMSB_useHi_10, _dividendMSB_T_59, _dividendMSB_T_64) node _dividendMSB_T_66 = cat(dividendMSB_useHi_10, _dividendMSB_T_65) node dividendMSB_hi_11 = bits(dividendMSB_lo_9, 7, 4) node dividendMSB_lo_11 = bits(dividendMSB_lo_9, 3, 0) node dividendMSB_useHi_11 = orr(dividendMSB_hi_11) node _dividendMSB_T_67 = bits(dividendMSB_hi_11, 3, 3) node _dividendMSB_T_68 = bits(dividendMSB_hi_11, 2, 2) node _dividendMSB_T_69 = bits(dividendMSB_hi_11, 1, 1) node _dividendMSB_T_70 = mux(_dividendMSB_T_68, UInt<2>(0h2), _dividendMSB_T_69) node _dividendMSB_T_71 = mux(_dividendMSB_T_67, UInt<2>(0h3), _dividendMSB_T_70) node _dividendMSB_T_72 = bits(dividendMSB_lo_11, 3, 3) node _dividendMSB_T_73 = bits(dividendMSB_lo_11, 2, 2) node _dividendMSB_T_74 = bits(dividendMSB_lo_11, 1, 1) node _dividendMSB_T_75 = mux(_dividendMSB_T_73, UInt<2>(0h2), _dividendMSB_T_74) node _dividendMSB_T_76 = mux(_dividendMSB_T_72, UInt<2>(0h3), _dividendMSB_T_75) node _dividendMSB_T_77 = mux(dividendMSB_useHi_11, _dividendMSB_T_71, _dividendMSB_T_76) node _dividendMSB_T_78 = cat(dividendMSB_useHi_11, _dividendMSB_T_77) node _dividendMSB_T_79 = mux(dividendMSB_useHi_9, _dividendMSB_T_66, _dividendMSB_T_78) node _dividendMSB_T_80 = cat(dividendMSB_useHi_9, _dividendMSB_T_79) node dividendMSB_hi_12 = bits(dividendMSB_lo_8, 15, 8) node dividendMSB_lo_12 = bits(dividendMSB_lo_8, 7, 0) node dividendMSB_useHi_12 = orr(dividendMSB_hi_12) node dividendMSB_hi_13 = bits(dividendMSB_hi_12, 7, 4) node dividendMSB_lo_13 = bits(dividendMSB_hi_12, 3, 0) node dividendMSB_useHi_13 = orr(dividendMSB_hi_13) node _dividendMSB_T_81 = bits(dividendMSB_hi_13, 3, 3) node _dividendMSB_T_82 = bits(dividendMSB_hi_13, 2, 2) node _dividendMSB_T_83 = bits(dividendMSB_hi_13, 1, 1) node _dividendMSB_T_84 = mux(_dividendMSB_T_82, UInt<2>(0h2), _dividendMSB_T_83) node _dividendMSB_T_85 = mux(_dividendMSB_T_81, UInt<2>(0h3), _dividendMSB_T_84) node _dividendMSB_T_86 = bits(dividendMSB_lo_13, 3, 3) node _dividendMSB_T_87 = bits(dividendMSB_lo_13, 2, 2) node _dividendMSB_T_88 = bits(dividendMSB_lo_13, 1, 1) node _dividendMSB_T_89 = mux(_dividendMSB_T_87, UInt<2>(0h2), _dividendMSB_T_88) node _dividendMSB_T_90 = mux(_dividendMSB_T_86, UInt<2>(0h3), _dividendMSB_T_89) node _dividendMSB_T_91 = mux(dividendMSB_useHi_13, _dividendMSB_T_85, _dividendMSB_T_90) node _dividendMSB_T_92 = cat(dividendMSB_useHi_13, _dividendMSB_T_91) node dividendMSB_hi_14 = bits(dividendMSB_lo_12, 7, 4) node dividendMSB_lo_14 = bits(dividendMSB_lo_12, 3, 0) node dividendMSB_useHi_14 = orr(dividendMSB_hi_14) node _dividendMSB_T_93 = bits(dividendMSB_hi_14, 3, 3) node _dividendMSB_T_94 = bits(dividendMSB_hi_14, 2, 2) node _dividendMSB_T_95 = bits(dividendMSB_hi_14, 1, 1) node _dividendMSB_T_96 = mux(_dividendMSB_T_94, UInt<2>(0h2), _dividendMSB_T_95) node _dividendMSB_T_97 = mux(_dividendMSB_T_93, UInt<2>(0h3), _dividendMSB_T_96) node _dividendMSB_T_98 = bits(dividendMSB_lo_14, 3, 3) node _dividendMSB_T_99 = bits(dividendMSB_lo_14, 2, 2) node _dividendMSB_T_100 = bits(dividendMSB_lo_14, 1, 1) node _dividendMSB_T_101 = mux(_dividendMSB_T_99, UInt<2>(0h2), _dividendMSB_T_100) node _dividendMSB_T_102 = mux(_dividendMSB_T_98, UInt<2>(0h3), _dividendMSB_T_101) node _dividendMSB_T_103 = mux(dividendMSB_useHi_14, _dividendMSB_T_97, _dividendMSB_T_102) node _dividendMSB_T_104 = cat(dividendMSB_useHi_14, _dividendMSB_T_103) node _dividendMSB_T_105 = mux(dividendMSB_useHi_12, _dividendMSB_T_92, _dividendMSB_T_104) node _dividendMSB_T_106 = cat(dividendMSB_useHi_12, _dividendMSB_T_105) node _dividendMSB_T_107 = mux(dividendMSB_useHi_8, _dividendMSB_T_80, _dividendMSB_T_106) node _dividendMSB_T_108 = cat(dividendMSB_useHi_8, _dividendMSB_T_107) node _dividendMSB_T_109 = mux(dividendMSB_useHi, _dividendMSB_T_54, _dividendMSB_T_108) node _dividendMSB_T_110 = cat(dividendMSB_useHi, _dividendMSB_T_109) node _dividendMSB_T_111 = not(alignMask) node dividendMSB = or(_dividendMSB_T_110, _dividendMSB_T_111) node _eOutPos_T = sub(dividendMSB, divisorMSB) node _eOutPos_T_1 = tail(_eOutPos_T, 1) node eOutPos = not(_eOutPos_T_1) node _eOut_T_9 = eq(count, UInt<1>(0h0)) node _eOut_T_10 = eq(divby0, UInt<1>(0h0)) node _eOut_T_11 = and(_eOut_T_9, _eOut_T_10) node _eOut_T_12 = geq(eOutPos, UInt<1>(0h1)) node eOut_1 = and(_eOut_T_11, _eOut_T_12) when eOut_1 : node _remainder_T_3 = bits(remainder, 63, 0) node _remainder_T_4 = dshl(_remainder_T_3, eOutPos) connect remainder, _remainder_T_4 node _count_T_4 = shr(eOutPos, 0) connect count, _count_T_4 node _T_19 = eq(isHi, UInt<1>(0h0)) node _T_20 = and(divby0, _T_19) when _T_20 : connect neg_out, UInt<1>(0h0) node _T_21 = and(io.resp.ready, io.resp.valid) node _T_22 = or(_T_21, io.kill) when _T_22 : connect state, UInt<3>(0h0) node _T_23 = and(io.req.ready, io.req.valid) when _T_23 : node _state_T_1 = or(lhs_sign, rhs_sign) node _state_T_2 = mux(_state_T_1, UInt<3>(0h1), UInt<3>(0h3)) node _state_T_3 = mux(cmdMul, UInt<3>(0h2), _state_T_2) connect state, _state_T_3 connect isHi, cmdHi connect resHi, UInt<1>(0h0) node _count_T_5 = eq(io.req.bits.dw, UInt<1>(0h0)) node _count_T_6 = and(UInt<1>(0h1), _count_T_5) node _count_T_7 = and(cmdMul, _count_T_6) node _count_T_8 = mux(_count_T_7, UInt<3>(0h4), UInt<1>(0h0)) connect count, _count_T_8 node _neg_out_T = neq(lhs_sign, rhs_sign) node _neg_out_T_1 = mux(cmdHi, lhs_sign, _neg_out_T) connect neg_out, _neg_out_T_1 node _divisor_T = cat(rhs_sign, rhs_in) connect divisor, _divisor_T connect remainder, lhs_in connect req, io.req.bits node _outMul_T = xor(UInt<3>(0h6), UInt<3>(0h7)) node _outMul_T_1 = and(state, _outMul_T) node _outMul_T_2 = not(UInt<3>(0h7)) node _outMul_T_3 = and(UInt<3>(0h6), _outMul_T_2) node outMul = eq(_outMul_T_1, _outMul_T_3) node _loOut_T = eq(req.dw, UInt<1>(0h0)) node _loOut_T_1 = and(UInt<1>(0h1), _loOut_T) node _loOut_T_2 = and(UInt<1>(0h1), _loOut_T_1) node _loOut_T_3 = and(_loOut_T_2, outMul) node _loOut_T_4 = bits(result, 63, 32) node _loOut_T_5 = bits(result, 31, 0) node loOut = mux(_loOut_T_3, _loOut_T_4, _loOut_T_5) node _hiOut_T = eq(req.dw, UInt<1>(0h0)) node _hiOut_T_1 = and(UInt<1>(0h1), _hiOut_T) node _hiOut_T_2 = bits(loOut, 31, 31) node _hiOut_T_3 = mux(_hiOut_T_2, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hiOut_T_4 = bits(result, 63, 32) node hiOut = mux(_hiOut_T_1, _hiOut_T_3, _hiOut_T_4) connect io.resp.bits.tag, req.tag node _io_resp_bits_data_T = cat(hiOut, loOut) connect io.resp.bits.data, _io_resp_bits_data_T node _io_resp_bits_full_data_T = bits(remainder, 128, 65) node _io_resp_bits_full_data_T_1 = bits(remainder, 63, 0) node _io_resp_bits_full_data_T_2 = cat(_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1) connect io.resp.bits.full_data, _io_resp_bits_full_data_T_2 node _io_resp_valid_T = eq(state, UInt<3>(0h6)) node _io_resp_valid_T_1 = eq(state, UInt<3>(0h7)) node _io_resp_valid_T_2 = or(_io_resp_valid_T, _io_resp_valid_T_1) connect io.resp.valid, _io_resp_valid_T_2 node _io_req_ready_T = eq(state, UInt<3>(0h0)) connect io.req.ready, _io_req_ready_T

module MulDiv_7( // @[Multiplier.scala:40:7] input clock, // @[Multiplier.scala:40:7] input reset, // @[Multiplier.scala:40:7] output io_req_ready, // @[Multiplier.scala:45:14] input io_req_valid, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_fn, // @[Multiplier.scala:45:14] input io_req_bits_dw, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in1, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in2, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_tag, // @[Multiplier.scala:45:14] input io_kill, // @[Multiplier.scala:45:14] input io_resp_ready, // @[Multiplier.scala:45:14] output io_resp_valid, // @[Multiplier.scala:45:14] output [63:0] io_resp_bits_data, // @[Multiplier.scala:45:14] output [4:0] io_resp_bits_tag // @[Multiplier.scala:45:14] ); wire io_req_valid_0 = io_req_valid; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_fn_0 = io_req_bits_fn; // @[Multiplier.scala:40:7] wire io_req_bits_dw_0 = io_req_bits_dw; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in1_0 = io_req_bits_in1; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in2_0 = io_req_bits_in2; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_tag_0 = io_req_bits_tag; // @[Multiplier.scala:40:7] wire io_kill_0 = io_kill; // @[Multiplier.scala:40:7] wire io_resp_ready_0 = io_resp_ready; // @[Multiplier.scala:40:7] wire [5:0] alignMask = 6'h3F; // @[Multiplier.scala:149:23] wire [5:0] _dividendMSB_T_111 = 6'h0; // @[Multiplier.scala:151:53] wire [2:0] _outMul_T = 3'h1; // @[Multiplier.scala:175:37] wire [2:0] _outMul_T_2 = 3'h0; // @[Multiplier.scala:175:70] wire [2:0] _outMul_T_3 = 3'h0; // @[Multiplier.scala:175:68] wire _io_req_ready_T; // @[Multiplier.scala:183:25] wire _io_resp_valid_T_2; // @[Multiplier.scala:182:42] wire [63:0] _io_resp_bits_data_T; // @[Multiplier.scala:180:27] wire [127:0] _io_resp_bits_full_data_T_2; // @[Multiplier.scala:181:32] wire io_req_ready_0; // @[Multiplier.scala:40:7] wire [63:0] io_resp_bits_data_0; // @[Multiplier.scala:40:7] wire [127:0] io_resp_bits_full_data; // @[Multiplier.scala:40:7] wire [4:0] io_resp_bits_tag_0; // @[Multiplier.scala:40:7] wire io_resp_valid_0; // @[Multiplier.scala:40:7] reg [2:0] state; // @[Multiplier.scala:51:22] reg [4:0] req_fn; // @[Multiplier.scala:53:16] reg req_dw; // @[Multiplier.scala:53:16] reg [63:0] req_in1; // @[Multiplier.scala:53:16] reg [63:0] req_in2; // @[Multiplier.scala:53:16] reg [4:0] req_tag; // @[Multiplier.scala:53:16] assign io_resp_bits_tag_0 = req_tag; // @[Multiplier.scala:40:7, :53:16] reg [6:0] count; // @[Multiplier.scala:54:18] reg neg_out; // @[Multiplier.scala:57:20] reg isHi; // @[Multiplier.scala:58:17] reg resHi; // @[Multiplier.scala:59:18] reg [64:0] divisor; // @[Multiplier.scala:60:20] wire [64:0] mpcand = divisor; // @[Multiplier.scala:60:20, :111:26] reg [129:0] remainder; // @[Multiplier.scala:61:22] wire [2:0] decoded_plaInput; // @[pla.scala:77:22] wire [2:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [3:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [3:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_3_2 = decoded_andMatrixOutputs_andMatrixInput_0; // @[pla.scala:91:29, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_4_2 = decoded_andMatrixOutputs_andMatrixInput_0_1; // @[pla.scala:91:29, :98:70] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire [1:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_1_2 = decoded_andMatrixOutputs_andMatrixInput_0_4; // @[pla.scala:90:45, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T = {decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_1 = |_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_2 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_3 = |_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_4 = {decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_5 = |_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo = {_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_plaInput = io_req_bits_fn_0[2:0]; // @[pla.scala:77:22] wire cmdMul = decoded[3]; // @[pla.scala:81:23] wire cmdHi = decoded[2]; // @[pla.scala:81:23] wire lhsSigned = decoded[1]; // @[pla.scala:81:23] wire rhsSigned = decoded[0]; // @[pla.scala:81:23] wire _count_T_5 = ~io_req_bits_dw_0; // @[Multiplier.scala:40:7, :78:60] wire _sign_T = io_req_bits_in1_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_1 = io_req_bits_in1_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_2 = io_req_bits_dw_0 ? _sign_T_1 : _sign_T; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire lhs_sign = lhsSigned & _sign_T_2; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T = {32{lhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_1 = io_req_bits_in1_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi = io_req_bits_dw_0 ? _hi_T_1 : _hi_T; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] lhs_in = {hi, io_req_bits_in1_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire _sign_T_3 = io_req_bits_in2_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_4 = io_req_bits_in2_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_5 = io_req_bits_dw_0 ? _sign_T_4 : _sign_T_3; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire rhs_sign = rhsSigned & _sign_T_5; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T_2 = {32{rhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_3 = io_req_bits_in2_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi_1 = io_req_bits_dw_0 ? _hi_T_3 : _hi_T_2; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] rhs_in = {hi_1, io_req_bits_in2_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire [64:0] _subtractor_T = remainder[128:64]; // @[Multiplier.scala:61:22, :88:29] wire [65:0] _subtractor_T_1 = {1'h0, _subtractor_T} - {1'h0, divisor}; // @[Multiplier.scala:60:20, :88:{29,37}] wire [64:0] subtractor = _subtractor_T_1[64:0]; // @[Multiplier.scala:88:37] wire [63:0] _result_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36] wire [63:0] _io_resp_bits_full_data_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36, :181:42] wire [63:0] _result_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57] wire [63:0] _mulReg_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :107:55] wire [63:0] _unrolls_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :134:58] wire [63:0] _dividendMSB_T = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :151:39] wire [63:0] _remainder_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :155:31] wire [63:0] _io_resp_bits_full_data_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :181:63] wire [63:0] result = resHi ? _result_T : _result_T_1; // @[Multiplier.scala:59:18, :89:{19,36,57}] wire [64:0] _negated_remainder_T = 65'h0 - {1'h0, result}; // @[Multiplier.scala:89:19, :90:27] wire [63:0] negated_remainder = _negated_remainder_T[63:0]; // @[Multiplier.scala:90:27] wire [64:0] _mulReg_T = remainder[129:65]; // @[Multiplier.scala:61:22, :107:31] wire [128:0] mulReg = {_mulReg_T, _mulReg_T_1}; // @[Multiplier.scala:107:{21,31,55}] wire mplierSign = remainder[64]; // @[Multiplier.scala:61:22, :108:31] wire [63:0] mplier = mulReg[63:0]; // @[Multiplier.scala:107:21, :109:24] wire [64:0] _accum_T = mulReg[128:64]; // @[Multiplier.scala:107:21, :110:23] wire [64:0] accum = _accum_T; // @[Multiplier.scala:110:{23,37}] wire [7:0] _prod_T = mplier[7:0]; // @[Multiplier.scala:109:24, :112:38] wire [8:0] _prod_T_1 = {mplierSign, _prod_T}; // @[Multiplier.scala:108:31, :112:{19,38}] wire [8:0] _prod_T_2 = _prod_T_1; // @[Multiplier.scala:112:{19,60}] wire [73:0] _prod_T_3 = {{65{_prod_T_2[8]}}, _prod_T_2} * {{9{mpcand[64]}}, mpcand}; // @[Multiplier.scala:111:26, :112:{60,67}] wire [74:0] _prod_T_4 = {_prod_T_3[73], _prod_T_3} + {{10{accum[64]}}, accum}; // @[Multiplier.scala:110:37, :112:{67,76}] wire [73:0] _prod_T_5 = _prod_T_4[73:0]; // @[Multiplier.scala:112:76] wire [73:0] prod = _prod_T_5; // @[Multiplier.scala:112:76] wire [73:0] nextMulReg_hi = prod; // @[Multiplier.scala:112:76, :113:25] wire [55:0] _nextMulReg_T = mplier[63:8]; // @[Multiplier.scala:109:24, :113:38] wire [129:0] nextMulReg = {nextMulReg_hi, _nextMulReg_T}; // @[Multiplier.scala:113:{25,38}] wire _nextMplierSign_T = count == 7'h6; // @[Multiplier.scala:54:18, :114:32] wire nextMplierSign = _nextMplierSign_T & neg_out; // @[Multiplier.scala:57:20, :114:{32,61}] wire [10:0] _GEN = {1'h0, count, 3'h0}; // @[Multiplier.scala:54:18, :116:54] wire [10:0] _eOutMask_T; // @[Multiplier.scala:116:54] assign _eOutMask_T = _GEN; // @[Multiplier.scala:116:54] wire [10:0] _eOutRes_T; // @[Multiplier.scala:119:46] assign _eOutRes_T = _GEN; // @[Multiplier.scala:116:54, :119:46] wire [5:0] _eOutMask_T_1 = _eOutMask_T[5:0]; // @[Multiplier.scala:116:{54,72}] wire [64:0] _eOutMask_T_2 = $signed(65'sh10000000000000000 >>> _eOutMask_T_1); // @[Multiplier.scala:116:{44,72}] wire [63:0] eOutMask = _eOutMask_T_2[63:0]; // @[Multiplier.scala:116:{44,91}] wire _eOut_T = count != 7'h7; // @[Multiplier.scala:54:18, :117:45] wire _eOut_T_1 = _eOut_T; // @[Multiplier.scala:117:{36,45}] wire _eOut_T_2 = |count; // @[Multiplier.scala:54:18, :117:83] wire _eOut_T_3 = _eOut_T_1 & _eOut_T_2; // @[Multiplier.scala:117:{36,74,83}] wire _eOut_T_4 = ~isHi; // @[Multiplier.scala:58:17, :118:7] wire _eOut_T_5 = _eOut_T_3 & _eOut_T_4; // @[Multiplier.scala:117:{74,91}, :118:7] wire [63:0] _eOut_T_6 = ~eOutMask; // @[Multiplier.scala:116:91, :118:26] wire [63:0] _eOut_T_7 = mplier & _eOut_T_6; // @[Multiplier.scala:109:24, :118:{24,26}] wire _eOut_T_8 = _eOut_T_7 == 64'h0; // @[Multiplier.scala:118:{24,37}] wire eOut = _eOut_T_5 & _eOut_T_8; // @[Multiplier.scala:117:91, :118:{13,37}] wire [11:0] _eOutRes_T_1 = 12'h40 - {1'h0, _eOutRes_T}; // @[Multiplier.scala:119:{38,46}] wire [10:0] _eOutRes_T_2 = _eOutRes_T_1[10:0]; // @[Multiplier.scala:119:38] wire [5:0] _eOutRes_T_3 = _eOutRes_T_2[5:0]; // @[Multiplier.scala:119:{38,64}] wire [128:0] eOutRes = mulReg >> _eOutRes_T_3; // @[Multiplier.scala:107:21, :119:{27,64}] wire [64:0] _nextMulReg1_T = nextMulReg[128:64]; // @[Multiplier.scala:113:25, :120:37] wire [129:0] _nextMulReg1_T_1 = eOut ? {1'h0, eOutRes} : nextMulReg; // @[Multiplier.scala:113:25, :118:13, :119:27, :120:55] wire [63:0] _nextMulReg1_T_2 = _nextMulReg1_T_1[63:0]; // @[Multiplier.scala:120:{55,82}] wire [128:0] nextMulReg1 = {_nextMulReg1_T, _nextMulReg1_T_2}; // @[Multiplier.scala:120:{26,37,82}] wire [64:0] _remainder_T = nextMulReg1[128:64]; // @[Multiplier.scala:120:26, :121:34] wire [63:0] _remainder_T_1 = nextMulReg1[63:0]; // @[Multiplier.scala:120:26, :121:67] wire [65:0] remainder_hi = {_remainder_T, nextMplierSign}; // @[Multiplier.scala:114:61, :121:{21,34}] wire [129:0] _remainder_T_2 = {remainder_hi, _remainder_T_1}; // @[Multiplier.scala:121:{21,67}] wire [7:0] _GEN_0 = {1'h0, count} + 8'h1; // @[Multiplier.scala:54:18, :123:20] wire [7:0] _count_T; // @[Multiplier.scala:123:20] assign _count_T = _GEN_0; // @[Multiplier.scala:123:20] wire [7:0] _count_T_2; // @[Multiplier.scala:144:20] assign _count_T_2 = _GEN_0; // @[Multiplier.scala:123:20, :144:20] wire [6:0] _count_T_1 = _count_T[6:0]; // @[Multiplier.scala:123:20] wire unrolls_less = subtractor[64]; // @[Multiplier.scala:88:37, :133:28] wire _divby0_T_1 = subtractor[64]; // @[Multiplier.scala:88:37, :133:28, :146:46] wire [63:0] _unrolls_T = remainder[127:64]; // @[Multiplier.scala:61:22, :134:24] wire [63:0] _unrolls_T_1 = subtractor[63:0]; // @[Multiplier.scala:88:37, :134:45] wire [63:0] _unrolls_T_2 = unrolls_less ? _unrolls_T : _unrolls_T_1; // @[Multiplier.scala:133:28, :134:{14,24,45}] wire _unrolls_T_4 = ~unrolls_less; // @[Multiplier.scala:133:28, :134:67] wire [127:0] unrolls_hi = {_unrolls_T_2, _unrolls_T_3}; // @[Multiplier.scala:134:{10,14,58}] wire [128:0] unrolls_0 = {unrolls_hi, _unrolls_T_4}; // @[Multiplier.scala:134:{10,67}] wire [2:0] _state_T = {1'h1, ~neg_out, 1'h1}; // @[Multiplier.scala:57:20, :139:19] wire [6:0] _count_T_3 = _count_T_2[6:0]; // @[Multiplier.scala:144:20] wire _divby0_T = ~(|count); // @[Multiplier.scala:54:18, :117:83, :146:24] wire _divby0_T_2 = ~_divby0_T_1; // @[Multiplier.scala:146:{35,46}] wire divby0 = _divby0_T & _divby0_T_2; // @[Multiplier.scala:146:{24,32,35}] wire [63:0] _divisorMSB_T = divisor[63:0]; // @[Multiplier.scala:60:20, :150:36] wire [31:0] divisorMSB_hi = _divisorMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] divisorMSB_lo = _divisorMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi = |divisorMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] divisorMSB_hi_1 = divisorMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] divisorMSB_lo_1 = divisorMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_1 = |divisorMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_2 = divisorMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_2 = divisorMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_2 = |divisorMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_3 = divisorMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_3 = divisorMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_3 = |divisorMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_1 = divisorMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_2 = divisorMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_3 = divisorMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_4 = _divisorMSB_T_2 ? 2'h2 : {1'h0, _divisorMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_5 = _divisorMSB_T_1 ? 2'h3 : _divisorMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_6 = divisorMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_7 = divisorMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_8 = divisorMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_9 = _divisorMSB_T_7 ? 2'h2 : {1'h0, _divisorMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_10 = _divisorMSB_T_6 ? 2'h3 : _divisorMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_11 = divisorMSB_useHi_3 ? _divisorMSB_T_5 : _divisorMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_12 = {divisorMSB_useHi_3, _divisorMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_4 = divisorMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_4 = divisorMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_4 = |divisorMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_13 = divisorMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_14 = divisorMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_15 = divisorMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_16 = _divisorMSB_T_14 ? 2'h2 : {1'h0, _divisorMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_17 = _divisorMSB_T_13 ? 2'h3 : _divisorMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_18 = divisorMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_19 = divisorMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_20 = divisorMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_21 = _divisorMSB_T_19 ? 2'h2 : {1'h0, _divisorMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_22 = _divisorMSB_T_18 ? 2'h3 : _divisorMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_23 = divisorMSB_useHi_4 ? _divisorMSB_T_17 : _divisorMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_24 = {divisorMSB_useHi_4, _divisorMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_25 = divisorMSB_useHi_2 ? _divisorMSB_T_12 : _divisorMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_26 = {divisorMSB_useHi_2, _divisorMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_5 = divisorMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_5 = divisorMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_5 = |divisorMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_6 = divisorMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_6 = divisorMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_6 = |divisorMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_27 = divisorMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_28 = divisorMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_29 = divisorMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_30 = _divisorMSB_T_28 ? 2'h2 : {1'h0, _divisorMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_31 = _divisorMSB_T_27 ? 2'h3 : _divisorMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_32 = divisorMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_33 = divisorMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_34 = divisorMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_35 = _divisorMSB_T_33 ? 2'h2 : {1'h0, _divisorMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_36 = _divisorMSB_T_32 ? 2'h3 : _divisorMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_37 = divisorMSB_useHi_6 ? _divisorMSB_T_31 : _divisorMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_38 = {divisorMSB_useHi_6, _divisorMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_7 = divisorMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_7 = divisorMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_7 = |divisorMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_39 = divisorMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_40 = divisorMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_41 = divisorMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_42 = _divisorMSB_T_40 ? 2'h2 : {1'h0, _divisorMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_43 = _divisorMSB_T_39 ? 2'h3 : _divisorMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_44 = divisorMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_45 = divisorMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_46 = divisorMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_47 = _divisorMSB_T_45 ? 2'h2 : {1'h0, _divisorMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_48 = _divisorMSB_T_44 ? 2'h3 : _divisorMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_49 = divisorMSB_useHi_7 ? _divisorMSB_T_43 : _divisorMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_50 = {divisorMSB_useHi_7, _divisorMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_51 = divisorMSB_useHi_5 ? _divisorMSB_T_38 : _divisorMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_52 = {divisorMSB_useHi_5, _divisorMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_53 = divisorMSB_useHi_1 ? _divisorMSB_T_26 : _divisorMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_54 = {divisorMSB_useHi_1, _divisorMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] divisorMSB_hi_8 = divisorMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] divisorMSB_lo_8 = divisorMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_8 = |divisorMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_9 = divisorMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_9 = divisorMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_9 = |divisorMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_10 = divisorMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_10 = divisorMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_10 = |divisorMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_55 = divisorMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_56 = divisorMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_57 = divisorMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_58 = _divisorMSB_T_56 ? 2'h2 : {1'h0, _divisorMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_59 = _divisorMSB_T_55 ? 2'h3 : _divisorMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_60 = divisorMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_61 = divisorMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_62 = divisorMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_63 = _divisorMSB_T_61 ? 2'h2 : {1'h0, _divisorMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_64 = _divisorMSB_T_60 ? 2'h3 : _divisorMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_65 = divisorMSB_useHi_10 ? _divisorMSB_T_59 : _divisorMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_66 = {divisorMSB_useHi_10, _divisorMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_11 = divisorMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_11 = divisorMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_11 = |divisorMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_67 = divisorMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_68 = divisorMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_69 = divisorMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_70 = _divisorMSB_T_68 ? 2'h2 : {1'h0, _divisorMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_71 = _divisorMSB_T_67 ? 2'h3 : _divisorMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_72 = divisorMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_73 = divisorMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_74 = divisorMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_75 = _divisorMSB_T_73 ? 2'h2 : {1'h0, _divisorMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_76 = _divisorMSB_T_72 ? 2'h3 : _divisorMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_77 = divisorMSB_useHi_11 ? _divisorMSB_T_71 : _divisorMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_78 = {divisorMSB_useHi_11, _divisorMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_79 = divisorMSB_useHi_9 ? _divisorMSB_T_66 : _divisorMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_80 = {divisorMSB_useHi_9, _divisorMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_12 = divisorMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_12 = divisorMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_12 = |divisorMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_13 = divisorMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_13 = divisorMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_13 = |divisorMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_81 = divisorMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_82 = divisorMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_83 = divisorMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_84 = _divisorMSB_T_82 ? 2'h2 : {1'h0, _divisorMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_85 = _divisorMSB_T_81 ? 2'h3 : _divisorMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_86 = divisorMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_87 = divisorMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_88 = divisorMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_89 = _divisorMSB_T_87 ? 2'h2 : {1'h0, _divisorMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_90 = _divisorMSB_T_86 ? 2'h3 : _divisorMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_91 = divisorMSB_useHi_13 ? _divisorMSB_T_85 : _divisorMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_92 = {divisorMSB_useHi_13, _divisorMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_14 = divisorMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_14 = divisorMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_14 = |divisorMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_93 = divisorMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_94 = divisorMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_95 = divisorMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_96 = _divisorMSB_T_94 ? 2'h2 : {1'h0, _divisorMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_97 = _divisorMSB_T_93 ? 2'h3 : _divisorMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_98 = divisorMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_99 = divisorMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_100 = divisorMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_101 = _divisorMSB_T_99 ? 2'h2 : {1'h0, _divisorMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_102 = _divisorMSB_T_98 ? 2'h3 : _divisorMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_103 = divisorMSB_useHi_14 ? _divisorMSB_T_97 : _divisorMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_104 = {divisorMSB_useHi_14, _divisorMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_105 = divisorMSB_useHi_12 ? _divisorMSB_T_92 : _divisorMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_106 = {divisorMSB_useHi_12, _divisorMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_107 = divisorMSB_useHi_8 ? _divisorMSB_T_80 : _divisorMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_108 = {divisorMSB_useHi_8, _divisorMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_109 = divisorMSB_useHi ? _divisorMSB_T_54 : _divisorMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _divisorMSB_T_110 = {divisorMSB_useHi, _divisorMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] divisorMSB = _divisorMSB_T_110; // @[CircuitMath.scala:36:10] wire [31:0] dividendMSB_hi = _dividendMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] dividendMSB_lo = _dividendMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi = |dividendMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] dividendMSB_hi_1 = dividendMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] dividendMSB_lo_1 = dividendMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_1 = |dividendMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_2 = dividendMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_2 = dividendMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_2 = |dividendMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_3 = dividendMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_3 = dividendMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_3 = |dividendMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_1 = dividendMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_2 = dividendMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_3 = dividendMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_4 = _dividendMSB_T_2 ? 2'h2 : {1'h0, _dividendMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_5 = _dividendMSB_T_1 ? 2'h3 : _dividendMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_6 = dividendMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_7 = dividendMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_8 = dividendMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_9 = _dividendMSB_T_7 ? 2'h2 : {1'h0, _dividendMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_10 = _dividendMSB_T_6 ? 2'h3 : _dividendMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_11 = dividendMSB_useHi_3 ? _dividendMSB_T_5 : _dividendMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_12 = {dividendMSB_useHi_3, _dividendMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_4 = dividendMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_4 = dividendMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_4 = |dividendMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_13 = dividendMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_14 = dividendMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_15 = dividendMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_16 = _dividendMSB_T_14 ? 2'h2 : {1'h0, _dividendMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_17 = _dividendMSB_T_13 ? 2'h3 : _dividendMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_18 = dividendMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_19 = dividendMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_20 = dividendMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_21 = _dividendMSB_T_19 ? 2'h2 : {1'h0, _dividendMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_22 = _dividendMSB_T_18 ? 2'h3 : _dividendMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_23 = dividendMSB_useHi_4 ? _dividendMSB_T_17 : _dividendMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_24 = {dividendMSB_useHi_4, _dividendMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_25 = dividendMSB_useHi_2 ? _dividendMSB_T_12 : _dividendMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_26 = {dividendMSB_useHi_2, _dividendMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_5 = dividendMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_5 = dividendMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_5 = |dividendMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_6 = dividendMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_6 = dividendMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_6 = |dividendMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_27 = dividendMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_28 = dividendMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_29 = dividendMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_30 = _dividendMSB_T_28 ? 2'h2 : {1'h0, _dividendMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_31 = _dividendMSB_T_27 ? 2'h3 : _dividendMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_32 = dividendMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_33 = dividendMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_34 = dividendMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_35 = _dividendMSB_T_33 ? 2'h2 : {1'h0, _dividendMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_36 = _dividendMSB_T_32 ? 2'h3 : _dividendMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_37 = dividendMSB_useHi_6 ? _dividendMSB_T_31 : _dividendMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_38 = {dividendMSB_useHi_6, _dividendMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_7 = dividendMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_7 = dividendMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_7 = |dividendMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_39 = dividendMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_40 = dividendMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_41 = dividendMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_42 = _dividendMSB_T_40 ? 2'h2 : {1'h0, _dividendMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_43 = _dividendMSB_T_39 ? 2'h3 : _dividendMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_44 = dividendMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_45 = dividendMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_46 = dividendMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_47 = _dividendMSB_T_45 ? 2'h2 : {1'h0, _dividendMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_48 = _dividendMSB_T_44 ? 2'h3 : _dividendMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_49 = dividendMSB_useHi_7 ? _dividendMSB_T_43 : _dividendMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_50 = {dividendMSB_useHi_7, _dividendMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_51 = dividendMSB_useHi_5 ? _dividendMSB_T_38 : _dividendMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_52 = {dividendMSB_useHi_5, _dividendMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_53 = dividendMSB_useHi_1 ? _dividendMSB_T_26 : _dividendMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_54 = {dividendMSB_useHi_1, _dividendMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] dividendMSB_hi_8 = dividendMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] dividendMSB_lo_8 = dividendMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_8 = |dividendMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_9 = dividendMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_9 = dividendMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_9 = |dividendMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_10 = dividendMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_10 = dividendMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_10 = |dividendMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_55 = dividendMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_56 = dividendMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_57 = dividendMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_58 = _dividendMSB_T_56 ? 2'h2 : {1'h0, _dividendMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_59 = _dividendMSB_T_55 ? 2'h3 : _dividendMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_60 = dividendMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_61 = dividendMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_62 = dividendMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_63 = _dividendMSB_T_61 ? 2'h2 : {1'h0, _dividendMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_64 = _dividendMSB_T_60 ? 2'h3 : _dividendMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_65 = dividendMSB_useHi_10 ? _dividendMSB_T_59 : _dividendMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_66 = {dividendMSB_useHi_10, _dividendMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_11 = dividendMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_11 = dividendMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_11 = |dividendMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_67 = dividendMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_68 = dividendMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_69 = dividendMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_70 = _dividendMSB_T_68 ? 2'h2 : {1'h0, _dividendMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_71 = _dividendMSB_T_67 ? 2'h3 : _dividendMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_72 = dividendMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_73 = dividendMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_74 = dividendMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_75 = _dividendMSB_T_73 ? 2'h2 : {1'h0, _dividendMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_76 = _dividendMSB_T_72 ? 2'h3 : _dividendMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_77 = dividendMSB_useHi_11 ? _dividendMSB_T_71 : _dividendMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_78 = {dividendMSB_useHi_11, _dividendMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_79 = dividendMSB_useHi_9 ? _dividendMSB_T_66 : _dividendMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_80 = {dividendMSB_useHi_9, _dividendMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_12 = dividendMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_12 = dividendMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_12 = |dividendMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_13 = dividendMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_13 = dividendMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_13 = |dividendMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_81 = dividendMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_82 = dividendMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_83 = dividendMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_84 = _dividendMSB_T_82 ? 2'h2 : {1'h0, _dividendMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_85 = _dividendMSB_T_81 ? 2'h3 : _dividendMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_86 = dividendMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_87 = dividendMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_88 = dividendMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_89 = _dividendMSB_T_87 ? 2'h2 : {1'h0, _dividendMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_90 = _dividendMSB_T_86 ? 2'h3 : _dividendMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_91 = dividendMSB_useHi_13 ? _dividendMSB_T_85 : _dividendMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_92 = {dividendMSB_useHi_13, _dividendMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_14 = dividendMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_14 = dividendMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_14 = |dividendMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_93 = dividendMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_94 = dividendMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_95 = dividendMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_96 = _dividendMSB_T_94 ? 2'h2 : {1'h0, _dividendMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_97 = _dividendMSB_T_93 ? 2'h3 : _dividendMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_98 = dividendMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_99 = dividendMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_100 = dividendMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_101 = _dividendMSB_T_99 ? 2'h2 : {1'h0, _dividendMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_102 = _dividendMSB_T_98 ? 2'h3 : _dividendMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_103 = dividendMSB_useHi_14 ? _dividendMSB_T_97 : _dividendMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_104 = {dividendMSB_useHi_14, _dividendMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_105 = dividendMSB_useHi_12 ? _dividendMSB_T_92 : _dividendMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_106 = {dividendMSB_useHi_12, _dividendMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_107 = dividendMSB_useHi_8 ? _dividendMSB_T_80 : _dividendMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_108 = {dividendMSB_useHi_8, _dividendMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_109 = dividendMSB_useHi ? _dividendMSB_T_54 : _dividendMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _dividendMSB_T_110 = {dividendMSB_useHi, _dividendMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] dividendMSB = _dividendMSB_T_110; // @[CircuitMath.scala:36:10] wire [6:0] _eOutPos_T = {1'h0, dividendMSB} - {1'h0, divisorMSB}; // @[Multiplier.scala:150:48, :151:51, :152:35] wire [5:0] _eOutPos_T_1 = _eOutPos_T[5:0]; // @[Multiplier.scala:152:35] wire [5:0] eOutPos = ~_eOutPos_T_1; // @[Multiplier.scala:152:{21,35}] wire [5:0] _count_T_4 = eOutPos; // @[Multiplier.scala:152:21, :156:26] wire _eOut_T_9 = ~(|count); // @[Multiplier.scala:54:18, :117:83, :146:24, :153:24] wire _eOut_T_10 = ~divby0; // @[Multiplier.scala:146:32, :153:35] wire _eOut_T_11 = _eOut_T_9 & _eOut_T_10; // @[Multiplier.scala:153:{24,32,35}] wire _eOut_T_12 = |eOutPos; // @[Multiplier.scala:152:21, :153:54] wire eOut_1 = _eOut_T_11 & _eOut_T_12; // @[Multiplier.scala:153:{32,43,54}] wire [126:0] _remainder_T_4 = {63'h0, _remainder_T_3} << eOutPos; // @[Multiplier.scala:152:21, :155:{31,39}] wire _state_T_1 = lhs_sign | rhs_sign; // @[Multiplier.scala:81:23, :165:46] wire [2:0] _state_T_2 = {1'h0, ~_state_T_1, 1'h1}; // @[Multiplier.scala:165:{36,46}] wire [2:0] _state_T_3 = cmdMul ? 3'h2 : _state_T_2; // @[Multiplier.scala:75:107, :165:{17,36}] wire _count_T_6 = _count_T_5; // @[Multiplier.scala:78:{50,60}] wire _count_T_7 = cmdMul & _count_T_6; // @[Multiplier.scala:75:107, :78:50, :168:46] wire [2:0] _count_T_8 = {_count_T_7, 2'h0}; // @[Multiplier.scala:168:{38,46}] wire _neg_out_T = lhs_sign != rhs_sign; // @[Multiplier.scala:81:23, :169:46] wire _neg_out_T_1 = cmdHi ? lhs_sign : _neg_out_T; // @[Multiplier.scala:75:107, :81:23, :169:{19,46}] wire [64:0] _divisor_T = {rhs_sign, rhs_in}; // @[Multiplier.scala:81:23, :83:9, :170:19] wire [2:0] _outMul_T_1 = state & 3'h1; // @[Multiplier.scala:51:22, :175:23] wire outMul = _outMul_T_1 == 3'h0; // @[Multiplier.scala:175:{23,52}] wire _loOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _loOut_T_1 = _loOut_T; // @[Multiplier.scala:78:{50,60}] wire _loOut_T_2 = _loOut_T_1; // @[Multiplier.scala:78:50, :176:30] wire _loOut_T_3 = _loOut_T_2 & outMul; // @[Multiplier.scala:175:52, :176:{30,48}] wire [31:0] _loOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65] wire [31:0] _hiOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65, :177:66] wire [31:0] _loOut_T_5 = result[31:0]; // @[Multiplier.scala:89:19, :176:82] wire [31:0] loOut = _loOut_T_3 ? _loOut_T_4 : _loOut_T_5; // @[Multiplier.scala:176:{18,48,65,82}] wire _hiOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _hiOut_T_1 = _hiOut_T; // @[Multiplier.scala:78:{50,60}] wire _hiOut_T_2 = loOut[31]; // @[Multiplier.scala:176:18, :177:50] wire [31:0] _hiOut_T_3 = {32{_hiOut_T_2}}; // @[Multiplier.scala:177:{39,50}] wire [31:0] hiOut = _hiOut_T_1 ? _hiOut_T_3 : _hiOut_T_4; // @[Multiplier.scala:78:50, :177:{18,39,66}] assign _io_resp_bits_data_T = {hiOut, loOut}; // @[Multiplier.scala:176:18, :177:18, :180:27] assign io_resp_bits_data_0 = _io_resp_bits_data_T; // @[Multiplier.scala:40:7, :180:27] assign _io_resp_bits_full_data_T_2 = {_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1}; // @[Multiplier.scala:181:{32,42,63}] assign io_resp_bits_full_data = _io_resp_bits_full_data_T_2; // @[Multiplier.scala:40:7, :181:32] wire _io_resp_valid_T = state == 3'h6; // @[Multiplier.scala:51:22, :182:27] wire _io_resp_valid_T_1 = &state; // @[Multiplier.scala:51:22, :182:51] assign _io_resp_valid_T_2 = _io_resp_valid_T | _io_resp_valid_T_1; // @[Multiplier.scala:182:{27,42,51}] assign io_resp_valid_0 = _io_resp_valid_T_2; // @[Multiplier.scala:40:7, :182:42] assign _io_req_ready_T = state == 3'h0; // @[Multiplier.scala:51:22, :183:25] assign io_req_ready_0 = _io_req_ready_T; // @[Multiplier.scala:40:7, :183:25] wire _T_10 = state == 3'h1; // @[Multiplier.scala:51:22, :92:39] wire _T_13 = state == 3'h5; // @[Multiplier.scala:51:22, :101:39] wire _T_14 = state == 3'h2; // @[Multiplier.scala:51:22, :106:39] wire _GEN_1 = _T_14 & (eOut | count == 7'h7); // @[Multiplier.scala:54:18, :101:57, :106:{39,50}, :118:13, :124:{16,25,55}, :125:13] wire _T_17 = state == 3'h3; // @[Multiplier.scala:51:22, :129:39] wire _T_18 = count == 7'h40; // @[Multiplier.scala:54:18, :138:17] wire _T_23 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Multiplier.scala:40:7] if (reset) // @[Multiplier.scala:40:7] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_23) // @[Decoupled.scala:51:35] state <= _state_T_3; // @[Multiplier.scala:51:22, :165:17] else if (io_resp_ready_0 & io_resp_valid_0 | io_kill_0) // @[Decoupled.scala:51:35] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_17 & _T_18) // @[Multiplier.scala:106:50, :129:{39,50}, :138:{17,42}, :139:13] state <= _state_T; // @[Multiplier.scala:51:22, :139:19] else if (_GEN_1) // @[Multiplier.scala:101:57, :106:50, :124:55, :125:13] state <= 3'h6; // @[Multiplier.scala:51:22] else if (_T_13) // @[Multiplier.scala:101:39] state <= 3'h7; // @[Multiplier.scala:51:22] else if (_T_10) // @[Multiplier.scala:92:39] state <= 3'h3; // @[Multiplier.scala:51:22] if (_T_23) begin // @[Decoupled.scala:51:35] req_fn <= io_req_bits_fn_0; // @[Multiplier.scala:40:7, :53:16] req_dw <= io_req_bits_dw_0; // @[Multiplier.scala:40:7, :53:16] req_in1 <= io_req_bits_in1_0; // @[Multiplier.scala:40:7, :53:16] req_in2 <= io_req_bits_in2_0; // @[Multiplier.scala:40:7, :53:16] req_tag <= io_req_bits_tag_0; // @[Multiplier.scala:40:7, :53:16] count <= {4'h0, _count_T_8}; // @[Multiplier.scala:54:18, :114:32, :168:{11,38}] isHi <= cmdHi; // @[Multiplier.scala:58:17, :75:107] divisor <= _divisor_T; // @[Multiplier.scala:60:20, :170:19] remainder <= {66'h0, lhs_in}; // @[Multiplier.scala:61:22, :83:9, :94:17, :171:15] end else begin // @[Decoupled.scala:51:35] if (_T_17) begin // @[Multiplier.scala:129:39] count <= eOut_1 ? {1'h0, _count_T_4} : _count_T_3; // @[Multiplier.scala:54:18, :144:{11,20}, :153:43, :154:19, :156:{15,26}] remainder <= eOut_1 ? {3'h0, _remainder_T_4} : {1'h0, unrolls_0}; // @[Multiplier.scala:61:22, :134:10, :137:15, :153:43, :154:19, :155:{19,39}] end else if (_T_14) begin // @[Multiplier.scala:106:39] count <= _count_T_1; // @[Multiplier.scala:54:18, :123:20] remainder <= _remainder_T_2; // @[Multiplier.scala:61:22, :121:21] end else if (_T_13 | _T_10 & remainder[63]) // @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15] remainder <= {66'h0, negated_remainder}; // @[Multiplier.scala:61:22, :90:27, :94:17] if (_T_10 & divisor[63]) // @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15] divisor <= subtractor; // @[Multiplier.scala:60:20, :88:37] end neg_out <= _T_23 ? _neg_out_T_1 : ~(_T_17 & divby0 & ~isHi) & neg_out; // @[Decoupled.scala:51:35] resHi <= ~_T_23 & (_T_17 & _T_18 | _GEN_1 ? isHi : ~_T_13 & resHi); // @[Decoupled.scala:51:35] always @(posedge) assign io_req_ready = io_req_ready_0; // @[Multiplier.scala:40:7] assign io_resp_valid = io_resp_valid_0; // @[Multiplier.scala:40:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[Multiplier.scala:40:7] assign io_resp_bits_tag = io_resp_bits_tag_0; // @[Multiplier.scala:40:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_51 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_102 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_103 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_51( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {9'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module FrontBus : output auto : { flip coupler_from_port_named_serial_tl_0_in_buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coupler_from_debug_sb_widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip fbus_clock_groups_in : { member : { fbus_0 : { clock : Clock, reset : Reset}}}, bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst fbus_clock_groups of ClockGroupAggregator_fbus inst clockGroup of ClockGroup_2 inst fixedClockNode of FixedClockBroadcast_2_1 inst broadcast of BundleBridgeNexus_NoOutput_2 inst fbus_xbar of TLXbar_fbus_i2_o1_a32d64s5k5z4u connect fbus_xbar.clock, childClock connect fbus_xbar.reset, childReset inst buffer of TLBuffer_a32d64s5k5z4u connect buffer.clock, childClock connect buffer.reset, childReset inst coupler_from_debug_sb of TLInterconnectCoupler_fbus_from_debug_sb connect coupler_from_debug_sb.clock, childClock connect coupler_from_debug_sb.reset, childReset inst coupler_from_port_named_serial_tl_0_in of TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in connect coupler_from_port_named_serial_tl_0_in.clock, childClock connect coupler_from_port_named_serial_tl_0_in.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn connect clockGroup.auto.in, fbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect buffer.auto.in, fbus_xbar.auto.anon_out connect buffer.auto.out.d, bus_xingIn.d connect bus_xingIn.a.bits, buffer.auto.out.a.bits connect bus_xingIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, bus_xingIn.a.ready connect fbus_xbar.auto.anon_in_0, coupler_from_debug_sb.auto.tl_out connect fbus_xbar.auto.anon_in_1, coupler_from_port_named_serial_tl_0_in.auto.tl_out connect auto.bus_xing_out, bus_xingOut connect fbus_clock_groups.auto.in, auto.fbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_from_debug_sb.auto.widget_anon_in, auto.coupler_from_debug_sb_widget_anon_in connect coupler_from_port_named_serial_tl_0_in.auto.buffer_in, auto.coupler_from_port_named_serial_tl_0_in_buffer_in connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset

module FrontBus( // @[ClockDomain.scala:14:9] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_debug_sb_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_debug_sb_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_fbus_clock_groups_in_member_fbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_fbus_clock_groups_in_member_fbus_0_reset, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [3:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_from_port_named_serial_tl_0_in_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _coupler_from_debug_sb_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_from_debug_sb_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [3:0] _coupler_from_debug_sb_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [31:0] _coupler_from_debug_sb_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_from_debug_sb_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_from_debug_sb_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_from_debug_sb_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [4:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire [4:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _fbus_xbar_auto_anon_in_1_a_ready; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_1_d_valid; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_in_1_d_bits_opcode; // @[BusWrapper.scala:240:32] wire [1:0] _fbus_xbar_auto_anon_in_1_d_bits_param; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_1_d_bits_size; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_1_d_bits_source; // @[BusWrapper.scala:240:32] wire [4:0] _fbus_xbar_auto_anon_in_1_d_bits_sink; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_1_d_bits_denied; // @[BusWrapper.scala:240:32] wire [63:0] _fbus_xbar_auto_anon_in_1_d_bits_data; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_1_d_bits_corrupt; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_a_ready; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_d_valid; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_in_0_d_bits_opcode; // @[BusWrapper.scala:240:32] wire [1:0] _fbus_xbar_auto_anon_in_0_d_bits_param; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_0_d_bits_size; // @[BusWrapper.scala:240:32] wire [4:0] _fbus_xbar_auto_anon_in_0_d_bits_sink; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_d_bits_denied; // @[BusWrapper.scala:240:32] wire [63:0] _fbus_xbar_auto_anon_in_0_d_bits_data; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_d_bits_corrupt; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_out_a_valid; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_out_a_bits_opcode; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_out_a_bits_param; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_out_a_bits_size; // @[BusWrapper.scala:240:32] wire [4:0] _fbus_xbar_auto_anon_out_a_bits_source; // @[BusWrapper.scala:240:32] wire [31:0] _fbus_xbar_auto_anon_out_a_bits_address; // @[BusWrapper.scala:240:32] wire [7:0] _fbus_xbar_auto_anon_out_a_bits_mask; // @[BusWrapper.scala:240:32] wire [63:0] _fbus_xbar_auto_anon_out_a_bits_data; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_out_a_bits_corrupt; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_out_d_ready; // @[BusWrapper.scala:240:32] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (auto_fbus_clock_groups_in_member_fbus_0_clock), .auto_anon_in_reset (auto_fbus_clock_groups_in_member_fbus_0_reset), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset), .auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock), .auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset) ); // @[ClockGroup.scala:115:114] TLXbar_fbus_i2_o1_a32d64s5k5z4u fbus_xbar ( // @[BusWrapper.scala:240:32] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_anon_in_1_a_ready (_fbus_xbar_auto_anon_in_1_a_ready), .auto_anon_in_1_a_valid (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_opcode (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_param (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_size (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_source (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_address (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_mask (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_data (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_corrupt (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_in_1_d_ready (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_anon_in_1_d_valid (_fbus_xbar_auto_anon_in_1_d_valid), .auto_anon_in_1_d_bits_opcode (_fbus_xbar_auto_anon_in_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (_fbus_xbar_auto_anon_in_1_d_bits_param), .auto_anon_in_1_d_bits_size (_fbus_xbar_auto_anon_in_1_d_bits_size), .auto_anon_in_1_d_bits_source (_fbus_xbar_auto_anon_in_1_d_bits_source), .auto_anon_in_1_d_bits_sink (_fbus_xbar_auto_anon_in_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (_fbus_xbar_auto_anon_in_1_d_bits_denied), .auto_anon_in_1_d_bits_data (_fbus_xbar_auto_anon_in_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (_fbus_xbar_auto_anon_in_1_d_bits_corrupt), .auto_anon_in_0_a_ready (_fbus_xbar_auto_anon_in_0_a_ready), .auto_anon_in_0_a_valid (_coupler_from_debug_sb_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_opcode (_coupler_from_debug_sb_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_size (_coupler_from_debug_sb_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_address (_coupler_from_debug_sb_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_mask (_coupler_from_debug_sb_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_data (_coupler_from_debug_sb_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_anon_in_0_d_ready (_coupler_from_debug_sb_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_anon_in_0_d_valid (_fbus_xbar_auto_anon_in_0_d_valid), .auto_anon_in_0_d_bits_opcode (_fbus_xbar_auto_anon_in_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (_fbus_xbar_auto_anon_in_0_d_bits_param), .auto_anon_in_0_d_bits_size (_fbus_xbar_auto_anon_in_0_d_bits_size), .auto_anon_in_0_d_bits_sink (_fbus_xbar_auto_anon_in_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (_fbus_xbar_auto_anon_in_0_d_bits_denied), .auto_anon_in_0_d_bits_data (_fbus_xbar_auto_anon_in_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (_fbus_xbar_auto_anon_in_0_d_bits_corrupt), .auto_anon_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_anon_out_a_valid (_fbus_xbar_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fbus_xbar_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fbus_xbar_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fbus_xbar_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fbus_xbar_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fbus_xbar_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fbus_xbar_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fbus_xbar_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fbus_xbar_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fbus_xbar_auto_anon_out_d_ready), .auto_anon_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[BusWrapper.scala:240:32] TLBuffer_a32d64s5k5z4u buffer ( // @[Buffer.scala:75:28] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_fbus_xbar_auto_anon_out_a_valid), // @[BusWrapper.scala:240:32] .auto_in_a_bits_opcode (_fbus_xbar_auto_anon_out_a_bits_opcode), // @[BusWrapper.scala:240:32] .auto_in_a_bits_param (_fbus_xbar_auto_anon_out_a_bits_param), // @[BusWrapper.scala:240:32] .auto_in_a_bits_size (_fbus_xbar_auto_anon_out_a_bits_size), // @[BusWrapper.scala:240:32] .auto_in_a_bits_source (_fbus_xbar_auto_anon_out_a_bits_source), // @[BusWrapper.scala:240:32] .auto_in_a_bits_address (_fbus_xbar_auto_anon_out_a_bits_address), // @[BusWrapper.scala:240:32] .auto_in_a_bits_mask (_fbus_xbar_auto_anon_out_a_bits_mask), // @[BusWrapper.scala:240:32] .auto_in_a_bits_data (_fbus_xbar_auto_anon_out_a_bits_data), // @[BusWrapper.scala:240:32] .auto_in_a_bits_corrupt (_fbus_xbar_auto_anon_out_a_bits_corrupt), // @[BusWrapper.scala:240:32] .auto_in_d_ready (_fbus_xbar_auto_anon_out_d_ready), // @[BusWrapper.scala:240:32] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (auto_bus_xing_out_a_ready), .auto_out_a_valid (auto_bus_xing_out_a_valid), .auto_out_a_bits_opcode (auto_bus_xing_out_a_bits_opcode), .auto_out_a_bits_param (auto_bus_xing_out_a_bits_param), .auto_out_a_bits_size (auto_bus_xing_out_a_bits_size), .auto_out_a_bits_source (auto_bus_xing_out_a_bits_source), .auto_out_a_bits_address (auto_bus_xing_out_a_bits_address), .auto_out_a_bits_mask (auto_bus_xing_out_a_bits_mask), .auto_out_a_bits_data (auto_bus_xing_out_a_bits_data), .auto_out_a_bits_corrupt (auto_bus_xing_out_a_bits_corrupt), .auto_out_d_ready (auto_bus_xing_out_d_ready), .auto_out_d_valid (auto_bus_xing_out_d_valid), .auto_out_d_bits_opcode (auto_bus_xing_out_d_bits_opcode), .auto_out_d_bits_param (auto_bus_xing_out_d_bits_param), .auto_out_d_bits_size (auto_bus_xing_out_d_bits_size), .auto_out_d_bits_source (auto_bus_xing_out_d_bits_source), .auto_out_d_bits_sink (auto_bus_xing_out_d_bits_sink), .auto_out_d_bits_denied (auto_bus_xing_out_d_bits_denied), .auto_out_d_bits_data (auto_bus_xing_out_d_bits_data), .auto_out_d_bits_corrupt (auto_bus_xing_out_d_bits_corrupt) ); // @[Buffer.scala:75:28] TLInterconnectCoupler_fbus_from_debug_sb coupler_from_debug_sb ( // @[LazyScope.scala:98:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_widget_anon_in_a_ready (auto_coupler_from_debug_sb_widget_anon_in_a_ready), .auto_widget_anon_in_a_valid (auto_coupler_from_debug_sb_widget_anon_in_a_valid), .auto_widget_anon_in_a_bits_opcode (auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode), .auto_widget_anon_in_a_bits_size (auto_coupler_from_debug_sb_widget_anon_in_a_bits_size), .auto_widget_anon_in_a_bits_address (auto_coupler_from_debug_sb_widget_anon_in_a_bits_address), .auto_widget_anon_in_a_bits_data (auto_coupler_from_debug_sb_widget_anon_in_a_bits_data), .auto_widget_anon_in_d_ready (auto_coupler_from_debug_sb_widget_anon_in_d_ready), .auto_widget_anon_in_d_valid (auto_coupler_from_debug_sb_widget_anon_in_d_valid), .auto_widget_anon_in_d_bits_opcode (auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), .auto_widget_anon_in_d_bits_param (auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), .auto_widget_anon_in_d_bits_size (auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), .auto_widget_anon_in_d_bits_sink (auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), .auto_widget_anon_in_d_bits_denied (auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), .auto_widget_anon_in_d_bits_data (auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), .auto_tl_out_a_ready (_fbus_xbar_auto_anon_in_0_a_ready), // @[BusWrapper.scala:240:32] .auto_tl_out_a_valid (_coupler_from_debug_sb_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_from_debug_sb_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_size (_coupler_from_debug_sb_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_address (_coupler_from_debug_sb_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_from_debug_sb_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_from_debug_sb_auto_tl_out_a_bits_data), .auto_tl_out_d_ready (_coupler_from_debug_sb_auto_tl_out_d_ready), .auto_tl_out_d_valid (_fbus_xbar_auto_anon_in_0_d_valid), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_opcode (_fbus_xbar_auto_anon_in_0_d_bits_opcode), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_param (_fbus_xbar_auto_anon_in_0_d_bits_param), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_size (_fbus_xbar_auto_anon_in_0_d_bits_size), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_sink (_fbus_xbar_auto_anon_in_0_d_bits_sink), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_denied (_fbus_xbar_auto_anon_in_0_d_bits_denied), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_data (_fbus_xbar_auto_anon_in_0_d_bits_data), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_corrupt (_fbus_xbar_auto_anon_in_0_d_bits_corrupt) // @[BusWrapper.scala:240:32] ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in coupler_from_port_named_serial_tl_0_in ( // @[LazyScope.scala:98:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_buffer_in_a_ready (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), .auto_buffer_in_a_valid (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid), .auto_buffer_in_a_bits_opcode (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode), .auto_buffer_in_a_bits_param (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param), .auto_buffer_in_a_bits_size (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size), .auto_buffer_in_a_bits_source (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source), .auto_buffer_in_a_bits_address (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address), .auto_buffer_in_a_bits_mask (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask), .auto_buffer_in_a_bits_data (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data), .auto_buffer_in_a_bits_corrupt (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt), .auto_buffer_in_d_ready (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready), .auto_buffer_in_d_valid (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), .auto_buffer_in_d_bits_opcode (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), .auto_buffer_in_d_bits_param (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), .auto_buffer_in_d_bits_size (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), .auto_buffer_in_d_bits_source (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), .auto_buffer_in_d_bits_sink (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), .auto_buffer_in_d_bits_denied (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), .auto_buffer_in_d_bits_data (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), .auto_buffer_in_d_bits_corrupt (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), .auto_tl_out_a_ready (_fbus_xbar_auto_anon_in_1_a_ready), // @[BusWrapper.scala:240:32] .auto_tl_out_a_valid (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_param (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_param), .auto_tl_out_a_bits_size (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_source (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_source), .auto_tl_out_a_bits_address (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_data), .auto_tl_out_a_bits_corrupt (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_corrupt), .auto_tl_out_d_ready (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_d_ready), .auto_tl_out_d_valid (_fbus_xbar_auto_anon_in_1_d_valid), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_opcode (_fbus_xbar_auto_anon_in_1_d_bits_opcode), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_param (_fbus_xbar_auto_anon_in_1_d_bits_param), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_size (_fbus_xbar_auto_anon_in_1_d_bits_size), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_source (_fbus_xbar_auto_anon_in_1_d_bits_source), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_sink (_fbus_xbar_auto_anon_in_1_d_bits_sink), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_denied (_fbus_xbar_auto_anon_in_1_d_bits_denied), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_data (_fbus_xbar_auto_anon_in_1_d_bits_data), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_corrupt (_fbus_xbar_auto_anon_in_1_d_bits_corrupt) // @[BusWrapper.scala:240:32] ); // @[LazyScope.scala:98:27] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_88 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_177 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_178 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_179 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_180 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_88( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module Tile_4 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_260 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_4( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_260 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MSHR_1 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<2>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 1, 0) node _req_clientBit_T = shr(request.source, 2) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<4>(0h8)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<2>(0h2)) node req_clientBit = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<2>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 1, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 2) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<4>(0h8)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<2>(0h2)) node probe_bit = and(_probe_bit_T_3, _probe_bit_T_4) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<2>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 1, 0) node _new_clientBit_T = shr(new_request.source, 2) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<4>(0h8)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<2>(0h2)) node new_clientBit = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)

module MSHR_1( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire req_clientBit = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:56:48] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire probe_bit = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:56:48] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire new_clientBit = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module PE_237 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_237( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a21d64s10k1z3u_1 : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)

module Repeater_TLBundleA_a21d64s10k1z3u_1( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [20:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [20:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [9:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [20:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [9:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [20:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [9:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [20:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [9:0] saved_source; // @[Repeater.scala:21:18] reg [20:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_8 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}} inst input_buffer of InputBuffer_8 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) inst route_arbiter of Arbiter6_RouteComputerReq_8 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<6>}[6], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(UInt<2>(0h2), io.in.flit[0].bits.flow.egress_node_id) when _T_11 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_12 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_12 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_13 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_13 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_14 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_14 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_15 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_15 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_16 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_16 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_17 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_17 : connect states[5].g, UInt<3>(0h2) node _T_18 = and(io.router_req.ready, io.router_req.valid) when _T_18 : node _T_19 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_19, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_23 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_23 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_24 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_24 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_25 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_25 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_26 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_26 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_27 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_27 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_28 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_28 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<6>, clock, reset, UInt<6>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}[6] wire vcalloc_vals : UInt<1>[6] node vcalloc_filter_lo_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[3]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[3]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_16, UInt<12>(0h800), UInt<12>(0h0)) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_15, UInt<12>(0h400), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_14, UInt<12>(0h200), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_13, UInt<12>(0h100), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_12, UInt<12>(0h80), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_11, UInt<12>(0h40), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_10, UInt<12>(0h20), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_9, UInt<12>(0h10), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_8, UInt<12>(0h8), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_7, UInt<12>(0h4), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_6, UInt<12>(0h2), _vcalloc_filter_T_26) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<12>(0h1), _vcalloc_filter_T_27) node _vcalloc_sel_T = bits(vcalloc_filter, 5, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 6) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_29 = and(io.router_req.ready, io.router_req.valid) when _T_29 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_31 = or(_T_30, vcalloc_vals[2]) node _T_32 = or(_T_31, vcalloc_vals[3]) node _T_33 = or(_T_32, vcalloc_vals[4]) node _T_34 = or(_T_33, vcalloc_vals[5]) when _T_34 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = bits(vcalloc_sel, 0, 0) node _mask_T_10 = bits(vcalloc_sel, 1, 1) node _mask_T_11 = bits(vcalloc_sel, 2, 2) node _mask_T_12 = bits(vcalloc_sel, 3, 3) node _mask_T_13 = bits(vcalloc_sel, 4, 4) node _mask_T_14 = bits(vcalloc_sel, 5, 5) node _mask_T_15 = mux(_mask_T_9, _mask_T_3, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_10, _mask_T_4, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_11, _mask_T_5, UInt<1>(0h0)) node _mask_T_18 = mux(_mask_T_12, _mask_T_6, UInt<1>(0h0)) node _mask_T_19 = mux(_mask_T_13, _mask_T_7, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_14, _mask_T_8, UInt<1>(0h0)) node _mask_T_21 = or(_mask_T_15, _mask_T_16) node _mask_T_22 = or(_mask_T_21, _mask_T_17) node _mask_T_23 = or(_mask_T_22, _mask_T_18) node _mask_T_24 = or(_mask_T_23, _mask_T_19) node _mask_T_25 = or(_mask_T_24, _mask_T_20) wire _mask_WIRE : UInt<6> connect _mask_WIRE, _mask_T_25 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_4 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[6] node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_14 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_15 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_15, _io_vcalloc_req_bits_T_11) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_20) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_21) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_22) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_33) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_38 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_44) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_60 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_68 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_63) node _io_vcalloc_req_bits_T_69 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_70 = or(_io_vcalloc_req_bits_T_69, _io_vcalloc_req_bits_T_65) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_70, _io_vcalloc_req_bits_T_66) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_71 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>[1] node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_72, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_76) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_77) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_9[0], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_9 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[1] node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_90 = or(_io_vcalloc_req_bits_T_89, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_90, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_88) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_93 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[1] node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_95) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_113 = or(_io_vcalloc_req_bits_T_112, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_114 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_114, _io_vcalloc_req_bits_T_110) wire _io_vcalloc_req_bits_WIRE_15 : UInt<3> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_115 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_15 wire _io_vcalloc_req_bits_WIRE_16 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_120) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_121) wire _io_vcalloc_req_bits_WIRE_17 : UInt<2> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_126 connect _io_vcalloc_req_bits_WIRE_16.egress_node_id, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_133, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_132) wire _io_vcalloc_req_bits_WIRE_18 : UInt<4> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_137 connect _io_vcalloc_req_bits_WIRE_16.egress_node, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_138 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_139 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_139) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_144, _io_vcalloc_req_bits_T_140) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_143) wire _io_vcalloc_req_bits_WIRE_19 : UInt<2> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE_16.ingress_node_id, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_154 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_149, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_152) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_153) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_154) wire _io_vcalloc_req_bits_WIRE_20 : UInt<4> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_159 connect _io_vcalloc_req_bits_WIRE_16.ingress_node, _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_21 : UInt<2> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_170 connect _io_vcalloc_req_bits_WIRE_16.vnet_id, _io_vcalloc_req_bits_WIRE_21 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_16 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].flow, states[0].flow node _T_35 = bits(vcalloc_sel, 0, 0) node _T_36 = and(vcalloc_vals[0], _T_35) node _T_37 = and(_T_36, io.vcalloc_req.ready) when _T_37 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_38 = bits(vcalloc_sel, 1, 1) node _T_39 = and(vcalloc_vals[1], _T_38) node _T_40 = and(_T_39, io.vcalloc_req.ready) when _T_40 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].flow, states[2].flow node _T_41 = bits(vcalloc_sel, 2, 2) node _T_42 = and(vcalloc_vals[2], _T_41) node _T_43 = and(_T_42, io.vcalloc_req.ready) when _T_43 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].flow, states[3].flow node _T_44 = bits(vcalloc_sel, 3, 3) node _T_45 = and(vcalloc_vals[3], _T_44) node _T_46 = and(_T_45, io.vcalloc_req.ready) when _T_46 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].flow, states[4].flow node _T_47 = bits(vcalloc_sel, 4, 4) node _T_48 = and(vcalloc_vals[4], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].flow, states[5].flow node _T_50 = bits(vcalloc_sel, 5, 5) node _T_51 = and(vcalloc_vals[5], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[5].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[3], _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(_io_debug_va_stall_T_3, _io_debug_va_stall_T_7) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 2, 0) node _io_debug_va_stall_T_10 = sub(_io_debug_va_stall_T_9, io.vcalloc_req.ready) node _io_debug_va_stall_T_11 = tail(_io_debug_va_stall_T_10, 1) connect io.debug.va_stall, _io_debug_va_stall_T_11 node _T_53 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_53 : node _T_54 = bits(vcalloc_sel, 0, 0) when _T_54 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_55 = eq(states[0].g, UInt<3>(0h2)) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = bits(vcalloc_sel, 1, 1) when _T_59 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_60 = eq(states[1].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_60, UInt<1>(0h1), "") : assert_4 node _T_64 = bits(vcalloc_sel, 2, 2) when _T_64 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) node _T_65 = eq(states[2].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_65, UInt<1>(0h1), "") : assert_5 node _T_69 = bits(vcalloc_sel, 3, 3) when _T_69 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].g, UInt<3>(0h3) node _T_70 = eq(states[3].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_70, UInt<1>(0h1), "") : assert_6 node _T_74 = bits(vcalloc_sel, 4, 4) when _T_74 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].g, UInt<3>(0h3) node _T_75 = eq(states[4].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_75, UInt<1>(0h1), "") : assert_7 node _T_79 = bits(vcalloc_sel, 5, 5) when _T_79 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].g, UInt<3>(0h3) node _T_80 = eq(states[5].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_80, UInt<1>(0h1), "") : assert_8 inst salloc_arb of SwitchArbiter_24 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1]) node credit_available_lo = cat(credit_available_lo_hi, states[0].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4]) node credit_available_hi = cat(credit_available_hi_hi, states[0].vc_sel.`0`[3]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_1 = cat(states[0].vc_sel.`1`[0], _credit_available_T) node credit_available_hi_1 = cat(states[0].vc_sel.`3`[0], states[0].vc_sel.`2`[0]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_2 = cat(credit_available_lo_hi_1, io.out_credit_available.`0`[0]) node credit_available_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_2 = cat(credit_available_hi_hi_1, io.out_credit_available.`0`[3]) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2) node credit_available_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3) node credit_available = neq(_credit_available_T_4, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_84 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_85 = and(_T_84, input_buffer.io.deq[0].bits.tail) when _T_85 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_hi_2 = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1]) node credit_available_lo_4 = cat(credit_available_lo_hi_2, states[1].vc_sel.`0`[0]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_4 = cat(credit_available_hi_hi_2, states[1].vc_sel.`0`[3]) node _credit_available_T_5 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_5 = cat(states[1].vc_sel.`1`[0], _credit_available_T_5) node credit_available_hi_5 = cat(states[1].vc_sel.`3`[0], states[1].vc_sel.`2`[0]) node _credit_available_T_6 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_6 = cat(credit_available_lo_hi_3, io.out_credit_available.`0`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_6 = cat(credit_available_hi_hi_3, io.out_credit_available.`0`[3]) node _credit_available_T_7 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_7 = cat(io.out_credit_available.`1`[0], _credit_available_T_7) node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_8 = cat(credit_available_hi_7, credit_available_lo_7) node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8) node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_86 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_87 = and(_T_86, input_buffer.io.deq[1].bits.tail) when _T_87 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_hi_4 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) node credit_available_lo_8 = cat(credit_available_lo_hi_4, states[2].vc_sel.`0`[0]) node credit_available_hi_hi_4 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_8 = cat(credit_available_hi_hi_4, states[2].vc_sel.`0`[3]) node _credit_available_T_10 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_9 = cat(states[2].vc_sel.`1`[0], _credit_available_T_10) node credit_available_hi_9 = cat(states[2].vc_sel.`3`[0], states[2].vc_sel.`2`[0]) node _credit_available_T_11 = cat(credit_available_hi_9, credit_available_lo_9) node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_10 = cat(credit_available_lo_hi_5, io.out_credit_available.`0`[0]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_10 = cat(credit_available_hi_hi_5, io.out_credit_available.`0`[3]) node _credit_available_T_12 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_11 = cat(io.out_credit_available.`1`[0], _credit_available_T_12) node credit_available_hi_11 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_13 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13) node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_88 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_89 = and(_T_88, input_buffer.io.deq[2].bits.tail) when _T_89 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_hi_6 = cat(states[3].vc_sel.`0`[2], states[3].vc_sel.`0`[1]) node credit_available_lo_12 = cat(credit_available_lo_hi_6, states[3].vc_sel.`0`[0]) node credit_available_hi_hi_6 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_12 = cat(credit_available_hi_hi_6, states[3].vc_sel.`0`[3]) node _credit_available_T_15 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_13 = cat(states[3].vc_sel.`1`[0], _credit_available_T_15) node credit_available_hi_13 = cat(states[3].vc_sel.`3`[0], states[3].vc_sel.`2`[0]) node _credit_available_T_16 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_hi_7 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_14 = cat(credit_available_lo_hi_7, io.out_credit_available.`0`[0]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_14 = cat(credit_available_hi_hi_7, io.out_credit_available.`0`[3]) node _credit_available_T_17 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_15 = cat(io.out_credit_available.`1`[0], _credit_available_T_17) node credit_available_hi_15 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_18 = cat(credit_available_hi_15, credit_available_lo_15) node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18) node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_90 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_91 = and(_T_90, input_buffer.io.deq[3].bits.tail) when _T_91 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_hi_8 = cat(states[4].vc_sel.`0`[2], states[4].vc_sel.`0`[1]) node credit_available_lo_16 = cat(credit_available_lo_hi_8, states[4].vc_sel.`0`[0]) node credit_available_hi_hi_8 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_16 = cat(credit_available_hi_hi_8, states[4].vc_sel.`0`[3]) node _credit_available_T_20 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_17 = cat(states[4].vc_sel.`1`[0], _credit_available_T_20) node credit_available_hi_17 = cat(states[4].vc_sel.`3`[0], states[4].vc_sel.`2`[0]) node _credit_available_T_21 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_hi_9 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_18 = cat(credit_available_lo_hi_9, io.out_credit_available.`0`[0]) node credit_available_hi_hi_9 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_18 = cat(credit_available_hi_hi_9, io.out_credit_available.`0`[3]) node _credit_available_T_22 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_19 = cat(io.out_credit_available.`1`[0], _credit_available_T_22) node credit_available_hi_19 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_23 = cat(credit_available_hi_19, credit_available_lo_19) node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23) node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_92 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_93 = and(_T_92, input_buffer.io.deq[4].bits.tail) when _T_93 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_hi_10 = cat(states[5].vc_sel.`0`[2], states[5].vc_sel.`0`[1]) node credit_available_lo_20 = cat(credit_available_lo_hi_10, states[5].vc_sel.`0`[0]) node credit_available_hi_hi_10 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_20 = cat(credit_available_hi_hi_10, states[5].vc_sel.`0`[3]) node _credit_available_T_25 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_21 = cat(states[5].vc_sel.`1`[0], _credit_available_T_25) node credit_available_hi_21 = cat(states[5].vc_sel.`3`[0], states[5].vc_sel.`2`[0]) node _credit_available_T_26 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_hi_11 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_22 = cat(credit_available_lo_hi_11, io.out_credit_available.`0`[0]) node credit_available_hi_hi_11 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_22 = cat(credit_available_hi_hi_11, io.out_credit_available.`0`[3]) node _credit_available_T_27 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_23 = cat(io.out_credit_available.`1`[0], _credit_available_T_27) node credit_available_hi_23 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_28 = cat(credit_available_hi_23, credit_available_lo_23) node _credit_available_T_29 = and(_credit_available_T_26, _credit_available_T_28) node credit_available_5 = neq(_credit_available_T_29, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_94 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_95 = and(_T_94, input_buffer.io.deq[5].bits.tail) when _T_95 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_17) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_21 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_8) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_9) node _io_in_vc_free_T_15 = or(_io_in_vc_free_T_14, _io_in_vc_free_T_10) node _io_in_vc_free_T_16 = or(_io_in_vc_free_T_15, _io_in_vc_free_T_11) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_16, _io_in_vc_free_T_12) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_17 node _io_in_vc_free_T_18 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_18, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_19 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 5, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _vc_sel_WIRE : UInt<1>[6] node _vc_sel_T_6 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = or(_vc_sel_T_6, _vc_sel_T_7) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_8) node _vc_sel_T_14 = or(_vc_sel_T_13, _vc_sel_T_9) node _vc_sel_T_15 = or(_vc_sel_T_14, _vc_sel_T_10) node _vc_sel_T_16 = or(_vc_sel_T_15, _vc_sel_T_11) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_16 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_21 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_22 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_23 = or(_vc_sel_T_17, _vc_sel_T_18) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_19) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_20) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_21) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_22) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_27 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_34 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_30) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_31) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_32) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_33) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_38 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_39 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_45 = or(_vc_sel_T_39, _vc_sel_T_40) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_41) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_42) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_43) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_44) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_49 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_56 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_52) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_53) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_54) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_55) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_60 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_61 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_64 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_65 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_66 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_67 = or(_vc_sel_T_61, _vc_sel_T_62) node _vc_sel_T_68 = or(_vc_sel_T_67, _vc_sel_T_63) node _vc_sel_T_69 = or(_vc_sel_T_68, _vc_sel_T_64) node _vc_sel_T_70 = or(_vc_sel_T_69, _vc_sel_T_65) node _vc_sel_T_71 = or(_vc_sel_T_70, _vc_sel_T_66) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_71 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_7 : UInt<1>[1] node _vc_sel_T_72 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_77 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_78 = or(_vc_sel_T_72, _vc_sel_T_73) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_74) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_75) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_76) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_77) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_82 connect _vc_sel_WIRE_7[0], _vc_sel_WIRE_8 connect vc_sel.`1`, _vc_sel_WIRE_7 wire _vc_sel_WIRE_9 : UInt<1>[1] node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_89 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_90 = or(_vc_sel_T_89, _vc_sel_T_85) node _vc_sel_T_91 = or(_vc_sel_T_90, _vc_sel_T_86) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_87) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_88) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_93 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 connect vc_sel.`2`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_11 : UInt<1>[1] node _vc_sel_T_94 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_96 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_97 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_98 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_100 = or(_vc_sel_T_94, _vc_sel_T_95) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_96) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_97) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_98) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_99) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_104 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 connect vc_sel.`3`, _vc_sel_WIRE_11 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node channel_oh_0 = or(_channel_oh_T_3, vc_sel.`0`[5]) node virt_channel_lo_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node virt_channel_lo = cat(virt_channel_lo_hi, vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[3]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 5, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_9 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_10 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_11 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_12 = or(_virt_channel_T_8, _virt_channel_T_9) node _virt_channel_T_13 = or(_virt_channel_T_12, _virt_channel_T_10) node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_11) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_14 node _T_96 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_96 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_14 = or(_salloc_outs_0_flit_payload_T_13, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_15 = or(_salloc_outs_0_flit_payload_T_14, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_15, _salloc_outs_0_flit_payload_T_11) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_16 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_14 = or(_salloc_outs_0_flit_head_T_13, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_15 = or(_salloc_outs_0_flit_head_T_14, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_15, _salloc_outs_0_flit_head_T_11) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_16 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_14 = or(_salloc_outs_0_flit_tail_T_13, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_15 = or(_salloc_outs_0_flit_tail_T_14, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_15, _salloc_outs_0_flit_tail_T_11) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_16 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_14 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_15 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_15, _salloc_outs_0_flit_flow_T_11) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_22 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_20) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_21) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_22) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_33) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_38 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_44) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_57 = or(_salloc_outs_0_flit_flow_T_56, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_57, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_55) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_60 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`0`[3], UInt<1>(0h0) connect states[0].vc_sel.`0`[4], UInt<1>(0h0) connect states[0].vc_sel.`0`[5], UInt<1>(0h0) connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`0`[5], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[3], UInt<1>(0h0) connect states[2].vc_sel.`0`[4], UInt<1>(0h0) connect states[2].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) node _T_97 = asUInt(reset) when _T_97 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0)

module InputUnit_8( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [5:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [5:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [5:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [5:0] mask; // @[InputUnit.scala:250:21] wire [5:0] _vcalloc_filter_T_3 = {vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [11:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 12'h1 : _vcalloc_filter_T_3[1] ? 12'h2 : _vcalloc_filter_T_3[2] ? 12'h4 : _vcalloc_filter_T_3[3] ? 12'h8 : _vcalloc_filter_T_3[4] ? 12'h10 : _vcalloc_filter_T_3[5] ? 12'h20 : vcalloc_vals_0 ? 12'h40 : vcalloc_vals_1 ? 12'h80 : vcalloc_vals_2 ? 12'h100 : vcalloc_vals_3 ? 12'h200 : vcalloc_vals_4 ? 12'h400 : {vcalloc_vals_5, 11'h0}; // @[OneHot.scala:85:71] wire [5:0] vcalloc_sel = vcalloc_filter[5:0] | vcalloc_filter[11:6]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_33 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_33( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_12 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<8>(0h80)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}} connect _WIRE_4.bits.sink, UInt<7>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_24 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_25 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_26 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_27 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_12( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module BoomTraceGenTile_1 : input clock : Clock input reset : Reset output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, status_out : { timeout : { valid : UInt<1>, bits : UInt<4>}, error : { valid : UInt<1>, bits : UInt<4>}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>} inst tlMasterXbar of TLXbar_MasterXbar_BoomTraceGenTile_i0_o0_a1d8s1k1z1u_1 connect tlMasterXbar.clock, clock connect tlMasterXbar.reset, reset inst tlSlaveXbar of TLXbar_SlaveXbar_BoomTraceGenTile_i0_o0_a1d8s1k1z1u_1 connect tlSlaveXbar.clock, clock connect tlSlaveXbar.reset, reset inst intXbar of IntXbar_i4_o1_1 inst broadcast of BundleBridgeNexus_UInt1_1 inst broadcast_1 of BundleBridgeNexus_UInt32_1 inst nexus of BundleBridgeNexus_NoOutput_8 inst nexus_1 of BundleBridgeNexus_TraceAux_1 inst broadcast_2 of BundleBridgeNexus_NoOutput_9 inst dcache of BoomNonBlockingDCache_1 connect dcache.clock, clock connect dcache.reset, reset inst buffer of TLBuffer_a32d64s4k3z4c_2 connect buffer.clock, clock connect buffer.reset, reset inst buffer_1 of TLBuffer_5 connect buffer_1.clock, clock connect buffer_1.reset, reset wire hartIdSinkNodeIn : UInt<1> invalidate hartIdSinkNodeIn wire hartidOut : UInt<1> invalidate hartidOut wire hartidIn : UInt<1> invalidate hartidIn connect hartidOut, hartidIn wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn wire reset_vectorOut : UInt<32> invalidate reset_vectorOut wire reset_vectorIn : UInt<32> invalidate reset_vectorIn connect reset_vectorOut, reset_vectorIn wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceSourceNodeOut.time invalidate traceSourceNodeOut.insns[0].tval invalidate traceSourceNodeOut.insns[0].cause invalidate traceSourceNodeOut.insns[0].interrupt invalidate traceSourceNodeOut.insns[0].exception invalidate traceSourceNodeOut.insns[0].priv invalidate traceSourceNodeOut.insns[0].insn invalidate traceSourceNodeOut.insns[0].iaddr invalidate traceSourceNodeOut.insns[0].valid wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreSourceNodeOut.cause invalidate traceCoreSourceNodeOut.tval invalidate traceCoreSourceNodeOut.priv invalidate traceCoreSourceNodeOut.group[0].ilastsize invalidate traceCoreSourceNodeOut.group[0].itype invalidate traceCoreSourceNodeOut.group[0].iaddr invalidate traceCoreSourceNodeOut.group[0].iretire wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>} connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0) connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0) wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>} invalidate traceAuxSinkNodeIn.stall invalidate traceAuxSinkNodeIn.enable wire bpwatchSourceNodeOut : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1] invalidate bpwatchSourceNodeOut[0].action invalidate bpwatchSourceNodeOut[0].ivalid[0] invalidate bpwatchSourceNodeOut[0].wvalid[0] invalidate bpwatchSourceNodeOut[0].rvalid[0] invalidate bpwatchSourceNodeOut[0].valid[0] wire int_localOut : UInt<1>[1] invalidate int_localOut[0] wire x1_int_localOut : UInt<1>[2] invalidate x1_int_localOut[0] invalidate x1_int_localOut[1] wire x1_int_localOut_1 : UInt<1>[1] invalidate x1_int_localOut_1[0] wire x1_int_localOut_2 : UInt<1>[1] invalidate x1_int_localOut_2[0] wire int_localIn : UInt<1>[1] invalidate int_localIn[0] wire x1_int_localIn : UInt<1>[2] invalidate x1_int_localIn[0] invalidate x1_int_localIn[1] wire x1_int_localIn_1 : UInt<1>[1] invalidate x1_int_localIn_1[0] wire x1_int_localIn_2 : UInt<1>[1] invalidate x1_int_localIn_2[0] connect int_localOut, int_localIn connect x1_int_localOut, x1_int_localIn connect x1_int_localOut_1, x1_int_localIn_1 connect x1_int_localOut_2, x1_int_localIn_2 wire intSinkNodeIn : UInt<1>[5] invalidate intSinkNodeIn[0] invalidate intSinkNodeIn[1] invalidate intSinkNodeIn[2] invalidate intSinkNodeIn[3] invalidate intSinkNodeIn[4] wire haltNodeOut : UInt<1>[1] invalidate haltNodeOut[0] wire ceaseNodeOut : UInt<1>[1] invalidate ceaseNodeOut[0] wire wfiNodeOut : UInt<1>[1] invalidate wfiNodeOut[0] wire statusNodeOut : { timeout : { valid : UInt<1>, bits : UInt<4>}, error : { valid : UInt<1>, bits : UInt<4>}} invalidate statusNodeOut.error.bits invalidate statusNodeOut.error.valid invalidate statusNodeOut.timeout.bits invalidate statusNodeOut.timeout.valid wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate masterNodeOut.e.bits.sink invalidate masterNodeOut.e.valid invalidate masterNodeOut.e.ready invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.c.bits.corrupt invalidate masterNodeOut.c.bits.data invalidate masterNodeOut.c.bits.address invalidate masterNodeOut.c.bits.source invalidate masterNodeOut.c.bits.size invalidate masterNodeOut.c.bits.param invalidate masterNodeOut.c.bits.opcode invalidate masterNodeOut.c.valid invalidate masterNodeOut.c.ready invalidate masterNodeOut.b.bits.corrupt invalidate masterNodeOut.b.bits.data invalidate masterNodeOut.b.bits.mask invalidate masterNodeOut.b.bits.address invalidate masterNodeOut.b.bits.source invalidate masterNodeOut.b.bits.size invalidate masterNodeOut.b.bits.param invalidate masterNodeOut.b.bits.opcode invalidate masterNodeOut.b.valid invalidate masterNodeOut.b.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready wire masterNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate masterNodeIn.e.bits.sink invalidate masterNodeIn.e.valid invalidate masterNodeIn.e.ready invalidate masterNodeIn.d.bits.corrupt invalidate masterNodeIn.d.bits.data invalidate masterNodeIn.d.bits.denied invalidate masterNodeIn.d.bits.sink invalidate masterNodeIn.d.bits.source invalidate masterNodeIn.d.bits.size invalidate masterNodeIn.d.bits.param invalidate masterNodeIn.d.bits.opcode invalidate masterNodeIn.d.valid invalidate masterNodeIn.d.ready invalidate masterNodeIn.c.bits.corrupt invalidate masterNodeIn.c.bits.data invalidate masterNodeIn.c.bits.address invalidate masterNodeIn.c.bits.source invalidate masterNodeIn.c.bits.size invalidate masterNodeIn.c.bits.param invalidate masterNodeIn.c.bits.opcode invalidate masterNodeIn.c.valid invalidate masterNodeIn.c.ready invalidate masterNodeIn.b.bits.corrupt invalidate masterNodeIn.b.bits.data invalidate masterNodeIn.b.bits.mask invalidate masterNodeIn.b.bits.address invalidate masterNodeIn.b.bits.source invalidate masterNodeIn.b.bits.size invalidate masterNodeIn.b.bits.param invalidate masterNodeIn.b.bits.opcode invalidate masterNodeIn.b.valid invalidate masterNodeIn.b.ready invalidate masterNodeIn.a.bits.corrupt invalidate masterNodeIn.a.bits.data invalidate masterNodeIn.a.bits.mask invalidate masterNodeIn.a.bits.address invalidate masterNodeIn.a.bits.source invalidate masterNodeIn.a.bits.size invalidate masterNodeIn.a.bits.param invalidate masterNodeIn.a.bits.opcode invalidate masterNodeIn.a.valid invalidate masterNodeIn.a.ready connect masterNodeOut, masterNodeIn connect intSinkNodeIn, intXbar.auto.anon_out connect hartIdSinkNodeIn, broadcast.auto.out connect broadcast.auto.in, hartidOut connect resetVectorSinkNodeIn, broadcast_1.auto.out connect broadcast_1.auto.in, reset_vectorOut connect traceAuxSinkNodeIn, nexus_1.auto.out connect broadcast_2.auto.in[0], bpwatchSourceNodeOut[0] connect intXbar.auto.anon_in_0[0], int_localOut[0] connect intXbar.auto.anon_in_1[0], x1_int_localOut[0] connect intXbar.auto.anon_in_1[1], x1_int_localOut[1] connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0] connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0] connect masterNodeIn.e.bits, dcache.auto.out.e.bits connect masterNodeIn.e.valid, dcache.auto.out.e.valid connect dcache.auto.out.e.ready, masterNodeIn.e.ready connect dcache.auto.out.d, masterNodeIn.d connect masterNodeIn.c.bits, dcache.auto.out.c.bits connect masterNodeIn.c.valid, dcache.auto.out.c.valid connect dcache.auto.out.c.ready, masterNodeIn.c.ready connect dcache.auto.out.b, masterNodeIn.b connect masterNodeIn.a.bits, dcache.auto.out.a.bits connect masterNodeIn.a.valid, dcache.auto.out.a.valid connect dcache.auto.out.a.ready, masterNodeIn.a.ready connect buffer.auto.in, masterNodeOut connect hartidIn, auto.hartid_in connect reset_vectorIn, auto.reset_vector_in connect auto.trace_source_out, traceSourceNodeOut connect auto.trace_core_source_out, traceCoreSourceNodeOut connect int_localIn, auto.int_local_in_0 connect x1_int_localIn, auto.int_local_in_1 connect x1_int_localIn_1, auto.int_local_in_2 connect x1_int_localIn_2, auto.int_local_in_3 connect auto.halt_out, haltNodeOut connect auto.cease_out, ceaseNodeOut connect auto.wfi_out, wfiNodeOut connect auto.status_out, statusNodeOut connect auto.buffer_out.e.bits, buffer.auto.out.e.bits connect auto.buffer_out.e.valid, buffer.auto.out.e.valid connect buffer.auto.out.e.ready, auto.buffer_out.e.ready connect buffer.auto.out.d, auto.buffer_out.d connect auto.buffer_out.c.bits, buffer.auto.out.c.bits connect auto.buffer_out.c.valid, buffer.auto.out.c.valid connect buffer.auto.out.c.ready, auto.buffer_out.c.ready connect buffer.auto.out.b, auto.buffer_out.b connect auto.buffer_out.a.bits, buffer.auto.out.a.bits connect auto.buffer_out.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, auto.buffer_out.a.ready inst tracegen of TraceGenerator_1 connect tracegen.clock, clock connect tracegen.reset, reset connect tracegen.io.hartid, hartIdSinkNodeIn inst ptw of DummyPTW_1 connect ptw.clock, clock connect ptw.reset, reset invalidate ptw.io.requestors[0].customCSRs.csrs[0].sdata invalidate ptw.io.requestors[0].customCSRs.csrs[0].set invalidate ptw.io.requestors[0].customCSRs.csrs[0].stall invalidate ptw.io.requestors[0].customCSRs.csrs[0].value invalidate ptw.io.requestors[0].customCSRs.csrs[0].wdata invalidate ptw.io.requestors[0].customCSRs.csrs[0].wen invalidate ptw.io.requestors[0].customCSRs.csrs[0].ren invalidate ptw.io.requestors[0].customCSRs.csrs[1].sdata invalidate ptw.io.requestors[0].customCSRs.csrs[1].set invalidate ptw.io.requestors[0].customCSRs.csrs[1].stall invalidate ptw.io.requestors[0].customCSRs.csrs[1].value invalidate ptw.io.requestors[0].customCSRs.csrs[1].wdata invalidate ptw.io.requestors[0].customCSRs.csrs[1].wen invalidate ptw.io.requestors[0].customCSRs.csrs[1].ren invalidate ptw.io.requestors[0].customCSRs.csrs[2].sdata invalidate ptw.io.requestors[0].customCSRs.csrs[2].set invalidate ptw.io.requestors[0].customCSRs.csrs[2].stall invalidate ptw.io.requestors[0].customCSRs.csrs[2].value invalidate ptw.io.requestors[0].customCSRs.csrs[2].wdata invalidate ptw.io.requestors[0].customCSRs.csrs[2].wen invalidate ptw.io.requestors[0].customCSRs.csrs[2].ren invalidate ptw.io.requestors[0].customCSRs.csrs[3].sdata invalidate ptw.io.requestors[0].customCSRs.csrs[3].set invalidate ptw.io.requestors[0].customCSRs.csrs[3].stall invalidate ptw.io.requestors[0].customCSRs.csrs[3].value invalidate ptw.io.requestors[0].customCSRs.csrs[3].wdata invalidate ptw.io.requestors[0].customCSRs.csrs[3].wen invalidate ptw.io.requestors[0].customCSRs.csrs[3].ren invalidate ptw.io.requestors[0].gstatus.uie invalidate ptw.io.requestors[0].gstatus.sie invalidate ptw.io.requestors[0].gstatus.hie invalidate ptw.io.requestors[0].gstatus.mie invalidate ptw.io.requestors[0].gstatus.upie invalidate ptw.io.requestors[0].gstatus.spie invalidate ptw.io.requestors[0].gstatus.ube invalidate ptw.io.requestors[0].gstatus.mpie invalidate ptw.io.requestors[0].gstatus.spp invalidate ptw.io.requestors[0].gstatus.vs invalidate ptw.io.requestors[0].gstatus.mpp invalidate ptw.io.requestors[0].gstatus.fs invalidate ptw.io.requestors[0].gstatus.xs invalidate ptw.io.requestors[0].gstatus.mprv invalidate ptw.io.requestors[0].gstatus.sum invalidate ptw.io.requestors[0].gstatus.mxr invalidate ptw.io.requestors[0].gstatus.tvm invalidate ptw.io.requestors[0].gstatus.tw invalidate ptw.io.requestors[0].gstatus.tsr invalidate ptw.io.requestors[0].gstatus.zero1 invalidate ptw.io.requestors[0].gstatus.sd_rv32 invalidate ptw.io.requestors[0].gstatus.uxl invalidate ptw.io.requestors[0].gstatus.sxl invalidate ptw.io.requestors[0].gstatus.sbe invalidate ptw.io.requestors[0].gstatus.mbe invalidate ptw.io.requestors[0].gstatus.gva invalidate ptw.io.requestors[0].gstatus.mpv invalidate ptw.io.requestors[0].gstatus.zero2 invalidate ptw.io.requestors[0].gstatus.sd invalidate ptw.io.requestors[0].gstatus.v invalidate ptw.io.requestors[0].gstatus.prv invalidate ptw.io.requestors[0].gstatus.dv invalidate ptw.io.requestors[0].gstatus.dprv invalidate ptw.io.requestors[0].gstatus.isa invalidate ptw.io.requestors[0].gstatus.wfi invalidate ptw.io.requestors[0].gstatus.cease invalidate ptw.io.requestors[0].gstatus.debug invalidate ptw.io.requestors[0].hstatus.zero1 invalidate ptw.io.requestors[0].hstatus.vsbe invalidate ptw.io.requestors[0].hstatus.gva invalidate ptw.io.requestors[0].hstatus.spv invalidate ptw.io.requestors[0].hstatus.spvp invalidate ptw.io.requestors[0].hstatus.hu invalidate ptw.io.requestors[0].hstatus.zero2 invalidate ptw.io.requestors[0].hstatus.vgein invalidate ptw.io.requestors[0].hstatus.zero3 invalidate ptw.io.requestors[0].hstatus.vtvm invalidate ptw.io.requestors[0].hstatus.vtw invalidate ptw.io.requestors[0].hstatus.vtsr invalidate ptw.io.requestors[0].hstatus.zero5 invalidate ptw.io.requestors[0].hstatus.vsxl invalidate ptw.io.requestors[0].hstatus.zero6 invalidate ptw.io.requestors[0].status.uie invalidate ptw.io.requestors[0].status.sie invalidate ptw.io.requestors[0].status.hie invalidate ptw.io.requestors[0].status.mie invalidate ptw.io.requestors[0].status.upie invalidate ptw.io.requestors[0].status.spie invalidate ptw.io.requestors[0].status.ube invalidate ptw.io.requestors[0].status.mpie invalidate ptw.io.requestors[0].status.spp invalidate ptw.io.requestors[0].status.vs invalidate ptw.io.requestors[0].status.mpp invalidate ptw.io.requestors[0].status.fs invalidate ptw.io.requestors[0].status.xs invalidate ptw.io.requestors[0].status.mprv invalidate ptw.io.requestors[0].status.sum invalidate ptw.io.requestors[0].status.mxr invalidate ptw.io.requestors[0].status.tvm invalidate ptw.io.requestors[0].status.tw invalidate ptw.io.requestors[0].status.tsr invalidate ptw.io.requestors[0].status.zero1 invalidate ptw.io.requestors[0].status.sd_rv32 invalidate ptw.io.requestors[0].status.uxl invalidate ptw.io.requestors[0].status.sxl invalidate ptw.io.requestors[0].status.sbe invalidate ptw.io.requestors[0].status.mbe invalidate ptw.io.requestors[0].status.gva invalidate ptw.io.requestors[0].status.mpv invalidate ptw.io.requestors[0].status.zero2 invalidate ptw.io.requestors[0].status.sd invalidate ptw.io.requestors[0].status.v invalidate ptw.io.requestors[0].status.prv invalidate ptw.io.requestors[0].status.dv invalidate ptw.io.requestors[0].status.dprv invalidate ptw.io.requestors[0].status.isa invalidate ptw.io.requestors[0].status.wfi invalidate ptw.io.requestors[0].status.cease invalidate ptw.io.requestors[0].status.debug invalidate ptw.io.requestors[0].vsatp.ppn invalidate ptw.io.requestors[0].vsatp.asid invalidate ptw.io.requestors[0].vsatp.mode invalidate ptw.io.requestors[0].hgatp.ppn invalidate ptw.io.requestors[0].hgatp.asid invalidate ptw.io.requestors[0].hgatp.mode invalidate ptw.io.requestors[0].ptbr.ppn invalidate ptw.io.requestors[0].ptbr.asid invalidate ptw.io.requestors[0].ptbr.mode invalidate ptw.io.requestors[0].resp.bits.gpa_is_pte invalidate ptw.io.requestors[0].resp.bits.gpa.bits invalidate ptw.io.requestors[0].resp.bits.gpa.valid invalidate ptw.io.requestors[0].resp.bits.homogeneous invalidate ptw.io.requestors[0].resp.bits.fragmented_superpage invalidate ptw.io.requestors[0].resp.bits.level invalidate ptw.io.requestors[0].resp.bits.pte.v invalidate ptw.io.requestors[0].resp.bits.pte.r invalidate ptw.io.requestors[0].resp.bits.pte.w invalidate ptw.io.requestors[0].resp.bits.pte.x invalidate ptw.io.requestors[0].resp.bits.pte.u invalidate ptw.io.requestors[0].resp.bits.pte.g invalidate ptw.io.requestors[0].resp.bits.pte.a invalidate ptw.io.requestors[0].resp.bits.pte.d invalidate ptw.io.requestors[0].resp.bits.pte.reserved_for_software invalidate ptw.io.requestors[0].resp.bits.pte.ppn invalidate ptw.io.requestors[0].resp.bits.pte.reserved_for_future invalidate ptw.io.requestors[0].resp.bits.hx invalidate ptw.io.requestors[0].resp.bits.hw invalidate ptw.io.requestors[0].resp.bits.hr invalidate ptw.io.requestors[0].resp.bits.gf invalidate ptw.io.requestors[0].resp.bits.pf invalidate ptw.io.requestors[0].resp.bits.ae_final invalidate ptw.io.requestors[0].resp.bits.ae_ptw invalidate ptw.io.requestors[0].resp.valid invalidate ptw.io.requestors[0].req.bits.bits.stage2 invalidate ptw.io.requestors[0].req.bits.bits.vstage1 invalidate ptw.io.requestors[0].req.bits.bits.need_gpa invalidate ptw.io.requestors[0].req.bits.bits.addr invalidate ptw.io.requestors[0].req.bits.valid invalidate ptw.io.requestors[0].req.valid invalidate ptw.io.requestors[0].req.ready inst lsu of LSU_1 connect lsu.clock, clock connect lsu.reset, reset inst boom_shim of BoomLSUShim_1 connect boom_shim.clock, clock connect boom_shim.reset, reset invalidate lsu.io.ptw.customCSRs.csrs[0].sdata invalidate lsu.io.ptw.customCSRs.csrs[0].set invalidate lsu.io.ptw.customCSRs.csrs[0].stall invalidate lsu.io.ptw.customCSRs.csrs[0].value invalidate lsu.io.ptw.customCSRs.csrs[0].wdata invalidate lsu.io.ptw.customCSRs.csrs[0].wen invalidate lsu.io.ptw.customCSRs.csrs[0].ren invalidate lsu.io.ptw.customCSRs.csrs[1].sdata invalidate lsu.io.ptw.customCSRs.csrs[1].set invalidate lsu.io.ptw.customCSRs.csrs[1].stall invalidate lsu.io.ptw.customCSRs.csrs[1].value invalidate lsu.io.ptw.customCSRs.csrs[1].wdata invalidate lsu.io.ptw.customCSRs.csrs[1].wen invalidate lsu.io.ptw.customCSRs.csrs[1].ren invalidate lsu.io.ptw.gstatus.uie invalidate lsu.io.ptw.gstatus.sie invalidate lsu.io.ptw.gstatus.hie invalidate lsu.io.ptw.gstatus.mie invalidate lsu.io.ptw.gstatus.upie invalidate lsu.io.ptw.gstatus.spie invalidate lsu.io.ptw.gstatus.ube invalidate lsu.io.ptw.gstatus.mpie invalidate lsu.io.ptw.gstatus.spp invalidate lsu.io.ptw.gstatus.vs invalidate lsu.io.ptw.gstatus.mpp invalidate lsu.io.ptw.gstatus.fs invalidate lsu.io.ptw.gstatus.xs invalidate lsu.io.ptw.gstatus.mprv invalidate lsu.io.ptw.gstatus.sum invalidate lsu.io.ptw.gstatus.mxr invalidate lsu.io.ptw.gstatus.tvm invalidate lsu.io.ptw.gstatus.tw invalidate lsu.io.ptw.gstatus.tsr invalidate lsu.io.ptw.gstatus.zero1 invalidate lsu.io.ptw.gstatus.sd_rv32 invalidate lsu.io.ptw.gstatus.uxl invalidate lsu.io.ptw.gstatus.sxl invalidate lsu.io.ptw.gstatus.sbe invalidate lsu.io.ptw.gstatus.mbe invalidate lsu.io.ptw.gstatus.gva invalidate lsu.io.ptw.gstatus.mpv invalidate lsu.io.ptw.gstatus.zero2 invalidate lsu.io.ptw.gstatus.sd invalidate lsu.io.ptw.gstatus.v invalidate lsu.io.ptw.gstatus.prv invalidate lsu.io.ptw.gstatus.dv invalidate lsu.io.ptw.gstatus.dprv invalidate lsu.io.ptw.gstatus.isa invalidate lsu.io.ptw.gstatus.wfi invalidate lsu.io.ptw.gstatus.cease invalidate lsu.io.ptw.gstatus.debug invalidate lsu.io.ptw.hstatus.zero1 invalidate lsu.io.ptw.hstatus.vsbe invalidate lsu.io.ptw.hstatus.gva invalidate lsu.io.ptw.hstatus.spv invalidate lsu.io.ptw.hstatus.spvp invalidate lsu.io.ptw.hstatus.hu invalidate lsu.io.ptw.hstatus.zero2 invalidate lsu.io.ptw.hstatus.vgein invalidate lsu.io.ptw.hstatus.zero3 invalidate lsu.io.ptw.hstatus.vtvm invalidate lsu.io.ptw.hstatus.vtw invalidate lsu.io.ptw.hstatus.vtsr invalidate lsu.io.ptw.hstatus.zero5 invalidate lsu.io.ptw.hstatus.vsxl invalidate lsu.io.ptw.hstatus.zero6 invalidate lsu.io.ptw.status.uie invalidate lsu.io.ptw.status.sie invalidate lsu.io.ptw.status.hie invalidate lsu.io.ptw.status.mie invalidate lsu.io.ptw.status.upie invalidate lsu.io.ptw.status.spie invalidate lsu.io.ptw.status.ube invalidate lsu.io.ptw.status.mpie invalidate lsu.io.ptw.status.spp invalidate lsu.io.ptw.status.vs invalidate lsu.io.ptw.status.mpp invalidate lsu.io.ptw.status.fs invalidate lsu.io.ptw.status.xs invalidate lsu.io.ptw.status.mprv invalidate lsu.io.ptw.status.sum invalidate lsu.io.ptw.status.mxr invalidate lsu.io.ptw.status.tvm invalidate lsu.io.ptw.status.tw invalidate lsu.io.ptw.status.tsr invalidate lsu.io.ptw.status.zero1 invalidate lsu.io.ptw.status.sd_rv32 invalidate lsu.io.ptw.status.uxl invalidate lsu.io.ptw.status.sxl invalidate lsu.io.ptw.status.sbe invalidate lsu.io.ptw.status.mbe invalidate lsu.io.ptw.status.gva invalidate lsu.io.ptw.status.mpv invalidate lsu.io.ptw.status.zero2 invalidate lsu.io.ptw.status.sd invalidate lsu.io.ptw.status.v invalidate lsu.io.ptw.status.prv invalidate lsu.io.ptw.status.dv invalidate lsu.io.ptw.status.dprv invalidate lsu.io.ptw.status.isa invalidate lsu.io.ptw.status.wfi invalidate lsu.io.ptw.status.cease invalidate lsu.io.ptw.status.debug invalidate lsu.io.ptw.vsatp.ppn invalidate lsu.io.ptw.vsatp.asid invalidate lsu.io.ptw.vsatp.mode invalidate lsu.io.ptw.hgatp.ppn invalidate lsu.io.ptw.hgatp.asid invalidate lsu.io.ptw.hgatp.mode invalidate lsu.io.ptw.ptbr.ppn invalidate lsu.io.ptw.ptbr.asid invalidate lsu.io.ptw.ptbr.mode invalidate lsu.io.ptw.resp.bits.gpa_is_pte invalidate lsu.io.ptw.resp.bits.gpa.bits invalidate lsu.io.ptw.resp.bits.gpa.valid invalidate lsu.io.ptw.resp.bits.homogeneous invalidate lsu.io.ptw.resp.bits.fragmented_superpage invalidate lsu.io.ptw.resp.bits.level invalidate lsu.io.ptw.resp.bits.pte.v invalidate lsu.io.ptw.resp.bits.pte.r invalidate lsu.io.ptw.resp.bits.pte.w invalidate lsu.io.ptw.resp.bits.pte.x invalidate lsu.io.ptw.resp.bits.pte.u invalidate lsu.io.ptw.resp.bits.pte.g invalidate lsu.io.ptw.resp.bits.pte.a invalidate lsu.io.ptw.resp.bits.pte.d invalidate lsu.io.ptw.resp.bits.pte.reserved_for_software invalidate lsu.io.ptw.resp.bits.pte.ppn invalidate lsu.io.ptw.resp.bits.pte.reserved_for_future invalidate lsu.io.ptw.resp.bits.hx invalidate lsu.io.ptw.resp.bits.hw invalidate lsu.io.ptw.resp.bits.hr invalidate lsu.io.ptw.resp.bits.gf invalidate lsu.io.ptw.resp.bits.pf invalidate lsu.io.ptw.resp.bits.ae_final invalidate lsu.io.ptw.resp.bits.ae_ptw invalidate lsu.io.ptw.resp.valid invalidate lsu.io.ptw.req.bits.bits.stage2 invalidate lsu.io.ptw.req.bits.bits.vstage1 invalidate lsu.io.ptw.req.bits.bits.need_gpa invalidate lsu.io.ptw.req.bits.bits.addr invalidate lsu.io.ptw.req.bits.valid invalidate lsu.io.ptw.req.valid invalidate lsu.io.ptw.req.ready connect ptw.io.requestors[0].req, lsu.io.ptw.req connect lsu.io.ptw.resp.bits.gpa_is_pte, ptw.io.requestors[0].resp.bits.gpa_is_pte connect lsu.io.ptw.resp.bits.gpa.bits, ptw.io.requestors[0].resp.bits.gpa.bits connect lsu.io.ptw.resp.bits.gpa.valid, ptw.io.requestors[0].resp.bits.gpa.valid connect lsu.io.ptw.resp.bits.homogeneous, ptw.io.requestors[0].resp.bits.homogeneous connect lsu.io.ptw.resp.bits.fragmented_superpage, ptw.io.requestors[0].resp.bits.fragmented_superpage connect lsu.io.ptw.resp.bits.level, ptw.io.requestors[0].resp.bits.level connect lsu.io.ptw.resp.bits.pte.v, ptw.io.requestors[0].resp.bits.pte.v connect lsu.io.ptw.resp.bits.pte.r, ptw.io.requestors[0].resp.bits.pte.r connect lsu.io.ptw.resp.bits.pte.w, ptw.io.requestors[0].resp.bits.pte.w connect lsu.io.ptw.resp.bits.pte.x, ptw.io.requestors[0].resp.bits.pte.x connect lsu.io.ptw.resp.bits.pte.u, ptw.io.requestors[0].resp.bits.pte.u connect lsu.io.ptw.resp.bits.pte.g, ptw.io.requestors[0].resp.bits.pte.g connect lsu.io.ptw.resp.bits.pte.a, ptw.io.requestors[0].resp.bits.pte.a connect lsu.io.ptw.resp.bits.pte.d, ptw.io.requestors[0].resp.bits.pte.d connect lsu.io.ptw.resp.bits.pte.reserved_for_software, ptw.io.requestors[0].resp.bits.pte.reserved_for_software connect lsu.io.ptw.resp.bits.pte.ppn, ptw.io.requestors[0].resp.bits.pte.ppn connect lsu.io.ptw.resp.bits.pte.reserved_for_future, ptw.io.requestors[0].resp.bits.pte.reserved_for_future connect lsu.io.ptw.resp.bits.hx, ptw.io.requestors[0].resp.bits.hx connect lsu.io.ptw.resp.bits.hw, ptw.io.requestors[0].resp.bits.hw connect lsu.io.ptw.resp.bits.hr, ptw.io.requestors[0].resp.bits.hr connect lsu.io.ptw.resp.bits.gf, ptw.io.requestors[0].resp.bits.gf connect lsu.io.ptw.resp.bits.pf, ptw.io.requestors[0].resp.bits.pf connect lsu.io.ptw.resp.bits.ae_final, ptw.io.requestors[0].resp.bits.ae_final connect lsu.io.ptw.resp.bits.ae_ptw, ptw.io.requestors[0].resp.bits.ae_ptw connect lsu.io.ptw.resp.valid, ptw.io.requestors[0].resp.valid connect dcache.io.lsu, lsu.io.dmem connect boom_shim.io.tracegen, tracegen.io.mem connect tracegen.io.fence_rdy, boom_shim.io.tracegen.ordered connect boom_shim.io.lsu, lsu.io.core invalidate lsu.io.hellacache.clock_enabled invalidate lsu.io.hellacache.keep_clock_enabled invalidate lsu.io.hellacache.perf.storeBufferEmptyAfterStore invalidate lsu.io.hellacache.perf.storeBufferEmptyAfterLoad invalidate lsu.io.hellacache.perf.canAcceptLoadThenLoad invalidate lsu.io.hellacache.perf.canAcceptStoreThenRMW invalidate lsu.io.hellacache.perf.canAcceptStoreThenLoad invalidate lsu.io.hellacache.perf.blocked invalidate lsu.io.hellacache.perf.tlbMiss invalidate lsu.io.hellacache.perf.grant invalidate lsu.io.hellacache.perf.release invalidate lsu.io.hellacache.perf.acquire invalidate lsu.io.hellacache.store_pending invalidate lsu.io.hellacache.ordered invalidate lsu.io.hellacache.s2_gpa_is_pte invalidate lsu.io.hellacache.s2_gpa invalidate lsu.io.hellacache.s2_xcpt.ae.st invalidate lsu.io.hellacache.s2_xcpt.ae.ld invalidate lsu.io.hellacache.s2_xcpt.gf.st invalidate lsu.io.hellacache.s2_xcpt.gf.ld invalidate lsu.io.hellacache.s2_xcpt.pf.st invalidate lsu.io.hellacache.s2_xcpt.pf.ld invalidate lsu.io.hellacache.s2_xcpt.ma.st invalidate lsu.io.hellacache.s2_xcpt.ma.ld invalidate lsu.io.hellacache.replay_next invalidate lsu.io.hellacache.resp.bits.store_data invalidate lsu.io.hellacache.resp.bits.data_raw invalidate lsu.io.hellacache.resp.bits.data_word_bypass invalidate lsu.io.hellacache.resp.bits.has_data invalidate lsu.io.hellacache.resp.bits.replay invalidate lsu.io.hellacache.resp.bits.mask invalidate lsu.io.hellacache.resp.bits.data invalidate lsu.io.hellacache.resp.bits.dv invalidate lsu.io.hellacache.resp.bits.dprv invalidate lsu.io.hellacache.resp.bits.signed invalidate lsu.io.hellacache.resp.bits.size invalidate lsu.io.hellacache.resp.bits.cmd invalidate lsu.io.hellacache.resp.bits.tag invalidate lsu.io.hellacache.resp.bits.addr invalidate lsu.io.hellacache.resp.valid invalidate lsu.io.hellacache.s2_paddr invalidate lsu.io.hellacache.s2_uncached invalidate lsu.io.hellacache.s2_kill invalidate lsu.io.hellacache.s2_nack_cause_raw invalidate lsu.io.hellacache.s2_nack invalidate lsu.io.hellacache.s1_data.mask invalidate lsu.io.hellacache.s1_data.data invalidate lsu.io.hellacache.s1_kill invalidate lsu.io.hellacache.req.bits.mask invalidate lsu.io.hellacache.req.bits.data invalidate lsu.io.hellacache.req.bits.no_xcpt invalidate lsu.io.hellacache.req.bits.no_alloc invalidate lsu.io.hellacache.req.bits.no_resp invalidate lsu.io.hellacache.req.bits.phys invalidate lsu.io.hellacache.req.bits.dv invalidate lsu.io.hellacache.req.bits.dprv invalidate lsu.io.hellacache.req.bits.signed invalidate lsu.io.hellacache.req.bits.size invalidate lsu.io.hellacache.req.bits.cmd invalidate lsu.io.hellacache.req.bits.tag invalidate lsu.io.hellacache.req.bits.addr invalidate lsu.io.hellacache.req.valid invalidate lsu.io.hellacache.req.ready connect lsu.io.hellacache.req.valid, UInt<1>(0h0) regreset ceaseNodeOut_0_cease_count : UInt<4>, clock, reset, UInt<4>(0h0) node ceaseNodeOut_0_cease = geq(ceaseNodeOut_0_cease_count, UInt<4>(0h8)) node _ceaseNodeOut_0_cease_T = eq(tracegen.io.finished, UInt<1>(0h0)) when _ceaseNodeOut_0_cease_T : connect ceaseNodeOut_0_cease_count, UInt<1>(0h0) node _ceaseNodeOut_0_cease_T_1 = eq(ceaseNodeOut_0_cease, UInt<1>(0h0)) node _ceaseNodeOut_0_cease_T_2 = and(tracegen.io.finished, _ceaseNodeOut_0_cease_T_1) when _ceaseNodeOut_0_cease_T_2 : node _ceaseNodeOut_0_cease_count_T = add(ceaseNodeOut_0_cease_count, UInt<1>(0h1)) node _ceaseNodeOut_0_cease_count_T_1 = tail(_ceaseNodeOut_0_cease_count_T, 1) connect ceaseNodeOut_0_cease_count, _ceaseNodeOut_0_cease_count_T_1 regreset ceaseNodeOut_0_prev_cease : UInt<1>, clock, reset, UInt<1>(0h0) connect ceaseNodeOut_0_prev_cease, ceaseNodeOut_0_cease node _ceaseNodeOut_0_T = eq(ceaseNodeOut_0_cease, UInt<1>(0h0)) node _ceaseNodeOut_0_T_1 = and(ceaseNodeOut_0_prev_cease, _ceaseNodeOut_0_T) node _ceaseNodeOut_0_T_2 = eq(_ceaseNodeOut_0_T_1, UInt<1>(0h0)) node _ceaseNodeOut_0_T_3 = asUInt(reset) node _ceaseNodeOut_0_T_4 = eq(_ceaseNodeOut_0_T_3, UInt<1>(0h0)) when _ceaseNodeOut_0_T_4 : node _ceaseNodeOut_0_T_5 = eq(_ceaseNodeOut_0_T_2, UInt<1>(0h0)) when _ceaseNodeOut_0_T_5 : printf(clock, UInt<1>(0h1), "Assertion failed: CEASE line can not glitch once raised\n at Interrupts.scala:121 assert(!(prev_cease & !cease), \"CEASE line can not glitch once raised\")\n") : ceaseNodeOut_0_printf assert(clock, _ceaseNodeOut_0_T_2, UInt<1>(0h1), "") : ceaseNodeOut_0_assert connect ceaseNodeOut[0], ceaseNodeOut_0_cease regreset haltNodeOut_0_r : UInt<1>, clock, reset, UInt<1>(0h0) when tracegen.io.timeout : connect haltNodeOut_0_r, UInt<1>(0h1) connect haltNodeOut[0], haltNodeOut_0_r connect wfiNodeOut[0], UInt<1>(0h0) connect statusNodeOut.timeout.valid, tracegen.io.timeout connect statusNodeOut.timeout.bits, UInt<1>(0h0) connect statusNodeOut.error.valid, UInt<1>(0h0) node _T = eq(tracegen.io.timeout, UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: TraceGen tile 1: request timed out\n at tracegen.scala:262 assert(!tracegen.io.timeout, s\"TraceGen tile ${outer.tileParams.tileId}: request timed out\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert

module BoomTraceGenTile_1( // @[tracegen.scala:229:7] input clock, // @[tracegen.scala:229:7] input reset, // @[tracegen.scala:229:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_status_out_timeout_valid, // @[LazyModuleImp.scala:107:25] output auto_cease_out_0, // @[LazyModuleImp.scala:107:25] output auto_halt_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] input auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _boom_shim_io_lsu_exe_0_req_valid; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_exe_0_req_bits_uop_uopc; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_ctrl_is_load; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_ctrl_is_sta; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_ctrl_is_std; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_exe_0_req_bits_uop_rob_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_exe_0_req_bits_uop_ldq_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_exe_0_req_bits_uop_stq_idx; // @[tracegen.scala:241:25] wire [4:0] _boom_shim_io_lsu_exe_0_req_bits_uop_mem_cmd; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_is_amo; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_uses_ldq; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_exe_0_req_bits_uop_uses_stq; // @[tracegen.scala:241:25] wire [63:0] _boom_shim_io_lsu_exe_0_req_bits_data; // @[tracegen.scala:241:25] wire [33:0] _boom_shim_io_lsu_exe_0_req_bits_addr; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_valid; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_dis_uops_0_bits_uopc; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_ctrl_is_load; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_ctrl_is_sta; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_ctrl_is_std; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_dis_uops_0_bits_rob_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_dis_uops_0_bits_ldq_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_dis_uops_0_bits_stq_idx; // @[tracegen.scala:241:25] wire [4:0] _boom_shim_io_lsu_dis_uops_0_bits_mem_cmd; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_is_amo; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_uses_ldq; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_dis_uops_0_bits_uses_stq; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_valids_0; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_uopc; // @[tracegen.scala:241:25] wire [31:0] _boom_shim_io_lsu_commit_uops_0_inst; // @[tracegen.scala:241:25] wire [31:0] _boom_shim_io_lsu_commit_uops_0_debug_inst; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_rvc; // @[tracegen.scala:241:25] wire [33:0] _boom_shim_io_lsu_commit_uops_0_debug_pc; // @[tracegen.scala:241:25] wire [2:0] _boom_shim_io_lsu_commit_uops_0_iq_type; // @[tracegen.scala:241:25] wire [9:0] _boom_shim_io_lsu_commit_uops_0_fu_code; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_ctrl_br_type; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_ctrl_op1_sel; // @[tracegen.scala:241:25] wire [2:0] _boom_shim_io_lsu_commit_uops_0_ctrl_op2_sel; // @[tracegen.scala:241:25] wire [2:0] _boom_shim_io_lsu_commit_uops_0_ctrl_imm_sel; // @[tracegen.scala:241:25] wire [4:0] _boom_shim_io_lsu_commit_uops_0_ctrl_op_fcn; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ctrl_fcn_dw; // @[tracegen.scala:241:25] wire [2:0] _boom_shim_io_lsu_commit_uops_0_ctrl_csr_cmd; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ctrl_is_load; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ctrl_is_sta; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ctrl_is_std; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_iw_state; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_iw_p1_poisoned; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_iw_p2_poisoned; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_br; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_jalr; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_jal; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_sfb; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_br_mask; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_br_tag; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_ftq_idx; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_edge_inst; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_pc_lob; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_taken; // @[tracegen.scala:241:25] wire [19:0] _boom_shim_io_lsu_commit_uops_0_imm_packed; // @[tracegen.scala:241:25] wire [11:0] _boom_shim_io_lsu_commit_uops_0_csr_addr; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_rob_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_ldq_idx; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_stq_idx; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_rxq_idx; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_pdst; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_prs1; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_prs2; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_prs3; // @[tracegen.scala:241:25] wire [3:0] _boom_shim_io_lsu_commit_uops_0_ppred; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_prs1_busy; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_prs2_busy; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_prs3_busy; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ppred_busy; // @[tracegen.scala:241:25] wire [6:0] _boom_shim_io_lsu_commit_uops_0_stale_pdst; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_exception; // @[tracegen.scala:241:25] wire [63:0] _boom_shim_io_lsu_commit_uops_0_exc_cause; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_bypassable; // @[tracegen.scala:241:25] wire [4:0] _boom_shim_io_lsu_commit_uops_0_mem_cmd; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_mem_size; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_mem_signed; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_fence; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_fencei; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_amo; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_uses_ldq; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_uses_stq; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_sys_pc2epc; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_is_unique; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_flush_on_commit; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ldst_is_rs1; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_ldst; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_lrs1; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_lrs2; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_commit_uops_0_lrs3; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_ldst_val; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_dst_rtype; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_lrs1_rtype; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_lrs2_rtype; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_frs3_en; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_fp_val; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_fp_single; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_xcpt_pf_if; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_xcpt_ae_if; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_xcpt_ma_if; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_bp_debug_if; // @[tracegen.scala:241:25] wire _boom_shim_io_lsu_commit_uops_0_bp_xcpt_if; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_debug_fsrc; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_lsu_commit_uops_0_debug_tsrc; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_rob_pnr_idx; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_lsu_rob_head_idx; // @[tracegen.scala:241:25] wire _boom_shim_io_tracegen_req_ready; // @[tracegen.scala:241:25] wire _boom_shim_io_tracegen_resp_valid; // @[tracegen.scala:241:25] wire [5:0] _boom_shim_io_tracegen_resp_bits_tag; // @[tracegen.scala:241:25] wire [1:0] _boom_shim_io_tracegen_resp_bits_size; // @[tracegen.scala:241:25] wire [63:0] _boom_shim_io_tracegen_resp_bits_data; // @[tracegen.scala:241:25] wire _boom_shim_io_tracegen_ordered; // @[tracegen.scala:241:25] wire [20:0] _lsu_io_ptw_req_bits_bits_addr; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_valid; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_uopc; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_exe_0_iresp_bits_uop_inst; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_inst; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_rvc; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_pc; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_iq_type; // @[tracegen.scala:240:19] wire [9:0] _lsu_io_core_exe_0_iresp_bits_uop_fu_code; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_iw_state; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_br; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_jalr; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_jal; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_sfb; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_br_mask; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_br_tag; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ftq_idx; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_edge_inst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_pc_lob; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_taken; // @[tracegen.scala:240:19] wire [19:0] _lsu_io_core_exe_0_iresp_bits_uop_imm_packed; // @[tracegen.scala:240:19] wire [11:0] _lsu_io_core_exe_0_iresp_bits_uop_csr_addr; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_rob_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ldq_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_stq_idx; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_rxq_idx; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_pdst; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs1; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs2; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs3; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ppred; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_prs1_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_prs2_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_prs3_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ppred_busy; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_stale_pdst; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_exception; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_core_exe_0_iresp_bits_uop_exc_cause; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_bypassable; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_mem_cmd; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_mem_size; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_mem_signed; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_fence; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_fencei; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_amo; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_uses_ldq; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_uses_stq; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_is_unique; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_ldst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs2; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs3; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_ldst_val; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_dst_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_frs3_en; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_fp_val; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_fp_single; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_core_exe_0_iresp_bits_data; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_valid; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_uopc; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_exe_0_fresp_bits_uop_inst; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_inst; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_rvc; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_pc; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_iq_type; // @[tracegen.scala:240:19] wire [9:0] _lsu_io_core_exe_0_fresp_bits_uop_fu_code; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_iw_state; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_br; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_jalr; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_jal; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_sfb; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_br_mask; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_br_tag; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ftq_idx; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_edge_inst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_pc_lob; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_taken; // @[tracegen.scala:240:19] wire [19:0] _lsu_io_core_exe_0_fresp_bits_uop_imm_packed; // @[tracegen.scala:240:19] wire [11:0] _lsu_io_core_exe_0_fresp_bits_uop_csr_addr; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_rob_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ldq_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_stq_idx; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_rxq_idx; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_pdst; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs1; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs2; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs3; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ppred; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_prs1_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_prs2_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_prs3_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ppred_busy; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_stale_pdst; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_exception; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_core_exe_0_fresp_bits_uop_exc_cause; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_bypassable; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_mem_cmd; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_mem_size; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_mem_signed; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_fence; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_fencei; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_amo; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_uses_ldq; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_uses_stq; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_is_unique; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_ldst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs2; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs3; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_ldst_val; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_dst_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_frs3_en; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_fp_val; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_fp_single; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if; // @[tracegen.scala:240:19] wire _lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc; // @[tracegen.scala:240:19] wire [64:0] _lsu_io_core_exe_0_fresp_bits_data; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_dis_ldq_idx_0; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_dis_stq_idx_0; // @[tracegen.scala:240:19] wire _lsu_io_core_ldq_full_0; // @[tracegen.scala:240:19] wire _lsu_io_core_stq_full_0; // @[tracegen.scala:240:19] wire _lsu_io_core_fp_stdata_ready; // @[tracegen.scala:240:19] wire _lsu_io_core_clr_bsy_0_valid; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_clr_bsy_0_bits; // @[tracegen.scala:240:19] wire _lsu_io_core_clr_bsy_1_valid; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_clr_bsy_1_bits; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_clr_unsafe_0_bits; // @[tracegen.scala:240:19] wire _lsu_io_core_spec_ld_wakeup_0_valid; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_spec_ld_wakeup_0_bits; // @[tracegen.scala:240:19] wire _lsu_io_core_ld_miss; // @[tracegen.scala:240:19] wire _lsu_io_core_fencei_rdy; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_valid; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_uopc; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_lxcpt_bits_uop_inst; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_core_lxcpt_bits_uop_debug_inst; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_rvc; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_core_lxcpt_bits_uop_debug_pc; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_lxcpt_bits_uop_iq_type; // @[tracegen.scala:240:19] wire [9:0] _lsu_io_core_lxcpt_bits_uop_fu_code; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_ctrl_br_type; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_load; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_sta; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_std; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_iw_state; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_br; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_jalr; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_jal; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_sfb; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_br_mask; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_br_tag; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_ftq_idx; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_edge_inst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_pc_lob; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_taken; // @[tracegen.scala:240:19] wire [19:0] _lsu_io_core_lxcpt_bits_uop_imm_packed; // @[tracegen.scala:240:19] wire [11:0] _lsu_io_core_lxcpt_bits_uop_csr_addr; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_rob_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_ldq_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_stq_idx; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_rxq_idx; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_pdst; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs1; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs2; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs3; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_core_lxcpt_bits_uop_ppred; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_prs1_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_prs2_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_prs3_busy; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ppred_busy; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_core_lxcpt_bits_uop_stale_pdst; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_exception; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_core_lxcpt_bits_uop_exc_cause; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_bypassable; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_lxcpt_bits_uop_mem_cmd; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_mem_size; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_mem_signed; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_fence; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_fencei; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_amo; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_uses_ldq; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_uses_stq; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_is_unique; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_flush_on_commit; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ldst_is_rs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_ldst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs2; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs3; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_ldst_val; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_dst_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs1_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs2_rtype; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_frs3_en; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_fp_val; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_fp_single; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_xcpt_pf_if; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_xcpt_ae_if; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_xcpt_ma_if; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_bp_debug_if; // @[tracegen.scala:240:19] wire _lsu_io_core_lxcpt_bits_uop_bp_xcpt_if; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_debug_fsrc; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_core_lxcpt_bits_uop_debug_tsrc; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_core_lxcpt_bits_cause; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_core_lxcpt_bits_badvaddr; // @[tracegen.scala:240:19] wire _lsu_io_core_perf_acquire; // @[tracegen.scala:240:19] wire _lsu_io_core_perf_release; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_valid; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_valid; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_uopc; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_inst; // @[tracegen.scala:240:19] wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_inst; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_rvc; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_pc; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_iq_type; // @[tracegen.scala:240:19] wire [9:0] _lsu_io_dmem_req_bits_0_bits_uop_fu_code; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:240:19] wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_iw_state; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_br; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_jalr; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_jal; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_sfb; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_br_mask; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_br_tag; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ftq_idx; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_edge_inst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_pc_lob; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_taken; // @[tracegen.scala:240:19] wire [19:0] _lsu_io_dmem_req_bits_0_bits_uop_imm_packed; // @[tracegen.scala:240:19] wire [11:0] _lsu_io_dmem_req_bits_0_bits_uop_csr_addr; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_rob_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ldq_idx; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_stq_idx; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_rxq_idx; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_pdst; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs1; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs2; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs3; // @[tracegen.scala:240:19] wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ppred; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_prs1_busy; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_prs2_busy; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_prs3_busy; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ppred_busy; // @[tracegen.scala:240:19] wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_stale_pdst; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_exception; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_dmem_req_bits_0_bits_uop_exc_cause; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_bypassable; // @[tracegen.scala:240:19] wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_cmd; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_size; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_mem_signed; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_fence; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_fencei; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_amo; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_uses_ldq; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_uses_stq; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_is_unique; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_ldst; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs3; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_val; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_dst_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_frs3_en; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_val; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_fp_single; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc; // @[tracegen.scala:240:19] wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc; // @[tracegen.scala:240:19] wire [33:0] _lsu_io_dmem_req_bits_0_bits_addr; // @[tracegen.scala:240:19] wire [63:0] _lsu_io_dmem_req_bits_0_bits_data; // @[tracegen.scala:240:19] wire _lsu_io_dmem_req_bits_0_bits_is_hella; // @[tracegen.scala:240:19] wire _lsu_io_dmem_s1_kill_0; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_rob_pnr_idx; // @[tracegen.scala:240:19] wire [5:0] _lsu_io_dmem_rob_head_idx; // @[tracegen.scala:240:19] wire _lsu_io_dmem_release_ready; // @[tracegen.scala:240:19] wire _lsu_io_dmem_force_order; // @[tracegen.scala:240:19] wire _ptw_io_requestors_0_resp_valid; // @[tracegen.scala:238:19] wire [43:0] _ptw_io_requestors_0_resp_bits_pte_ppn; // @[tracegen.scala:238:19] wire _tracegen_io_finished; // @[tracegen.scala:235:24] wire _tracegen_io_timeout; // @[tracegen.scala:235:24] wire _tracegen_io_mem_req_valid; // @[tracegen.scala:235:24] wire [39:0] _tracegen_io_mem_req_bits_addr; // @[tracegen.scala:235:24] wire [6:0] _tracegen_io_mem_req_bits_tag; // @[tracegen.scala:235:24] wire [4:0] _tracegen_io_mem_req_bits_cmd; // @[tracegen.scala:235:24] wire [63:0] _tracegen_io_mem_req_bits_data; // @[tracegen.scala:235:24] wire [63:0] _tracegen_io_mem_s1_data_data; // @[tracegen.scala:235:24] wire _dcache_io_lsu_req_ready; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_valid; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_uopc; // @[tracegen.scala:221:26] wire [31:0] _dcache_io_lsu_resp_0_bits_uop_inst; // @[tracegen.scala:221:26] wire [31:0] _dcache_io_lsu_resp_0_bits_uop_debug_inst; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_rvc; // @[tracegen.scala:221:26] wire [33:0] _dcache_io_lsu_resp_0_bits_uop_debug_pc; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_iq_type; // @[tracegen.scala:221:26] wire [9:0] _dcache_io_lsu_resp_0_bits_uop_fu_code; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_br_type; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel; // @[tracegen.scala:221:26] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_load; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_std; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_iw_state; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_br; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_jalr; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_jal; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_sfb; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_br_mask; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_br_tag; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ftq_idx; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_edge_inst; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_pc_lob; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_taken; // @[tracegen.scala:221:26] wire [19:0] _dcache_io_lsu_resp_0_bits_uop_imm_packed; // @[tracegen.scala:221:26] wire [11:0] _dcache_io_lsu_resp_0_bits_uop_csr_addr; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_rob_idx; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ldq_idx; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_stq_idx; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_rxq_idx; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_pdst; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs1; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs2; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs3; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ppred; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_prs1_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_prs2_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_prs3_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ppred_busy; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_resp_0_bits_uop_stale_pdst; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_exception; // @[tracegen.scala:221:26] wire [63:0] _dcache_io_lsu_resp_0_bits_uop_exc_cause; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_bypassable; // @[tracegen.scala:221:26] wire [4:0] _dcache_io_lsu_resp_0_bits_uop_mem_cmd; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_mem_size; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_mem_signed; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_fence; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_fencei; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_amo; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_uses_ldq; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_uses_stq; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_is_unique; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_flush_on_commit; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_ldst; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs1; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs2; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs3; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_ldst_val; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_dst_rtype; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs1_rtype; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs2_rtype; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_frs3_en; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_fp_val; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_fp_single; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_bp_debug_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_debug_fsrc; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_resp_0_bits_uop_debug_tsrc; // @[tracegen.scala:221:26] wire [63:0] _dcache_io_lsu_resp_0_bits_data; // @[tracegen.scala:221:26] wire _dcache_io_lsu_resp_0_bits_is_hella; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_valid; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_uopc; // @[tracegen.scala:221:26] wire [31:0] _dcache_io_lsu_nack_0_bits_uop_inst; // @[tracegen.scala:221:26] wire [31:0] _dcache_io_lsu_nack_0_bits_uop_debug_inst; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_rvc; // @[tracegen.scala:221:26] wire [33:0] _dcache_io_lsu_nack_0_bits_uop_debug_pc; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_iq_type; // @[tracegen.scala:221:26] wire [9:0] _dcache_io_lsu_nack_0_bits_uop_fu_code; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_br_type; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel; // @[tracegen.scala:221:26] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_load; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_std; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_iw_state; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_br; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_jalr; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_jal; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_sfb; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_br_mask; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_br_tag; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ftq_idx; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_edge_inst; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_pc_lob; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_taken; // @[tracegen.scala:221:26] wire [19:0] _dcache_io_lsu_nack_0_bits_uop_imm_packed; // @[tracegen.scala:221:26] wire [11:0] _dcache_io_lsu_nack_0_bits_uop_csr_addr; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_rob_idx; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ldq_idx; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_stq_idx; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_rxq_idx; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_pdst; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs1; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs2; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs3; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ppred; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_prs1_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_prs2_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_prs3_busy; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ppred_busy; // @[tracegen.scala:221:26] wire [6:0] _dcache_io_lsu_nack_0_bits_uop_stale_pdst; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_exception; // @[tracegen.scala:221:26] wire [63:0] _dcache_io_lsu_nack_0_bits_uop_exc_cause; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_bypassable; // @[tracegen.scala:221:26] wire [4:0] _dcache_io_lsu_nack_0_bits_uop_mem_cmd; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_mem_size; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_mem_signed; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_fence; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_fencei; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_amo; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_uses_ldq; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_uses_stq; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_is_unique; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_flush_on_commit; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_ldst; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs1; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs2; // @[tracegen.scala:221:26] wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs3; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_ldst_val; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_dst_rtype; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs1_rtype; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs2_rtype; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_frs3_en; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_fp_val; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_fp_single; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_bp_debug_if; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_debug_fsrc; // @[tracegen.scala:221:26] wire [1:0] _dcache_io_lsu_nack_0_bits_uop_debug_tsrc; // @[tracegen.scala:221:26] wire [33:0] _dcache_io_lsu_nack_0_bits_addr; // @[tracegen.scala:221:26] wire [63:0] _dcache_io_lsu_nack_0_bits_data; // @[tracegen.scala:221:26] wire _dcache_io_lsu_nack_0_bits_is_hella; // @[tracegen.scala:221:26] wire _dcache_io_lsu_release_valid; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_release_bits_opcode; // @[tracegen.scala:221:26] wire [2:0] _dcache_io_lsu_release_bits_param; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_release_bits_size; // @[tracegen.scala:221:26] wire [3:0] _dcache_io_lsu_release_bits_source; // @[tracegen.scala:221:26] wire [31:0] _dcache_io_lsu_release_bits_address; // @[tracegen.scala:221:26] wire [63:0] _dcache_io_lsu_release_bits_data; // @[tracegen.scala:221:26] wire _dcache_io_lsu_ordered; // @[tracegen.scala:221:26] wire _dcache_io_lsu_perf_acquire; // @[tracegen.scala:221:26] wire _dcache_io_lsu_perf_release; // @[tracegen.scala:221:26] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[tracegen.scala:229:7] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[tracegen.scala:229:7] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[tracegen.scala:229:7] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[tracegen.scala:229:7] wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[tracegen.scala:229:7] wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[tracegen.scala:229:7] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[tracegen.scala:229:7] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[tracegen.scala:229:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[tracegen.scala:229:7] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[tracegen.scala:229:7] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[tracegen.scala:229:7] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[tracegen.scala:229:7] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[tracegen.scala:229:7] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[tracegen.scala:229:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[tracegen.scala:229:7] wire auto_hartid_in_0 = auto_hartid_in; // @[tracegen.scala:229:7] wire _ceaseNodeOut_0_T_3 = reset; // @[Interrupts.scala:121:13] wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[tracegen.scala:229:7] wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[tracegen.scala:229:7] wire auto_status_out_error_valid = 1'h0; // @[tracegen.scala:229:7] wire auto_wfi_out_0 = 1'h0; // @[tracegen.scala:229:7] wire auto_int_local_in_3_0 = 1'h0; // @[tracegen.scala:229:7] wire auto_int_local_in_2_0 = 1'h0; // @[tracegen.scala:229:7] wire auto_int_local_in_1_0 = 1'h0; // @[tracegen.scala:229:7] wire auto_int_local_in_1_1 = 1'h0; // @[tracegen.scala:229:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[tracegen.scala:229:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[tracegen.scala:229:7] wire auto_trace_source_out_insns_0_valid = 1'h0; // @[tracegen.scala:229:7] wire auto_trace_source_out_insns_0_exception = 1'h0; // @[tracegen.scala:229:7] wire auto_trace_source_out_insns_0_interrupt = 1'h0; // @[tracegen.scala:229:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_auto_in_0_valid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_2_nodeIn_0_valid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceSourceNodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire bpwatchSourceNodeOut_0_valid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1 = 1'h0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0 = 1'h0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0 = 1'h0; // @[MixedNode.scala:542:17] wire x1_int_localIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire x1_int_localIn_1 = 1'h0; // @[MixedNode.scala:551:17] wire x1_int_localIn_1_0 = 1'h0; // @[MixedNode.scala:551:17] wire x1_int_localIn_2_0 = 1'h0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1 = 1'h0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2 = 1'h0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3 = 1'h0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4 = 1'h0; // @[MixedNode.scala:551:17] wire wfiNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire statusNodeOut_error_valid = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire masterNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire [3:0] auto_status_out_timeout_bits = 4'h0; // @[tracegen.scala:229:7] wire [3:0] auto_status_out_error_bits = 4'h0; // @[tracegen.scala:229:7] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[tracegen.scala:229:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[tracegen.scala:229:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] statusNodeOut_timeout_bits = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] statusNodeOut_error_bits = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[tracegen.scala:229:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[tracegen.scala:229:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[tracegen.scala:229:7] wire [31:0] auto_trace_source_out_insns_0_insn = 32'h0; // @[tracegen.scala:229:7] wire [31:0] auto_reset_vector_in = 32'h0; // @[tracegen.scala:229:7] wire [31:0] broadcast_1_auto_in = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_1_auto_out = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_1_nodeIn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] broadcast_1_nodeOut = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] resetVectorSinkNodeIn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] reset_vectorOut = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] reset_vectorIn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceSourceNodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire [39:0] auto_trace_source_out_insns_0_iaddr = 40'h0; // @[tracegen.scala:229:7] wire [39:0] auto_trace_source_out_insns_0_tval = 40'h0; // @[tracegen.scala:229:7] wire [39:0] traceSourceNodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17] wire [2:0] auto_trace_source_out_insns_0_priv = 3'h0; // @[tracegen.scala:229:7] wire [2:0] broadcast_2_auto_in_0_action = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] broadcast_2_nodeIn_0_action = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] traceSourceNodeOut_insns_0_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] bpwatchSourceNodeOut_0_action = 3'h0; // @[MixedNode.scala:542:17] wire [63:0] auto_trace_source_out_insns_0_cause = 64'h0; // @[tracegen.scala:229:7] wire [63:0] auto_trace_source_out_time = 64'h0; // @[tracegen.scala:229:7] wire [63:0] traceSourceNodeOut_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_time = 64'h0; // @[MixedNode.scala:542:17] wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire statusNodeOut_timeout_valid; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0; // @[MixedNode.scala:542:17] wire haltNodeOut_0; // @[MixedNode.scala:542:17] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[MixedNode.scala:551:17] wire hartidIn = auto_hartid_in_0; // @[MixedNode.scala:551:17] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_a_bits_size_0; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_a_bits_source_0; // @[tracegen.scala:229:7] wire [31:0] auto_buffer_out_a_bits_address_0; // @[tracegen.scala:229:7] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[tracegen.scala:229:7] wire [63:0] auto_buffer_out_a_bits_data_0; // @[tracegen.scala:229:7] wire auto_buffer_out_a_valid_0; // @[tracegen.scala:229:7] wire auto_buffer_out_b_ready_0; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_c_bits_param_0; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_c_bits_size_0; // @[tracegen.scala:229:7] wire [3:0] auto_buffer_out_c_bits_source_0; // @[tracegen.scala:229:7] wire [31:0] auto_buffer_out_c_bits_address_0; // @[tracegen.scala:229:7] wire [63:0] auto_buffer_out_c_bits_data_0; // @[tracegen.scala:229:7] wire auto_buffer_out_c_valid_0; // @[tracegen.scala:229:7] wire auto_buffer_out_d_ready_0; // @[tracegen.scala:229:7] wire [2:0] auto_buffer_out_e_bits_sink_0; // @[tracegen.scala:229:7] wire auto_buffer_out_e_valid_0; // @[tracegen.scala:229:7] wire auto_status_out_timeout_valid_0; // @[tracegen.scala:229:7] wire auto_cease_out_0_0; // @[tracegen.scala:229:7] wire auto_halt_out_0_0; // @[tracegen.scala:229:7] wire hartidOut; // @[MixedNode.scala:542:17] wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire broadcast_nodeOut; // @[MixedNode.scala:542:17] wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire masterNodeOut_b_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] masterNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] masterNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] masterNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire masterNodeOut_c_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] masterNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] masterNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire masterNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] masterNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [3:0] masterNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] masterNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire masterNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] masterNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17] wire masterNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire masterNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire masterNodeOut_e_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] wire int_localOut_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] assign auto_halt_out_0_0 = haltNodeOut_0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0_cease; // @[Interrupts.scala:111:29] assign auto_cease_out_0_0 = ceaseNodeOut_0; // @[MixedNode.scala:542:17] assign auto_status_out_timeout_valid_0 = statusNodeOut_timeout_valid; // @[MixedNode.scala:542:17] wire masterNodeIn_a_ready = masterNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_valid = masterNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_opcode = masterNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_param = masterNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_size = masterNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] masterNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_source = masterNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_address = masterNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] masterNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_mask = masterNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] masterNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_data = masterNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire masterNodeIn_b_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_b_ready = masterNodeOut_b_ready; // @[Buffer.scala:40:9] wire masterNodeIn_b_valid = masterNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_b_bits_opcode = masterNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] masterNodeIn_b_bits_param = masterNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_b_bits_size = masterNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_b_bits_source = masterNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] masterNodeIn_b_bits_address = masterNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] masterNodeIn_b_bits_mask = masterNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] masterNodeIn_b_bits_data = masterNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_b_bits_corrupt = masterNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_c_ready = masterNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_c_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_valid = masterNodeOut_c_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_opcode = masterNodeOut_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] masterNodeIn_c_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_param = masterNodeOut_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] masterNodeIn_c_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_size = masterNodeOut_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] masterNodeIn_c_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_source = masterNodeOut_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] masterNodeIn_c_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_address = masterNodeOut_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] masterNodeIn_c_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_data = masterNodeOut_c_bits_data; // @[Buffer.scala:40:9] wire masterNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_d_ready = masterNodeOut_d_ready; // @[Buffer.scala:40:9] wire masterNodeIn_d_valid = masterNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_d_bits_opcode = masterNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] masterNodeIn_d_bits_param = masterNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_d_bits_size = masterNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [3:0] masterNodeIn_d_bits_source = masterNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] masterNodeIn_d_bits_sink = masterNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_bits_denied = masterNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] masterNodeIn_d_bits_data = masterNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_d_bits_corrupt = masterNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_e_ready = masterNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire masterNodeIn_e_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_valid = masterNodeOut_e_valid; // @[Buffer.scala:40:9] wire [2:0] masterNodeIn_e_bits_sink; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_bits_sink = masterNodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign masterNodeOut_a_valid = masterNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_opcode = masterNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_param = masterNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_size = masterNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_source = masterNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_address = masterNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_mask = masterNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_a_bits_data = masterNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_b_ready = masterNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_valid = masterNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_opcode = masterNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_param = masterNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_size = masterNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_source = masterNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_address = masterNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_c_bits_data = masterNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_d_ready = masterNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_e_valid = masterNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign masterNodeOut_e_bits_sink = masterNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] reg [3:0] ceaseNodeOut_0_cease_count; // @[Interrupts.scala:110:26] assign ceaseNodeOut_0_cease = ceaseNodeOut_0_cease_count[3]; // @[Interrupts.scala:110:26, :111:29] assign ceaseNodeOut_0 = ceaseNodeOut_0_cease; // @[Interrupts.scala:111:29] wire _ceaseNodeOut_0_cease_T = ~_tracegen_io_finished; // @[Interrupts.scala:112:13] wire _ceaseNodeOut_0_cease_T_1 = ~ceaseNodeOut_0_cease; // @[Interrupts.scala:111:29, :113:22] wire _ceaseNodeOut_0_cease_T_2 = _tracegen_io_finished & _ceaseNodeOut_0_cease_T_1; // @[Interrupts.scala:113:{19,22}] wire [4:0] _ceaseNodeOut_0_cease_count_T = {1'h0, ceaseNodeOut_0_cease_count} + 5'h1; // @[Interrupts.scala:110:26, :113:51] wire [3:0] _ceaseNodeOut_0_cease_count_T_1 = _ceaseNodeOut_0_cease_count_T[3:0]; // @[Interrupts.scala:113:51] reg ceaseNodeOut_0_prev_cease; // @[Interrupts.scala:120:31] wire _ceaseNodeOut_0_T = ~ceaseNodeOut_0_cease; // @[Interrupts.scala:111:29, :113:22, :121:29] wire _ceaseNodeOut_0_T_1 = ceaseNodeOut_0_prev_cease & _ceaseNodeOut_0_T; // @[Interrupts.scala:120:31, :121:{27,29}] wire _ceaseNodeOut_0_T_2 = ~_ceaseNodeOut_0_T_1; // @[Interrupts.scala:121:{14,27}] wire _ceaseNodeOut_0_T_4 = ~_ceaseNodeOut_0_T_3; // @[Interrupts.scala:121:13] wire _ceaseNodeOut_0_T_5 = ~_ceaseNodeOut_0_T_2; // @[Interrupts.scala:121:{13,14}] reg haltNodeOut_0_r; // @[Interrupts.scala:97:55] assign haltNodeOut_0 = haltNodeOut_0_r; // @[Interrupts.scala:97:55]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_91 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_183 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_184 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_185 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_186 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_91( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_207 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_375 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_207( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_375 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLDebugModuleInnerAsync : output auto : { flip dmiXing_in : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, dmInner_sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip dmInner_custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip dmInner_tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip debug_clock : Clock, flip debug_reset : Reset, flip tl_clock : Clock, flip tl_reset : Reset, flip dmactive : UInt<1>, flip innerCtrl : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[4], hrmask : UInt<1>[4]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip debugUnavail : UInt<1>[4], hgDebugInt : UInt<1>[4], flip hartIsInReset : UInt<1>[4]} input rf_reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst dmInner of TLDebugModuleInner connect dmInner.clock, childClock connect dmInner.reset, childReset inst dmiXing of TLAsyncCrossingSink_a9d32s1k1z2u connect dmiXing.clock, childClock connect dmiXing.reset, childReset connect dmInner.auto.dmi_in, dmiXing.auto.out connect dmInner.auto.tl_in, auto.dmInner_tl_in connect dmInner.auto.custom_in, auto.dmInner_custom_in connect dmInner.auto.sb2tlOpt_out.d, auto.dmInner_sb2tlOpt_out.d connect auto.dmInner_sb2tlOpt_out.a.bits, dmInner.auto.sb2tlOpt_out.a.bits connect auto.dmInner_sb2tlOpt_out.a.valid, dmInner.auto.sb2tlOpt_out.a.valid connect dmInner.auto.sb2tlOpt_out.a.ready, auto.dmInner_sb2tlOpt_out.a.ready connect dmiXing.auto.in, auto.dmiXing_in connect childClock, io.debug_clock connect childReset, io.debug_reset inst dmactive_synced_dmactive_synced_dmactiveSync of AsyncResetSynchronizerShiftReg_w1_d3_i0_30 connect dmactive_synced_dmactive_synced_dmactiveSync.clock, childClock connect dmactive_synced_dmactive_synced_dmactiveSync.reset, childReset connect dmactive_synced_dmactive_synced_dmactiveSync.io.d, io.dmactive wire dmactive_synced : UInt<1> connect dmactive_synced, dmactive_synced_dmactive_synced_dmactiveSync.io.q connect dmInner.clock, io.debug_clock connect dmInner.reset, io.debug_reset connect dmInner.io.tl_clock, io.tl_clock connect dmInner.io.tl_reset, io.tl_reset connect dmInner.io.dmactive, dmactive_synced inst dmactive_synced_dmInner_io_innerCtrl_sink of AsyncQueueSink_DebugInternalBundle connect dmactive_synced_dmInner_io_innerCtrl_sink.clock, childClock connect dmactive_synced_dmInner_io_innerCtrl_sink.reset, childReset connect dmactive_synced_dmInner_io_innerCtrl_sink.io.async, io.innerCtrl connect dmInner.io.innerCtrl, dmactive_synced_dmInner_io_innerCtrl_sink.io.deq connect dmInner.io.debugUnavail[0], io.debugUnavail[0] connect dmInner.io.debugUnavail[1], io.debugUnavail[1] connect dmInner.io.debugUnavail[2], io.debugUnavail[2] connect dmInner.io.debugUnavail[3], io.debugUnavail[3] connect io.hgDebugInt, dmInner.io.hgDebugInt connect dmInner.io.hartIsInReset[0], io.hartIsInReset[0] connect dmInner.io.hartIsInReset[1], io.hartIsInReset[1] connect dmInner.io.hartIsInReset[2], io.hartIsInReset[2] connect dmInner.io.hartIsInReset[3], io.hartIsInReset[3]

module TLDebugModuleInnerAsync( // @[Debug.scala:1871:9] input [2:0] auto_dmiXing_in_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmiXing_in_a_mem_0_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmiXing_in_a_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_ridx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_widx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmiXing_in_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmiXing_in_d_mem_0_size, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_mem_0_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmiXing_in_d_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_ridx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_widx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_debug_clock, // @[Debug.scala:1877:16] input io_debug_reset, // @[Debug.scala:1877:16] input io_tl_clock, // @[Debug.scala:1877:16] input io_tl_reset, // @[Debug.scala:1877:16] input io_dmactive, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_resumereq, // @[Debug.scala:1877:16] input [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hasel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_0, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_1, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_2, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_3, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_1, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_2, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_3, // @[Debug.scala:1877:16] output io_innerCtrl_ridx, // @[Debug.scala:1877:16] input io_innerCtrl_widx, // @[Debug.scala:1877:16] output io_innerCtrl_safe_ridx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_widx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_source_reset_n, // @[Debug.scala:1877:16] output io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:1877:16] output io_hgDebugInt_0, // @[Debug.scala:1877:16] output io_hgDebugInt_1, // @[Debug.scala:1877:16] output io_hgDebugInt_2, // @[Debug.scala:1877:16] output io_hgDebugInt_3, // @[Debug.scala:1877:16] input io_hartIsInReset_0, // @[Debug.scala:1877:16] input io_hartIsInReset_1, // @[Debug.scala:1877:16] input io_hartIsInReset_2, // @[Debug.scala:1877:16] input io_hartIsInReset_3, // @[Debug.scala:1877:16] input rf_reset // @[Debug.scala:1904:22] ); wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala:211:22] wire [9:0] _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3; // @[AsyncQueue.scala:211:22] wire _dmiXing_auto_out_a_valid; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_opcode; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_param; // @[Debug.scala:1858:27] wire [1:0] _dmiXing_auto_out_a_bits_size; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_source; // @[Debug.scala:1858:27] wire [8:0] _dmiXing_auto_out_a_bits_address; // @[Debug.scala:1858:27] wire [3:0] _dmiXing_auto_out_a_bits_mask; // @[Debug.scala:1858:27] wire [31:0] _dmiXing_auto_out_a_bits_data; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_d_ready; // @[Debug.scala:1858:27] wire _dmInner_auto_dmi_in_a_ready; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_valid; // @[Debug.scala:1857:27] wire [2:0] _dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala:1857:27] wire [1:0] _dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala:1857:27] wire [31:0] _dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala:1857:27] wire [2:0] auto_dmiXing_in_a_mem_0_opcode_0 = auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala:1871:9] wire [8:0] auto_dmiXing_in_a_mem_0_address_0 = auto_dmiXing_in_a_mem_0_address; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_a_mem_0_data_0 = auto_dmiXing_in_a_mem_0_data; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_widx_0 = auto_dmiXing_in_a_widx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_widx_valid_0 = auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_source_reset_n_0 = auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_ridx_0 = auto_dmiXing_in_d_ridx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_ridx_valid_0 = auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_sink_reset_n_0 = auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_valid_0 = auto_dmInner_tl_in_a_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_param_0 = auto_dmInner_tl_in_a_bits_param; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_a_bits_size_0 = auto_dmInner_tl_in_a_bits_size; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_a_bits_source_0 = auto_dmInner_tl_in_a_bits_source; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_a_bits_address_0 = auto_dmInner_tl_in_a_bits_address; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_a_bits_data_0 = auto_dmInner_tl_in_a_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_ready_0 = auto_dmInner_tl_in_d_ready; // @[Debug.scala:1871:9] wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1871:9] wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1871:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1871:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1871:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_resumereq_0 = io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1871:9] wire [9:0] io_innerCtrl_mem_0_hartsel_0 = io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_ackhavereset_0 = io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hasel_0 = io_innerCtrl_mem_0_hasel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_0_0 = io_innerCtrl_mem_0_hamask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_1_0 = io_innerCtrl_mem_0_hamask_1; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_2_0 = io_innerCtrl_mem_0_hamask_2; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_3_0 = io_innerCtrl_mem_0_hamask_3; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_0_0 = io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_1_0 = io_innerCtrl_mem_0_hrmask_1; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_2_0 = io_innerCtrl_mem_0_hrmask_2; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_3_0 = io_innerCtrl_mem_0_hrmask_3; // @[Debug.scala:1871:9] wire io_innerCtrl_widx_0 = io_innerCtrl_widx; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_widx_valid_0 = io_innerCtrl_safe_widx_valid; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_source_reset_n_0 = io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1871:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1871:9] wire io_hartIsInReset_1_0 = io_hartIsInReset_1; // @[Debug.scala:1871:9] wire io_hartIsInReset_2_0 = io_hartIsInReset_2; // @[Debug.scala:1871:9] wire io_hartIsInReset_3_0 = io_hartIsInReset_3; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_1 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_2 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_3 = 1'h0; // @[Debug.scala:1871:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire auto_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[AsyncQueue.scala:211:22] wire [31:0] auto_dmiXing_in_b_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [31:0] auto_dmiXing_in_c_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [3:0] auto_dmiXing_in_b_mem_0_mask = 4'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_b_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_c_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_c_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1871:9] wire [3:0] auto_dmiXing_in_a_mem_0_mask = 4'hF; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_a_mem_0_size = 2'h2; // @[Debug.scala:1858:27, :1871:9] wire [2:0] auto_dmiXing_in_a_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_b_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1871:9] wire childClock = io_debug_clock_0; // @[Debug.scala:1871:9] wire childReset = io_debug_reset_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_0_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_1_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_2_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_3_0; // @[Debug.scala:1871:9] wire dmactive_synced; // @[ShiftReg.scala:48:24] TLDebugModuleInner dmInner ( // @[Debug.scala:1857:27] .clock (io_debug_clock_0), // @[Debug.scala:1871:9] .reset (io_debug_reset_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_ready (auto_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_valid (auto_dmInner_sb2tlOpt_out_a_valid_0), .auto_sb2tlOpt_out_a_bits_opcode (auto_dmInner_sb2tlOpt_out_a_bits_opcode_0), .auto_sb2tlOpt_out_a_bits_size (auto_dmInner_sb2tlOpt_out_a_bits_size_0), .auto_sb2tlOpt_out_a_bits_address (auto_dmInner_sb2tlOpt_out_a_bits_address_0), .auto_sb2tlOpt_out_a_bits_data (auto_dmInner_sb2tlOpt_out_a_bits_data_0), .auto_sb2tlOpt_out_d_ready (auto_dmInner_sb2tlOpt_out_d_ready_0), .auto_sb2tlOpt_out_d_valid (auto_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_opcode (auto_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_param (auto_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_size (auto_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_sink (auto_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_denied (auto_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_data (auto_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_a_ready (auto_dmInner_tl_in_a_ready_0), .auto_tl_in_a_valid (auto_dmInner_tl_in_a_valid_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_opcode (auto_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_param (auto_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_size (auto_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_source (auto_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_address (auto_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_mask (auto_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_data (auto_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_corrupt (auto_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_d_ready (auto_dmInner_tl_in_d_ready_0), // @[Debug.scala:1871:9] .auto_tl_in_d_valid (auto_dmInner_tl_in_d_valid_0), .auto_tl_in_d_bits_opcode (auto_dmInner_tl_in_d_bits_opcode_0), .auto_tl_in_d_bits_size (auto_dmInner_tl_in_d_bits_size_0), .auto_tl_in_d_bits_source (auto_dmInner_tl_in_d_bits_source_0), .auto_tl_in_d_bits_data (auto_dmInner_tl_in_d_bits_data_0), .auto_dmi_in_a_ready (_dmInner_auto_dmi_in_a_ready), .auto_dmi_in_a_valid (_dmiXing_auto_out_a_valid), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_param (_dmiXing_auto_out_a_bits_param), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_size (_dmiXing_auto_out_a_bits_size), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_source (_dmiXing_auto_out_a_bits_source), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_address (_dmiXing_auto_out_a_bits_address), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_mask (_dmiXing_auto_out_a_bits_mask), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_data (_dmiXing_auto_out_a_bits_data), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), // @[Debug.scala:1858:27] .auto_dmi_in_d_ready (_dmiXing_auto_out_d_ready), // @[Debug.scala:1858:27] .auto_dmi_in_d_valid (_dmInner_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), .auto_dmi_in_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), .auto_dmi_in_d_bits_data (_dmInner_auto_dmi_in_d_bits_data), .io_dmactive (dmactive_synced), // @[ShiftReg.scala:48:24] .io_innerCtrl_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3), // @[AsyncQueue.scala:211:22] .io_hgDebugInt_0 (io_hgDebugInt_0_0), .io_hgDebugInt_1 (io_hgDebugInt_1_0), .io_hgDebugInt_2 (io_hgDebugInt_2_0), .io_hgDebugInt_3 (io_hgDebugInt_3_0), .io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1871:9] .io_hartIsInReset_1 (io_hartIsInReset_1_0), // @[Debug.scala:1871:9] .io_hartIsInReset_2 (io_hartIsInReset_2_0), // @[Debug.scala:1871:9] .io_hartIsInReset_3 (io_hartIsInReset_3_0), // @[Debug.scala:1871:9] .io_tl_clock (io_tl_clock_0), // @[Debug.scala:1871:9] .io_tl_reset (io_tl_reset_0) // @[Debug.scala:1871:9] ); // @[Debug.scala:1857:27] TLAsyncCrossingSink_a9d32s1k1z2u dmiXing ( // @[Debug.scala:1858:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_mem_0_opcode (auto_dmiXing_in_a_mem_0_opcode_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_address (auto_dmiXing_in_a_mem_0_address_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_data (auto_dmiXing_in_a_mem_0_data_0), // @[Debug.scala:1871:9] .auto_in_a_ridx (auto_dmiXing_in_a_ridx_0), .auto_in_a_widx (auto_dmiXing_in_a_widx_0), // @[Debug.scala:1871:9] .auto_in_a_safe_ridx_valid (auto_dmiXing_in_a_safe_ridx_valid_0), .auto_in_a_safe_widx_valid (auto_dmiXing_in_a_safe_widx_valid_0), // @[Debug.scala:1871:9] .auto_in_a_safe_source_reset_n (auto_dmiXing_in_a_safe_source_reset_n_0), // @[Debug.scala:1871:9] .auto_in_a_safe_sink_reset_n (auto_dmiXing_in_a_safe_sink_reset_n_0), .auto_in_d_mem_0_opcode (auto_dmiXing_in_d_mem_0_opcode_0), .auto_in_d_mem_0_size (auto_dmiXing_in_d_mem_0_size_0), .auto_in_d_mem_0_source (auto_dmiXing_in_d_mem_0_source_0), .auto_in_d_mem_0_data (auto_dmiXing_in_d_mem_0_data_0), .auto_in_d_ridx (auto_dmiXing_in_d_ridx_0), // @[Debug.scala:1871:9] .auto_in_d_widx (auto_dmiXing_in_d_widx_0), .auto_in_d_safe_ridx_valid (auto_dmiXing_in_d_safe_ridx_valid_0), // @[Debug.scala:1871:9] .auto_in_d_safe_widx_valid (auto_dmiXing_in_d_safe_widx_valid_0), .auto_in_d_safe_source_reset_n (auto_dmiXing_in_d_safe_source_reset_n_0), .auto_in_d_safe_sink_reset_n (auto_dmiXing_in_d_safe_sink_reset_n_0), // @[Debug.scala:1871:9] .auto_out_a_ready (_dmInner_auto_dmi_in_a_ready), // @[Debug.scala:1857:27] .auto_out_a_valid (_dmiXing_auto_out_a_valid), .auto_out_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), .auto_out_a_bits_param (_dmiXing_auto_out_a_bits_param), .auto_out_a_bits_size (_dmiXing_auto_out_a_bits_size), .auto_out_a_bits_source (_dmiXing_auto_out_a_bits_source), .auto_out_a_bits_address (_dmiXing_auto_out_a_bits_address), .auto_out_a_bits_mask (_dmiXing_auto_out_a_bits_mask), .auto_out_a_bits_data (_dmiXing_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), .auto_out_d_ready (_dmiXing_auto_out_d_ready), .auto_out_d_valid (_dmInner_auto_dmi_in_d_valid), // @[Debug.scala:1857:27] .auto_out_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), // @[Debug.scala:1857:27] .auto_out_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), // @[Debug.scala:1857:27] .auto_out_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), // @[Debug.scala:1857:27] .auto_out_d_bits_data (_dmInner_auto_dmi_in_d_bits_data) // @[Debug.scala:1857:27] ); // @[Debug.scala:1858:27] AsyncResetSynchronizerShiftReg_w1_d3_i0_30 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala:45:23] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_d (io_dmactive_0), // @[Debug.scala:1871:9] .io_q (dmactive_synced) ); // @[ShiftReg.scala:45:23] AsyncQueueSink_DebugInternalBundle dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala:211:22] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_deq_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), .io_deq_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), .io_deq_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), .io_deq_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), .io_deq_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), .io_deq_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), .io_deq_bits_hamask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1), .io_deq_bits_hamask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2), .io_deq_bits_hamask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3), .io_deq_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), .io_deq_bits_hrmask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1), .io_deq_bits_hrmask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2), .io_deq_bits_hrmask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3), .io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), // @[Debug.scala:1871:9] .io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), // @[Debug.scala:1871:9] .io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), // @[Debug.scala:1871:9] .io_async_mem_0_hasel (io_innerCtrl_mem_0_hasel_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_0 (io_innerCtrl_mem_0_hamask_0_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_1 (io_innerCtrl_mem_0_hamask_1_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_2 (io_innerCtrl_mem_0_hamask_2_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_3 (io_innerCtrl_mem_0_hamask_3_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_1 (io_innerCtrl_mem_0_hrmask_1_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_2 (io_innerCtrl_mem_0_hrmask_2_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_3 (io_innerCtrl_mem_0_hrmask_3_0), // @[Debug.scala:1871:9] .io_async_ridx (io_innerCtrl_ridx_0), .io_async_widx (io_innerCtrl_widx_0), // @[Debug.scala:1871:9] .io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0), .io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), // @[Debug.scala:1871:9] .io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), // @[Debug.scala:1871:9] .io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0) ); // @[AsyncQueue.scala:211:22] assign auto_dmiXing_in_a_ridx = auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_ridx_valid = auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_sink_reset_n = auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_opcode = auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_size = auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_source = auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_data = auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_widx = auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_widx_valid = auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_source_reset_n = auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_a_ready = auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_valid = auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_opcode = auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_size = auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_source = auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_data = auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] assign io_innerCtrl_ridx = io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_ridx_valid = io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_0 = io_hgDebugInt_0_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_1 = io_hgDebugInt_1_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_2 = io_hgDebugInt_2_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_3 = io_hgDebugInt_3_0; // @[Debug.scala:1871:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_18 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = or(UInt<1>(0h0), _T_70) node _T_72 = and(_T_21, _T_71) node _T_73 = asUInt(reset) node _T_74 = eq(_T_73, UInt<1>(0h0)) when _T_74 : node _T_75 = eq(_T_72, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_72, UInt<1>(0h1), "") : assert_2 node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<14>(0h2000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<13>(0h1000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<17>(0h10000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<18>(0h2f000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<17>(0h10000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<13>(0h1000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<13>(0h1000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = or(_T_84, _T_89) node _T_121 = or(_T_120, _T_94) node _T_122 = or(_T_121, _T_99) node _T_123 = or(_T_122, _T_104) node _T_124 = or(_T_123, _T_109) node _T_125 = or(_T_124, _T_114) node _T_126 = or(_T_125, _T_119) node _T_127 = and(_T_79, _T_126) node _T_128 = or(UInt<1>(0h0), _T_127) node _T_129 = and(UInt<1>(0h0), _T_128) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_129, UInt<1>(0h1), "") : assert_3 node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_136 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_136, UInt<1>(0h1), "") : assert_5 node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(is_aligned, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_143 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_143, UInt<1>(0h1), "") : assert_7 node _T_147 = not(io.in.a.bits.mask) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_148, UInt<1>(0h1), "") : assert_8 node _T_152 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_T_152, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_152, UInt<1>(0h1), "") : assert_9 node _T_156 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_156 : node _T_157 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_158 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<14>(0h2000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<13>(0h1000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<17>(0h10000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<18>(0h2f000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<17>(0h10000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<13>(0h1000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<27>(0h4000000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<13>(0h1000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = or(_T_168, _T_173) node _T_205 = or(_T_204, _T_178) node _T_206 = or(_T_205, _T_183) node _T_207 = or(_T_206, _T_188) node _T_208 = or(_T_207, _T_193) node _T_209 = or(_T_208, _T_198) node _T_210 = or(_T_209, _T_203) node _T_211 = and(_T_163, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = and(_T_162, _T_212) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_213, UInt<1>(0h1), "") : assert_10 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<14>(0h2000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<17>(0h10000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<18>(0h2f000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<27>(0h4000000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = or(_T_225, _T_230) node _T_262 = or(_T_261, _T_235) node _T_263 = or(_T_262, _T_240) node _T_264 = or(_T_263, _T_245) node _T_265 = or(_T_264, _T_250) node _T_266 = or(_T_265, _T_255) node _T_267 = or(_T_266, _T_260) node _T_268 = and(_T_220, _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = and(UInt<1>(0h0), _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_270, UInt<1>(0h1), "") : assert_11 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_277 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_277, UInt<1>(0h1), "") : assert_13 node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(is_aligned, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_284 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_284, UInt<1>(0h1), "") : assert_15 node _T_288 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_288, UInt<1>(0h1), "") : assert_16 node _T_292 = not(io.in.a.bits.mask) node _T_293 = eq(_T_292, UInt<1>(0h0)) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_293, UInt<1>(0h1), "") : assert_17 node _T_297 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_297, UInt<1>(0h1), "") : assert_18 node _T_301 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_301 : node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_306 = and(_T_304, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_307, UInt<1>(0h1), "") : assert_19 node _T_311 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_312 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_313 = and(_T_311, _T_312) node _T_314 = or(UInt<1>(0h0), _T_313) node _T_315 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = and(_T_314, _T_319) node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_322 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_323 = and(_T_321, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<14>(0h2000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<27>(0h4000000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = or(_T_329, _T_334) node _T_361 = or(_T_360, _T_339) node _T_362 = or(_T_361, _T_344) node _T_363 = or(_T_362, _T_349) node _T_364 = or(_T_363, _T_354) node _T_365 = or(_T_364, _T_359) node _T_366 = and(_T_324, _T_365) node _T_367 = or(UInt<1>(0h0), _T_320) node _T_368 = or(_T_367, _T_366) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_368, UInt<1>(0h1), "") : assert_20 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_378 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_378, UInt<1>(0h1), "") : assert_23 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_382, UInt<1>(0h1), "") : assert_24 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_386, UInt<1>(0h1), "") : assert_25 node _T_390 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_390 : node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_398 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_399 = and(_T_397, _T_398) node _T_400 = or(UInt<1>(0h0), _T_399) node _T_401 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_402 = cvt(_T_401) node _T_403 = and(_T_402, asSInt(UInt<13>(0h1000))) node _T_404 = asSInt(_T_403) node _T_405 = eq(_T_404, asSInt(UInt<1>(0h0))) node _T_406 = and(_T_400, _T_405) node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_409 = and(_T_407, _T_408) node _T_410 = or(UInt<1>(0h0), _T_409) node _T_411 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<14>(0h2000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_417 = cvt(_T_416) node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000))) node _T_419 = asSInt(_T_418) node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0))) node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_422 = cvt(_T_421) node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000))) node _T_424 = asSInt(_T_423) node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0))) node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<27>(0h4000000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<13>(0h1000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = or(_T_415, _T_420) node _T_442 = or(_T_441, _T_425) node _T_443 = or(_T_442, _T_430) node _T_444 = or(_T_443, _T_435) node _T_445 = or(_T_444, _T_440) node _T_446 = and(_T_410, _T_445) node _T_447 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_448 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<17>(0h10000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = and(_T_447, _T_452) node _T_454 = or(UInt<1>(0h0), _T_406) node _T_455 = or(_T_454, _T_446) node _T_456 = or(_T_455, _T_453) node _T_457 = and(_T_396, _T_456) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_457, UInt<1>(0h1), "") : assert_26 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(is_aligned, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_467 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_467, UInt<1>(0h1), "") : assert_29 node _T_471 = eq(io.in.a.bits.mask, mask) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_471, UInt<1>(0h1), "") : assert_30 node _T_475 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_475 : node _T_476 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_477 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_480 = and(_T_478, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_483 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_484 = and(_T_482, _T_483) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_487 = cvt(_T_486) node _T_488 = and(_T_487, asSInt(UInt<13>(0h1000))) node _T_489 = asSInt(_T_488) node _T_490 = eq(_T_489, asSInt(UInt<1>(0h0))) node _T_491 = and(_T_485, _T_490) node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_493 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_494 = and(_T_492, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<14>(0h2000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_502 = cvt(_T_501) node _T_503 = and(_T_502, asSInt(UInt<18>(0h2f000))) node _T_504 = asSInt(_T_503) node _T_505 = eq(_T_504, asSInt(UInt<1>(0h0))) node _T_506 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<17>(0h10000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<13>(0h1000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<27>(0h4000000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = or(_T_500, _T_505) node _T_527 = or(_T_526, _T_510) node _T_528 = or(_T_527, _T_515) node _T_529 = or(_T_528, _T_520) node _T_530 = or(_T_529, _T_525) node _T_531 = and(_T_495, _T_530) node _T_532 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_533 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<17>(0h10000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = and(_T_532, _T_537) node _T_539 = or(UInt<1>(0h0), _T_491) node _T_540 = or(_T_539, _T_531) node _T_541 = or(_T_540, _T_538) node _T_542 = and(_T_481, _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_542, UInt<1>(0h1), "") : assert_31 node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(is_aligned, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_552 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_552, UInt<1>(0h1), "") : assert_34 node _T_556 = not(mask) node _T_557 = and(io.in.a.bits.mask, _T_556) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_558, UInt<1>(0h1), "") : assert_35 node _T_562 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_562 : node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_567 = and(_T_565, _T_566) node _T_568 = or(UInt<1>(0h0), _T_567) node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_570 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<14>(0h2000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<13>(0h1000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_584 = cvt(_T_583) node _T_585 = and(_T_584, asSInt(UInt<18>(0h2f000))) node _T_586 = asSInt(_T_585) node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0))) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_594 = cvt(_T_593) node _T_595 = and(_T_594, asSInt(UInt<13>(0h1000))) node _T_596 = asSInt(_T_595) node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0))) node _T_598 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_599 = cvt(_T_598) node _T_600 = and(_T_599, asSInt(UInt<27>(0h4000000))) node _T_601 = asSInt(_T_600) node _T_602 = eq(_T_601, asSInt(UInt<1>(0h0))) node _T_603 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = or(_T_577, _T_582) node _T_609 = or(_T_608, _T_587) node _T_610 = or(_T_609, _T_592) node _T_611 = or(_T_610, _T_597) node _T_612 = or(_T_611, _T_602) node _T_613 = or(_T_612, _T_607) node _T_614 = and(_T_572, _T_613) node _T_615 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<17>(0h10000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = and(_T_615, _T_620) node _T_622 = or(UInt<1>(0h0), _T_614) node _T_623 = or(_T_622, _T_621) node _T_624 = and(_T_568, _T_623) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_624, UInt<1>(0h1), "") : assert_36 node _T_628 = asUInt(reset) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(is_aligned, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_634 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_634, UInt<1>(0h1), "") : assert_39 node _T_638 = eq(io.in.a.bits.mask, mask) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_638, UInt<1>(0h1), "") : assert_40 node _T_642 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_642 : node _T_643 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_644 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_645 = and(_T_643, _T_644) node _T_646 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_647 = and(_T_645, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_650 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<18>(0h2f000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<17>(0h10000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<13>(0h1000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<27>(0h4000000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = or(_T_657, _T_662) node _T_689 = or(_T_688, _T_667) node _T_690 = or(_T_689, _T_672) node _T_691 = or(_T_690, _T_677) node _T_692 = or(_T_691, _T_682) node _T_693 = or(_T_692, _T_687) node _T_694 = and(_T_652, _T_693) node _T_695 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_696 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<17>(0h10000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = and(_T_695, _T_700) node _T_702 = or(UInt<1>(0h0), _T_694) node _T_703 = or(_T_702, _T_701) node _T_704 = and(_T_648, _T_703) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_704, UInt<1>(0h1), "") : assert_41 node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_711 = asUInt(reset) node _T_712 = eq(_T_711, UInt<1>(0h0)) when _T_712 : node _T_713 = eq(is_aligned, UInt<1>(0h0)) when _T_713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_714 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_714, UInt<1>(0h1), "") : assert_44 node _T_718 = eq(io.in.a.bits.mask, mask) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_718, UInt<1>(0h1), "") : assert_45 node _T_722 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_722 : node _T_723 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_724 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_725 = and(_T_723, _T_724) node _T_726 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_727 = and(_T_725, _T_726) node _T_728 = or(UInt<1>(0h0), _T_727) node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_730 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(UInt<1>(0h0), _T_731) node _T_733 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = and(_T_732, _T_737) node _T_739 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_740 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<14>(0h2000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<17>(0h10000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<18>(0h2f000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<17>(0h10000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<27>(0h4000000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<13>(0h1000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = or(_T_744, _T_749) node _T_776 = or(_T_775, _T_754) node _T_777 = or(_T_776, _T_759) node _T_778 = or(_T_777, _T_764) node _T_779 = or(_T_778, _T_769) node _T_780 = or(_T_779, _T_774) node _T_781 = and(_T_739, _T_780) node _T_782 = or(UInt<1>(0h0), _T_738) node _T_783 = or(_T_782, _T_781) node _T_784 = and(_T_728, _T_783) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_784, UInt<1>(0h1), "") : assert_46 node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(is_aligned, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_794 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_794, UInt<1>(0h1), "") : assert_49 node _T_798 = eq(io.in.a.bits.mask, mask) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_798, UInt<1>(0h1), "") : assert_50 node _T_802 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(_T_802, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_802, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_806 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(_T_806, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_806, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_810 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_810 : node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_814 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_814, UInt<1>(0h1), "") : assert_54 node _T_818 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_818, UInt<1>(0h1), "") : assert_55 node _T_822 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_822, UInt<1>(0h1), "") : assert_56 node _T_826 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_826, UInt<1>(0h1), "") : assert_57 node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(sink_ok, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_837 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_837, UInt<1>(0h1), "") : assert_60 node _T_841 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_841, UInt<1>(0h1), "") : assert_61 node _T_845 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_845, UInt<1>(0h1), "") : assert_62 node _T_849 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_849, UInt<1>(0h1), "") : assert_63 node _T_853 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_854 = or(UInt<1>(0h1), _T_853) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_854, UInt<1>(0h1), "") : assert_64 node _T_858 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_858 : node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(sink_ok, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_865, UInt<1>(0h1), "") : assert_67 node _T_869 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_869, UInt<1>(0h1), "") : assert_68 node _T_873 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_873, UInt<1>(0h1), "") : assert_69 node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_878 = or(_T_877, io.in.d.bits.corrupt) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_878, UInt<1>(0h1), "") : assert_70 node _T_882 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_883 = or(UInt<1>(0h1), _T_882) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_883, UInt<1>(0h1), "") : assert_71 node _T_887 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_887 : node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_891 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_891, UInt<1>(0h1), "") : assert_73 node _T_895 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_895, UInt<1>(0h1), "") : assert_74 node _T_899 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_900 = or(UInt<1>(0h1), _T_899) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_900, UInt<1>(0h1), "") : assert_75 node _T_904 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_904 : node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_908 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_908, UInt<1>(0h1), "") : assert_77 node _T_912 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_913 = or(_T_912, io.in.d.bits.corrupt) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_913, UInt<1>(0h1), "") : assert_78 node _T_917 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_918 = or(UInt<1>(0h1), _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_918, UInt<1>(0h1), "") : assert_79 node _T_922 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_926 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(_T_926, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_926, UInt<1>(0h1), "") : assert_81 node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_930, UInt<1>(0h1), "") : assert_82 node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_935 = or(UInt<1>(0h1), _T_934) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_935, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_939 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_939, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_943 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_943, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_947 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_947, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_951 = eq(a_first, UInt<1>(0h0)) node _T_952 = and(io.in.a.valid, _T_951) when _T_952 : node _T_953 = eq(io.in.a.bits.opcode, opcode) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_953, UInt<1>(0h1), "") : assert_87 node _T_957 = eq(io.in.a.bits.param, param) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_957, UInt<1>(0h1), "") : assert_88 node _T_961 = eq(io.in.a.bits.size, size) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_961, UInt<1>(0h1), "") : assert_89 node _T_965 = eq(io.in.a.bits.source, source) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_965, UInt<1>(0h1), "") : assert_90 node _T_969 = eq(io.in.a.bits.address, address) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_969, UInt<1>(0h1), "") : assert_91 node _T_973 = and(io.in.a.ready, io.in.a.valid) node _T_974 = and(_T_973, a_first) when _T_974 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_975 = eq(d_first, UInt<1>(0h0)) node _T_976 = and(io.in.d.valid, _T_975) when _T_976 : node _T_977 = eq(io.in.d.bits.opcode, opcode_1) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_977, UInt<1>(0h1), "") : assert_92 node _T_981 = eq(io.in.d.bits.param, param_1) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_981, UInt<1>(0h1), "") : assert_93 node _T_985 = eq(io.in.d.bits.size, size_1) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_985, UInt<1>(0h1), "") : assert_94 node _T_989 = eq(io.in.d.bits.source, source_1) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_989, UInt<1>(0h1), "") : assert_95 node _T_993 = eq(io.in.d.bits.sink, sink) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_993, UInt<1>(0h1), "") : assert_96 node _T_997 = eq(io.in.d.bits.denied, denied) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_997, UInt<1>(0h1), "") : assert_97 node _T_1001 = and(io.in.d.ready, io.in.d.valid) node _T_1002 = and(_T_1001, d_first) when _T_1002 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1003 = and(io.in.a.valid, a_first_1) node _T_1004 = and(_T_1003, UInt<1>(0h1)) when _T_1004 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1005 = and(io.in.a.ready, io.in.a.valid) node _T_1006 = and(_T_1005, a_first_1) node _T_1007 = and(_T_1006, UInt<1>(0h1)) when _T_1007 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1008 = dshr(inflight, io.in.a.bits.source) node _T_1009 = bits(_T_1008, 0, 0) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1014 = and(io.in.d.valid, d_first_1) node _T_1015 = and(_T_1014, UInt<1>(0h1)) node _T_1016 = eq(d_release_ack, UInt<1>(0h0)) node _T_1017 = and(_T_1015, _T_1016) when _T_1017 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1018 = and(io.in.d.ready, io.in.d.valid) node _T_1019 = and(_T_1018, d_first_1) node _T_1020 = and(_T_1019, UInt<1>(0h1)) node _T_1021 = eq(d_release_ack, UInt<1>(0h0)) node _T_1022 = and(_T_1020, _T_1021) when _T_1022 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1023 = and(io.in.d.valid, d_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) node _T_1025 = eq(d_release_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1027 = dshr(inflight, io.in.d.bits.source) node _T_1028 = bits(_T_1027, 0, 0) node _T_1029 = or(_T_1028, same_cycle_resp) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1033 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1034 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1035 = or(_T_1033, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_100 node _T_1039 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_101 else : node _T_1043 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1044 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1045 = or(_T_1043, _T_1044) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_102 node _T_1049 = eq(io.in.d.bits.size, a_size_lookup) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_103 node _T_1053 = and(io.in.d.valid, d_first_1) node _T_1054 = and(_T_1053, a_first_1) node _T_1055 = and(_T_1054, io.in.a.valid) node _T_1056 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = eq(d_release_ack, UInt<1>(0h0)) node _T_1059 = and(_T_1057, _T_1058) when _T_1059 : node _T_1060 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1061 = or(_T_1060, io.in.a.ready) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_104 node _T_1065 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1066 = orr(a_set_wo_ready) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = or(_T_1065, _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_36 node _T_1072 = orr(inflight) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) node _T_1074 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1075 = or(_T_1073, _T_1074) node _T_1076 = lt(watchdog, plusarg_reader.out) node _T_1077 = or(_T_1075, _T_1076) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1081 = and(io.in.a.ready, io.in.a.valid) node _T_1082 = and(io.in.d.ready, io.in.d.valid) node _T_1083 = or(_T_1081, _T_1082) when _T_1083 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1084 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1085 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1086 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1087 = and(_T_1085, _T_1086) node _T_1088 = and(_T_1084, _T_1087) when _T_1088 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1089 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1090 = and(_T_1089, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1091 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1092 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1093 = and(_T_1091, _T_1092) node _T_1094 = and(_T_1090, _T_1093) when _T_1094 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1095 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1096 = bits(_T_1095, 0, 0) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1101 = and(io.in.d.valid, d_first_2) node _T_1102 = and(_T_1101, UInt<1>(0h1)) node _T_1103 = and(_T_1102, d_release_ack_1) when _T_1103 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1104 = and(io.in.d.ready, io.in.d.valid) node _T_1105 = and(_T_1104, d_first_2) node _T_1106 = and(_T_1105, UInt<1>(0h1)) node _T_1107 = and(_T_1106, d_release_ack_1) when _T_1107 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1108 = and(io.in.d.valid, d_first_2) node _T_1109 = and(_T_1108, UInt<1>(0h1)) node _T_1110 = and(_T_1109, d_release_ack_1) when _T_1110 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1111 = dshr(inflight_1, io.in.d.bits.source) node _T_1112 = bits(_T_1111, 0, 0) node _T_1113 = or(_T_1112, same_cycle_resp_1) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1117 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_109 else : node _T_1121 = eq(io.in.d.bits.size, c_size_lookup) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_110 node _T_1125 = and(io.in.d.valid, d_first_2) node _T_1126 = and(_T_1125, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1127 = and(_T_1126, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1128 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1129 = and(_T_1127, _T_1128) node _T_1130 = and(_T_1129, d_release_ack_1) node _T_1131 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _T_1133 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1134 = or(_T_1133, _WIRE_23.ready) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_111 node _T_1138 = orr(c_set_wo_ready) when _T_1138 : node _T_1139 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_37 node _T_1143 = orr(inflight_1) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) node _T_1145 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1146 = or(_T_1144, _T_1145) node _T_1147 = lt(watchdog_1, plusarg_reader_1.out) node _T_1148 = or(_T_1146, _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1152 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1153 = and(io.in.d.ready, io.in.d.valid) node _T_1154 = or(_T_1152, _T_1153) when _T_1154 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_18( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h0; // @[Edges.scala:92:37] wire _a_first_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:92:37] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire a_first_beats1_opdata = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire a_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:92:28] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] a_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h2; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] io_in_a_bits_mask = 8'hF; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:657:53] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:657:61] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [4:0] _a_sizes_set_interm_T_1 = 5'h5; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'h4; // @[Monitor.scala:658:51] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [11:0] is_aligned_mask = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFFC; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFFC; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC; // @[package.scala:243:71] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [28:0] _is_aligned_T = {27'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_0_1 = _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_0_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire mask_sub_1_1 = mask_sub_sub_0_1; // @[Misc.scala:215:29] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_1 = _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_3_1 = mask_sub_sub_1_1; // @[Misc.scala:215:29] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1081 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1081; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1081; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [28:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1004 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1004; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1004; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1081 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = {3'h0, a_set}; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'h5 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1053 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1053 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1125 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1125 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_166 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_166( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_122 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_122( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IntToFPUnit : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<65>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip fcsr_rm : UInt<3>} connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.sfence.bits.hg invalidate io.resp.bits.sfence.bits.hv invalidate io.resp.bits.sfence.bits.asid invalidate io.resp.bits.sfence.bits.addr invalidate io.resp.bits.sfence.bits.rs2 invalidate io.resp.bits.sfence.bits.rs1 invalidate io.resp.bits.sfence.valid invalidate io.resp.bits.mxcpt.bits invalidate io.resp.bits.mxcpt.valid invalidate io.resp.bits.addr invalidate io.resp.bits.fflags.bits.flags invalidate io.resp.bits.fflags.bits.uop.debug_tsrc invalidate io.resp.bits.fflags.bits.uop.debug_fsrc invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.resp.bits.fflags.bits.uop.bp_debug_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.resp.bits.fflags.bits.uop.fp_single invalidate io.resp.bits.fflags.bits.uop.fp_val invalidate io.resp.bits.fflags.bits.uop.frs3_en invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype invalidate io.resp.bits.fflags.bits.uop.dst_rtype invalidate io.resp.bits.fflags.bits.uop.ldst_val invalidate io.resp.bits.fflags.bits.uop.lrs3 invalidate io.resp.bits.fflags.bits.uop.lrs2 invalidate io.resp.bits.fflags.bits.uop.lrs1 invalidate io.resp.bits.fflags.bits.uop.ldst invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.resp.bits.fflags.bits.uop.flush_on_commit invalidate io.resp.bits.fflags.bits.uop.is_unique invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.resp.bits.fflags.bits.uop.uses_stq invalidate io.resp.bits.fflags.bits.uop.uses_ldq invalidate io.resp.bits.fflags.bits.uop.is_amo invalidate io.resp.bits.fflags.bits.uop.is_fencei invalidate io.resp.bits.fflags.bits.uop.is_fence invalidate io.resp.bits.fflags.bits.uop.mem_signed invalidate io.resp.bits.fflags.bits.uop.mem_size invalidate io.resp.bits.fflags.bits.uop.mem_cmd invalidate io.resp.bits.fflags.bits.uop.bypassable invalidate io.resp.bits.fflags.bits.uop.exc_cause invalidate io.resp.bits.fflags.bits.uop.exception invalidate io.resp.bits.fflags.bits.uop.stale_pdst invalidate io.resp.bits.fflags.bits.uop.ppred_busy invalidate io.resp.bits.fflags.bits.uop.prs3_busy invalidate io.resp.bits.fflags.bits.uop.prs2_busy invalidate io.resp.bits.fflags.bits.uop.prs1_busy invalidate io.resp.bits.fflags.bits.uop.ppred invalidate io.resp.bits.fflags.bits.uop.prs3 invalidate io.resp.bits.fflags.bits.uop.prs2 invalidate io.resp.bits.fflags.bits.uop.prs1 invalidate io.resp.bits.fflags.bits.uop.pdst invalidate io.resp.bits.fflags.bits.uop.rxq_idx invalidate io.resp.bits.fflags.bits.uop.stq_idx invalidate io.resp.bits.fflags.bits.uop.ldq_idx invalidate io.resp.bits.fflags.bits.uop.rob_idx invalidate io.resp.bits.fflags.bits.uop.csr_addr invalidate io.resp.bits.fflags.bits.uop.imm_packed invalidate io.resp.bits.fflags.bits.uop.taken invalidate io.resp.bits.fflags.bits.uop.pc_lob invalidate io.resp.bits.fflags.bits.uop.edge_inst invalidate io.resp.bits.fflags.bits.uop.ftq_idx invalidate io.resp.bits.fflags.bits.uop.br_tag invalidate io.resp.bits.fflags.bits.uop.br_mask invalidate io.resp.bits.fflags.bits.uop.is_sfb invalidate io.resp.bits.fflags.bits.uop.is_jal invalidate io.resp.bits.fflags.bits.uop.is_jalr invalidate io.resp.bits.fflags.bits.uop.is_br invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_state invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type invalidate io.resp.bits.fflags.bits.uop.fu_code invalidate io.resp.bits.fflags.bits.uop.iq_type invalidate io.resp.bits.fflags.bits.uop.debug_pc invalidate io.resp.bits.fflags.bits.uop.is_rvc invalidate io.resp.bits.fflags.bits.uop.debug_inst invalidate io.resp.bits.fflags.bits.uop.inst invalidate io.resp.bits.fflags.bits.uop.uopc invalidate io.resp.bits.fflags.valid invalidate io.resp.bits.data invalidate io.resp.bits.predicated invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.req.ready, UInt<1>(0h1) wire _r_valids_WIRE : UInt<1>[2] connect _r_valids_WIRE[0], UInt<1>(0h0) connect _r_valids_WIRE[1], UInt<1>(0h0) regreset r_valids : UInt<1>[2], clock, reset, _r_valids_WIRE reg r_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[2], clock node _r_valids_0_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask) node _r_valids_0_T_1 = neq(_r_valids_0_T, UInt<1>(0h0)) node _r_valids_0_T_2 = eq(_r_valids_0_T_1, UInt<1>(0h0)) node _r_valids_0_T_3 = and(io.req.valid, _r_valids_0_T_2) node _r_valids_0_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_0_T_5 = and(_r_valids_0_T_3, _r_valids_0_T_4) connect r_valids[0], _r_valids_0_T_5 connect r_uops[0], io.req.bits.uop node _r_uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_0_br_mask_T_1 = and(io.req.bits.uop.br_mask, _r_uops_0_br_mask_T) connect r_uops[0].br_mask, _r_uops_0_br_mask_T_1 node _r_valids_1_T = and(io.brupdate.b1.mispredict_mask, r_uops[0].br_mask) node _r_valids_1_T_1 = neq(_r_valids_1_T, UInt<1>(0h0)) node _r_valids_1_T_2 = eq(_r_valids_1_T_1, UInt<1>(0h0)) node _r_valids_1_T_3 = and(r_valids[0], _r_valids_1_T_2) node _r_valids_1_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_1_T_5 = and(_r_valids_1_T_3, _r_valids_1_T_4) connect r_valids[1], _r_valids_1_T_5 connect r_uops[1], r_uops[0] node _r_uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_1_br_mask_T_1 = and(r_uops[0].br_mask, _r_uops_1_br_mask_T) connect r_uops[1].br_mask, _r_uops_1_br_mask_T_1 node _io_resp_valid_T = and(io.brupdate.b1.mispredict_mask, r_uops[1].br_mask) node _io_resp_valid_T_1 = neq(_io_resp_valid_T, UInt<1>(0h0)) node _io_resp_valid_T_2 = eq(_io_resp_valid_T_1, UInt<1>(0h0)) node _io_resp_valid_T_3 = and(r_valids[1], _io_resp_valid_T_2) connect io.resp.valid, _io_resp_valid_T_3 connect io.resp.bits.predicated, UInt<1>(0h0) connect io.resp.bits.uop, r_uops[1] node _io_resp_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_resp_bits_uop_br_mask_T_1 = and(r_uops[1].br_mask, _io_resp_bits_uop_br_mask_T) connect io.resp.bits.uop.br_mask, _io_resp_bits_uop_br_mask_T_1 inst fp_decoder of UOPCodeFPUDecoder connect fp_decoder.clock, clock connect fp_decoder.reset, reset connect fp_decoder.io.uopc, io.req.bits.uop.uopc node _fp_rm_T = bits(io.req.bits.uop.imm_packed, 2, 0) node _fp_rm_T_1 = eq(_fp_rm_T, UInt<3>(0h7)) node _fp_rm_T_2 = bits(io.req.bits.uop.imm_packed, 2, 0) node fp_rm = mux(_fp_rm_T_1, io.fcsr_rm, _fp_rm_T_2) wire req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect req.vec, fp_decoder.io.sigs.vec connect req.wflags, fp_decoder.io.sigs.wflags connect req.sqrt, fp_decoder.io.sigs.sqrt connect req.div, fp_decoder.io.sigs.div connect req.fma, fp_decoder.io.sigs.fma connect req.fastpipe, fp_decoder.io.sigs.fastpipe connect req.toint, fp_decoder.io.sigs.toint connect req.fromint, fp_decoder.io.sigs.fromint connect req.typeTagOut, fp_decoder.io.sigs.typeTagOut connect req.typeTagIn, fp_decoder.io.sigs.typeTagIn connect req.swap23, fp_decoder.io.sigs.swap23 connect req.swap12, fp_decoder.io.sigs.swap12 connect req.ren3, fp_decoder.io.sigs.ren3 connect req.ren2, fp_decoder.io.sigs.ren2 connect req.ren1, fp_decoder.io.sigs.ren1 connect req.wen, fp_decoder.io.sigs.wen connect req.ldst, fp_decoder.io.sigs.ldst connect req.rm, fp_rm node _req_in1_prev_unswizzled_T = bits(io.req.bits.rs1_data, 31, 31) node _req_in1_prev_unswizzled_T_1 = bits(io.req.bits.rs1_data, 52, 52) node _req_in1_prev_unswizzled_T_2 = bits(io.req.bits.rs1_data, 30, 0) node req_in1_prev_unswizzled_hi = cat(_req_in1_prev_unswizzled_T, _req_in1_prev_unswizzled_T_1) node req_in1_prev_unswizzled = cat(req_in1_prev_unswizzled_hi, _req_in1_prev_unswizzled_T_2) node req_in1_prev_prev_sign = bits(req_in1_prev_unswizzled, 32, 32) node req_in1_prev_prev_fractIn = bits(req_in1_prev_unswizzled, 22, 0) node req_in1_prev_prev_expIn = bits(req_in1_prev_unswizzled, 31, 23) node _req_in1_prev_prev_fractOut_T = shl(req_in1_prev_prev_fractIn, 53) node req_in1_prev_prev_fractOut = shr(_req_in1_prev_prev_fractOut_T, 24) node req_in1_prev_prev_expOut_expCode = bits(req_in1_prev_prev_expIn, 8, 6) node _req_in1_prev_prev_expOut_commonCase_T = add(req_in1_prev_prev_expIn, UInt<12>(0h800)) node _req_in1_prev_prev_expOut_commonCase_T_1 = tail(_req_in1_prev_prev_expOut_commonCase_T, 1) node _req_in1_prev_prev_expOut_commonCase_T_2 = sub(_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node req_in1_prev_prev_expOut_commonCase = tail(_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _req_in1_prev_prev_expOut_T = eq(req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _req_in1_prev_prev_expOut_T_1 = geq(req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _req_in1_prev_prev_expOut_T_2 = or(_req_in1_prev_prev_expOut_T, _req_in1_prev_prev_expOut_T_1) node _req_in1_prev_prev_expOut_T_3 = bits(req_in1_prev_prev_expOut_commonCase, 8, 0) node _req_in1_prev_prev_expOut_T_4 = cat(req_in1_prev_prev_expOut_expCode, _req_in1_prev_prev_expOut_T_3) node _req_in1_prev_prev_expOut_T_5 = bits(req_in1_prev_prev_expOut_commonCase, 11, 0) node req_in1_prev_prev_expOut = mux(_req_in1_prev_prev_expOut_T_2, _req_in1_prev_prev_expOut_T_4, _req_in1_prev_prev_expOut_T_5) node req_in1_prev_prev_hi = cat(req_in1_prev_prev_sign, req_in1_prev_prev_expOut) node req_in1_floats_0 = cat(req_in1_prev_prev_hi, req_in1_prev_prev_fractOut) node _req_in1_prev_isbox_T = bits(io.req.bits.rs1_data, 64, 60) node req_in1_prev_isbox = andr(_req_in1_prev_isbox_T) node req_in1_oks_0 = and(req_in1_prev_isbox, UInt<1>(0h1)) node _req_in1_truncIdx_T = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in1_truncIdx = bits(_req_in1_truncIdx_T, 0, 0) node _req_in1_T = eq(req_in1_truncIdx, UInt<1>(0h1)) node _req_in1_T_1 = mux(_req_in1_T, UInt<1>(0h1), req_in1_oks_0) node _req_in1_truncIdx_T_1 = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in1_truncIdx_1 = bits(_req_in1_truncIdx_T_1, 0, 0) node _req_in1_T_2 = eq(req_in1_truncIdx_1, UInt<1>(0h1)) node _req_in1_T_3 = mux(_req_in1_T_2, io.req.bits.rs1_data, req_in1_floats_0) node _req_in1_T_4 = mux(_req_in1_T_1, _req_in1_T_3, UInt<65>(0he008000000000000)) connect req.in1, _req_in1_T_4 node _req_in2_prev_unswizzled_T = bits(io.req.bits.rs2_data, 31, 31) node _req_in2_prev_unswizzled_T_1 = bits(io.req.bits.rs2_data, 52, 52) node _req_in2_prev_unswizzled_T_2 = bits(io.req.bits.rs2_data, 30, 0) node req_in2_prev_unswizzled_hi = cat(_req_in2_prev_unswizzled_T, _req_in2_prev_unswizzled_T_1) node req_in2_prev_unswizzled = cat(req_in2_prev_unswizzled_hi, _req_in2_prev_unswizzled_T_2) node req_in2_prev_prev_sign = bits(req_in2_prev_unswizzled, 32, 32) node req_in2_prev_prev_fractIn = bits(req_in2_prev_unswizzled, 22, 0) node req_in2_prev_prev_expIn = bits(req_in2_prev_unswizzled, 31, 23) node _req_in2_prev_prev_fractOut_T = shl(req_in2_prev_prev_fractIn, 53) node req_in2_prev_prev_fractOut = shr(_req_in2_prev_prev_fractOut_T, 24) node req_in2_prev_prev_expOut_expCode = bits(req_in2_prev_prev_expIn, 8, 6) node _req_in2_prev_prev_expOut_commonCase_T = add(req_in2_prev_prev_expIn, UInt<12>(0h800)) node _req_in2_prev_prev_expOut_commonCase_T_1 = tail(_req_in2_prev_prev_expOut_commonCase_T, 1) node _req_in2_prev_prev_expOut_commonCase_T_2 = sub(_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node req_in2_prev_prev_expOut_commonCase = tail(_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _req_in2_prev_prev_expOut_T = eq(req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _req_in2_prev_prev_expOut_T_1 = geq(req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _req_in2_prev_prev_expOut_T_2 = or(_req_in2_prev_prev_expOut_T, _req_in2_prev_prev_expOut_T_1) node _req_in2_prev_prev_expOut_T_3 = bits(req_in2_prev_prev_expOut_commonCase, 8, 0) node _req_in2_prev_prev_expOut_T_4 = cat(req_in2_prev_prev_expOut_expCode, _req_in2_prev_prev_expOut_T_3) node _req_in2_prev_prev_expOut_T_5 = bits(req_in2_prev_prev_expOut_commonCase, 11, 0) node req_in2_prev_prev_expOut = mux(_req_in2_prev_prev_expOut_T_2, _req_in2_prev_prev_expOut_T_4, _req_in2_prev_prev_expOut_T_5) node req_in2_prev_prev_hi = cat(req_in2_prev_prev_sign, req_in2_prev_prev_expOut) node req_in2_floats_0 = cat(req_in2_prev_prev_hi, req_in2_prev_prev_fractOut) node _req_in2_prev_isbox_T = bits(io.req.bits.rs2_data, 64, 60) node req_in2_prev_isbox = andr(_req_in2_prev_isbox_T) node req_in2_oks_0 = and(req_in2_prev_isbox, UInt<1>(0h1)) node _req_in2_truncIdx_T = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in2_truncIdx = bits(_req_in2_truncIdx_T, 0, 0) node _req_in2_T = eq(req_in2_truncIdx, UInt<1>(0h1)) node _req_in2_T_1 = mux(_req_in2_T, UInt<1>(0h1), req_in2_oks_0) node _req_in2_truncIdx_T_1 = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in2_truncIdx_1 = bits(_req_in2_truncIdx_T_1, 0, 0) node _req_in2_T_2 = eq(req_in2_truncIdx_1, UInt<1>(0h1)) node _req_in2_T_3 = mux(_req_in2_T_2, io.req.bits.rs2_data, req_in2_floats_0) node _req_in2_T_4 = mux(_req_in2_T_1, _req_in2_T_3, UInt<65>(0he008000000000000)) connect req.in2, _req_in2_T_4 invalidate req.in3 node _req_typ_T = bits(io.req.bits.uop.imm_packed, 9, 8) connect req.typ, _req_typ_T invalidate req.fmt invalidate req.fmaCmd node _T = and(io.req.valid, fp_decoder.io.sigs.fromint) node _T_1 = bits(req.in1, 64, 64) node _T_2 = and(_T, _T_1) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed: [func] IntToFP integer input has 65th high-order bit set!\n at functional-unit.scala:618 assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _T_7 = eq(fp_decoder.io.sigs.fromint, UInt<1>(0h0)) node _T_8 = and(io.req.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: [func] Only support fromInt micro-ops.\n at functional-unit.scala:621 assert (!(io.req.valid && !fp_ctrl.fromint),\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 inst ifpu of IntToFP connect ifpu.clock, clock connect ifpu.reset, reset connect ifpu.io.in.valid, io.req.valid connect ifpu.io.in.bits.in1, req.in1 connect ifpu.io.in.bits.typ, req.typ connect ifpu.io.in.bits.rm, req.rm connect ifpu.io.in.bits.vec, req.vec connect ifpu.io.in.bits.wflags, req.wflags connect ifpu.io.in.bits.sqrt, req.sqrt connect ifpu.io.in.bits.div, req.div connect ifpu.io.in.bits.fma, req.fma connect ifpu.io.in.bits.fastpipe, req.fastpipe connect ifpu.io.in.bits.toint, req.toint connect ifpu.io.in.bits.fromint, req.fromint connect ifpu.io.in.bits.typeTagOut, req.typeTagOut connect ifpu.io.in.bits.typeTagIn, req.typeTagIn connect ifpu.io.in.bits.swap23, req.swap23 connect ifpu.io.in.bits.swap12, req.swap12 connect ifpu.io.in.bits.ren3, req.ren3 connect ifpu.io.in.bits.ren2, req.ren2 connect ifpu.io.in.bits.ren1, req.ren1 connect ifpu.io.in.bits.wen, req.wen connect ifpu.io.in.bits.ldst, req.ldst connect ifpu.io.in.bits.in1, io.req.bits.rs1_data node _out_double_T = eq(fp_decoder.io.sigs.typeTagOut, UInt<1>(0h1)) regreset out_double_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect out_double_pipe_v, io.req.valid reg out_double_pipe_b : UInt<1>, clock when io.req.valid : connect out_double_pipe_b, _out_double_T regreset out_double_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect out_double_pipe_pipe_v, out_double_pipe_v reg out_double_pipe_pipe_b : UInt<1>, clock when out_double_pipe_v : connect out_double_pipe_pipe_b, out_double_pipe_b wire out_double_pipe_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect out_double_pipe_pipe_out.valid, out_double_pipe_pipe_v connect out_double_pipe_pipe_out.bits, out_double_pipe_pipe_b node _io_resp_bits_data_opts_bigger_swizzledNaN_T = andr(UInt<20>(0hfffff)) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_1 = bits(ifpu.io.out.bits.data, 31, 31) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_2 = bits(ifpu.io.out.bits.data, 32, 32) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_3 = bits(ifpu.io.out.bits.data, 30, 0) node io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi = cat(UInt<20>(0hfffff), _io_resp_bits_data_opts_bigger_swizzledNaN_T_2) node io_resp_bits_data_opts_bigger_swizzledNaN_lo = cat(io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi, _io_resp_bits_data_opts_bigger_swizzledNaN_T_3) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo = cat(UInt<7>(0h7f), _io_resp_bits_data_opts_bigger_swizzledNaN_T_1) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _io_resp_bits_data_opts_bigger_swizzledNaN_T) node io_resp_bits_data_opts_bigger_swizzledNaN_hi = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi, io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo) node io_resp_bits_data_opts_bigger_swizzledNaN = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi, io_resp_bits_data_opts_bigger_swizzledNaN_lo) node _io_resp_bits_data_opts_bigger_T = andr(UInt<3>(0h7)) node io_resp_bits_data_opts_bigger = mux(_io_resp_bits_data_opts_bigger_T, io_resp_bits_data_opts_bigger_swizzledNaN, UInt<65>(0h1ffffffffffffffff)) node io_resp_bits_data_opts_0 = or(io_resp_bits_data_opts_bigger, UInt<1>(0h0)) node _io_resp_bits_data_T = eq(out_double_pipe_pipe_out.bits, UInt<1>(0h1)) node _io_resp_bits_data_T_1 = mux(_io_resp_bits_data_T, ifpu.io.out.bits.data, io_resp_bits_data_opts_0) connect io.resp.bits.data, _io_resp_bits_data_T_1 connect io.resp.bits.fflags.valid, ifpu.io.out.valid connect io.resp.bits.fflags.bits.uop.debug_tsrc, io.resp.bits.uop.debug_tsrc connect io.resp.bits.fflags.bits.uop.debug_fsrc, io.resp.bits.uop.debug_fsrc connect io.resp.bits.fflags.bits.uop.bp_xcpt_if, io.resp.bits.uop.bp_xcpt_if connect io.resp.bits.fflags.bits.uop.bp_debug_if, io.resp.bits.uop.bp_debug_if connect io.resp.bits.fflags.bits.uop.xcpt_ma_if, io.resp.bits.uop.xcpt_ma_if connect io.resp.bits.fflags.bits.uop.xcpt_ae_if, io.resp.bits.uop.xcpt_ae_if connect io.resp.bits.fflags.bits.uop.xcpt_pf_if, io.resp.bits.uop.xcpt_pf_if connect io.resp.bits.fflags.bits.uop.fp_single, io.resp.bits.uop.fp_single connect io.resp.bits.fflags.bits.uop.fp_val, io.resp.bits.uop.fp_val connect io.resp.bits.fflags.bits.uop.frs3_en, io.resp.bits.uop.frs3_en connect io.resp.bits.fflags.bits.uop.lrs2_rtype, io.resp.bits.uop.lrs2_rtype connect io.resp.bits.fflags.bits.uop.lrs1_rtype, io.resp.bits.uop.lrs1_rtype connect io.resp.bits.fflags.bits.uop.dst_rtype, io.resp.bits.uop.dst_rtype connect io.resp.bits.fflags.bits.uop.ldst_val, io.resp.bits.uop.ldst_val connect io.resp.bits.fflags.bits.uop.lrs3, io.resp.bits.uop.lrs3 connect io.resp.bits.fflags.bits.uop.lrs2, io.resp.bits.uop.lrs2 connect io.resp.bits.fflags.bits.uop.lrs1, io.resp.bits.uop.lrs1 connect io.resp.bits.fflags.bits.uop.ldst, io.resp.bits.uop.ldst connect io.resp.bits.fflags.bits.uop.ldst_is_rs1, io.resp.bits.uop.ldst_is_rs1 connect io.resp.bits.fflags.bits.uop.flush_on_commit, io.resp.bits.uop.flush_on_commit connect io.resp.bits.fflags.bits.uop.is_unique, io.resp.bits.uop.is_unique connect io.resp.bits.fflags.bits.uop.is_sys_pc2epc, io.resp.bits.uop.is_sys_pc2epc connect io.resp.bits.fflags.bits.uop.uses_stq, io.resp.bits.uop.uses_stq connect io.resp.bits.fflags.bits.uop.uses_ldq, io.resp.bits.uop.uses_ldq connect io.resp.bits.fflags.bits.uop.is_amo, io.resp.bits.uop.is_amo connect io.resp.bits.fflags.bits.uop.is_fencei, io.resp.bits.uop.is_fencei connect io.resp.bits.fflags.bits.uop.is_fence, io.resp.bits.uop.is_fence connect io.resp.bits.fflags.bits.uop.mem_signed, io.resp.bits.uop.mem_signed connect io.resp.bits.fflags.bits.uop.mem_size, io.resp.bits.uop.mem_size connect io.resp.bits.fflags.bits.uop.mem_cmd, io.resp.bits.uop.mem_cmd connect io.resp.bits.fflags.bits.uop.bypassable, io.resp.bits.uop.bypassable connect io.resp.bits.fflags.bits.uop.exc_cause, io.resp.bits.uop.exc_cause connect io.resp.bits.fflags.bits.uop.exception, io.resp.bits.uop.exception connect io.resp.bits.fflags.bits.uop.stale_pdst, io.resp.bits.uop.stale_pdst connect io.resp.bits.fflags.bits.uop.ppred_busy, io.resp.bits.uop.ppred_busy connect io.resp.bits.fflags.bits.uop.prs3_busy, io.resp.bits.uop.prs3_busy connect io.resp.bits.fflags.bits.uop.prs2_busy, io.resp.bits.uop.prs2_busy connect io.resp.bits.fflags.bits.uop.prs1_busy, io.resp.bits.uop.prs1_busy connect io.resp.bits.fflags.bits.uop.ppred, io.resp.bits.uop.ppred connect io.resp.bits.fflags.bits.uop.prs3, io.resp.bits.uop.prs3 connect io.resp.bits.fflags.bits.uop.prs2, io.resp.bits.uop.prs2 connect io.resp.bits.fflags.bits.uop.prs1, io.resp.bits.uop.prs1 connect io.resp.bits.fflags.bits.uop.pdst, io.resp.bits.uop.pdst connect io.resp.bits.fflags.bits.uop.rxq_idx, io.resp.bits.uop.rxq_idx connect io.resp.bits.fflags.bits.uop.stq_idx, io.resp.bits.uop.stq_idx connect io.resp.bits.fflags.bits.uop.ldq_idx, io.resp.bits.uop.ldq_idx connect io.resp.bits.fflags.bits.uop.rob_idx, io.resp.bits.uop.rob_idx connect io.resp.bits.fflags.bits.uop.csr_addr, io.resp.bits.uop.csr_addr connect io.resp.bits.fflags.bits.uop.imm_packed, io.resp.bits.uop.imm_packed connect io.resp.bits.fflags.bits.uop.taken, io.resp.bits.uop.taken connect io.resp.bits.fflags.bits.uop.pc_lob, io.resp.bits.uop.pc_lob connect io.resp.bits.fflags.bits.uop.edge_inst, io.resp.bits.uop.edge_inst connect io.resp.bits.fflags.bits.uop.ftq_idx, io.resp.bits.uop.ftq_idx connect io.resp.bits.fflags.bits.uop.br_tag, io.resp.bits.uop.br_tag connect io.resp.bits.fflags.bits.uop.br_mask, io.resp.bits.uop.br_mask connect io.resp.bits.fflags.bits.uop.is_sfb, io.resp.bits.uop.is_sfb connect io.resp.bits.fflags.bits.uop.is_jal, io.resp.bits.uop.is_jal connect io.resp.bits.fflags.bits.uop.is_jalr, io.resp.bits.uop.is_jalr connect io.resp.bits.fflags.bits.uop.is_br, io.resp.bits.uop.is_br connect io.resp.bits.fflags.bits.uop.iw_p2_poisoned, io.resp.bits.uop.iw_p2_poisoned connect io.resp.bits.fflags.bits.uop.iw_p1_poisoned, io.resp.bits.uop.iw_p1_poisoned connect io.resp.bits.fflags.bits.uop.iw_state, io.resp.bits.uop.iw_state connect io.resp.bits.fflags.bits.uop.ctrl.is_std, io.resp.bits.uop.ctrl.is_std connect io.resp.bits.fflags.bits.uop.ctrl.is_sta, io.resp.bits.uop.ctrl.is_sta connect io.resp.bits.fflags.bits.uop.ctrl.is_load, io.resp.bits.uop.ctrl.is_load connect io.resp.bits.fflags.bits.uop.ctrl.csr_cmd, io.resp.bits.uop.ctrl.csr_cmd connect io.resp.bits.fflags.bits.uop.ctrl.fcn_dw, io.resp.bits.uop.ctrl.fcn_dw connect io.resp.bits.fflags.bits.uop.ctrl.op_fcn, io.resp.bits.uop.ctrl.op_fcn connect io.resp.bits.fflags.bits.uop.ctrl.imm_sel, io.resp.bits.uop.ctrl.imm_sel connect io.resp.bits.fflags.bits.uop.ctrl.op2_sel, io.resp.bits.uop.ctrl.op2_sel connect io.resp.bits.fflags.bits.uop.ctrl.op1_sel, io.resp.bits.uop.ctrl.op1_sel connect io.resp.bits.fflags.bits.uop.ctrl.br_type, io.resp.bits.uop.ctrl.br_type connect io.resp.bits.fflags.bits.uop.fu_code, io.resp.bits.uop.fu_code connect io.resp.bits.fflags.bits.uop.iq_type, io.resp.bits.uop.iq_type connect io.resp.bits.fflags.bits.uop.debug_pc, io.resp.bits.uop.debug_pc connect io.resp.bits.fflags.bits.uop.is_rvc, io.resp.bits.uop.is_rvc connect io.resp.bits.fflags.bits.uop.debug_inst, io.resp.bits.uop.debug_inst connect io.resp.bits.fflags.bits.uop.inst, io.resp.bits.uop.inst connect io.resp.bits.fflags.bits.uop.uopc, io.resp.bits.uop.uopc connect io.resp.bits.fflags.bits.flags, ifpu.io.out.bits.exc

module IntToFPUnit( // @[functional-unit.scala:591:7] input clock, // @[functional-unit.scala:591:7] input reset, // @[functional-unit.scala:591:7] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14] ); wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [64:0] _ifpu_io_out_bits_data; // @[functional-unit.scala:624:20] wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[functional-unit.scala:600:26] wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[functional-unit.scala:600:26] wire _fp_decoder_io_sigs_fromint; // @[functional-unit.scala:600:26] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:591:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:591:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:591:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:591:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:591:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:591:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:591:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:591:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:591:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:591:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:591:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[functional-unit.scala:591:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:591:7] wire _io_resp_bits_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _io_resp_bits_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[functional-unit.scala:591:7] wire [64:0] req_in3 = 65'h0; // @[functional-unit.scala:605:17] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_ready = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:591:7] wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35] wire req_vec = 1'h0; // @[functional-unit.scala:605:17] wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:591:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:591:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [1:0] req_fmaCmd = 2'h0; // @[functional-unit.scala:605:17] wire [1:0] req_fmt = 2'h0; // @[functional-unit.scala:605:17] wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47] wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0 = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst_0 = io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0 = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_rvc_0 = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0 = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0 = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_br_0 = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jalr_0 = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jal_0 = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sfb_0 = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire [15:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [15:0] io_resp_bits_fflags_bits_uop_br_mask_0 = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_br_tag_0 = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx_0 = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_edge_inst_0 = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0 = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_taken_0 = io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0 = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0 = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx_0 = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx_0 = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx_0 = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0 = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_pdst_0 = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs1_0 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs2_0 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs3_0 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ppred_0 = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs1_busy_0 = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs2_busy_0 = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs3_busy_0 = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ppred_busy_0 = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst_0 = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_exception_0 = io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0 = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bypassable_0 = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0 = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0 = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_mem_signed_0 = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fence_0 = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fencei_0 = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_amo_0 = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_ldq_0 = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_stq_0 = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_unique_0 = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit_0 = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0 = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_val_0 = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0 = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_frs3_en_0 = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_val_0 = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_single_0 = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if_0 = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0 = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0 = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [64:0] _io_resp_bits_data_T_1; // @[package.scala:39:76] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_valid_0; // @[functional-unit.scala:591:7] wire [64:0] io_resp_bits_data_0; // @[functional-unit.scala:591:7] wire io_resp_valid_0; // @[functional-unit.scala:591:7] reg r_valids_0; // @[functional-unit.scala:236:27] reg r_valids_1; // @[functional-unit.scala:236:27] reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_is_br; // @[functional-unit.scala:237:23] reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_0_is_jal; // @[functional-unit.scala:237:23] reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23] reg [15:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_0_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_pdst; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs1; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs2; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs3; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ppred; // @[functional-unit.scala:237:23] reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_0_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_0_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23] reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_0_is_fence; // @[functional-unit.scala:237:23] reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_0_is_amo; // @[functional-unit.scala:237:23] reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_0_is_unique; // @[functional-unit.scala:237:23] reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_0_fp_val; // @[functional-unit.scala:237:23] reg r_uops_0_fp_single; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uopc_0 = r_uops_1_uopc; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_inst_0 = r_uops_1_inst; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_inst_0 = r_uops_1_debug_inst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_rvc_0 = r_uops_1_is_rvc; // @[functional-unit.scala:237:23, :591:7] reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_pc_0 = r_uops_1_debug_pc; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iq_type_0 = r_uops_1_iq_type; // @[functional-unit.scala:237:23, :591:7] reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fu_code_0 = r_uops_1_fu_code; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_state_0 = r_uops_1_iw_state; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_br; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_br_0 = r_uops_1_is_br; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jalr_0 = r_uops_1_is_jalr; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jal; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jal_0 = r_uops_1_is_jal; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sfb_0 = r_uops_1_is_sfb; // @[functional-unit.scala:237:23, :591:7] reg [15:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_br_tag_0 = r_uops_1_br_tag; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ftq_idx_0 = r_uops_1_ftq_idx; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_edge_inst_0 = r_uops_1_edge_inst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pc_lob_0 = r_uops_1_pc_lob; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_taken; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_taken_0 = r_uops_1_taken; // @[functional-unit.scala:237:23, :591:7] reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_imm_packed_0 = r_uops_1_imm_packed; // @[functional-unit.scala:237:23, :591:7] reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_csr_addr_0 = r_uops_1_csr_addr; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rob_idx_0 = r_uops_1_rob_idx; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldq_idx_0 = r_uops_1_ldq_idx; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stq_idx_0 = r_uops_1_stq_idx; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rxq_idx_0 = r_uops_1_rxq_idx; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pdst_0 = r_uops_1_pdst; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_prs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_0 = r_uops_1_prs1; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_prs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_0 = r_uops_1_prs2; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_prs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_0 = r_uops_1_prs3; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ppred; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_0 = r_uops_1_ppred; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_busy_0 = r_uops_1_prs1_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_busy_0 = r_uops_1_prs2_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_busy_0 = r_uops_1_prs3_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_busy_0 = r_uops_1_ppred_busy; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stale_pdst_0 = r_uops_1_stale_pdst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_exception; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exception_0 = r_uops_1_exception; // @[functional-unit.scala:237:23, :591:7] reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exc_cause_0 = r_uops_1_exc_cause; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bypassable; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bypassable_0 = r_uops_1_bypassable; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_cmd_0 = r_uops_1_mem_cmd; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_size_0 = r_uops_1_mem_size; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_signed_0 = r_uops_1_mem_signed; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fence; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fence_0 = r_uops_1_is_fence; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fencei_0 = r_uops_1_is_fencei; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_amo; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_amo_0 = r_uops_1_is_amo; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_ldq_0 = r_uops_1_uses_ldq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_stq_0 = r_uops_1_uses_stq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_unique; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_unique_0 = r_uops_1_is_unique; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_flush_on_commit_0 = r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_0 = r_uops_1_ldst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_0 = r_uops_1_lrs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_0 = r_uops_1_lrs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs3_0 = r_uops_1_lrs3; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_val_0 = r_uops_1_ldst_val; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_dst_rtype_0 = r_uops_1_dst_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_frs3_en_0 = r_uops_1_frs3_en; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_val_0 = r_uops_1_fp_val; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_single; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_single_0 = r_uops_1_fp_single; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_debug_if_0 = r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_fsrc_0 = r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_tsrc_0 = r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23, :591:7] wire [15:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _r_valids_0_T_1 = |_r_valids_0_T; // @[util.scala:118:{51,59}] wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59] wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :591:7] wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :591:7] wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}] wire [15:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51] wire _r_valids_1_T_1 = |_r_valids_1_T; // @[util.scala:118:{51,59}] wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59] wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :591:7] wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51] wire _io_resp_valid_T_1 = |_io_resp_valid_T; // @[util.scala:118:{51,59}] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59] assign _io_resp_valid_T_3 = r_valids_1 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :591:7] wire [15:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _io_resp_bits_uop_br_mask_T_1 = r_uops_1_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}] assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [2:0] _fp_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire [2:0] _fp_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire _fp_rm_T_1 = &_fp_rm_T; // @[util.scala:289:58] wire [2:0] fp_rm = _fp_rm_T_1 ? io_fcsr_rm_0 : _fp_rm_T_2; // @[util.scala:289:58] wire [2:0] req_rm = fp_rm; // @[functional-unit.scala:604:18, :605:17] wire [1:0] _req_typ_T; // @[util.scala:295:59] wire [64:0] _req_in1_T_4; // @[FPU.scala:369:10] wire [64:0] _req_in2_T_4; // @[FPU.scala:369:10] wire req_ldst; // @[functional-unit.scala:605:17] wire req_wen; // @[functional-unit.scala:605:17] wire req_ren1; // @[functional-unit.scala:605:17] wire req_ren2; // @[functional-unit.scala:605:17] wire req_ren3; // @[functional-unit.scala:605:17] wire req_swap12; // @[functional-unit.scala:605:17] wire req_swap23; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagIn; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagOut; // @[functional-unit.scala:605:17] wire req_fromint; // @[functional-unit.scala:605:17] wire req_toint; // @[functional-unit.scala:605:17] wire req_fastpipe; // @[functional-unit.scala:605:17] wire req_fma; // @[functional-unit.scala:605:17] wire req_div; // @[functional-unit.scala:605:17] wire req_sqrt; // @[functional-unit.scala:605:17] wire req_wflags; // @[functional-unit.scala:605:17] wire [1:0] req_typ; // @[functional-unit.scala:605:17] wire [64:0] req_in1; // @[functional-unit.scala:605:17] wire [64:0] req_in2; // @[functional-unit.scala:605:17] wire _req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in1_prev_unswizzled_hi = {_req_in1_prev_unswizzled_T, _req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in1_prev_unswizzled = {req_in1_prev_unswizzled_hi, _req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in1_prev_prev_sign = req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in1_prev_prev_fractIn = req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in1_prev_prev_expIn = req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in1_prev_prev_fractOut_T = {req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in1_prev_prev_fractOut = _req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in1_prev_prev_expOut_expCode = req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T = {4'h0, req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in1_prev_prev_expOut_commonCase_T_1 = _req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in1_prev_prev_expOut_commonCase = _req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in1_prev_prev_expOut_T_5 = req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in1_prev_prev_expOut_T = req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in1_prev_prev_expOut_T_1 = req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in1_prev_prev_expOut_T_2 = _req_in1_prev_prev_expOut_T | _req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in1_prev_prev_expOut_T_3 = req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in1_prev_prev_expOut_T_4 = {req_in1_prev_prev_expOut_expCode, _req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in1_prev_prev_expOut = _req_in1_prev_prev_expOut_T_2 ? _req_in1_prev_prev_expOut_T_4 : _req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in1_prev_prev_hi = {req_in1_prev_prev_sign, req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in1_floats_0 = {req_in1_prev_prev_hi, req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire req_in1_prev_isbox = &_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in1_oks_0 = req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in1_truncIdx_T; // @[package.scala:38:21] wire req_in1_truncIdx = _req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in1_T = req_in1_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in1_T_1 = _req_in1_T | req_in1_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in1_truncIdx_T_1; // @[package.scala:38:21] wire req_in1_truncIdx_1 = _req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in1_T_2 = req_in1_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in1_T_3 = _req_in1_T_2 ? io_req_bits_rs1_data_0 : req_in1_floats_0; // @[package.scala:39:{76,86}] assign _req_in1_T_4 = _req_in1_T_1 ? _req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in1 = _req_in1_T_4; // @[FPU.scala:369:10] wire _req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in2_prev_unswizzled_hi = {_req_in2_prev_unswizzled_T, _req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in2_prev_unswizzled = {req_in2_prev_unswizzled_hi, _req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in2_prev_prev_sign = req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in2_prev_prev_fractIn = req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in2_prev_prev_expIn = req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in2_prev_prev_fractOut_T = {req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in2_prev_prev_fractOut = _req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in2_prev_prev_expOut_expCode = req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T = {4'h0, req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in2_prev_prev_expOut_commonCase_T_1 = _req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in2_prev_prev_expOut_commonCase = _req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in2_prev_prev_expOut_T_5 = req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in2_prev_prev_expOut_T = req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in2_prev_prev_expOut_T_1 = req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in2_prev_prev_expOut_T_2 = _req_in2_prev_prev_expOut_T | _req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in2_prev_prev_expOut_T_3 = req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in2_prev_prev_expOut_T_4 = {req_in2_prev_prev_expOut_expCode, _req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in2_prev_prev_expOut = _req_in2_prev_prev_expOut_T_2 ? _req_in2_prev_prev_expOut_T_4 : _req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in2_prev_prev_hi = {req_in2_prev_prev_sign, req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in2_floats_0 = {req_in2_prev_prev_hi, req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire req_in2_prev_isbox = &_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in2_oks_0 = req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in2_truncIdx_T; // @[package.scala:38:21] wire req_in2_truncIdx = _req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in2_T = req_in2_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in2_T_1 = _req_in2_T | req_in2_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in2_truncIdx_T_1; // @[package.scala:38:21] wire req_in2_truncIdx_1 = _req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in2_T_2 = req_in2_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in2_T_3 = _req_in2_T_2 ? io_req_bits_rs2_data_0 : req_in2_floats_0; // @[package.scala:39:{76,86}] assign _req_in2_T_4 = _req_in2_T_1 ? _req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in2 = _req_in2_T_4; // @[FPU.scala:369:10] assign _req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] assign req_typ = _req_typ_T; // @[util.scala:295:59]